2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
33 #include "radeon_asic.h"
35 #include "rv515_reg_safe.h"
37 /* This files gather functions specifics to: rv515 */
38 int rv515_debugfs_pipes_info_init(struct radeon_device
*rdev
);
39 int rv515_debugfs_ga_info_init(struct radeon_device
*rdev
);
40 void rv515_gpu_init(struct radeon_device
*rdev
);
41 int rv515_mc_wait_for_idle(struct radeon_device
*rdev
);
43 void rv515_debugfs(struct radeon_device
*rdev
)
45 if (r100_debugfs_rbbm_init(rdev
)) {
46 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
48 if (rv515_debugfs_pipes_info_init(rdev
)) {
49 DRM_ERROR("Failed to register debugfs file for pipes !\n");
51 if (rv515_debugfs_ga_info_init(rdev
)) {
52 DRM_ERROR("Failed to register debugfs file for pipes !\n");
56 void rv515_ring_start(struct radeon_device
*rdev
, struct radeon_ring
*ring
)
60 r
= radeon_ring_lock(rdev
, ring
, 64);
64 radeon_ring_write(ring
, PACKET0(ISYNC_CNTL
, 0));
65 radeon_ring_write(ring
,
69 ISYNC_CPSCRATCH_IDLEGUI
);
70 radeon_ring_write(ring
, PACKET0(WAIT_UNTIL
, 0));
71 radeon_ring_write(ring
, WAIT_2D_IDLECLEAN
| WAIT_3D_IDLECLEAN
);
72 radeon_ring_write(ring
, PACKET0(R300_DST_PIPE_CONFIG
, 0));
73 radeon_ring_write(ring
, R300_PIPE_AUTO_CONFIG
);
74 radeon_ring_write(ring
, PACKET0(GB_SELECT
, 0));
75 radeon_ring_write(ring
, 0);
76 radeon_ring_write(ring
, PACKET0(GB_ENABLE
, 0));
77 radeon_ring_write(ring
, 0);
78 radeon_ring_write(ring
, PACKET0(R500_SU_REG_DEST
, 0));
79 radeon_ring_write(ring
, (1 << rdev
->num_gb_pipes
) - 1);
80 radeon_ring_write(ring
, PACKET0(VAP_INDEX_OFFSET
, 0));
81 radeon_ring_write(ring
, 0);
82 radeon_ring_write(ring
, PACKET0(RB3D_DSTCACHE_CTLSTAT
, 0));
83 radeon_ring_write(ring
, RB3D_DC_FLUSH
| RB3D_DC_FREE
);
84 radeon_ring_write(ring
, PACKET0(ZB_ZCACHE_CTLSTAT
, 0));
85 radeon_ring_write(ring
, ZC_FLUSH
| ZC_FREE
);
86 radeon_ring_write(ring
, PACKET0(WAIT_UNTIL
, 0));
87 radeon_ring_write(ring
, WAIT_2D_IDLECLEAN
| WAIT_3D_IDLECLEAN
);
88 radeon_ring_write(ring
, PACKET0(GB_AA_CONFIG
, 0));
89 radeon_ring_write(ring
, 0);
90 radeon_ring_write(ring
, PACKET0(RB3D_DSTCACHE_CTLSTAT
, 0));
91 radeon_ring_write(ring
, RB3D_DC_FLUSH
| RB3D_DC_FREE
);
92 radeon_ring_write(ring
, PACKET0(ZB_ZCACHE_CTLSTAT
, 0));
93 radeon_ring_write(ring
, ZC_FLUSH
| ZC_FREE
);
94 radeon_ring_write(ring
, PACKET0(GB_MSPOS0
, 0));
95 radeon_ring_write(ring
,
102 (6 << MSBD0_Y_SHIFT
) |
103 (6 << MSBD0_X_SHIFT
)));
104 radeon_ring_write(ring
, PACKET0(GB_MSPOS1
, 0));
105 radeon_ring_write(ring
,
106 ((6 << MS_X3_SHIFT
) |
112 (6 << MSBD1_SHIFT
)));
113 radeon_ring_write(ring
, PACKET0(GA_ENHANCE
, 0));
114 radeon_ring_write(ring
, GA_DEADLOCK_CNTL
| GA_FASTSYNC_CNTL
);
115 radeon_ring_write(ring
, PACKET0(GA_POLY_MODE
, 0));
116 radeon_ring_write(ring
, FRONT_PTYPE_TRIANGE
| BACK_PTYPE_TRIANGE
);
117 radeon_ring_write(ring
, PACKET0(GA_ROUND_MODE
, 0));
118 radeon_ring_write(ring
, GEOMETRY_ROUND_NEAREST
| COLOR_ROUND_NEAREST
);
119 radeon_ring_write(ring
, PACKET0(0x20C8, 0));
120 radeon_ring_write(ring
, 0);
121 radeon_ring_unlock_commit(rdev
, ring
);
124 int rv515_mc_wait_for_idle(struct radeon_device
*rdev
)
129 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
131 tmp
= RREG32_MC(MC_STATUS
);
132 if (tmp
& MC_STATUS_IDLE
) {
140 void rv515_vga_render_disable(struct radeon_device
*rdev
)
142 WREG32(R_000300_VGA_RENDER_CONTROL
,
143 RREG32(R_000300_VGA_RENDER_CONTROL
) & C_000300_VGA_VSTATUS_CNTL
);
146 void rv515_gpu_init(struct radeon_device
*rdev
)
148 unsigned pipe_select_current
, gb_pipe_select
, tmp
;
150 if (r100_gui_wait_for_idle(rdev
)) {
151 printk(KERN_WARNING
"Failed to wait GUI idle while "
152 "resetting GPU. Bad things might happen.\n");
154 rv515_vga_render_disable(rdev
);
155 r420_pipes_init(rdev
);
156 gb_pipe_select
= RREG32(R400_GB_PIPE_SELECT
);
157 tmp
= RREG32(R300_DST_PIPE_CONFIG
);
158 pipe_select_current
= (tmp
>> 2) & 3;
159 tmp
= (1 << pipe_select_current
) |
160 (((gb_pipe_select
>> 8) & 0xF) << 4);
161 WREG32_PLL(0x000D, tmp
);
162 if (r100_gui_wait_for_idle(rdev
)) {
163 printk(KERN_WARNING
"Failed to wait GUI idle while "
164 "resetting GPU. Bad things might happen.\n");
166 if (rv515_mc_wait_for_idle(rdev
)) {
167 printk(KERN_WARNING
"Failed to wait MC idle while "
168 "programming pipes. Bad things might happen.\n");
172 static void rv515_vram_get_type(struct radeon_device
*rdev
)
176 rdev
->mc
.vram_width
= 128;
177 rdev
->mc
.vram_is_ddr
= true;
178 tmp
= RREG32_MC(RV515_MC_CNTL
) & MEM_NUM_CHANNELS_MASK
;
181 rdev
->mc
.vram_width
= 64;
184 rdev
->mc
.vram_width
= 128;
187 rdev
->mc
.vram_width
= 128;
192 void rv515_mc_init(struct radeon_device
*rdev
)
195 rv515_vram_get_type(rdev
);
196 r100_vram_init_sizes(rdev
);
197 radeon_vram_location(rdev
, &rdev
->mc
, 0);
198 rdev
->mc
.gtt_base_align
= 0;
199 if (!(rdev
->flags
& RADEON_IS_AGP
))
200 radeon_gtt_location(rdev
, &rdev
->mc
);
201 radeon_update_bandwidth_info(rdev
);
204 uint32_t rv515_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
)
208 WREG32(MC_IND_INDEX
, 0x7f0000 | (reg
& 0xffff));
209 r
= RREG32(MC_IND_DATA
);
210 WREG32(MC_IND_INDEX
, 0);
214 void rv515_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
216 WREG32(MC_IND_INDEX
, 0xff0000 | ((reg
) & 0xffff));
217 WREG32(MC_IND_DATA
, (v
));
218 WREG32(MC_IND_INDEX
, 0);
221 #if defined(CONFIG_DEBUG_FS)
222 static int rv515_debugfs_pipes_info(struct seq_file
*m
, void *data
)
224 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
225 struct drm_device
*dev
= node
->minor
->dev
;
226 struct radeon_device
*rdev
= dev
->dev_private
;
229 tmp
= RREG32(GB_PIPE_SELECT
);
230 seq_printf(m
, "GB_PIPE_SELECT 0x%08x\n", tmp
);
231 tmp
= RREG32(SU_REG_DEST
);
232 seq_printf(m
, "SU_REG_DEST 0x%08x\n", tmp
);
233 tmp
= RREG32(GB_TILE_CONFIG
);
234 seq_printf(m
, "GB_TILE_CONFIG 0x%08x\n", tmp
);
235 tmp
= RREG32(DST_PIPE_CONFIG
);
236 seq_printf(m
, "DST_PIPE_CONFIG 0x%08x\n", tmp
);
240 static int rv515_debugfs_ga_info(struct seq_file
*m
, void *data
)
242 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
243 struct drm_device
*dev
= node
->minor
->dev
;
244 struct radeon_device
*rdev
= dev
->dev_private
;
247 tmp
= RREG32(0x2140);
248 seq_printf(m
, "VAP_CNTL_STATUS 0x%08x\n", tmp
);
249 radeon_asic_reset(rdev
);
250 tmp
= RREG32(0x425C);
251 seq_printf(m
, "GA_IDLE 0x%08x\n", tmp
);
255 static struct drm_info_list rv515_pipes_info_list
[] = {
256 {"rv515_pipes_info", rv515_debugfs_pipes_info
, 0, NULL
},
259 static struct drm_info_list rv515_ga_info_list
[] = {
260 {"rv515_ga_info", rv515_debugfs_ga_info
, 0, NULL
},
264 int rv515_debugfs_pipes_info_init(struct radeon_device
*rdev
)
266 #if defined(CONFIG_DEBUG_FS)
267 return radeon_debugfs_add_files(rdev
, rv515_pipes_info_list
, 1);
273 int rv515_debugfs_ga_info_init(struct radeon_device
*rdev
)
275 #if defined(CONFIG_DEBUG_FS)
276 return radeon_debugfs_add_files(rdev
, rv515_ga_info_list
, 1);
282 void rv515_mc_stop(struct radeon_device
*rdev
, struct rv515_mc_save
*save
)
284 save
->vga_render_control
= RREG32(R_000300_VGA_RENDER_CONTROL
);
285 save
->vga_hdp_control
= RREG32(R_000328_VGA_HDP_CONTROL
);
288 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK
, 0);
289 WREG32(R_000300_VGA_RENDER_CONTROL
, 0);
290 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK
, 1);
291 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK
, 1);
292 WREG32(R_006080_D1CRTC_CONTROL
, 0);
293 WREG32(R_006880_D2CRTC_CONTROL
, 0);
294 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK
, 0);
295 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK
, 0);
296 WREG32(R_000330_D1VGA_CONTROL
, 0);
297 WREG32(R_000338_D2VGA_CONTROL
, 0);
300 void rv515_mc_resume(struct radeon_device
*rdev
, struct rv515_mc_save
*save
)
302 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS
, rdev
->mc
.vram_start
);
303 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS
, rdev
->mc
.vram_start
);
304 WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS
, rdev
->mc
.vram_start
);
305 WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS
, rdev
->mc
.vram_start
);
306 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS
, rdev
->mc
.vram_start
);
307 /* Unlock host access */
308 WREG32(R_000328_VGA_HDP_CONTROL
, save
->vga_hdp_control
);
310 WREG32(R_000300_VGA_RENDER_CONTROL
, save
->vga_render_control
);
313 void rv515_mc_program(struct radeon_device
*rdev
)
315 struct rv515_mc_save save
;
317 /* Stops all mc clients */
318 rv515_mc_stop(rdev
, &save
);
320 /* Wait for mc idle */
321 if (rv515_mc_wait_for_idle(rdev
))
322 dev_warn(rdev
->dev
, "Wait MC idle timeout before updating MC.\n");
323 /* Write VRAM size in case we are limiting it */
324 WREG32(R_0000F8_CONFIG_MEMSIZE
, rdev
->mc
.real_vram_size
);
325 /* Program MC, should be a 32bits limited address space */
326 WREG32_MC(R_000001_MC_FB_LOCATION
,
327 S_000001_MC_FB_START(rdev
->mc
.vram_start
>> 16) |
328 S_000001_MC_FB_TOP(rdev
->mc
.vram_end
>> 16));
329 WREG32(R_000134_HDP_FB_LOCATION
,
330 S_000134_HDP_FB_START(rdev
->mc
.vram_start
>> 16));
331 if (rdev
->flags
& RADEON_IS_AGP
) {
332 WREG32_MC(R_000002_MC_AGP_LOCATION
,
333 S_000002_MC_AGP_START(rdev
->mc
.gtt_start
>> 16) |
334 S_000002_MC_AGP_TOP(rdev
->mc
.gtt_end
>> 16));
335 WREG32_MC(R_000003_MC_AGP_BASE
, lower_32_bits(rdev
->mc
.agp_base
));
336 WREG32_MC(R_000004_MC_AGP_BASE_2
,
337 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev
->mc
.agp_base
)));
339 WREG32_MC(R_000002_MC_AGP_LOCATION
, 0xFFFFFFFF);
340 WREG32_MC(R_000003_MC_AGP_BASE
, 0);
341 WREG32_MC(R_000004_MC_AGP_BASE_2
, 0);
344 rv515_mc_resume(rdev
, &save
);
347 void rv515_clock_startup(struct radeon_device
*rdev
)
349 if (radeon_dynclks
!= -1 && radeon_dynclks
)
350 radeon_atom_set_clock_gating(rdev
, 1);
351 /* We need to force on some of the block */
352 WREG32_PLL(R_00000F_CP_DYN_CNTL
,
353 RREG32_PLL(R_00000F_CP_DYN_CNTL
) | S_00000F_CP_FORCEON(1));
354 WREG32_PLL(R_000011_E2_DYN_CNTL
,
355 RREG32_PLL(R_000011_E2_DYN_CNTL
) | S_000011_E2_FORCEON(1));
356 WREG32_PLL(R_000013_IDCT_DYN_CNTL
,
357 RREG32_PLL(R_000013_IDCT_DYN_CNTL
) | S_000013_IDCT_FORCEON(1));
360 static int rv515_startup(struct radeon_device
*rdev
)
364 rv515_mc_program(rdev
);
366 rv515_clock_startup(rdev
);
367 /* Initialize GPU configuration (# pipes, ...) */
368 rv515_gpu_init(rdev
);
369 /* Initialize GART (initialize after TTM so we can allocate
370 * memory through TTM but finalize after TTM) */
371 if (rdev
->flags
& RADEON_IS_PCIE
) {
372 r
= rv370_pcie_gart_enable(rdev
);
377 /* allocate wb buffer */
378 r
= radeon_wb_init(rdev
);
382 r
= radeon_fence_driver_start_ring(rdev
, RADEON_RING_TYPE_GFX_INDEX
);
384 dev_err(rdev
->dev
, "failed initializing CP fences (%d).\n", r
);
390 rdev
->config
.r300
.hdp_cntl
= RREG32(RADEON_HOST_PATH_CNTL
);
392 r
= r100_cp_init(rdev
, 1024 * 1024);
394 dev_err(rdev
->dev
, "failed initializing CP (%d).\n", r
);
398 r
= radeon_ib_pool_init(rdev
);
400 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
407 int rv515_resume(struct radeon_device
*rdev
)
411 /* Make sur GART are not working */
412 if (rdev
->flags
& RADEON_IS_PCIE
)
413 rv370_pcie_gart_disable(rdev
);
414 /* Resume clock before doing reset */
415 rv515_clock_startup(rdev
);
416 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
417 if (radeon_asic_reset(rdev
)) {
418 dev_warn(rdev
->dev
, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
419 RREG32(R_000E40_RBBM_STATUS
),
420 RREG32(R_0007C0_CP_STAT
));
423 atom_asic_init(rdev
->mode_info
.atom_context
);
424 /* Resume clock after posting */
425 rv515_clock_startup(rdev
);
426 /* Initialize surface registers */
427 radeon_surface_init(rdev
);
429 rdev
->accel_working
= true;
430 r
= rv515_startup(rdev
);
432 rdev
->accel_working
= false;
437 int rv515_suspend(struct radeon_device
*rdev
)
439 r100_cp_disable(rdev
);
440 radeon_wb_disable(rdev
);
441 rs600_irq_disable(rdev
);
442 if (rdev
->flags
& RADEON_IS_PCIE
)
443 rv370_pcie_gart_disable(rdev
);
447 void rv515_set_safe_registers(struct radeon_device
*rdev
)
449 rdev
->config
.r300
.reg_safe_bm
= rv515_reg_safe_bm
;
450 rdev
->config
.r300
.reg_safe_bm_size
= ARRAY_SIZE(rv515_reg_safe_bm
);
453 void rv515_fini(struct radeon_device
*rdev
)
456 radeon_wb_fini(rdev
);
457 radeon_ib_pool_fini(rdev
);
458 radeon_gem_fini(rdev
);
459 rv370_pcie_gart_fini(rdev
);
460 radeon_agp_fini(rdev
);
461 radeon_irq_kms_fini(rdev
);
462 radeon_fence_driver_fini(rdev
);
463 radeon_bo_fini(rdev
);
464 radeon_atombios_fini(rdev
);
469 int rv515_init(struct radeon_device
*rdev
)
473 /* Initialize scratch registers */
474 radeon_scratch_init(rdev
);
475 /* Initialize surface registers */
476 radeon_surface_init(rdev
);
477 /* TODO: disable VGA need to use VGA request */
478 /* restore some register to sane defaults */
479 r100_restore_sanity(rdev
);
481 if (!radeon_get_bios(rdev
)) {
482 if (ASIC_IS_AVIVO(rdev
))
485 if (rdev
->is_atom_bios
) {
486 r
= radeon_atombios_init(rdev
);
490 dev_err(rdev
->dev
, "Expecting atombios for RV515 GPU\n");
493 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
494 if (radeon_asic_reset(rdev
)) {
496 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
497 RREG32(R_000E40_RBBM_STATUS
),
498 RREG32(R_0007C0_CP_STAT
));
500 /* check if cards are posted or not */
501 if (radeon_boot_test_post_card(rdev
) == false)
503 /* Initialize clocks */
504 radeon_get_clock_info(rdev
->ddev
);
506 if (rdev
->flags
& RADEON_IS_AGP
) {
507 r
= radeon_agp_init(rdev
);
509 radeon_agp_disable(rdev
);
512 /* initialize memory controller */
516 r
= radeon_fence_driver_init(rdev
);
519 r
= radeon_irq_kms_init(rdev
);
523 r
= radeon_bo_init(rdev
);
526 r
= rv370_pcie_gart_init(rdev
);
529 rv515_set_safe_registers(rdev
);
531 rdev
->accel_working
= true;
532 r
= rv515_startup(rdev
);
534 /* Somethings want wront with the accel init stop accel */
535 dev_err(rdev
->dev
, "Disabling GPU acceleration\n");
537 radeon_wb_fini(rdev
);
538 radeon_ib_pool_fini(rdev
);
539 radeon_irq_kms_fini(rdev
);
540 rv370_pcie_gart_fini(rdev
);
541 radeon_agp_fini(rdev
);
542 rdev
->accel_working
= false;
547 void atom_rv515_force_tv_scaler(struct radeon_device
*rdev
, struct radeon_crtc
*crtc
)
549 int index_reg
= 0x6578 + crtc
->crtc_offset
;
550 int data_reg
= 0x657c + crtc
->crtc_offset
;
552 WREG32(0x659C + crtc
->crtc_offset
, 0x0);
553 WREG32(0x6594 + crtc
->crtc_offset
, 0x705);
554 WREG32(0x65A4 + crtc
->crtc_offset
, 0x10001);
555 WREG32(0x65D8 + crtc
->crtc_offset
, 0x0);
556 WREG32(0x65B0 + crtc
->crtc_offset
, 0x0);
557 WREG32(0x65C0 + crtc
->crtc_offset
, 0x0);
558 WREG32(0x65D4 + crtc
->crtc_offset
, 0x0);
559 WREG32(index_reg
, 0x0);
560 WREG32(data_reg
, 0x841880A8);
561 WREG32(index_reg
, 0x1);
562 WREG32(data_reg
, 0x84208680);
563 WREG32(index_reg
, 0x2);
564 WREG32(data_reg
, 0xBFF880B0);
565 WREG32(index_reg
, 0x100);
566 WREG32(data_reg
, 0x83D88088);
567 WREG32(index_reg
, 0x101);
568 WREG32(data_reg
, 0x84608680);
569 WREG32(index_reg
, 0x102);
570 WREG32(data_reg
, 0xBFF080D0);
571 WREG32(index_reg
, 0x200);
572 WREG32(data_reg
, 0x83988068);
573 WREG32(index_reg
, 0x201);
574 WREG32(data_reg
, 0x84A08680);
575 WREG32(index_reg
, 0x202);
576 WREG32(data_reg
, 0xBFF080F8);
577 WREG32(index_reg
, 0x300);
578 WREG32(data_reg
, 0x83588058);
579 WREG32(index_reg
, 0x301);
580 WREG32(data_reg
, 0x84E08660);
581 WREG32(index_reg
, 0x302);
582 WREG32(data_reg
, 0xBFF88120);
583 WREG32(index_reg
, 0x400);
584 WREG32(data_reg
, 0x83188040);
585 WREG32(index_reg
, 0x401);
586 WREG32(data_reg
, 0x85008660);
587 WREG32(index_reg
, 0x402);
588 WREG32(data_reg
, 0xBFF88150);
589 WREG32(index_reg
, 0x500);
590 WREG32(data_reg
, 0x82D88030);
591 WREG32(index_reg
, 0x501);
592 WREG32(data_reg
, 0x85408640);
593 WREG32(index_reg
, 0x502);
594 WREG32(data_reg
, 0xBFF88180);
595 WREG32(index_reg
, 0x600);
596 WREG32(data_reg
, 0x82A08018);
597 WREG32(index_reg
, 0x601);
598 WREG32(data_reg
, 0x85808620);
599 WREG32(index_reg
, 0x602);
600 WREG32(data_reg
, 0xBFF081B8);
601 WREG32(index_reg
, 0x700);
602 WREG32(data_reg
, 0x82608010);
603 WREG32(index_reg
, 0x701);
604 WREG32(data_reg
, 0x85A08600);
605 WREG32(index_reg
, 0x702);
606 WREG32(data_reg
, 0x800081F0);
607 WREG32(index_reg
, 0x800);
608 WREG32(data_reg
, 0x8228BFF8);
609 WREG32(index_reg
, 0x801);
610 WREG32(data_reg
, 0x85E085E0);
611 WREG32(index_reg
, 0x802);
612 WREG32(data_reg
, 0xBFF88228);
613 WREG32(index_reg
, 0x10000);
614 WREG32(data_reg
, 0x82A8BF00);
615 WREG32(index_reg
, 0x10001);
616 WREG32(data_reg
, 0x82A08CC0);
617 WREG32(index_reg
, 0x10002);
618 WREG32(data_reg
, 0x8008BEF8);
619 WREG32(index_reg
, 0x10100);
620 WREG32(data_reg
, 0x81F0BF28);
621 WREG32(index_reg
, 0x10101);
622 WREG32(data_reg
, 0x83608CA0);
623 WREG32(index_reg
, 0x10102);
624 WREG32(data_reg
, 0x8018BED0);
625 WREG32(index_reg
, 0x10200);
626 WREG32(data_reg
, 0x8148BF38);
627 WREG32(index_reg
, 0x10201);
628 WREG32(data_reg
, 0x84408C80);
629 WREG32(index_reg
, 0x10202);
630 WREG32(data_reg
, 0x8008BEB8);
631 WREG32(index_reg
, 0x10300);
632 WREG32(data_reg
, 0x80B0BF78);
633 WREG32(index_reg
, 0x10301);
634 WREG32(data_reg
, 0x85008C20);
635 WREG32(index_reg
, 0x10302);
636 WREG32(data_reg
, 0x8020BEA0);
637 WREG32(index_reg
, 0x10400);
638 WREG32(data_reg
, 0x8028BF90);
639 WREG32(index_reg
, 0x10401);
640 WREG32(data_reg
, 0x85E08BC0);
641 WREG32(index_reg
, 0x10402);
642 WREG32(data_reg
, 0x8018BE90);
643 WREG32(index_reg
, 0x10500);
644 WREG32(data_reg
, 0xBFB8BFB0);
645 WREG32(index_reg
, 0x10501);
646 WREG32(data_reg
, 0x86C08B40);
647 WREG32(index_reg
, 0x10502);
648 WREG32(data_reg
, 0x8010BE90);
649 WREG32(index_reg
, 0x10600);
650 WREG32(data_reg
, 0xBF58BFC8);
651 WREG32(index_reg
, 0x10601);
652 WREG32(data_reg
, 0x87A08AA0);
653 WREG32(index_reg
, 0x10602);
654 WREG32(data_reg
, 0x8010BE98);
655 WREG32(index_reg
, 0x10700);
656 WREG32(data_reg
, 0xBF10BFF0);
657 WREG32(index_reg
, 0x10701);
658 WREG32(data_reg
, 0x886089E0);
659 WREG32(index_reg
, 0x10702);
660 WREG32(data_reg
, 0x8018BEB0);
661 WREG32(index_reg
, 0x10800);
662 WREG32(data_reg
, 0xBED8BFE8);
663 WREG32(index_reg
, 0x10801);
664 WREG32(data_reg
, 0x89408940);
665 WREG32(index_reg
, 0x10802);
666 WREG32(data_reg
, 0xBFE8BED8);
667 WREG32(index_reg
, 0x20000);
668 WREG32(data_reg
, 0x80008000);
669 WREG32(index_reg
, 0x20001);
670 WREG32(data_reg
, 0x90008000);
671 WREG32(index_reg
, 0x20002);
672 WREG32(data_reg
, 0x80008000);
673 WREG32(index_reg
, 0x20003);
674 WREG32(data_reg
, 0x80008000);
675 WREG32(index_reg
, 0x20100);
676 WREG32(data_reg
, 0x80108000);
677 WREG32(index_reg
, 0x20101);
678 WREG32(data_reg
, 0x8FE0BF70);
679 WREG32(index_reg
, 0x20102);
680 WREG32(data_reg
, 0xBFE880C0);
681 WREG32(index_reg
, 0x20103);
682 WREG32(data_reg
, 0x80008000);
683 WREG32(index_reg
, 0x20200);
684 WREG32(data_reg
, 0x8018BFF8);
685 WREG32(index_reg
, 0x20201);
686 WREG32(data_reg
, 0x8F80BF08);
687 WREG32(index_reg
, 0x20202);
688 WREG32(data_reg
, 0xBFD081A0);
689 WREG32(index_reg
, 0x20203);
690 WREG32(data_reg
, 0xBFF88000);
691 WREG32(index_reg
, 0x20300);
692 WREG32(data_reg
, 0x80188000);
693 WREG32(index_reg
, 0x20301);
694 WREG32(data_reg
, 0x8EE0BEC0);
695 WREG32(index_reg
, 0x20302);
696 WREG32(data_reg
, 0xBFB082A0);
697 WREG32(index_reg
, 0x20303);
698 WREG32(data_reg
, 0x80008000);
699 WREG32(index_reg
, 0x20400);
700 WREG32(data_reg
, 0x80188000);
701 WREG32(index_reg
, 0x20401);
702 WREG32(data_reg
, 0x8E00BEA0);
703 WREG32(index_reg
, 0x20402);
704 WREG32(data_reg
, 0xBF8883C0);
705 WREG32(index_reg
, 0x20403);
706 WREG32(data_reg
, 0x80008000);
707 WREG32(index_reg
, 0x20500);
708 WREG32(data_reg
, 0x80188000);
709 WREG32(index_reg
, 0x20501);
710 WREG32(data_reg
, 0x8D00BE90);
711 WREG32(index_reg
, 0x20502);
712 WREG32(data_reg
, 0xBF588500);
713 WREG32(index_reg
, 0x20503);
714 WREG32(data_reg
, 0x80008008);
715 WREG32(index_reg
, 0x20600);
716 WREG32(data_reg
, 0x80188000);
717 WREG32(index_reg
, 0x20601);
718 WREG32(data_reg
, 0x8BC0BE98);
719 WREG32(index_reg
, 0x20602);
720 WREG32(data_reg
, 0xBF308660);
721 WREG32(index_reg
, 0x20603);
722 WREG32(data_reg
, 0x80008008);
723 WREG32(index_reg
, 0x20700);
724 WREG32(data_reg
, 0x80108000);
725 WREG32(index_reg
, 0x20701);
726 WREG32(data_reg
, 0x8A80BEB0);
727 WREG32(index_reg
, 0x20702);
728 WREG32(data_reg
, 0xBF0087C0);
729 WREG32(index_reg
, 0x20703);
730 WREG32(data_reg
, 0x80008008);
731 WREG32(index_reg
, 0x20800);
732 WREG32(data_reg
, 0x80108000);
733 WREG32(index_reg
, 0x20801);
734 WREG32(data_reg
, 0x8920BED0);
735 WREG32(index_reg
, 0x20802);
736 WREG32(data_reg
, 0xBED08920);
737 WREG32(index_reg
, 0x20803);
738 WREG32(data_reg
, 0x80008010);
739 WREG32(index_reg
, 0x30000);
740 WREG32(data_reg
, 0x90008000);
741 WREG32(index_reg
, 0x30001);
742 WREG32(data_reg
, 0x80008000);
743 WREG32(index_reg
, 0x30100);
744 WREG32(data_reg
, 0x8FE0BF90);
745 WREG32(index_reg
, 0x30101);
746 WREG32(data_reg
, 0xBFF880A0);
747 WREG32(index_reg
, 0x30200);
748 WREG32(data_reg
, 0x8F60BF40);
749 WREG32(index_reg
, 0x30201);
750 WREG32(data_reg
, 0xBFE88180);
751 WREG32(index_reg
, 0x30300);
752 WREG32(data_reg
, 0x8EC0BF00);
753 WREG32(index_reg
, 0x30301);
754 WREG32(data_reg
, 0xBFC88280);
755 WREG32(index_reg
, 0x30400);
756 WREG32(data_reg
, 0x8DE0BEE0);
757 WREG32(index_reg
, 0x30401);
758 WREG32(data_reg
, 0xBFA083A0);
759 WREG32(index_reg
, 0x30500);
760 WREG32(data_reg
, 0x8CE0BED0);
761 WREG32(index_reg
, 0x30501);
762 WREG32(data_reg
, 0xBF7884E0);
763 WREG32(index_reg
, 0x30600);
764 WREG32(data_reg
, 0x8BA0BED8);
765 WREG32(index_reg
, 0x30601);
766 WREG32(data_reg
, 0xBF508640);
767 WREG32(index_reg
, 0x30700);
768 WREG32(data_reg
, 0x8A60BEE8);
769 WREG32(index_reg
, 0x30701);
770 WREG32(data_reg
, 0xBF2087A0);
771 WREG32(index_reg
, 0x30800);
772 WREG32(data_reg
, 0x8900BF00);
773 WREG32(index_reg
, 0x30801);
774 WREG32(data_reg
, 0xBF008900);
777 struct rv515_watermark
{
778 u32 lb_request_fifo_depth
;
779 fixed20_12 num_line_pair
;
780 fixed20_12 estimated_width
;
781 fixed20_12 worst_case_latency
;
782 fixed20_12 consumption_rate
;
783 fixed20_12 active_time
;
785 fixed20_12 priority_mark_max
;
786 fixed20_12 priority_mark
;
790 void rv515_crtc_bandwidth_compute(struct radeon_device
*rdev
,
791 struct radeon_crtc
*crtc
,
792 struct rv515_watermark
*wm
)
794 struct drm_display_mode
*mode
= &crtc
->base
.mode
;
796 fixed20_12 pclk
, request_fifo_depth
, tolerable_latency
, estimated_width
;
797 fixed20_12 consumption_time
, line_time
, chunk_time
, read_delay_latency
;
799 if (!crtc
->base
.enabled
) {
800 /* FIXME: wouldn't it better to set priority mark to maximum */
801 wm
->lb_request_fifo_depth
= 4;
805 if (crtc
->vsc
.full
> dfixed_const(2))
806 wm
->num_line_pair
.full
= dfixed_const(2);
808 wm
->num_line_pair
.full
= dfixed_const(1);
810 b
.full
= dfixed_const(mode
->crtc_hdisplay
);
811 c
.full
= dfixed_const(256);
812 a
.full
= dfixed_div(b
, c
);
813 request_fifo_depth
.full
= dfixed_mul(a
, wm
->num_line_pair
);
814 request_fifo_depth
.full
= dfixed_ceil(request_fifo_depth
);
815 if (a
.full
< dfixed_const(4)) {
816 wm
->lb_request_fifo_depth
= 4;
818 wm
->lb_request_fifo_depth
= dfixed_trunc(request_fifo_depth
);
821 /* Determine consumption rate
822 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
823 * vtaps = number of vertical taps,
824 * vsc = vertical scaling ratio, defined as source/destination
825 * hsc = horizontal scaling ration, defined as source/destination
827 a
.full
= dfixed_const(mode
->clock
);
828 b
.full
= dfixed_const(1000);
829 a
.full
= dfixed_div(a
, b
);
830 pclk
.full
= dfixed_div(b
, a
);
831 if (crtc
->rmx_type
!= RMX_OFF
) {
832 b
.full
= dfixed_const(2);
833 if (crtc
->vsc
.full
> b
.full
)
834 b
.full
= crtc
->vsc
.full
;
835 b
.full
= dfixed_mul(b
, crtc
->hsc
);
836 c
.full
= dfixed_const(2);
837 b
.full
= dfixed_div(b
, c
);
838 consumption_time
.full
= dfixed_div(pclk
, b
);
840 consumption_time
.full
= pclk
.full
;
842 a
.full
= dfixed_const(1);
843 wm
->consumption_rate
.full
= dfixed_div(a
, consumption_time
);
846 /* Determine line time
847 * LineTime = total time for one line of displayhtotal
848 * LineTime = total number of horizontal pixels
849 * pclk = pixel clock period(ns)
851 a
.full
= dfixed_const(crtc
->base
.mode
.crtc_htotal
);
852 line_time
.full
= dfixed_mul(a
, pclk
);
854 /* Determine active time
855 * ActiveTime = time of active region of display within one line,
856 * hactive = total number of horizontal active pixels
857 * htotal = total number of horizontal pixels
859 a
.full
= dfixed_const(crtc
->base
.mode
.crtc_htotal
);
860 b
.full
= dfixed_const(crtc
->base
.mode
.crtc_hdisplay
);
861 wm
->active_time
.full
= dfixed_mul(line_time
, b
);
862 wm
->active_time
.full
= dfixed_div(wm
->active_time
, a
);
864 /* Determine chunk time
865 * ChunkTime = the time it takes the DCP to send one chunk of data
866 * to the LB which consists of pipeline delay and inter chunk gap
867 * sclk = system clock(Mhz)
869 a
.full
= dfixed_const(600 * 1000);
870 chunk_time
.full
= dfixed_div(a
, rdev
->pm
.sclk
);
871 read_delay_latency
.full
= dfixed_const(1000);
873 /* Determine the worst case latency
874 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
875 * WorstCaseLatency = worst case time from urgent to when the MC starts
877 * READ_DELAY_IDLE_MAX = constant of 1us
878 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
879 * which consists of pipeline delay and inter chunk gap
881 if (dfixed_trunc(wm
->num_line_pair
) > 1) {
882 a
.full
= dfixed_const(3);
883 wm
->worst_case_latency
.full
= dfixed_mul(a
, chunk_time
);
884 wm
->worst_case_latency
.full
+= read_delay_latency
.full
;
886 wm
->worst_case_latency
.full
= chunk_time
.full
+ read_delay_latency
.full
;
889 /* Determine the tolerable latency
890 * TolerableLatency = Any given request has only 1 line time
891 * for the data to be returned
892 * LBRequestFifoDepth = Number of chunk requests the LB can
893 * put into the request FIFO for a display
894 * LineTime = total time for one line of display
895 * ChunkTime = the time it takes the DCP to send one chunk
896 * of data to the LB which consists of
897 * pipeline delay and inter chunk gap
899 if ((2+wm
->lb_request_fifo_depth
) >= dfixed_trunc(request_fifo_depth
)) {
900 tolerable_latency
.full
= line_time
.full
;
902 tolerable_latency
.full
= dfixed_const(wm
->lb_request_fifo_depth
- 2);
903 tolerable_latency
.full
= request_fifo_depth
.full
- tolerable_latency
.full
;
904 tolerable_latency
.full
= dfixed_mul(tolerable_latency
, chunk_time
);
905 tolerable_latency
.full
= line_time
.full
- tolerable_latency
.full
;
907 /* We assume worst case 32bits (4 bytes) */
908 wm
->dbpp
.full
= dfixed_const(2 * 16);
910 /* Determine the maximum priority mark
911 * width = viewport width in pixels
913 a
.full
= dfixed_const(16);
914 wm
->priority_mark_max
.full
= dfixed_const(crtc
->base
.mode
.crtc_hdisplay
);
915 wm
->priority_mark_max
.full
= dfixed_div(wm
->priority_mark_max
, a
);
916 wm
->priority_mark_max
.full
= dfixed_ceil(wm
->priority_mark_max
);
918 /* Determine estimated width */
919 estimated_width
.full
= tolerable_latency
.full
- wm
->worst_case_latency
.full
;
920 estimated_width
.full
= dfixed_div(estimated_width
, consumption_time
);
921 if (dfixed_trunc(estimated_width
) > crtc
->base
.mode
.crtc_hdisplay
) {
922 wm
->priority_mark
.full
= wm
->priority_mark_max
.full
;
924 a
.full
= dfixed_const(16);
925 wm
->priority_mark
.full
= dfixed_div(estimated_width
, a
);
926 wm
->priority_mark
.full
= dfixed_ceil(wm
->priority_mark
);
927 wm
->priority_mark
.full
= wm
->priority_mark_max
.full
- wm
->priority_mark
.full
;
931 void rv515_bandwidth_avivo_update(struct radeon_device
*rdev
)
933 struct drm_display_mode
*mode0
= NULL
;
934 struct drm_display_mode
*mode1
= NULL
;
935 struct rv515_watermark wm0
;
936 struct rv515_watermark wm1
;
938 u32 d1mode_priority_a_cnt
= MODE_PRIORITY_OFF
;
939 u32 d2mode_priority_a_cnt
= MODE_PRIORITY_OFF
;
940 fixed20_12 priority_mark02
, priority_mark12
, fill_rate
;
943 if (rdev
->mode_info
.crtcs
[0]->base
.enabled
)
944 mode0
= &rdev
->mode_info
.crtcs
[0]->base
.mode
;
945 if (rdev
->mode_info
.crtcs
[1]->base
.enabled
)
946 mode1
= &rdev
->mode_info
.crtcs
[1]->base
.mode
;
947 rs690_line_buffer_adjust(rdev
, mode0
, mode1
);
949 rv515_crtc_bandwidth_compute(rdev
, rdev
->mode_info
.crtcs
[0], &wm0
);
950 rv515_crtc_bandwidth_compute(rdev
, rdev
->mode_info
.crtcs
[1], &wm1
);
952 tmp
= wm0
.lb_request_fifo_depth
;
953 tmp
|= wm1
.lb_request_fifo_depth
<< 16;
954 WREG32(LB_MAX_REQ_OUTSTANDING
, tmp
);
956 if (mode0
&& mode1
) {
957 if (dfixed_trunc(wm0
.dbpp
) > 64)
958 a
.full
= dfixed_div(wm0
.dbpp
, wm0
.num_line_pair
);
960 a
.full
= wm0
.num_line_pair
.full
;
961 if (dfixed_trunc(wm1
.dbpp
) > 64)
962 b
.full
= dfixed_div(wm1
.dbpp
, wm1
.num_line_pair
);
964 b
.full
= wm1
.num_line_pair
.full
;
966 fill_rate
.full
= dfixed_div(wm0
.sclk
, a
);
967 if (wm0
.consumption_rate
.full
> fill_rate
.full
) {
968 b
.full
= wm0
.consumption_rate
.full
- fill_rate
.full
;
969 b
.full
= dfixed_mul(b
, wm0
.active_time
);
970 a
.full
= dfixed_const(16);
971 b
.full
= dfixed_div(b
, a
);
972 a
.full
= dfixed_mul(wm0
.worst_case_latency
,
973 wm0
.consumption_rate
);
974 priority_mark02
.full
= a
.full
+ b
.full
;
976 a
.full
= dfixed_mul(wm0
.worst_case_latency
,
977 wm0
.consumption_rate
);
978 b
.full
= dfixed_const(16 * 1000);
979 priority_mark02
.full
= dfixed_div(a
, b
);
981 if (wm1
.consumption_rate
.full
> fill_rate
.full
) {
982 b
.full
= wm1
.consumption_rate
.full
- fill_rate
.full
;
983 b
.full
= dfixed_mul(b
, wm1
.active_time
);
984 a
.full
= dfixed_const(16);
985 b
.full
= dfixed_div(b
, a
);
986 a
.full
= dfixed_mul(wm1
.worst_case_latency
,
987 wm1
.consumption_rate
);
988 priority_mark12
.full
= a
.full
+ b
.full
;
990 a
.full
= dfixed_mul(wm1
.worst_case_latency
,
991 wm1
.consumption_rate
);
992 b
.full
= dfixed_const(16 * 1000);
993 priority_mark12
.full
= dfixed_div(a
, b
);
995 if (wm0
.priority_mark
.full
> priority_mark02
.full
)
996 priority_mark02
.full
= wm0
.priority_mark
.full
;
997 if (dfixed_trunc(priority_mark02
) < 0)
998 priority_mark02
.full
= 0;
999 if (wm0
.priority_mark_max
.full
> priority_mark02
.full
)
1000 priority_mark02
.full
= wm0
.priority_mark_max
.full
;
1001 if (wm1
.priority_mark
.full
> priority_mark12
.full
)
1002 priority_mark12
.full
= wm1
.priority_mark
.full
;
1003 if (dfixed_trunc(priority_mark12
) < 0)
1004 priority_mark12
.full
= 0;
1005 if (wm1
.priority_mark_max
.full
> priority_mark12
.full
)
1006 priority_mark12
.full
= wm1
.priority_mark_max
.full
;
1007 d1mode_priority_a_cnt
= dfixed_trunc(priority_mark02
);
1008 d2mode_priority_a_cnt
= dfixed_trunc(priority_mark12
);
1009 if (rdev
->disp_priority
== 2) {
1010 d1mode_priority_a_cnt
|= MODE_PRIORITY_ALWAYS_ON
;
1011 d2mode_priority_a_cnt
|= MODE_PRIORITY_ALWAYS_ON
;
1014 if (dfixed_trunc(wm0
.dbpp
) > 64)
1015 a
.full
= dfixed_div(wm0
.dbpp
, wm0
.num_line_pair
);
1017 a
.full
= wm0
.num_line_pair
.full
;
1018 fill_rate
.full
= dfixed_div(wm0
.sclk
, a
);
1019 if (wm0
.consumption_rate
.full
> fill_rate
.full
) {
1020 b
.full
= wm0
.consumption_rate
.full
- fill_rate
.full
;
1021 b
.full
= dfixed_mul(b
, wm0
.active_time
);
1022 a
.full
= dfixed_const(16);
1023 b
.full
= dfixed_div(b
, a
);
1024 a
.full
= dfixed_mul(wm0
.worst_case_latency
,
1025 wm0
.consumption_rate
);
1026 priority_mark02
.full
= a
.full
+ b
.full
;
1028 a
.full
= dfixed_mul(wm0
.worst_case_latency
,
1029 wm0
.consumption_rate
);
1030 b
.full
= dfixed_const(16);
1031 priority_mark02
.full
= dfixed_div(a
, b
);
1033 if (wm0
.priority_mark
.full
> priority_mark02
.full
)
1034 priority_mark02
.full
= wm0
.priority_mark
.full
;
1035 if (dfixed_trunc(priority_mark02
) < 0)
1036 priority_mark02
.full
= 0;
1037 if (wm0
.priority_mark_max
.full
> priority_mark02
.full
)
1038 priority_mark02
.full
= wm0
.priority_mark_max
.full
;
1039 d1mode_priority_a_cnt
= dfixed_trunc(priority_mark02
);
1040 if (rdev
->disp_priority
== 2)
1041 d1mode_priority_a_cnt
|= MODE_PRIORITY_ALWAYS_ON
;
1043 if (dfixed_trunc(wm1
.dbpp
) > 64)
1044 a
.full
= dfixed_div(wm1
.dbpp
, wm1
.num_line_pair
);
1046 a
.full
= wm1
.num_line_pair
.full
;
1047 fill_rate
.full
= dfixed_div(wm1
.sclk
, a
);
1048 if (wm1
.consumption_rate
.full
> fill_rate
.full
) {
1049 b
.full
= wm1
.consumption_rate
.full
- fill_rate
.full
;
1050 b
.full
= dfixed_mul(b
, wm1
.active_time
);
1051 a
.full
= dfixed_const(16);
1052 b
.full
= dfixed_div(b
, a
);
1053 a
.full
= dfixed_mul(wm1
.worst_case_latency
,
1054 wm1
.consumption_rate
);
1055 priority_mark12
.full
= a
.full
+ b
.full
;
1057 a
.full
= dfixed_mul(wm1
.worst_case_latency
,
1058 wm1
.consumption_rate
);
1059 b
.full
= dfixed_const(16 * 1000);
1060 priority_mark12
.full
= dfixed_div(a
, b
);
1062 if (wm1
.priority_mark
.full
> priority_mark12
.full
)
1063 priority_mark12
.full
= wm1
.priority_mark
.full
;
1064 if (dfixed_trunc(priority_mark12
) < 0)
1065 priority_mark12
.full
= 0;
1066 if (wm1
.priority_mark_max
.full
> priority_mark12
.full
)
1067 priority_mark12
.full
= wm1
.priority_mark_max
.full
;
1068 d2mode_priority_a_cnt
= dfixed_trunc(priority_mark12
);
1069 if (rdev
->disp_priority
== 2)
1070 d2mode_priority_a_cnt
|= MODE_PRIORITY_ALWAYS_ON
;
1073 WREG32(D1MODE_PRIORITY_A_CNT
, d1mode_priority_a_cnt
);
1074 WREG32(D1MODE_PRIORITY_B_CNT
, d1mode_priority_a_cnt
);
1075 WREG32(D2MODE_PRIORITY_A_CNT
, d2mode_priority_a_cnt
);
1076 WREG32(D2MODE_PRIORITY_B_CNT
, d2mode_priority_a_cnt
);
1079 void rv515_bandwidth_update(struct radeon_device
*rdev
)
1082 struct drm_display_mode
*mode0
= NULL
;
1083 struct drm_display_mode
*mode1
= NULL
;
1085 radeon_update_display_priority(rdev
);
1087 if (rdev
->mode_info
.crtcs
[0]->base
.enabled
)
1088 mode0
= &rdev
->mode_info
.crtcs
[0]->base
.mode
;
1089 if (rdev
->mode_info
.crtcs
[1]->base
.enabled
)
1090 mode1
= &rdev
->mode_info
.crtcs
[1]->base
.mode
;
1092 * Set display0/1 priority up in the memory controller for
1093 * modes if the user specifies HIGH for displaypriority
1096 if ((rdev
->disp_priority
== 2) &&
1097 (rdev
->family
== CHIP_RV515
)) {
1098 tmp
= RREG32_MC(MC_MISC_LAT_TIMER
);
1099 tmp
&= ~MC_DISP1R_INIT_LAT_MASK
;
1100 tmp
&= ~MC_DISP0R_INIT_LAT_MASK
;
1102 tmp
|= (1 << MC_DISP1R_INIT_LAT_SHIFT
);
1104 tmp
|= (1 << MC_DISP0R_INIT_LAT_SHIFT
);
1105 WREG32_MC(MC_MISC_LAT_TIMER
, tmp
);
1107 rv515_bandwidth_avivo_update(rdev
);