2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/firmware.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
33 #include "radeon_asic.h"
34 #include "radeon_drm.h"
39 #define R700_PFP_UCODE_SIZE 848
40 #define R700_PM4_UCODE_SIZE 1360
42 static void rv770_gpu_init(struct radeon_device
*rdev
);
43 void rv770_fini(struct radeon_device
*rdev
);
49 int rv770_pcie_gart_enable(struct radeon_device
*rdev
)
54 if (rdev
->gart
.table
.vram
.robj
== NULL
) {
55 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
58 r
= radeon_gart_table_vram_pin(rdev
);
61 radeon_gart_restore(rdev
);
63 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
64 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
65 EFFECTIVE_L2_QUEUE_SIZE(7));
66 WREG32(VM_L2_CNTL2
, 0);
67 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
68 /* Setup TLB control */
69 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
70 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
71 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
72 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
73 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
74 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
75 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
76 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
77 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
78 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
79 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
80 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
81 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
82 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
83 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
84 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
85 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
86 (u32
)(rdev
->dummy_page
.addr
>> 12));
87 for (i
= 1; i
< 7; i
++)
88 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
90 r600_pcie_gart_tlb_flush(rdev
);
91 rdev
->gart
.ready
= true;
95 void rv770_pcie_gart_disable(struct radeon_device
*rdev
)
100 /* Disable all tables */
101 for (i
= 0; i
< 7; i
++)
102 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
105 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
106 EFFECTIVE_L2_QUEUE_SIZE(7));
107 WREG32(VM_L2_CNTL2
, 0);
108 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
109 /* Setup TLB control */
110 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
111 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
112 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
113 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
114 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
115 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
116 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
117 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
118 if (rdev
->gart
.table
.vram
.robj
) {
119 r
= radeon_bo_reserve(rdev
->gart
.table
.vram
.robj
, false);
120 if (likely(r
== 0)) {
121 radeon_bo_kunmap(rdev
->gart
.table
.vram
.robj
);
122 radeon_bo_unpin(rdev
->gart
.table
.vram
.robj
);
123 radeon_bo_unreserve(rdev
->gart
.table
.vram
.robj
);
128 void rv770_pcie_gart_fini(struct radeon_device
*rdev
)
130 radeon_gart_fini(rdev
);
131 rv770_pcie_gart_disable(rdev
);
132 radeon_gart_table_vram_free(rdev
);
136 void rv770_agp_enable(struct radeon_device
*rdev
)
142 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
143 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
144 EFFECTIVE_L2_QUEUE_SIZE(7));
145 WREG32(VM_L2_CNTL2
, 0);
146 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
147 /* Setup TLB control */
148 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
149 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
150 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
151 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
152 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
153 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
154 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
155 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
156 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
157 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
158 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
159 for (i
= 0; i
< 7; i
++)
160 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
163 static void rv770_mc_program(struct radeon_device
*rdev
)
165 struct rv515_mc_save save
;
170 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
171 WREG32((0x2c14 + j
), 0x00000000);
172 WREG32((0x2c18 + j
), 0x00000000);
173 WREG32((0x2c1c + j
), 0x00000000);
174 WREG32((0x2c20 + j
), 0x00000000);
175 WREG32((0x2c24 + j
), 0x00000000);
177 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL
, 0);
179 rv515_mc_stop(rdev
, &save
);
180 if (r600_mc_wait_for_idle(rdev
)) {
181 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
183 /* Lockout access through VGA aperture*/
184 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
185 /* Update configuration */
186 if (rdev
->flags
& RADEON_IS_AGP
) {
187 if (rdev
->mc
.vram_start
< rdev
->mc
.gtt_start
) {
188 /* VRAM before AGP */
189 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
190 rdev
->mc
.vram_start
>> 12);
191 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
192 rdev
->mc
.gtt_end
>> 12);
195 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
196 rdev
->mc
.gtt_start
>> 12);
197 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
198 rdev
->mc
.vram_end
>> 12);
201 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
202 rdev
->mc
.vram_start
>> 12);
203 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
204 rdev
->mc
.vram_end
>> 12);
206 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, 0);
207 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
208 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
209 WREG32(MC_VM_FB_LOCATION
, tmp
);
210 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
211 WREG32(HDP_NONSURFACE_INFO
, (2 << 7));
212 WREG32(HDP_NONSURFACE_SIZE
, (rdev
->mc
.mc_vram_size
- 1) | 0x3FF);
213 if (rdev
->flags
& RADEON_IS_AGP
) {
214 WREG32(MC_VM_AGP_TOP
, rdev
->mc
.gtt_end
>> 16);
215 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 16);
216 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
218 WREG32(MC_VM_AGP_BASE
, 0);
219 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
220 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
222 if (r600_mc_wait_for_idle(rdev
)) {
223 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
225 rv515_mc_resume(rdev
, &save
);
226 /* we need to own VRAM, so turn off the VGA renderer here
227 * to stop it overwriting our objects */
228 rv515_vga_render_disable(rdev
);
235 void r700_cp_stop(struct radeon_device
*rdev
)
237 WREG32(CP_ME_CNTL
, (CP_ME_HALT
| CP_PFP_HALT
));
240 static int rv770_cp_load_microcode(struct radeon_device
*rdev
)
242 const __be32
*fw_data
;
245 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
249 WREG32(CP_RB_CNTL
, RB_NO_UPDATE
| (15 << 8) | (3 << 0));
252 WREG32(GRBM_SOFT_RESET
, SOFT_RESET_CP
);
253 RREG32(GRBM_SOFT_RESET
);
255 WREG32(GRBM_SOFT_RESET
, 0);
257 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
258 WREG32(CP_PFP_UCODE_ADDR
, 0);
259 for (i
= 0; i
< R700_PFP_UCODE_SIZE
; i
++)
260 WREG32(CP_PFP_UCODE_DATA
, be32_to_cpup(fw_data
++));
261 WREG32(CP_PFP_UCODE_ADDR
, 0);
263 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
264 WREG32(CP_ME_RAM_WADDR
, 0);
265 for (i
= 0; i
< R700_PM4_UCODE_SIZE
; i
++)
266 WREG32(CP_ME_RAM_DATA
, be32_to_cpup(fw_data
++));
268 WREG32(CP_PFP_UCODE_ADDR
, 0);
269 WREG32(CP_ME_RAM_WADDR
, 0);
270 WREG32(CP_ME_RAM_RADDR
, 0);
274 void r700_cp_fini(struct radeon_device
*rdev
)
277 radeon_ring_fini(rdev
);
283 static u32
r700_get_tile_pipe_to_backend_map(struct radeon_device
*rdev
,
286 u32 backend_disable_mask
)
289 u32 enabled_backends_mask
;
290 u32 enabled_backends_count
;
292 u32 swizzle_pipe
[R7XX_MAX_PIPES
];
295 bool force_no_swizzle
;
297 if (num_tile_pipes
> R7XX_MAX_PIPES
)
298 num_tile_pipes
= R7XX_MAX_PIPES
;
299 if (num_tile_pipes
< 1)
301 if (num_backends
> R7XX_MAX_BACKENDS
)
302 num_backends
= R7XX_MAX_BACKENDS
;
303 if (num_backends
< 1)
306 enabled_backends_mask
= 0;
307 enabled_backends_count
= 0;
308 for (i
= 0; i
< R7XX_MAX_BACKENDS
; ++i
) {
309 if (((backend_disable_mask
>> i
) & 1) == 0) {
310 enabled_backends_mask
|= (1 << i
);
311 ++enabled_backends_count
;
313 if (enabled_backends_count
== num_backends
)
317 if (enabled_backends_count
== 0) {
318 enabled_backends_mask
= 1;
319 enabled_backends_count
= 1;
322 if (enabled_backends_count
!= num_backends
)
323 num_backends
= enabled_backends_count
;
325 switch (rdev
->family
) {
328 force_no_swizzle
= false;
333 force_no_swizzle
= true;
337 memset((uint8_t *)&swizzle_pipe
[0], 0, sizeof(u32
) * R7XX_MAX_PIPES
);
338 switch (num_tile_pipes
) {
347 if (force_no_swizzle
) {
358 if (force_no_swizzle
) {
371 if (force_no_swizzle
) {
386 if (force_no_swizzle
) {
403 if (force_no_swizzle
) {
422 if (force_no_swizzle
) {
445 for (cur_pipe
= 0; cur_pipe
< num_tile_pipes
; ++cur_pipe
) {
446 while (((1 << cur_backend
) & enabled_backends_mask
) == 0)
447 cur_backend
= (cur_backend
+ 1) % R7XX_MAX_BACKENDS
;
449 backend_map
|= (u32
)(((cur_backend
& 3) << (swizzle_pipe
[cur_pipe
] * 2)));
451 cur_backend
= (cur_backend
+ 1) % R7XX_MAX_BACKENDS
;
457 static void rv770_gpu_init(struct radeon_device
*rdev
)
459 int i
, j
, num_qd_pipes
;
464 u32 num_gs_verts_per_thread
;
466 u32 gs_prim_buffer_depth
= 0;
467 u32 sq_ms_fifo_sizes
;
469 u32 sq_thread_resource_mgmt
;
470 u32 hdp_host_path_cntl
;
471 u32 sq_dyn_gpr_size_simd_ab_0
;
473 u32 gb_tiling_config
= 0;
474 u32 cc_rb_backend_disable
= 0;
475 u32 cc_gc_shader_pipe_config
= 0;
479 /* setup chip specs */
480 switch (rdev
->family
) {
482 rdev
->config
.rv770
.max_pipes
= 4;
483 rdev
->config
.rv770
.max_tile_pipes
= 8;
484 rdev
->config
.rv770
.max_simds
= 10;
485 rdev
->config
.rv770
.max_backends
= 4;
486 rdev
->config
.rv770
.max_gprs
= 256;
487 rdev
->config
.rv770
.max_threads
= 248;
488 rdev
->config
.rv770
.max_stack_entries
= 512;
489 rdev
->config
.rv770
.max_hw_contexts
= 8;
490 rdev
->config
.rv770
.max_gs_threads
= 16 * 2;
491 rdev
->config
.rv770
.sx_max_export_size
= 128;
492 rdev
->config
.rv770
.sx_max_export_pos_size
= 16;
493 rdev
->config
.rv770
.sx_max_export_smx_size
= 112;
494 rdev
->config
.rv770
.sq_num_cf_insts
= 2;
496 rdev
->config
.rv770
.sx_num_of_sets
= 7;
497 rdev
->config
.rv770
.sc_prim_fifo_size
= 0xF9;
498 rdev
->config
.rv770
.sc_hiz_tile_fifo_size
= 0x30;
499 rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
= 0x130;
502 rdev
->config
.rv770
.max_pipes
= 2;
503 rdev
->config
.rv770
.max_tile_pipes
= 4;
504 rdev
->config
.rv770
.max_simds
= 8;
505 rdev
->config
.rv770
.max_backends
= 2;
506 rdev
->config
.rv770
.max_gprs
= 128;
507 rdev
->config
.rv770
.max_threads
= 248;
508 rdev
->config
.rv770
.max_stack_entries
= 256;
509 rdev
->config
.rv770
.max_hw_contexts
= 8;
510 rdev
->config
.rv770
.max_gs_threads
= 16 * 2;
511 rdev
->config
.rv770
.sx_max_export_size
= 256;
512 rdev
->config
.rv770
.sx_max_export_pos_size
= 32;
513 rdev
->config
.rv770
.sx_max_export_smx_size
= 224;
514 rdev
->config
.rv770
.sq_num_cf_insts
= 2;
516 rdev
->config
.rv770
.sx_num_of_sets
= 7;
517 rdev
->config
.rv770
.sc_prim_fifo_size
= 0xf9;
518 rdev
->config
.rv770
.sc_hiz_tile_fifo_size
= 0x30;
519 rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
= 0x130;
520 if (rdev
->config
.rv770
.sx_max_export_pos_size
> 16) {
521 rdev
->config
.rv770
.sx_max_export_pos_size
-= 16;
522 rdev
->config
.rv770
.sx_max_export_smx_size
+= 16;
526 rdev
->config
.rv770
.max_pipes
= 2;
527 rdev
->config
.rv770
.max_tile_pipes
= 2;
528 rdev
->config
.rv770
.max_simds
= 2;
529 rdev
->config
.rv770
.max_backends
= 1;
530 rdev
->config
.rv770
.max_gprs
= 256;
531 rdev
->config
.rv770
.max_threads
= 192;
532 rdev
->config
.rv770
.max_stack_entries
= 256;
533 rdev
->config
.rv770
.max_hw_contexts
= 4;
534 rdev
->config
.rv770
.max_gs_threads
= 8 * 2;
535 rdev
->config
.rv770
.sx_max_export_size
= 128;
536 rdev
->config
.rv770
.sx_max_export_pos_size
= 16;
537 rdev
->config
.rv770
.sx_max_export_smx_size
= 112;
538 rdev
->config
.rv770
.sq_num_cf_insts
= 1;
540 rdev
->config
.rv770
.sx_num_of_sets
= 7;
541 rdev
->config
.rv770
.sc_prim_fifo_size
= 0x40;
542 rdev
->config
.rv770
.sc_hiz_tile_fifo_size
= 0x30;
543 rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
= 0x130;
546 rdev
->config
.rv770
.max_pipes
= 4;
547 rdev
->config
.rv770
.max_tile_pipes
= 4;
548 rdev
->config
.rv770
.max_simds
= 8;
549 rdev
->config
.rv770
.max_backends
= 4;
550 rdev
->config
.rv770
.max_gprs
= 256;
551 rdev
->config
.rv770
.max_threads
= 248;
552 rdev
->config
.rv770
.max_stack_entries
= 512;
553 rdev
->config
.rv770
.max_hw_contexts
= 8;
554 rdev
->config
.rv770
.max_gs_threads
= 16 * 2;
555 rdev
->config
.rv770
.sx_max_export_size
= 256;
556 rdev
->config
.rv770
.sx_max_export_pos_size
= 32;
557 rdev
->config
.rv770
.sx_max_export_smx_size
= 224;
558 rdev
->config
.rv770
.sq_num_cf_insts
= 2;
560 rdev
->config
.rv770
.sx_num_of_sets
= 7;
561 rdev
->config
.rv770
.sc_prim_fifo_size
= 0x100;
562 rdev
->config
.rv770
.sc_hiz_tile_fifo_size
= 0x30;
563 rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
= 0x130;
565 if (rdev
->config
.rv770
.sx_max_export_pos_size
> 16) {
566 rdev
->config
.rv770
.sx_max_export_pos_size
-= 16;
567 rdev
->config
.rv770
.sx_max_export_smx_size
+= 16;
576 for (i
= 0; i
< 32; i
++) {
577 WREG32((0x2c14 + j
), 0x00000000);
578 WREG32((0x2c18 + j
), 0x00000000);
579 WREG32((0x2c1c + j
), 0x00000000);
580 WREG32((0x2c20 + j
), 0x00000000);
581 WREG32((0x2c24 + j
), 0x00000000);
585 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
587 /* setup tiling, simd, pipe config */
588 mc_arb_ramcfg
= RREG32(MC_ARB_RAMCFG
);
590 switch (rdev
->config
.rv770
.max_tile_pipes
) {
593 gb_tiling_config
|= PIPE_TILING(0);
596 gb_tiling_config
|= PIPE_TILING(1);
599 gb_tiling_config
|= PIPE_TILING(2);
602 gb_tiling_config
|= PIPE_TILING(3);
605 rdev
->config
.rv770
.tiling_npipes
= rdev
->config
.rv770
.max_tile_pipes
;
607 if (rdev
->family
== CHIP_RV770
)
608 gb_tiling_config
|= BANK_TILING(1);
610 gb_tiling_config
|= BANK_TILING((mc_arb_ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
);
611 rdev
->config
.rv770
.tiling_nbanks
= 4 << ((gb_tiling_config
>> 4) & 0x3);
613 gb_tiling_config
|= GROUP_SIZE(0);
614 rdev
->config
.rv770
.tiling_group_size
= 256;
616 if (((mc_arb_ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
) > 3) {
617 gb_tiling_config
|= ROW_TILING(3);
618 gb_tiling_config
|= SAMPLE_SPLIT(3);
621 ROW_TILING(((mc_arb_ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
));
623 SAMPLE_SPLIT(((mc_arb_ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
));
626 gb_tiling_config
|= BANK_SWAPS(1);
628 cc_rb_backend_disable
= RREG32(CC_RB_BACKEND_DISABLE
) & 0x00ff0000;
629 cc_rb_backend_disable
|=
630 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK
<< rdev
->config
.rv770
.max_backends
) & R7XX_MAX_BACKENDS_MASK
);
632 cc_gc_shader_pipe_config
= RREG32(CC_GC_SHADER_PIPE_CONFIG
) & 0xffffff00;
633 cc_gc_shader_pipe_config
|=
634 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK
<< rdev
->config
.rv770
.max_pipes
) & R7XX_MAX_PIPES_MASK
);
635 cc_gc_shader_pipe_config
|=
636 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK
<< rdev
->config
.rv770
.max_simds
) & R7XX_MAX_SIMDS_MASK
);
638 if (rdev
->family
== CHIP_RV740
)
641 backend_map
= r700_get_tile_pipe_to_backend_map(rdev
,
642 rdev
->config
.rv770
.max_tile_pipes
,
644 r600_count_pipe_bits((cc_rb_backend_disable
&
645 R7XX_MAX_BACKENDS_MASK
) >> 16)),
646 (cc_rb_backend_disable
>> 16));
647 gb_tiling_config
|= BACKEND_MAP(backend_map
);
650 WREG32(GB_TILING_CONFIG
, gb_tiling_config
);
651 WREG32(DCP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
652 WREG32(HDP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
654 WREG32(CC_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
655 WREG32(CC_GC_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
656 WREG32(GC_USER_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
657 WREG32(CC_SYS_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
659 WREG32(CGTS_SYS_TCC_DISABLE
, 0);
660 WREG32(CGTS_TCC_DISABLE
, 0);
661 WREG32(CGTS_USER_SYS_TCC_DISABLE
, 0);
662 WREG32(CGTS_USER_TCC_DISABLE
, 0);
665 R7XX_MAX_PIPES
- r600_count_pipe_bits((cc_gc_shader_pipe_config
& INACTIVE_QD_PIPES_MASK
) >> 8);
666 WREG32(VGT_OUT_DEALLOC_CNTL
, (num_qd_pipes
* 4) & DEALLOC_DIST_MASK
);
667 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, ((num_qd_pipes
* 4) - 2) & VTX_REUSE_DEPTH_MASK
);
669 /* set HW defaults for 3D engine */
670 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) |
671 ROQ_IB2_START(0x2b)));
673 WREG32(CP_MEQ_THRESHOLDS
, STQ_SPLIT(0x30));
675 ta_aux_cntl
= RREG32(TA_CNTL_AUX
);
676 WREG32(TA_CNTL_AUX
, ta_aux_cntl
| DISABLE_CUBE_ANISO
);
678 sx_debug_1
= RREG32(SX_DEBUG_1
);
679 sx_debug_1
|= ENABLE_NEW_SMX_ADDRESS
;
680 WREG32(SX_DEBUG_1
, sx_debug_1
);
682 smx_dc_ctl0
= RREG32(SMX_DC_CTL0
);
683 smx_dc_ctl0
&= ~CACHE_DEPTH(0x1ff);
684 smx_dc_ctl0
|= CACHE_DEPTH((rdev
->config
.rv770
.sx_num_of_sets
* 64) - 1);
685 WREG32(SMX_DC_CTL0
, smx_dc_ctl0
);
687 if (rdev
->family
!= CHIP_RV740
)
688 WREG32(SMX_EVENT_CTL
, (ES_FLUSH_CTL(4) |
693 db_debug3
= RREG32(DB_DEBUG3
);
694 db_debug3
&= ~DB_CLK_OFF_DELAY(0x1f);
695 switch (rdev
->family
) {
698 db_debug3
|= DB_CLK_OFF_DELAY(0x1f);
703 db_debug3
|= DB_CLK_OFF_DELAY(2);
706 WREG32(DB_DEBUG3
, db_debug3
);
708 if (rdev
->family
!= CHIP_RV770
) {
709 db_debug4
= RREG32(DB_DEBUG4
);
710 db_debug4
|= DISABLE_TILE_COVERED_FOR_PS_ITER
;
711 WREG32(DB_DEBUG4
, db_debug4
);
714 WREG32(SX_EXPORT_BUFFER_SIZES
, (COLOR_BUFFER_SIZE((rdev
->config
.rv770
.sx_max_export_size
/ 4) - 1) |
715 POSITION_BUFFER_SIZE((rdev
->config
.rv770
.sx_max_export_pos_size
/ 4) - 1) |
716 SMX_BUFFER_SIZE((rdev
->config
.rv770
.sx_max_export_smx_size
/ 4) - 1)));
718 WREG32(PA_SC_FIFO_SIZE
, (SC_PRIM_FIFO_SIZE(rdev
->config
.rv770
.sc_prim_fifo_size
) |
719 SC_HIZ_TILE_FIFO_SIZE(rdev
->config
.rv770
.sc_hiz_tile_fifo_size
) |
720 SC_EARLYZ_TILE_FIFO_SIZE(rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
)));
722 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
724 WREG32(VGT_NUM_INSTANCES
, 1);
726 WREG32(SPI_CONFIG_CNTL
, GPR_WRITE_PRIORITY(0));
728 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(4));
730 WREG32(CP_PERFMON_CNTL
, 0);
732 sq_ms_fifo_sizes
= (CACHE_FIFO_SIZE(16 * rdev
->config
.rv770
.sq_num_cf_insts
) |
733 DONE_FIFO_HIWATER(0xe0) |
734 ALU_UPDATE_FIFO_HIWATER(0x8));
735 switch (rdev
->family
) {
739 sq_ms_fifo_sizes
|= FETCH_FIFO_HIWATER(0x1);
743 sq_ms_fifo_sizes
|= FETCH_FIFO_HIWATER(0x4);
746 WREG32(SQ_MS_FIFO_SIZES
, sq_ms_fifo_sizes
);
748 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
749 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
751 sq_config
= RREG32(SQ_CONFIG
);
752 sq_config
&= ~(PS_PRIO(3) |
756 sq_config
|= (DX9_CONSTS
|
763 if (rdev
->family
== CHIP_RV710
)
764 /* no vertex cache */
765 sq_config
&= ~VC_ENABLE
;
767 WREG32(SQ_CONFIG
, sq_config
);
769 WREG32(SQ_GPR_RESOURCE_MGMT_1
, (NUM_PS_GPRS((rdev
->config
.rv770
.max_gprs
* 24)/64) |
770 NUM_VS_GPRS((rdev
->config
.rv770
.max_gprs
* 24)/64) |
771 NUM_CLAUSE_TEMP_GPRS(((rdev
->config
.rv770
.max_gprs
* 24)/64)/2)));
773 WREG32(SQ_GPR_RESOURCE_MGMT_2
, (NUM_GS_GPRS((rdev
->config
.rv770
.max_gprs
* 7)/64) |
774 NUM_ES_GPRS((rdev
->config
.rv770
.max_gprs
* 7)/64)));
776 sq_thread_resource_mgmt
= (NUM_PS_THREADS((rdev
->config
.rv770
.max_threads
* 4)/8) |
777 NUM_VS_THREADS((rdev
->config
.rv770
.max_threads
* 2)/8) |
778 NUM_ES_THREADS((rdev
->config
.rv770
.max_threads
* 1)/8));
779 if (((rdev
->config
.rv770
.max_threads
* 1) / 8) > rdev
->config
.rv770
.max_gs_threads
)
780 sq_thread_resource_mgmt
|= NUM_GS_THREADS(rdev
->config
.rv770
.max_gs_threads
);
782 sq_thread_resource_mgmt
|= NUM_GS_THREADS((rdev
->config
.rv770
.max_gs_threads
* 1)/8);
783 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
785 WREG32(SQ_STACK_RESOURCE_MGMT_1
, (NUM_PS_STACK_ENTRIES((rdev
->config
.rv770
.max_stack_entries
* 1)/4) |
786 NUM_VS_STACK_ENTRIES((rdev
->config
.rv770
.max_stack_entries
* 1)/4)));
788 WREG32(SQ_STACK_RESOURCE_MGMT_2
, (NUM_GS_STACK_ENTRIES((rdev
->config
.rv770
.max_stack_entries
* 1)/4) |
789 NUM_ES_STACK_ENTRIES((rdev
->config
.rv770
.max_stack_entries
* 1)/4)));
791 sq_dyn_gpr_size_simd_ab_0
= (SIMDA_RING0((rdev
->config
.rv770
.max_gprs
* 38)/64) |
792 SIMDA_RING1((rdev
->config
.rv770
.max_gprs
* 38)/64) |
793 SIMDB_RING0((rdev
->config
.rv770
.max_gprs
* 38)/64) |
794 SIMDB_RING1((rdev
->config
.rv770
.max_gprs
* 38)/64));
796 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0
, sq_dyn_gpr_size_simd_ab_0
);
797 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1
, sq_dyn_gpr_size_simd_ab_0
);
798 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2
, sq_dyn_gpr_size_simd_ab_0
);
799 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3
, sq_dyn_gpr_size_simd_ab_0
);
800 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4
, sq_dyn_gpr_size_simd_ab_0
);
801 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5
, sq_dyn_gpr_size_simd_ab_0
);
802 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6
, sq_dyn_gpr_size_simd_ab_0
);
803 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7
, sq_dyn_gpr_size_simd_ab_0
);
805 WREG32(PA_SC_FORCE_EOV_MAX_CNTS
, (FORCE_EOV_MAX_CLK_CNT(4095) |
806 FORCE_EOV_MAX_REZ_CNT(255)));
808 if (rdev
->family
== CHIP_RV710
)
809 WREG32(VGT_CACHE_INVALIDATION
, (CACHE_INVALIDATION(TC_ONLY
) |
810 AUTO_INVLD_EN(ES_AND_GS_AUTO
)));
812 WREG32(VGT_CACHE_INVALIDATION
, (CACHE_INVALIDATION(VC_AND_TC
) |
813 AUTO_INVLD_EN(ES_AND_GS_AUTO
)));
815 switch (rdev
->family
) {
819 gs_prim_buffer_depth
= 384;
822 gs_prim_buffer_depth
= 128;
828 num_gs_verts_per_thread
= rdev
->config
.rv770
.max_pipes
* 16;
829 vgt_gs_per_es
= gs_prim_buffer_depth
+ num_gs_verts_per_thread
;
830 /* Max value for this is 256 */
831 if (vgt_gs_per_es
> 256)
834 WREG32(VGT_ES_PER_GS
, 128);
835 WREG32(VGT_GS_PER_ES
, vgt_gs_per_es
);
836 WREG32(VGT_GS_PER_VS
, 2);
838 /* more default values. 2D/3D driver should adjust as needed */
839 WREG32(VGT_GS_VERTEX_REUSE
, 16);
840 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
841 WREG32(VGT_STRMOUT_EN
, 0);
843 WREG32(PA_SC_MODE_CNTL
, 0);
844 WREG32(PA_SC_EDGERULE
, 0xaaaaaaaa);
845 WREG32(PA_SC_AA_CONFIG
, 0);
846 WREG32(PA_SC_CLIPRECT_RULE
, 0xffff);
847 WREG32(PA_SC_LINE_STIPPLE
, 0);
848 WREG32(SPI_INPUT_Z
, 0);
849 WREG32(SPI_PS_IN_CONTROL_0
, NUM_INTERP(2));
850 WREG32(CB_COLOR7_FRAG
, 0);
852 /* clear render buffer base addresses */
853 WREG32(CB_COLOR0_BASE
, 0);
854 WREG32(CB_COLOR1_BASE
, 0);
855 WREG32(CB_COLOR2_BASE
, 0);
856 WREG32(CB_COLOR3_BASE
, 0);
857 WREG32(CB_COLOR4_BASE
, 0);
858 WREG32(CB_COLOR5_BASE
, 0);
859 WREG32(CB_COLOR6_BASE
, 0);
860 WREG32(CB_COLOR7_BASE
, 0);
864 hdp_host_path_cntl
= RREG32(HDP_HOST_PATH_CNTL
);
865 WREG32(HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
867 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
869 WREG32(PA_CL_ENHANCE
, (CLIP_VTX_REORDER_ENA
|
874 int rv770_mc_init(struct radeon_device
*rdev
)
877 int chansize
, numchan
;
879 /* Get VRAM informations */
880 rdev
->mc
.vram_is_ddr
= true;
881 tmp
= RREG32(MC_ARB_RAMCFG
);
882 if (tmp
& CHANSIZE_OVERRIDE
) {
884 } else if (tmp
& CHANSIZE_MASK
) {
889 tmp
= RREG32(MC_SHARED_CHMAP
);
890 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
905 rdev
->mc
.vram_width
= numchan
* chansize
;
906 /* Could aper size report 0 ? */
907 rdev
->mc
.aper_base
= drm_get_resource_start(rdev
->ddev
, 0);
908 rdev
->mc
.aper_size
= drm_get_resource_len(rdev
->ddev
, 0);
909 /* Setup GPU memory space */
910 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
);
911 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
);
912 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
913 r600_vram_gtt_location(rdev
, &rdev
->mc
);
914 radeon_update_bandwidth_info(rdev
);
919 static int rv770_startup(struct radeon_device
*rdev
)
923 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
924 r
= r600_init_microcode(rdev
);
926 DRM_ERROR("Failed to load firmware!\n");
931 rv770_mc_program(rdev
);
932 if (rdev
->flags
& RADEON_IS_AGP
) {
933 rv770_agp_enable(rdev
);
935 r
= rv770_pcie_gart_enable(rdev
);
939 rv770_gpu_init(rdev
);
940 r
= r600_blit_init(rdev
);
942 r600_blit_fini(rdev
);
943 rdev
->asic
->copy
= NULL
;
944 dev_warn(rdev
->dev
, "failed blitter (%d) falling back to memcpy\n", r
);
946 /* pin copy shader into vram */
947 if (rdev
->r600_blit
.shader_obj
) {
948 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
949 if (unlikely(r
!= 0))
951 r
= radeon_bo_pin(rdev
->r600_blit
.shader_obj
, RADEON_GEM_DOMAIN_VRAM
,
952 &rdev
->r600_blit
.shader_gpu_addr
);
953 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
955 DRM_ERROR("failed to pin blit object %d\n", r
);
960 r
= r600_irq_init(rdev
);
962 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
963 radeon_irq_kms_fini(rdev
);
968 r
= radeon_ring_init(rdev
, rdev
->cp
.ring_size
);
971 r
= rv770_cp_load_microcode(rdev
);
974 r
= r600_cp_resume(rdev
);
977 /* write back buffer are not vital so don't worry about failure */
978 r600_wb_enable(rdev
);
982 int rv770_resume(struct radeon_device
*rdev
)
986 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
987 * posting will perform necessary task to bring back GPU into good
991 atom_asic_init(rdev
->mode_info
.atom_context
);
992 /* Initialize clocks */
993 r
= radeon_clocks_init(rdev
);
998 r
= rv770_startup(rdev
);
1000 DRM_ERROR("r600 startup failed on resume\n");
1004 r
= r600_ib_test(rdev
);
1006 DRM_ERROR("radeon: failled testing IB (%d).\n", r
);
1010 r
= r600_audio_init(rdev
);
1012 dev_err(rdev
->dev
, "radeon: audio init failed\n");
1020 int rv770_suspend(struct radeon_device
*rdev
)
1024 r600_audio_fini(rdev
);
1025 /* FIXME: we should wait for ring to be empty */
1027 rdev
->cp
.ready
= false;
1028 r600_irq_suspend(rdev
);
1029 r600_wb_disable(rdev
);
1030 rv770_pcie_gart_disable(rdev
);
1031 /* unpin shaders bo */
1032 if (rdev
->r600_blit
.shader_obj
) {
1033 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
1034 if (likely(r
== 0)) {
1035 radeon_bo_unpin(rdev
->r600_blit
.shader_obj
);
1036 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
1042 /* Plan is to move initialization in that function and use
1043 * helper function so that radeon_device_init pretty much
1044 * do nothing more than calling asic specific function. This
1045 * should also allow to remove a bunch of callback function
1048 int rv770_init(struct radeon_device
*rdev
)
1052 r
= radeon_dummy_page_init(rdev
);
1055 /* This don't do much */
1056 r
= radeon_gem_init(rdev
);
1060 if (!radeon_get_bios(rdev
)) {
1061 if (ASIC_IS_AVIVO(rdev
))
1064 /* Must be an ATOMBIOS */
1065 if (!rdev
->is_atom_bios
) {
1066 dev_err(rdev
->dev
, "Expecting atombios for R600 GPU\n");
1069 r
= radeon_atombios_init(rdev
);
1072 /* Post card if necessary */
1073 if (!r600_card_posted(rdev
)) {
1075 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
1078 DRM_INFO("GPU not posted. posting now...\n");
1079 atom_asic_init(rdev
->mode_info
.atom_context
);
1081 /* Initialize scratch registers */
1082 r600_scratch_init(rdev
);
1083 /* Initialize surface registers */
1084 radeon_surface_init(rdev
);
1085 /* Initialize clocks */
1086 radeon_get_clock_info(rdev
->ddev
);
1087 r
= radeon_clocks_init(rdev
);
1090 /* Initialize power management */
1091 radeon_pm_init(rdev
);
1093 r
= radeon_fence_driver_init(rdev
);
1096 /* initialize AGP */
1097 if (rdev
->flags
& RADEON_IS_AGP
) {
1098 r
= radeon_agp_init(rdev
);
1100 radeon_agp_disable(rdev
);
1102 r
= rv770_mc_init(rdev
);
1105 /* Memory manager */
1106 r
= radeon_bo_init(rdev
);
1110 r
= radeon_irq_kms_init(rdev
);
1114 rdev
->cp
.ring_obj
= NULL
;
1115 r600_ring_init(rdev
, 1024 * 1024);
1117 rdev
->ih
.ring_obj
= NULL
;
1118 r600_ih_ring_init(rdev
, 64 * 1024);
1120 r
= r600_pcie_gart_init(rdev
);
1124 rdev
->accel_working
= true;
1125 r
= rv770_startup(rdev
);
1127 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
1130 r600_irq_fini(rdev
);
1131 radeon_irq_kms_fini(rdev
);
1132 rv770_pcie_gart_fini(rdev
);
1133 rdev
->accel_working
= false;
1135 if (rdev
->accel_working
) {
1136 r
= radeon_ib_pool_init(rdev
);
1138 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
1139 rdev
->accel_working
= false;
1141 r
= r600_ib_test(rdev
);
1143 dev_err(rdev
->dev
, "IB test failed (%d).\n", r
);
1144 rdev
->accel_working
= false;
1149 r
= r600_audio_init(rdev
);
1151 dev_err(rdev
->dev
, "radeon: audio init failed\n");
1158 void rv770_fini(struct radeon_device
*rdev
)
1160 radeon_pm_fini(rdev
);
1161 r600_blit_fini(rdev
);
1164 r600_irq_fini(rdev
);
1165 radeon_irq_kms_fini(rdev
);
1166 rv770_pcie_gart_fini(rdev
);
1167 radeon_gem_fini(rdev
);
1168 radeon_fence_driver_fini(rdev
);
1169 radeon_clocks_fini(rdev
);
1170 radeon_agp_fini(rdev
);
1171 radeon_bo_fini(rdev
);
1172 radeon_atombios_fini(rdev
);
1175 radeon_dummy_page_fini(rdev
);