2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/firmware.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
33 #include "radeon_asic.h"
34 #include "radeon_drm.h"
39 #define R700_PFP_UCODE_SIZE 848
40 #define R700_PM4_UCODE_SIZE 1360
42 static void rv770_gpu_init(struct radeon_device
*rdev
);
43 void rv770_fini(struct radeon_device
*rdev
);
45 /* get temperature in millidegrees */
46 u32
rv770_get_temp(struct radeon_device
*rdev
)
48 u32 temp
= (RREG32(CG_MULT_THERMAL_STATUS
) & ASIC_T_MASK
) >>
55 actual_temp
= (temp
>> 1) & 0xff;
57 return actual_temp
* 1000;
60 void rv770_pm_misc(struct radeon_device
*rdev
)
62 int req_ps_idx
= rdev
->pm
.requested_power_state_index
;
63 int req_cm_idx
= rdev
->pm
.requested_clock_mode_index
;
64 struct radeon_power_state
*ps
= &rdev
->pm
.power_state
[req_ps_idx
];
65 struct radeon_voltage
*voltage
= &ps
->clock_info
[req_cm_idx
].voltage
;
67 if ((voltage
->type
== VOLTAGE_SW
) && voltage
->voltage
) {
68 if (voltage
->voltage
!= rdev
->pm
.current_vddc
) {
69 radeon_atom_set_voltage(rdev
, voltage
->voltage
);
70 rdev
->pm
.current_vddc
= voltage
->voltage
;
71 DRM_DEBUG("Setting: v: %d\n", voltage
->voltage
);
79 int rv770_pcie_gart_enable(struct radeon_device
*rdev
)
84 if (rdev
->gart
.table
.vram
.robj
== NULL
) {
85 dev_err(rdev
->dev
, "No VRAM object for PCIE GART.\n");
88 r
= radeon_gart_table_vram_pin(rdev
);
91 radeon_gart_restore(rdev
);
93 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
94 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
95 EFFECTIVE_L2_QUEUE_SIZE(7));
96 WREG32(VM_L2_CNTL2
, 0);
97 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
98 /* Setup TLB control */
99 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
100 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
101 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
102 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
103 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
104 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
105 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
106 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
107 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
108 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
109 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
110 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR
, rdev
->mc
.gtt_start
>> 12);
111 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR
, rdev
->mc
.gtt_end
>> 12);
112 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, rdev
->gart
.table_addr
>> 12);
113 WREG32(VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
| PAGE_TABLE_DEPTH(0) |
114 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
);
115 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
116 (u32
)(rdev
->dummy_page
.addr
>> 12));
117 for (i
= 1; i
< 7; i
++)
118 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
120 r600_pcie_gart_tlb_flush(rdev
);
121 rdev
->gart
.ready
= true;
125 void rv770_pcie_gart_disable(struct radeon_device
*rdev
)
130 /* Disable all tables */
131 for (i
= 0; i
< 7; i
++)
132 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
135 WREG32(VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
|
136 EFFECTIVE_L2_QUEUE_SIZE(7));
137 WREG32(VM_L2_CNTL2
, 0);
138 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
139 /* Setup TLB control */
140 tmp
= EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
141 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
142 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
143 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
144 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
145 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
146 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
147 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
148 if (rdev
->gart
.table
.vram
.robj
) {
149 r
= radeon_bo_reserve(rdev
->gart
.table
.vram
.robj
, false);
150 if (likely(r
== 0)) {
151 radeon_bo_kunmap(rdev
->gart
.table
.vram
.robj
);
152 radeon_bo_unpin(rdev
->gart
.table
.vram
.robj
);
153 radeon_bo_unreserve(rdev
->gart
.table
.vram
.robj
);
158 void rv770_pcie_gart_fini(struct radeon_device
*rdev
)
160 radeon_gart_fini(rdev
);
161 rv770_pcie_gart_disable(rdev
);
162 radeon_gart_table_vram_free(rdev
);
166 void rv770_agp_enable(struct radeon_device
*rdev
)
172 WREG32(VM_L2_CNTL
, ENABLE_L2_CACHE
| ENABLE_L2_FRAGMENT_PROCESSING
|
173 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
|
174 EFFECTIVE_L2_QUEUE_SIZE(7));
175 WREG32(VM_L2_CNTL2
, 0);
176 WREG32(VM_L2_CNTL3
, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
177 /* Setup TLB control */
178 tmp
= ENABLE_L1_TLB
| ENABLE_L1_FRAGMENT_PROCESSING
|
179 SYSTEM_ACCESS_MODE_NOT_IN_SYS
|
180 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU
|
181 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
182 WREG32(MC_VM_MD_L1_TLB0_CNTL
, tmp
);
183 WREG32(MC_VM_MD_L1_TLB1_CNTL
, tmp
);
184 WREG32(MC_VM_MD_L1_TLB2_CNTL
, tmp
);
185 WREG32(MC_VM_MB_L1_TLB0_CNTL
, tmp
);
186 WREG32(MC_VM_MB_L1_TLB1_CNTL
, tmp
);
187 WREG32(MC_VM_MB_L1_TLB2_CNTL
, tmp
);
188 WREG32(MC_VM_MB_L1_TLB3_CNTL
, tmp
);
189 for (i
= 0; i
< 7; i
++)
190 WREG32(VM_CONTEXT0_CNTL
+ (i
* 4), 0);
193 static void rv770_mc_program(struct radeon_device
*rdev
)
195 struct rv515_mc_save save
;
200 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x18) {
201 WREG32((0x2c14 + j
), 0x00000000);
202 WREG32((0x2c18 + j
), 0x00000000);
203 WREG32((0x2c1c + j
), 0x00000000);
204 WREG32((0x2c20 + j
), 0x00000000);
205 WREG32((0x2c24 + j
), 0x00000000);
207 /* r7xx hw bug. Read from HDP_DEBUG1 rather
208 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
210 tmp
= RREG32(HDP_DEBUG1
);
212 rv515_mc_stop(rdev
, &save
);
213 if (r600_mc_wait_for_idle(rdev
)) {
214 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
216 /* Lockout access through VGA aperture*/
217 WREG32(VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
);
218 /* Update configuration */
219 if (rdev
->flags
& RADEON_IS_AGP
) {
220 if (rdev
->mc
.vram_start
< rdev
->mc
.gtt_start
) {
221 /* VRAM before AGP */
222 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
223 rdev
->mc
.vram_start
>> 12);
224 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
225 rdev
->mc
.gtt_end
>> 12);
228 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
229 rdev
->mc
.gtt_start
>> 12);
230 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
231 rdev
->mc
.vram_end
>> 12);
234 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR
,
235 rdev
->mc
.vram_start
>> 12);
236 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
237 rdev
->mc
.vram_end
>> 12);
239 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
, 0);
240 tmp
= ((rdev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
241 tmp
|= ((rdev
->mc
.vram_start
>> 24) & 0xFFFF);
242 WREG32(MC_VM_FB_LOCATION
, tmp
);
243 WREG32(HDP_NONSURFACE_BASE
, (rdev
->mc
.vram_start
>> 8));
244 WREG32(HDP_NONSURFACE_INFO
, (2 << 7));
245 WREG32(HDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
246 if (rdev
->flags
& RADEON_IS_AGP
) {
247 WREG32(MC_VM_AGP_TOP
, rdev
->mc
.gtt_end
>> 16);
248 WREG32(MC_VM_AGP_BOT
, rdev
->mc
.gtt_start
>> 16);
249 WREG32(MC_VM_AGP_BASE
, rdev
->mc
.agp_base
>> 22);
251 WREG32(MC_VM_AGP_BASE
, 0);
252 WREG32(MC_VM_AGP_TOP
, 0x0FFFFFFF);
253 WREG32(MC_VM_AGP_BOT
, 0x0FFFFFFF);
255 if (r600_mc_wait_for_idle(rdev
)) {
256 dev_warn(rdev
->dev
, "Wait for MC idle timedout !\n");
258 rv515_mc_resume(rdev
, &save
);
259 /* we need to own VRAM, so turn off the VGA renderer here
260 * to stop it overwriting our objects */
261 rv515_vga_render_disable(rdev
);
268 void r700_cp_stop(struct radeon_device
*rdev
)
270 WREG32(CP_ME_CNTL
, (CP_ME_HALT
| CP_PFP_HALT
));
273 static int rv770_cp_load_microcode(struct radeon_device
*rdev
)
275 const __be32
*fw_data
;
278 if (!rdev
->me_fw
|| !rdev
->pfp_fw
)
282 WREG32(CP_RB_CNTL
, RB_NO_UPDATE
| (15 << 8) | (3 << 0));
285 WREG32(GRBM_SOFT_RESET
, SOFT_RESET_CP
);
286 RREG32(GRBM_SOFT_RESET
);
288 WREG32(GRBM_SOFT_RESET
, 0);
290 fw_data
= (const __be32
*)rdev
->pfp_fw
->data
;
291 WREG32(CP_PFP_UCODE_ADDR
, 0);
292 for (i
= 0; i
< R700_PFP_UCODE_SIZE
; i
++)
293 WREG32(CP_PFP_UCODE_DATA
, be32_to_cpup(fw_data
++));
294 WREG32(CP_PFP_UCODE_ADDR
, 0);
296 fw_data
= (const __be32
*)rdev
->me_fw
->data
;
297 WREG32(CP_ME_RAM_WADDR
, 0);
298 for (i
= 0; i
< R700_PM4_UCODE_SIZE
; i
++)
299 WREG32(CP_ME_RAM_DATA
, be32_to_cpup(fw_data
++));
301 WREG32(CP_PFP_UCODE_ADDR
, 0);
302 WREG32(CP_ME_RAM_WADDR
, 0);
303 WREG32(CP_ME_RAM_RADDR
, 0);
307 void r700_cp_fini(struct radeon_device
*rdev
)
310 radeon_ring_fini(rdev
);
316 static u32
r700_get_tile_pipe_to_backend_map(struct radeon_device
*rdev
,
319 u32 backend_disable_mask
)
322 u32 enabled_backends_mask
;
323 u32 enabled_backends_count
;
325 u32 swizzle_pipe
[R7XX_MAX_PIPES
];
328 bool force_no_swizzle
;
330 if (num_tile_pipes
> R7XX_MAX_PIPES
)
331 num_tile_pipes
= R7XX_MAX_PIPES
;
332 if (num_tile_pipes
< 1)
334 if (num_backends
> R7XX_MAX_BACKENDS
)
335 num_backends
= R7XX_MAX_BACKENDS
;
336 if (num_backends
< 1)
339 enabled_backends_mask
= 0;
340 enabled_backends_count
= 0;
341 for (i
= 0; i
< R7XX_MAX_BACKENDS
; ++i
) {
342 if (((backend_disable_mask
>> i
) & 1) == 0) {
343 enabled_backends_mask
|= (1 << i
);
344 ++enabled_backends_count
;
346 if (enabled_backends_count
== num_backends
)
350 if (enabled_backends_count
== 0) {
351 enabled_backends_mask
= 1;
352 enabled_backends_count
= 1;
355 if (enabled_backends_count
!= num_backends
)
356 num_backends
= enabled_backends_count
;
358 switch (rdev
->family
) {
361 force_no_swizzle
= false;
366 force_no_swizzle
= true;
370 memset((uint8_t *)&swizzle_pipe
[0], 0, sizeof(u32
) * R7XX_MAX_PIPES
);
371 switch (num_tile_pipes
) {
380 if (force_no_swizzle
) {
391 if (force_no_swizzle
) {
404 if (force_no_swizzle
) {
419 if (force_no_swizzle
) {
436 if (force_no_swizzle
) {
455 if (force_no_swizzle
) {
478 for (cur_pipe
= 0; cur_pipe
< num_tile_pipes
; ++cur_pipe
) {
479 while (((1 << cur_backend
) & enabled_backends_mask
) == 0)
480 cur_backend
= (cur_backend
+ 1) % R7XX_MAX_BACKENDS
;
482 backend_map
|= (u32
)(((cur_backend
& 3) << (swizzle_pipe
[cur_pipe
] * 2)));
484 cur_backend
= (cur_backend
+ 1) % R7XX_MAX_BACKENDS
;
490 static void rv770_gpu_init(struct radeon_device
*rdev
)
492 int i
, j
, num_qd_pipes
;
497 u32 num_gs_verts_per_thread
;
499 u32 gs_prim_buffer_depth
= 0;
500 u32 sq_ms_fifo_sizes
;
502 u32 sq_thread_resource_mgmt
;
503 u32 hdp_host_path_cntl
;
504 u32 sq_dyn_gpr_size_simd_ab_0
;
506 u32 gb_tiling_config
= 0;
507 u32 cc_rb_backend_disable
= 0;
508 u32 cc_gc_shader_pipe_config
= 0;
512 /* setup chip specs */
513 switch (rdev
->family
) {
515 rdev
->config
.rv770
.max_pipes
= 4;
516 rdev
->config
.rv770
.max_tile_pipes
= 8;
517 rdev
->config
.rv770
.max_simds
= 10;
518 rdev
->config
.rv770
.max_backends
= 4;
519 rdev
->config
.rv770
.max_gprs
= 256;
520 rdev
->config
.rv770
.max_threads
= 248;
521 rdev
->config
.rv770
.max_stack_entries
= 512;
522 rdev
->config
.rv770
.max_hw_contexts
= 8;
523 rdev
->config
.rv770
.max_gs_threads
= 16 * 2;
524 rdev
->config
.rv770
.sx_max_export_size
= 128;
525 rdev
->config
.rv770
.sx_max_export_pos_size
= 16;
526 rdev
->config
.rv770
.sx_max_export_smx_size
= 112;
527 rdev
->config
.rv770
.sq_num_cf_insts
= 2;
529 rdev
->config
.rv770
.sx_num_of_sets
= 7;
530 rdev
->config
.rv770
.sc_prim_fifo_size
= 0xF9;
531 rdev
->config
.rv770
.sc_hiz_tile_fifo_size
= 0x30;
532 rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
= 0x130;
535 rdev
->config
.rv770
.max_pipes
= 2;
536 rdev
->config
.rv770
.max_tile_pipes
= 4;
537 rdev
->config
.rv770
.max_simds
= 8;
538 rdev
->config
.rv770
.max_backends
= 2;
539 rdev
->config
.rv770
.max_gprs
= 128;
540 rdev
->config
.rv770
.max_threads
= 248;
541 rdev
->config
.rv770
.max_stack_entries
= 256;
542 rdev
->config
.rv770
.max_hw_contexts
= 8;
543 rdev
->config
.rv770
.max_gs_threads
= 16 * 2;
544 rdev
->config
.rv770
.sx_max_export_size
= 256;
545 rdev
->config
.rv770
.sx_max_export_pos_size
= 32;
546 rdev
->config
.rv770
.sx_max_export_smx_size
= 224;
547 rdev
->config
.rv770
.sq_num_cf_insts
= 2;
549 rdev
->config
.rv770
.sx_num_of_sets
= 7;
550 rdev
->config
.rv770
.sc_prim_fifo_size
= 0xf9;
551 rdev
->config
.rv770
.sc_hiz_tile_fifo_size
= 0x30;
552 rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
= 0x130;
553 if (rdev
->config
.rv770
.sx_max_export_pos_size
> 16) {
554 rdev
->config
.rv770
.sx_max_export_pos_size
-= 16;
555 rdev
->config
.rv770
.sx_max_export_smx_size
+= 16;
559 rdev
->config
.rv770
.max_pipes
= 2;
560 rdev
->config
.rv770
.max_tile_pipes
= 2;
561 rdev
->config
.rv770
.max_simds
= 2;
562 rdev
->config
.rv770
.max_backends
= 1;
563 rdev
->config
.rv770
.max_gprs
= 256;
564 rdev
->config
.rv770
.max_threads
= 192;
565 rdev
->config
.rv770
.max_stack_entries
= 256;
566 rdev
->config
.rv770
.max_hw_contexts
= 4;
567 rdev
->config
.rv770
.max_gs_threads
= 8 * 2;
568 rdev
->config
.rv770
.sx_max_export_size
= 128;
569 rdev
->config
.rv770
.sx_max_export_pos_size
= 16;
570 rdev
->config
.rv770
.sx_max_export_smx_size
= 112;
571 rdev
->config
.rv770
.sq_num_cf_insts
= 1;
573 rdev
->config
.rv770
.sx_num_of_sets
= 7;
574 rdev
->config
.rv770
.sc_prim_fifo_size
= 0x40;
575 rdev
->config
.rv770
.sc_hiz_tile_fifo_size
= 0x30;
576 rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
= 0x130;
579 rdev
->config
.rv770
.max_pipes
= 4;
580 rdev
->config
.rv770
.max_tile_pipes
= 4;
581 rdev
->config
.rv770
.max_simds
= 8;
582 rdev
->config
.rv770
.max_backends
= 4;
583 rdev
->config
.rv770
.max_gprs
= 256;
584 rdev
->config
.rv770
.max_threads
= 248;
585 rdev
->config
.rv770
.max_stack_entries
= 512;
586 rdev
->config
.rv770
.max_hw_contexts
= 8;
587 rdev
->config
.rv770
.max_gs_threads
= 16 * 2;
588 rdev
->config
.rv770
.sx_max_export_size
= 256;
589 rdev
->config
.rv770
.sx_max_export_pos_size
= 32;
590 rdev
->config
.rv770
.sx_max_export_smx_size
= 224;
591 rdev
->config
.rv770
.sq_num_cf_insts
= 2;
593 rdev
->config
.rv770
.sx_num_of_sets
= 7;
594 rdev
->config
.rv770
.sc_prim_fifo_size
= 0x100;
595 rdev
->config
.rv770
.sc_hiz_tile_fifo_size
= 0x30;
596 rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
= 0x130;
598 if (rdev
->config
.rv770
.sx_max_export_pos_size
> 16) {
599 rdev
->config
.rv770
.sx_max_export_pos_size
-= 16;
600 rdev
->config
.rv770
.sx_max_export_smx_size
+= 16;
609 for (i
= 0; i
< 32; i
++) {
610 WREG32((0x2c14 + j
), 0x00000000);
611 WREG32((0x2c18 + j
), 0x00000000);
612 WREG32((0x2c1c + j
), 0x00000000);
613 WREG32((0x2c20 + j
), 0x00000000);
614 WREG32((0x2c24 + j
), 0x00000000);
618 WREG32(GRBM_CNTL
, GRBM_READ_TIMEOUT(0xff));
620 /* setup tiling, simd, pipe config */
621 mc_arb_ramcfg
= RREG32(MC_ARB_RAMCFG
);
623 switch (rdev
->config
.rv770
.max_tile_pipes
) {
626 gb_tiling_config
|= PIPE_TILING(0);
629 gb_tiling_config
|= PIPE_TILING(1);
632 gb_tiling_config
|= PIPE_TILING(2);
635 gb_tiling_config
|= PIPE_TILING(3);
638 rdev
->config
.rv770
.tiling_npipes
= rdev
->config
.rv770
.max_tile_pipes
;
640 if (rdev
->family
== CHIP_RV770
)
641 gb_tiling_config
|= BANK_TILING(1);
643 gb_tiling_config
|= BANK_TILING((mc_arb_ramcfg
& NOOFBANK_MASK
) >> NOOFBANK_SHIFT
);
644 rdev
->config
.rv770
.tiling_nbanks
= 4 << ((gb_tiling_config
>> 4) & 0x3);
646 gb_tiling_config
|= GROUP_SIZE(0);
647 rdev
->config
.rv770
.tiling_group_size
= 256;
649 if (((mc_arb_ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
) > 3) {
650 gb_tiling_config
|= ROW_TILING(3);
651 gb_tiling_config
|= SAMPLE_SPLIT(3);
654 ROW_TILING(((mc_arb_ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
));
656 SAMPLE_SPLIT(((mc_arb_ramcfg
& NOOFROWS_MASK
) >> NOOFROWS_SHIFT
));
659 gb_tiling_config
|= BANK_SWAPS(1);
661 cc_rb_backend_disable
= RREG32(CC_RB_BACKEND_DISABLE
) & 0x00ff0000;
662 cc_rb_backend_disable
|=
663 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK
<< rdev
->config
.rv770
.max_backends
) & R7XX_MAX_BACKENDS_MASK
);
665 cc_gc_shader_pipe_config
= RREG32(CC_GC_SHADER_PIPE_CONFIG
) & 0xffffff00;
666 cc_gc_shader_pipe_config
|=
667 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK
<< rdev
->config
.rv770
.max_pipes
) & R7XX_MAX_PIPES_MASK
);
668 cc_gc_shader_pipe_config
|=
669 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK
<< rdev
->config
.rv770
.max_simds
) & R7XX_MAX_SIMDS_MASK
);
671 if (rdev
->family
== CHIP_RV740
)
674 backend_map
= r700_get_tile_pipe_to_backend_map(rdev
,
675 rdev
->config
.rv770
.max_tile_pipes
,
677 r600_count_pipe_bits((cc_rb_backend_disable
&
678 R7XX_MAX_BACKENDS_MASK
) >> 16)),
679 (cc_rb_backend_disable
>> 16));
681 rdev
->config
.rv770
.tile_config
= gb_tiling_config
;
682 gb_tiling_config
|= BACKEND_MAP(backend_map
);
684 WREG32(GB_TILING_CONFIG
, gb_tiling_config
);
685 WREG32(DCP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
686 WREG32(HDP_TILING_CONFIG
, (gb_tiling_config
& 0xffff));
688 WREG32(CC_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
689 WREG32(CC_GC_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
690 WREG32(GC_USER_SHADER_PIPE_CONFIG
, cc_gc_shader_pipe_config
);
691 WREG32(CC_SYS_RB_BACKEND_DISABLE
, cc_rb_backend_disable
);
693 WREG32(CGTS_SYS_TCC_DISABLE
, 0);
694 WREG32(CGTS_TCC_DISABLE
, 0);
695 WREG32(CGTS_USER_SYS_TCC_DISABLE
, 0);
696 WREG32(CGTS_USER_TCC_DISABLE
, 0);
699 R7XX_MAX_PIPES
- r600_count_pipe_bits((cc_gc_shader_pipe_config
& INACTIVE_QD_PIPES_MASK
) >> 8);
700 WREG32(VGT_OUT_DEALLOC_CNTL
, (num_qd_pipes
* 4) & DEALLOC_DIST_MASK
);
701 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL
, ((num_qd_pipes
* 4) - 2) & VTX_REUSE_DEPTH_MASK
);
703 /* set HW defaults for 3D engine */
704 WREG32(CP_QUEUE_THRESHOLDS
, (ROQ_IB1_START(0x16) |
705 ROQ_IB2_START(0x2b)));
707 WREG32(CP_MEQ_THRESHOLDS
, STQ_SPLIT(0x30));
709 ta_aux_cntl
= RREG32(TA_CNTL_AUX
);
710 WREG32(TA_CNTL_AUX
, ta_aux_cntl
| DISABLE_CUBE_ANISO
);
712 sx_debug_1
= RREG32(SX_DEBUG_1
);
713 sx_debug_1
|= ENABLE_NEW_SMX_ADDRESS
;
714 WREG32(SX_DEBUG_1
, sx_debug_1
);
716 smx_dc_ctl0
= RREG32(SMX_DC_CTL0
);
717 smx_dc_ctl0
&= ~CACHE_DEPTH(0x1ff);
718 smx_dc_ctl0
|= CACHE_DEPTH((rdev
->config
.rv770
.sx_num_of_sets
* 64) - 1);
719 WREG32(SMX_DC_CTL0
, smx_dc_ctl0
);
721 if (rdev
->family
!= CHIP_RV740
)
722 WREG32(SMX_EVENT_CTL
, (ES_FLUSH_CTL(4) |
727 db_debug3
= RREG32(DB_DEBUG3
);
728 db_debug3
&= ~DB_CLK_OFF_DELAY(0x1f);
729 switch (rdev
->family
) {
732 db_debug3
|= DB_CLK_OFF_DELAY(0x1f);
737 db_debug3
|= DB_CLK_OFF_DELAY(2);
740 WREG32(DB_DEBUG3
, db_debug3
);
742 if (rdev
->family
!= CHIP_RV770
) {
743 db_debug4
= RREG32(DB_DEBUG4
);
744 db_debug4
|= DISABLE_TILE_COVERED_FOR_PS_ITER
;
745 WREG32(DB_DEBUG4
, db_debug4
);
748 WREG32(SX_EXPORT_BUFFER_SIZES
, (COLOR_BUFFER_SIZE((rdev
->config
.rv770
.sx_max_export_size
/ 4) - 1) |
749 POSITION_BUFFER_SIZE((rdev
->config
.rv770
.sx_max_export_pos_size
/ 4) - 1) |
750 SMX_BUFFER_SIZE((rdev
->config
.rv770
.sx_max_export_smx_size
/ 4) - 1)));
752 WREG32(PA_SC_FIFO_SIZE
, (SC_PRIM_FIFO_SIZE(rdev
->config
.rv770
.sc_prim_fifo_size
) |
753 SC_HIZ_TILE_FIFO_SIZE(rdev
->config
.rv770
.sc_hiz_tile_fifo_size
) |
754 SC_EARLYZ_TILE_FIFO_SIZE(rdev
->config
.rv770
.sc_earlyz_tile_fifo_fize
)));
756 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
758 WREG32(VGT_NUM_INSTANCES
, 1);
760 WREG32(SPI_CONFIG_CNTL
, GPR_WRITE_PRIORITY(0));
762 WREG32(SPI_CONFIG_CNTL_1
, VTX_DONE_DELAY(4));
764 WREG32(CP_PERFMON_CNTL
, 0);
766 sq_ms_fifo_sizes
= (CACHE_FIFO_SIZE(16 * rdev
->config
.rv770
.sq_num_cf_insts
) |
767 DONE_FIFO_HIWATER(0xe0) |
768 ALU_UPDATE_FIFO_HIWATER(0x8));
769 switch (rdev
->family
) {
773 sq_ms_fifo_sizes
|= FETCH_FIFO_HIWATER(0x1);
777 sq_ms_fifo_sizes
|= FETCH_FIFO_HIWATER(0x4);
780 WREG32(SQ_MS_FIFO_SIZES
, sq_ms_fifo_sizes
);
782 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
783 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
785 sq_config
= RREG32(SQ_CONFIG
);
786 sq_config
&= ~(PS_PRIO(3) |
790 sq_config
|= (DX9_CONSTS
|
797 if (rdev
->family
== CHIP_RV710
)
798 /* no vertex cache */
799 sq_config
&= ~VC_ENABLE
;
801 WREG32(SQ_CONFIG
, sq_config
);
803 WREG32(SQ_GPR_RESOURCE_MGMT_1
, (NUM_PS_GPRS((rdev
->config
.rv770
.max_gprs
* 24)/64) |
804 NUM_VS_GPRS((rdev
->config
.rv770
.max_gprs
* 24)/64) |
805 NUM_CLAUSE_TEMP_GPRS(((rdev
->config
.rv770
.max_gprs
* 24)/64)/2)));
807 WREG32(SQ_GPR_RESOURCE_MGMT_2
, (NUM_GS_GPRS((rdev
->config
.rv770
.max_gprs
* 7)/64) |
808 NUM_ES_GPRS((rdev
->config
.rv770
.max_gprs
* 7)/64)));
810 sq_thread_resource_mgmt
= (NUM_PS_THREADS((rdev
->config
.rv770
.max_threads
* 4)/8) |
811 NUM_VS_THREADS((rdev
->config
.rv770
.max_threads
* 2)/8) |
812 NUM_ES_THREADS((rdev
->config
.rv770
.max_threads
* 1)/8));
813 if (((rdev
->config
.rv770
.max_threads
* 1) / 8) > rdev
->config
.rv770
.max_gs_threads
)
814 sq_thread_resource_mgmt
|= NUM_GS_THREADS(rdev
->config
.rv770
.max_gs_threads
);
816 sq_thread_resource_mgmt
|= NUM_GS_THREADS((rdev
->config
.rv770
.max_gs_threads
* 1)/8);
817 WREG32(SQ_THREAD_RESOURCE_MGMT
, sq_thread_resource_mgmt
);
819 WREG32(SQ_STACK_RESOURCE_MGMT_1
, (NUM_PS_STACK_ENTRIES((rdev
->config
.rv770
.max_stack_entries
* 1)/4) |
820 NUM_VS_STACK_ENTRIES((rdev
->config
.rv770
.max_stack_entries
* 1)/4)));
822 WREG32(SQ_STACK_RESOURCE_MGMT_2
, (NUM_GS_STACK_ENTRIES((rdev
->config
.rv770
.max_stack_entries
* 1)/4) |
823 NUM_ES_STACK_ENTRIES((rdev
->config
.rv770
.max_stack_entries
* 1)/4)));
825 sq_dyn_gpr_size_simd_ab_0
= (SIMDA_RING0((rdev
->config
.rv770
.max_gprs
* 38)/64) |
826 SIMDA_RING1((rdev
->config
.rv770
.max_gprs
* 38)/64) |
827 SIMDB_RING0((rdev
->config
.rv770
.max_gprs
* 38)/64) |
828 SIMDB_RING1((rdev
->config
.rv770
.max_gprs
* 38)/64));
830 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0
, sq_dyn_gpr_size_simd_ab_0
);
831 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1
, sq_dyn_gpr_size_simd_ab_0
);
832 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2
, sq_dyn_gpr_size_simd_ab_0
);
833 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3
, sq_dyn_gpr_size_simd_ab_0
);
834 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4
, sq_dyn_gpr_size_simd_ab_0
);
835 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5
, sq_dyn_gpr_size_simd_ab_0
);
836 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6
, sq_dyn_gpr_size_simd_ab_0
);
837 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7
, sq_dyn_gpr_size_simd_ab_0
);
839 WREG32(PA_SC_FORCE_EOV_MAX_CNTS
, (FORCE_EOV_MAX_CLK_CNT(4095) |
840 FORCE_EOV_MAX_REZ_CNT(255)));
842 if (rdev
->family
== CHIP_RV710
)
843 WREG32(VGT_CACHE_INVALIDATION
, (CACHE_INVALIDATION(TC_ONLY
) |
844 AUTO_INVLD_EN(ES_AND_GS_AUTO
)));
846 WREG32(VGT_CACHE_INVALIDATION
, (CACHE_INVALIDATION(VC_AND_TC
) |
847 AUTO_INVLD_EN(ES_AND_GS_AUTO
)));
849 switch (rdev
->family
) {
853 gs_prim_buffer_depth
= 384;
856 gs_prim_buffer_depth
= 128;
862 num_gs_verts_per_thread
= rdev
->config
.rv770
.max_pipes
* 16;
863 vgt_gs_per_es
= gs_prim_buffer_depth
+ num_gs_verts_per_thread
;
864 /* Max value for this is 256 */
865 if (vgt_gs_per_es
> 256)
868 WREG32(VGT_ES_PER_GS
, 128);
869 WREG32(VGT_GS_PER_ES
, vgt_gs_per_es
);
870 WREG32(VGT_GS_PER_VS
, 2);
872 /* more default values. 2D/3D driver should adjust as needed */
873 WREG32(VGT_GS_VERTEX_REUSE
, 16);
874 WREG32(PA_SC_LINE_STIPPLE_STATE
, 0);
875 WREG32(VGT_STRMOUT_EN
, 0);
877 WREG32(PA_SC_MODE_CNTL
, 0);
878 WREG32(PA_SC_EDGERULE
, 0xaaaaaaaa);
879 WREG32(PA_SC_AA_CONFIG
, 0);
880 WREG32(PA_SC_CLIPRECT_RULE
, 0xffff);
881 WREG32(PA_SC_LINE_STIPPLE
, 0);
882 WREG32(SPI_INPUT_Z
, 0);
883 WREG32(SPI_PS_IN_CONTROL_0
, NUM_INTERP(2));
884 WREG32(CB_COLOR7_FRAG
, 0);
886 /* clear render buffer base addresses */
887 WREG32(CB_COLOR0_BASE
, 0);
888 WREG32(CB_COLOR1_BASE
, 0);
889 WREG32(CB_COLOR2_BASE
, 0);
890 WREG32(CB_COLOR3_BASE
, 0);
891 WREG32(CB_COLOR4_BASE
, 0);
892 WREG32(CB_COLOR5_BASE
, 0);
893 WREG32(CB_COLOR6_BASE
, 0);
894 WREG32(CB_COLOR7_BASE
, 0);
898 hdp_host_path_cntl
= RREG32(HDP_HOST_PATH_CNTL
);
899 WREG32(HDP_HOST_PATH_CNTL
, hdp_host_path_cntl
);
901 WREG32(PA_SC_MULTI_CHIP_CNTL
, 0);
903 WREG32(PA_CL_ENHANCE
, (CLIP_VTX_REORDER_ENA
|
908 static int rv770_vram_scratch_init(struct radeon_device
*rdev
)
913 if (rdev
->vram_scratch
.robj
== NULL
) {
914 r
= radeon_bo_create(rdev
, NULL
, RADEON_GPU_PAGE_SIZE
,
915 true, RADEON_GEM_DOMAIN_VRAM
,
916 &rdev
->vram_scratch
.robj
);
922 r
= radeon_bo_reserve(rdev
->vram_scratch
.robj
, false);
923 if (unlikely(r
!= 0))
925 r
= radeon_bo_pin(rdev
->vram_scratch
.robj
,
926 RADEON_GEM_DOMAIN_VRAM
, &gpu_addr
);
928 radeon_bo_unreserve(rdev
->vram_scratch
.robj
);
931 r
= radeon_bo_kmap(rdev
->vram_scratch
.robj
,
932 (void **)&rdev
->vram_scratch
.ptr
);
934 radeon_bo_unpin(rdev
->vram_scratch
.robj
);
935 radeon_bo_unreserve(rdev
->vram_scratch
.robj
);
940 static void rv770_vram_scratch_fini(struct radeon_device
*rdev
)
944 if (rdev
->vram_scratch
.robj
== NULL
) {
947 r
= radeon_bo_reserve(rdev
->vram_scratch
.robj
, false);
948 if (likely(r
== 0)) {
949 radeon_bo_kunmap(rdev
->vram_scratch
.robj
);
950 radeon_bo_unpin(rdev
->vram_scratch
.robj
);
951 radeon_bo_unreserve(rdev
->vram_scratch
.robj
);
953 radeon_bo_unref(&rdev
->vram_scratch
.robj
);
956 int rv770_mc_init(struct radeon_device
*rdev
)
959 int chansize
, numchan
;
961 /* Get VRAM informations */
962 rdev
->mc
.vram_is_ddr
= true;
963 tmp
= RREG32(MC_ARB_RAMCFG
);
964 if (tmp
& CHANSIZE_OVERRIDE
) {
966 } else if (tmp
& CHANSIZE_MASK
) {
971 tmp
= RREG32(MC_SHARED_CHMAP
);
972 switch ((tmp
& NOOFCHAN_MASK
) >> NOOFCHAN_SHIFT
) {
987 rdev
->mc
.vram_width
= numchan
* chansize
;
988 /* Could aper size report 0 ? */
989 rdev
->mc
.aper_base
= pci_resource_start(rdev
->pdev
, 0);
990 rdev
->mc
.aper_size
= pci_resource_len(rdev
->pdev
, 0);
991 /* Setup GPU memory space */
992 rdev
->mc
.mc_vram_size
= RREG32(CONFIG_MEMSIZE
);
993 rdev
->mc
.real_vram_size
= RREG32(CONFIG_MEMSIZE
);
994 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
995 r600_vram_gtt_location(rdev
, &rdev
->mc
);
996 radeon_update_bandwidth_info(rdev
);
1001 static int rv770_startup(struct radeon_device
*rdev
)
1005 if (!rdev
->me_fw
|| !rdev
->pfp_fw
|| !rdev
->rlc_fw
) {
1006 r
= r600_init_microcode(rdev
);
1008 DRM_ERROR("Failed to load firmware!\n");
1013 rv770_mc_program(rdev
);
1014 if (rdev
->flags
& RADEON_IS_AGP
) {
1015 rv770_agp_enable(rdev
);
1017 r
= rv770_pcie_gart_enable(rdev
);
1021 r
= rv770_vram_scratch_init(rdev
);
1024 rv770_gpu_init(rdev
);
1025 r
= r600_blit_init(rdev
);
1027 r600_blit_fini(rdev
);
1028 rdev
->asic
->copy
= NULL
;
1029 dev_warn(rdev
->dev
, "failed blitter (%d) falling back to memcpy\n", r
);
1031 /* pin copy shader into vram */
1032 if (rdev
->r600_blit
.shader_obj
) {
1033 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
1034 if (unlikely(r
!= 0))
1036 r
= radeon_bo_pin(rdev
->r600_blit
.shader_obj
, RADEON_GEM_DOMAIN_VRAM
,
1037 &rdev
->r600_blit
.shader_gpu_addr
);
1038 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
1040 DRM_ERROR("failed to pin blit object %d\n", r
);
1045 r
= r600_irq_init(rdev
);
1047 DRM_ERROR("radeon: IH init failed (%d).\n", r
);
1048 radeon_irq_kms_fini(rdev
);
1053 r
= radeon_ring_init(rdev
, rdev
->cp
.ring_size
);
1056 r
= rv770_cp_load_microcode(rdev
);
1059 r
= r600_cp_resume(rdev
);
1062 /* write back buffer are not vital so don't worry about failure */
1063 r600_wb_enable(rdev
);
1067 int rv770_resume(struct radeon_device
*rdev
)
1071 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1072 * posting will perform necessary task to bring back GPU into good
1076 atom_asic_init(rdev
->mode_info
.atom_context
);
1077 /* Initialize clocks */
1078 r
= radeon_clocks_init(rdev
);
1083 r
= rv770_startup(rdev
);
1085 DRM_ERROR("r600 startup failed on resume\n");
1089 r
= r600_ib_test(rdev
);
1091 DRM_ERROR("radeon: failled testing IB (%d).\n", r
);
1095 r
= r600_audio_init(rdev
);
1097 dev_err(rdev
->dev
, "radeon: audio init failed\n");
1105 int rv770_suspend(struct radeon_device
*rdev
)
1109 r600_audio_fini(rdev
);
1110 /* FIXME: we should wait for ring to be empty */
1112 rdev
->cp
.ready
= false;
1113 r600_irq_suspend(rdev
);
1114 r600_wb_disable(rdev
);
1115 rv770_pcie_gart_disable(rdev
);
1116 /* unpin shaders bo */
1117 if (rdev
->r600_blit
.shader_obj
) {
1118 r
= radeon_bo_reserve(rdev
->r600_blit
.shader_obj
, false);
1119 if (likely(r
== 0)) {
1120 radeon_bo_unpin(rdev
->r600_blit
.shader_obj
);
1121 radeon_bo_unreserve(rdev
->r600_blit
.shader_obj
);
1127 /* Plan is to move initialization in that function and use
1128 * helper function so that radeon_device_init pretty much
1129 * do nothing more than calling asic specific function. This
1130 * should also allow to remove a bunch of callback function
1133 int rv770_init(struct radeon_device
*rdev
)
1137 r
= radeon_dummy_page_init(rdev
);
1140 /* This don't do much */
1141 r
= radeon_gem_init(rdev
);
1145 if (!radeon_get_bios(rdev
)) {
1146 if (ASIC_IS_AVIVO(rdev
))
1149 /* Must be an ATOMBIOS */
1150 if (!rdev
->is_atom_bios
) {
1151 dev_err(rdev
->dev
, "Expecting atombios for R600 GPU\n");
1154 r
= radeon_atombios_init(rdev
);
1157 /* Post card if necessary */
1158 if (!r600_card_posted(rdev
)) {
1160 dev_err(rdev
->dev
, "Card not posted and no BIOS - ignoring\n");
1163 DRM_INFO("GPU not posted. posting now...\n");
1164 atom_asic_init(rdev
->mode_info
.atom_context
);
1166 /* Initialize scratch registers */
1167 r600_scratch_init(rdev
);
1168 /* Initialize surface registers */
1169 radeon_surface_init(rdev
);
1170 /* Initialize clocks */
1171 radeon_get_clock_info(rdev
->ddev
);
1172 r
= radeon_clocks_init(rdev
);
1176 r
= radeon_fence_driver_init(rdev
);
1179 /* initialize AGP */
1180 if (rdev
->flags
& RADEON_IS_AGP
) {
1181 r
= radeon_agp_init(rdev
);
1183 radeon_agp_disable(rdev
);
1185 r
= rv770_mc_init(rdev
);
1188 /* Memory manager */
1189 r
= radeon_bo_init(rdev
);
1193 r
= radeon_irq_kms_init(rdev
);
1197 rdev
->cp
.ring_obj
= NULL
;
1198 r600_ring_init(rdev
, 1024 * 1024);
1200 rdev
->ih
.ring_obj
= NULL
;
1201 r600_ih_ring_init(rdev
, 64 * 1024);
1203 r
= r600_pcie_gart_init(rdev
);
1207 rdev
->accel_working
= true;
1208 r
= rv770_startup(rdev
);
1210 dev_err(rdev
->dev
, "disabling GPU acceleration\n");
1213 r600_irq_fini(rdev
);
1214 radeon_irq_kms_fini(rdev
);
1215 rv770_pcie_gart_fini(rdev
);
1216 rdev
->accel_working
= false;
1218 if (rdev
->accel_working
) {
1219 r
= radeon_ib_pool_init(rdev
);
1221 dev_err(rdev
->dev
, "IB initialization failed (%d).\n", r
);
1222 rdev
->accel_working
= false;
1224 r
= r600_ib_test(rdev
);
1226 dev_err(rdev
->dev
, "IB test failed (%d).\n", r
);
1227 rdev
->accel_working
= false;
1232 r
= r600_audio_init(rdev
);
1234 dev_err(rdev
->dev
, "radeon: audio init failed\n");
1241 void rv770_fini(struct radeon_device
*rdev
)
1243 r600_blit_fini(rdev
);
1246 r600_irq_fini(rdev
);
1247 radeon_irq_kms_fini(rdev
);
1248 rv770_pcie_gart_fini(rdev
);
1249 rv770_vram_scratch_fini(rdev
);
1250 radeon_gem_fini(rdev
);
1251 radeon_fence_driver_fini(rdev
);
1252 radeon_clocks_fini(rdev
);
1253 radeon_agp_fini(rdev
);
1254 radeon_bo_fini(rdev
);
1255 radeon_atombios_fini(rdev
);
1258 radeon_dummy_page_fini(rdev
);