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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / radeon / si.c
1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
27 #include <drm/drmP.h>
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include "radeon_audio.h"
31 #include <drm/radeon_drm.h>
32 #include "sid.h"
33 #include "atom.h"
34 #include "si_blit_shaders.h"
35 #include "clearstate_si.h"
36 #include "radeon_ucode.h"
37
38
39 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
40 MODULE_FIRMWARE("radeon/TAHITI_me.bin");
41 MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
42 MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
43 MODULE_FIRMWARE("radeon/TAHITI_mc2.bin");
44 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
45 MODULE_FIRMWARE("radeon/TAHITI_smc.bin");
46
47 MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
48 MODULE_FIRMWARE("radeon/tahiti_me.bin");
49 MODULE_FIRMWARE("radeon/tahiti_ce.bin");
50 MODULE_FIRMWARE("radeon/tahiti_mc.bin");
51 MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
52 MODULE_FIRMWARE("radeon/tahiti_smc.bin");
53
54 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
55 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
56 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
57 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
58 MODULE_FIRMWARE("radeon/PITCAIRN_mc2.bin");
59 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
60 MODULE_FIRMWARE("radeon/PITCAIRN_smc.bin");
61
62 MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
63 MODULE_FIRMWARE("radeon/pitcairn_me.bin");
64 MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
65 MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
66 MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
67 MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
68 MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
69
70 MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
71 MODULE_FIRMWARE("radeon/VERDE_me.bin");
72 MODULE_FIRMWARE("radeon/VERDE_ce.bin");
73 MODULE_FIRMWARE("radeon/VERDE_mc.bin");
74 MODULE_FIRMWARE("radeon/VERDE_mc2.bin");
75 MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
76 MODULE_FIRMWARE("radeon/VERDE_smc.bin");
77
78 MODULE_FIRMWARE("radeon/verde_pfp.bin");
79 MODULE_FIRMWARE("radeon/verde_me.bin");
80 MODULE_FIRMWARE("radeon/verde_ce.bin");
81 MODULE_FIRMWARE("radeon/verde_mc.bin");
82 MODULE_FIRMWARE("radeon/verde_rlc.bin");
83 MODULE_FIRMWARE("radeon/verde_smc.bin");
84 MODULE_FIRMWARE("radeon/verde_k_smc.bin");
85
86 MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
87 MODULE_FIRMWARE("radeon/OLAND_me.bin");
88 MODULE_FIRMWARE("radeon/OLAND_ce.bin");
89 MODULE_FIRMWARE("radeon/OLAND_mc.bin");
90 MODULE_FIRMWARE("radeon/OLAND_mc2.bin");
91 MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
92 MODULE_FIRMWARE("radeon/OLAND_smc.bin");
93
94 MODULE_FIRMWARE("radeon/oland_pfp.bin");
95 MODULE_FIRMWARE("radeon/oland_me.bin");
96 MODULE_FIRMWARE("radeon/oland_ce.bin");
97 MODULE_FIRMWARE("radeon/oland_mc.bin");
98 MODULE_FIRMWARE("radeon/oland_rlc.bin");
99 MODULE_FIRMWARE("radeon/oland_smc.bin");
100 MODULE_FIRMWARE("radeon/oland_k_smc.bin");
101
102 MODULE_FIRMWARE("radeon/HAINAN_pfp.bin");
103 MODULE_FIRMWARE("radeon/HAINAN_me.bin");
104 MODULE_FIRMWARE("radeon/HAINAN_ce.bin");
105 MODULE_FIRMWARE("radeon/HAINAN_mc.bin");
106 MODULE_FIRMWARE("radeon/HAINAN_mc2.bin");
107 MODULE_FIRMWARE("radeon/HAINAN_rlc.bin");
108 MODULE_FIRMWARE("radeon/HAINAN_smc.bin");
109
110 MODULE_FIRMWARE("radeon/hainan_pfp.bin");
111 MODULE_FIRMWARE("radeon/hainan_me.bin");
112 MODULE_FIRMWARE("radeon/hainan_ce.bin");
113 MODULE_FIRMWARE("radeon/hainan_mc.bin");
114 MODULE_FIRMWARE("radeon/hainan_rlc.bin");
115 MODULE_FIRMWARE("radeon/hainan_smc.bin");
116 MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
117 MODULE_FIRMWARE("radeon/banks_k_2_smc.bin");
118
119 MODULE_FIRMWARE("radeon/si58_mc.bin");
120
121 static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);
122 static void si_pcie_gen3_enable(struct radeon_device *rdev);
123 static void si_program_aspm(struct radeon_device *rdev);
124 extern void sumo_rlc_fini(struct radeon_device *rdev);
125 extern int sumo_rlc_init(struct radeon_device *rdev);
126 extern int r600_ih_ring_alloc(struct radeon_device *rdev);
127 extern void r600_ih_ring_fini(struct radeon_device *rdev);
128 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
129 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
130 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
131 extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
132 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
133 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
134 static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
135 bool enable);
136 static void si_init_pg(struct radeon_device *rdev);
137 static void si_init_cg(struct radeon_device *rdev);
138 static void si_fini_pg(struct radeon_device *rdev);
139 static void si_fini_cg(struct radeon_device *rdev);
140 static void si_rlc_stop(struct radeon_device *rdev);
141
142 static const u32 crtc_offsets[] =
143 {
144 EVERGREEN_CRTC0_REGISTER_OFFSET,
145 EVERGREEN_CRTC1_REGISTER_OFFSET,
146 EVERGREEN_CRTC2_REGISTER_OFFSET,
147 EVERGREEN_CRTC3_REGISTER_OFFSET,
148 EVERGREEN_CRTC4_REGISTER_OFFSET,
149 EVERGREEN_CRTC5_REGISTER_OFFSET
150 };
151
152 static const u32 si_disp_int_status[] =
153 {
154 DISP_INTERRUPT_STATUS,
155 DISP_INTERRUPT_STATUS_CONTINUE,
156 DISP_INTERRUPT_STATUS_CONTINUE2,
157 DISP_INTERRUPT_STATUS_CONTINUE3,
158 DISP_INTERRUPT_STATUS_CONTINUE4,
159 DISP_INTERRUPT_STATUS_CONTINUE5
160 };
161
162 #define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc))
163 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
164 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
165
166 static const u32 verde_rlc_save_restore_register_list[] =
167 {
168 (0x8000 << 16) | (0x98f4 >> 2),
169 0x00000000,
170 (0x8040 << 16) | (0x98f4 >> 2),
171 0x00000000,
172 (0x8000 << 16) | (0xe80 >> 2),
173 0x00000000,
174 (0x8040 << 16) | (0xe80 >> 2),
175 0x00000000,
176 (0x8000 << 16) | (0x89bc >> 2),
177 0x00000000,
178 (0x8040 << 16) | (0x89bc >> 2),
179 0x00000000,
180 (0x8000 << 16) | (0x8c1c >> 2),
181 0x00000000,
182 (0x8040 << 16) | (0x8c1c >> 2),
183 0x00000000,
184 (0x9c00 << 16) | (0x98f0 >> 2),
185 0x00000000,
186 (0x9c00 << 16) | (0xe7c >> 2),
187 0x00000000,
188 (0x8000 << 16) | (0x9148 >> 2),
189 0x00000000,
190 (0x8040 << 16) | (0x9148 >> 2),
191 0x00000000,
192 (0x9c00 << 16) | (0x9150 >> 2),
193 0x00000000,
194 (0x9c00 << 16) | (0x897c >> 2),
195 0x00000000,
196 (0x9c00 << 16) | (0x8d8c >> 2),
197 0x00000000,
198 (0x9c00 << 16) | (0xac54 >> 2),
199 0X00000000,
200 0x3,
201 (0x9c00 << 16) | (0x98f8 >> 2),
202 0x00000000,
203 (0x9c00 << 16) | (0x9910 >> 2),
204 0x00000000,
205 (0x9c00 << 16) | (0x9914 >> 2),
206 0x00000000,
207 (0x9c00 << 16) | (0x9918 >> 2),
208 0x00000000,
209 (0x9c00 << 16) | (0x991c >> 2),
210 0x00000000,
211 (0x9c00 << 16) | (0x9920 >> 2),
212 0x00000000,
213 (0x9c00 << 16) | (0x9924 >> 2),
214 0x00000000,
215 (0x9c00 << 16) | (0x9928 >> 2),
216 0x00000000,
217 (0x9c00 << 16) | (0x992c >> 2),
218 0x00000000,
219 (0x9c00 << 16) | (0x9930 >> 2),
220 0x00000000,
221 (0x9c00 << 16) | (0x9934 >> 2),
222 0x00000000,
223 (0x9c00 << 16) | (0x9938 >> 2),
224 0x00000000,
225 (0x9c00 << 16) | (0x993c >> 2),
226 0x00000000,
227 (0x9c00 << 16) | (0x9940 >> 2),
228 0x00000000,
229 (0x9c00 << 16) | (0x9944 >> 2),
230 0x00000000,
231 (0x9c00 << 16) | (0x9948 >> 2),
232 0x00000000,
233 (0x9c00 << 16) | (0x994c >> 2),
234 0x00000000,
235 (0x9c00 << 16) | (0x9950 >> 2),
236 0x00000000,
237 (0x9c00 << 16) | (0x9954 >> 2),
238 0x00000000,
239 (0x9c00 << 16) | (0x9958 >> 2),
240 0x00000000,
241 (0x9c00 << 16) | (0x995c >> 2),
242 0x00000000,
243 (0x9c00 << 16) | (0x9960 >> 2),
244 0x00000000,
245 (0x9c00 << 16) | (0x9964 >> 2),
246 0x00000000,
247 (0x9c00 << 16) | (0x9968 >> 2),
248 0x00000000,
249 (0x9c00 << 16) | (0x996c >> 2),
250 0x00000000,
251 (0x9c00 << 16) | (0x9970 >> 2),
252 0x00000000,
253 (0x9c00 << 16) | (0x9974 >> 2),
254 0x00000000,
255 (0x9c00 << 16) | (0x9978 >> 2),
256 0x00000000,
257 (0x9c00 << 16) | (0x997c >> 2),
258 0x00000000,
259 (0x9c00 << 16) | (0x9980 >> 2),
260 0x00000000,
261 (0x9c00 << 16) | (0x9984 >> 2),
262 0x00000000,
263 (0x9c00 << 16) | (0x9988 >> 2),
264 0x00000000,
265 (0x9c00 << 16) | (0x998c >> 2),
266 0x00000000,
267 (0x9c00 << 16) | (0x8c00 >> 2),
268 0x00000000,
269 (0x9c00 << 16) | (0x8c14 >> 2),
270 0x00000000,
271 (0x9c00 << 16) | (0x8c04 >> 2),
272 0x00000000,
273 (0x9c00 << 16) | (0x8c08 >> 2),
274 0x00000000,
275 (0x8000 << 16) | (0x9b7c >> 2),
276 0x00000000,
277 (0x8040 << 16) | (0x9b7c >> 2),
278 0x00000000,
279 (0x8000 << 16) | (0xe84 >> 2),
280 0x00000000,
281 (0x8040 << 16) | (0xe84 >> 2),
282 0x00000000,
283 (0x8000 << 16) | (0x89c0 >> 2),
284 0x00000000,
285 (0x8040 << 16) | (0x89c0 >> 2),
286 0x00000000,
287 (0x8000 << 16) | (0x914c >> 2),
288 0x00000000,
289 (0x8040 << 16) | (0x914c >> 2),
290 0x00000000,
291 (0x8000 << 16) | (0x8c20 >> 2),
292 0x00000000,
293 (0x8040 << 16) | (0x8c20 >> 2),
294 0x00000000,
295 (0x8000 << 16) | (0x9354 >> 2),
296 0x00000000,
297 (0x8040 << 16) | (0x9354 >> 2),
298 0x00000000,
299 (0x9c00 << 16) | (0x9060 >> 2),
300 0x00000000,
301 (0x9c00 << 16) | (0x9364 >> 2),
302 0x00000000,
303 (0x9c00 << 16) | (0x9100 >> 2),
304 0x00000000,
305 (0x9c00 << 16) | (0x913c >> 2),
306 0x00000000,
307 (0x8000 << 16) | (0x90e0 >> 2),
308 0x00000000,
309 (0x8000 << 16) | (0x90e4 >> 2),
310 0x00000000,
311 (0x8000 << 16) | (0x90e8 >> 2),
312 0x00000000,
313 (0x8040 << 16) | (0x90e0 >> 2),
314 0x00000000,
315 (0x8040 << 16) | (0x90e4 >> 2),
316 0x00000000,
317 (0x8040 << 16) | (0x90e8 >> 2),
318 0x00000000,
319 (0x9c00 << 16) | (0x8bcc >> 2),
320 0x00000000,
321 (0x9c00 << 16) | (0x8b24 >> 2),
322 0x00000000,
323 (0x9c00 << 16) | (0x88c4 >> 2),
324 0x00000000,
325 (0x9c00 << 16) | (0x8e50 >> 2),
326 0x00000000,
327 (0x9c00 << 16) | (0x8c0c >> 2),
328 0x00000000,
329 (0x9c00 << 16) | (0x8e58 >> 2),
330 0x00000000,
331 (0x9c00 << 16) | (0x8e5c >> 2),
332 0x00000000,
333 (0x9c00 << 16) | (0x9508 >> 2),
334 0x00000000,
335 (0x9c00 << 16) | (0x950c >> 2),
336 0x00000000,
337 (0x9c00 << 16) | (0x9494 >> 2),
338 0x00000000,
339 (0x9c00 << 16) | (0xac0c >> 2),
340 0x00000000,
341 (0x9c00 << 16) | (0xac10 >> 2),
342 0x00000000,
343 (0x9c00 << 16) | (0xac14 >> 2),
344 0x00000000,
345 (0x9c00 << 16) | (0xae00 >> 2),
346 0x00000000,
347 (0x9c00 << 16) | (0xac08 >> 2),
348 0x00000000,
349 (0x9c00 << 16) | (0x88d4 >> 2),
350 0x00000000,
351 (0x9c00 << 16) | (0x88c8 >> 2),
352 0x00000000,
353 (0x9c00 << 16) | (0x88cc >> 2),
354 0x00000000,
355 (0x9c00 << 16) | (0x89b0 >> 2),
356 0x00000000,
357 (0x9c00 << 16) | (0x8b10 >> 2),
358 0x00000000,
359 (0x9c00 << 16) | (0x8a14 >> 2),
360 0x00000000,
361 (0x9c00 << 16) | (0x9830 >> 2),
362 0x00000000,
363 (0x9c00 << 16) | (0x9834 >> 2),
364 0x00000000,
365 (0x9c00 << 16) | (0x9838 >> 2),
366 0x00000000,
367 (0x9c00 << 16) | (0x9a10 >> 2),
368 0x00000000,
369 (0x8000 << 16) | (0x9870 >> 2),
370 0x00000000,
371 (0x8000 << 16) | (0x9874 >> 2),
372 0x00000000,
373 (0x8001 << 16) | (0x9870 >> 2),
374 0x00000000,
375 (0x8001 << 16) | (0x9874 >> 2),
376 0x00000000,
377 (0x8040 << 16) | (0x9870 >> 2),
378 0x00000000,
379 (0x8040 << 16) | (0x9874 >> 2),
380 0x00000000,
381 (0x8041 << 16) | (0x9870 >> 2),
382 0x00000000,
383 (0x8041 << 16) | (0x9874 >> 2),
384 0x00000000,
385 0x00000000
386 };
387
388 static const u32 tahiti_golden_rlc_registers[] =
389 {
390 0xc424, 0xffffffff, 0x00601005,
391 0xc47c, 0xffffffff, 0x10104040,
392 0xc488, 0xffffffff, 0x0100000a,
393 0xc314, 0xffffffff, 0x00000800,
394 0xc30c, 0xffffffff, 0x800000f4,
395 0xf4a8, 0xffffffff, 0x00000000
396 };
397
398 static const u32 tahiti_golden_registers[] =
399 {
400 0x9a10, 0x00010000, 0x00018208,
401 0x9830, 0xffffffff, 0x00000000,
402 0x9834, 0xf00fffff, 0x00000400,
403 0x9838, 0x0002021c, 0x00020200,
404 0xc78, 0x00000080, 0x00000000,
405 0xd030, 0x000300c0, 0x00800040,
406 0xd830, 0x000300c0, 0x00800040,
407 0x5bb0, 0x000000f0, 0x00000070,
408 0x5bc0, 0x00200000, 0x50100000,
409 0x7030, 0x31000311, 0x00000011,
410 0x277c, 0x00000003, 0x000007ff,
411 0x240c, 0x000007ff, 0x00000000,
412 0x8a14, 0xf000001f, 0x00000007,
413 0x8b24, 0xffffffff, 0x00ffffff,
414 0x8b10, 0x0000ff0f, 0x00000000,
415 0x28a4c, 0x07ffffff, 0x4e000000,
416 0x28350, 0x3f3f3fff, 0x2a00126a,
417 0x30, 0x000000ff, 0x0040,
418 0x34, 0x00000040, 0x00004040,
419 0x9100, 0x07ffffff, 0x03000000,
420 0x8e88, 0x01ff1f3f, 0x00000000,
421 0x8e84, 0x01ff1f3f, 0x00000000,
422 0x9060, 0x0000007f, 0x00000020,
423 0x9508, 0x00010000, 0x00010000,
424 0xac14, 0x00000200, 0x000002fb,
425 0xac10, 0xffffffff, 0x0000543b,
426 0xac0c, 0xffffffff, 0xa9210876,
427 0x88d0, 0xffffffff, 0x000fff40,
428 0x88d4, 0x0000001f, 0x00000010,
429 0x1410, 0x20000000, 0x20fffed8,
430 0x15c0, 0x000c0fc0, 0x000c0400
431 };
432
433 static const u32 tahiti_golden_registers2[] =
434 {
435 0xc64, 0x00000001, 0x00000001
436 };
437
438 static const u32 pitcairn_golden_rlc_registers[] =
439 {
440 0xc424, 0xffffffff, 0x00601004,
441 0xc47c, 0xffffffff, 0x10102020,
442 0xc488, 0xffffffff, 0x01000020,
443 0xc314, 0xffffffff, 0x00000800,
444 0xc30c, 0xffffffff, 0x800000a4
445 };
446
447 static const u32 pitcairn_golden_registers[] =
448 {
449 0x9a10, 0x00010000, 0x00018208,
450 0x9830, 0xffffffff, 0x00000000,
451 0x9834, 0xf00fffff, 0x00000400,
452 0x9838, 0x0002021c, 0x00020200,
453 0xc78, 0x00000080, 0x00000000,
454 0xd030, 0x000300c0, 0x00800040,
455 0xd830, 0x000300c0, 0x00800040,
456 0x5bb0, 0x000000f0, 0x00000070,
457 0x5bc0, 0x00200000, 0x50100000,
458 0x7030, 0x31000311, 0x00000011,
459 0x2ae4, 0x00073ffe, 0x000022a2,
460 0x240c, 0x000007ff, 0x00000000,
461 0x8a14, 0xf000001f, 0x00000007,
462 0x8b24, 0xffffffff, 0x00ffffff,
463 0x8b10, 0x0000ff0f, 0x00000000,
464 0x28a4c, 0x07ffffff, 0x4e000000,
465 0x28350, 0x3f3f3fff, 0x2a00126a,
466 0x30, 0x000000ff, 0x0040,
467 0x34, 0x00000040, 0x00004040,
468 0x9100, 0x07ffffff, 0x03000000,
469 0x9060, 0x0000007f, 0x00000020,
470 0x9508, 0x00010000, 0x00010000,
471 0xac14, 0x000003ff, 0x000000f7,
472 0xac10, 0xffffffff, 0x00000000,
473 0xac0c, 0xffffffff, 0x32761054,
474 0x88d4, 0x0000001f, 0x00000010,
475 0x15c0, 0x000c0fc0, 0x000c0400
476 };
477
478 static const u32 verde_golden_rlc_registers[] =
479 {
480 0xc424, 0xffffffff, 0x033f1005,
481 0xc47c, 0xffffffff, 0x10808020,
482 0xc488, 0xffffffff, 0x00800008,
483 0xc314, 0xffffffff, 0x00001000,
484 0xc30c, 0xffffffff, 0x80010014
485 };
486
487 static const u32 verde_golden_registers[] =
488 {
489 0x9a10, 0x00010000, 0x00018208,
490 0x9830, 0xffffffff, 0x00000000,
491 0x9834, 0xf00fffff, 0x00000400,
492 0x9838, 0x0002021c, 0x00020200,
493 0xc78, 0x00000080, 0x00000000,
494 0xd030, 0x000300c0, 0x00800040,
495 0xd030, 0x000300c0, 0x00800040,
496 0xd830, 0x000300c0, 0x00800040,
497 0xd830, 0x000300c0, 0x00800040,
498 0x5bb0, 0x000000f0, 0x00000070,
499 0x5bc0, 0x00200000, 0x50100000,
500 0x7030, 0x31000311, 0x00000011,
501 0x2ae4, 0x00073ffe, 0x000022a2,
502 0x2ae4, 0x00073ffe, 0x000022a2,
503 0x2ae4, 0x00073ffe, 0x000022a2,
504 0x240c, 0x000007ff, 0x00000000,
505 0x240c, 0x000007ff, 0x00000000,
506 0x240c, 0x000007ff, 0x00000000,
507 0x8a14, 0xf000001f, 0x00000007,
508 0x8a14, 0xf000001f, 0x00000007,
509 0x8a14, 0xf000001f, 0x00000007,
510 0x8b24, 0xffffffff, 0x00ffffff,
511 0x8b10, 0x0000ff0f, 0x00000000,
512 0x28a4c, 0x07ffffff, 0x4e000000,
513 0x28350, 0x3f3f3fff, 0x0000124a,
514 0x28350, 0x3f3f3fff, 0x0000124a,
515 0x28350, 0x3f3f3fff, 0x0000124a,
516 0x30, 0x000000ff, 0x0040,
517 0x34, 0x00000040, 0x00004040,
518 0x9100, 0x07ffffff, 0x03000000,
519 0x9100, 0x07ffffff, 0x03000000,
520 0x8e88, 0x01ff1f3f, 0x00000000,
521 0x8e88, 0x01ff1f3f, 0x00000000,
522 0x8e88, 0x01ff1f3f, 0x00000000,
523 0x8e84, 0x01ff1f3f, 0x00000000,
524 0x8e84, 0x01ff1f3f, 0x00000000,
525 0x8e84, 0x01ff1f3f, 0x00000000,
526 0x9060, 0x0000007f, 0x00000020,
527 0x9508, 0x00010000, 0x00010000,
528 0xac14, 0x000003ff, 0x00000003,
529 0xac14, 0x000003ff, 0x00000003,
530 0xac14, 0x000003ff, 0x00000003,
531 0xac10, 0xffffffff, 0x00000000,
532 0xac10, 0xffffffff, 0x00000000,
533 0xac10, 0xffffffff, 0x00000000,
534 0xac0c, 0xffffffff, 0x00001032,
535 0xac0c, 0xffffffff, 0x00001032,
536 0xac0c, 0xffffffff, 0x00001032,
537 0x88d4, 0x0000001f, 0x00000010,
538 0x88d4, 0x0000001f, 0x00000010,
539 0x88d4, 0x0000001f, 0x00000010,
540 0x15c0, 0x000c0fc0, 0x000c0400
541 };
542
543 static const u32 oland_golden_rlc_registers[] =
544 {
545 0xc424, 0xffffffff, 0x00601005,
546 0xc47c, 0xffffffff, 0x10104040,
547 0xc488, 0xffffffff, 0x0100000a,
548 0xc314, 0xffffffff, 0x00000800,
549 0xc30c, 0xffffffff, 0x800000f4
550 };
551
552 static const u32 oland_golden_registers[] =
553 {
554 0x9a10, 0x00010000, 0x00018208,
555 0x9830, 0xffffffff, 0x00000000,
556 0x9834, 0xf00fffff, 0x00000400,
557 0x9838, 0x0002021c, 0x00020200,
558 0xc78, 0x00000080, 0x00000000,
559 0xd030, 0x000300c0, 0x00800040,
560 0xd830, 0x000300c0, 0x00800040,
561 0x5bb0, 0x000000f0, 0x00000070,
562 0x5bc0, 0x00200000, 0x50100000,
563 0x7030, 0x31000311, 0x00000011,
564 0x2ae4, 0x00073ffe, 0x000022a2,
565 0x240c, 0x000007ff, 0x00000000,
566 0x8a14, 0xf000001f, 0x00000007,
567 0x8b24, 0xffffffff, 0x00ffffff,
568 0x8b10, 0x0000ff0f, 0x00000000,
569 0x28a4c, 0x07ffffff, 0x4e000000,
570 0x28350, 0x3f3f3fff, 0x00000082,
571 0x30, 0x000000ff, 0x0040,
572 0x34, 0x00000040, 0x00004040,
573 0x9100, 0x07ffffff, 0x03000000,
574 0x9060, 0x0000007f, 0x00000020,
575 0x9508, 0x00010000, 0x00010000,
576 0xac14, 0x000003ff, 0x000000f3,
577 0xac10, 0xffffffff, 0x00000000,
578 0xac0c, 0xffffffff, 0x00003210,
579 0x88d4, 0x0000001f, 0x00000010,
580 0x15c0, 0x000c0fc0, 0x000c0400
581 };
582
583 static const u32 hainan_golden_registers[] =
584 {
585 0x9a10, 0x00010000, 0x00018208,
586 0x9830, 0xffffffff, 0x00000000,
587 0x9834, 0xf00fffff, 0x00000400,
588 0x9838, 0x0002021c, 0x00020200,
589 0xd0c0, 0xff000fff, 0x00000100,
590 0xd030, 0x000300c0, 0x00800040,
591 0xd8c0, 0xff000fff, 0x00000100,
592 0xd830, 0x000300c0, 0x00800040,
593 0x2ae4, 0x00073ffe, 0x000022a2,
594 0x240c, 0x000007ff, 0x00000000,
595 0x8a14, 0xf000001f, 0x00000007,
596 0x8b24, 0xffffffff, 0x00ffffff,
597 0x8b10, 0x0000ff0f, 0x00000000,
598 0x28a4c, 0x07ffffff, 0x4e000000,
599 0x28350, 0x3f3f3fff, 0x00000000,
600 0x30, 0x000000ff, 0x0040,
601 0x34, 0x00000040, 0x00004040,
602 0x9100, 0x03e00000, 0x03600000,
603 0x9060, 0x0000007f, 0x00000020,
604 0x9508, 0x00010000, 0x00010000,
605 0xac14, 0x000003ff, 0x000000f1,
606 0xac10, 0xffffffff, 0x00000000,
607 0xac0c, 0xffffffff, 0x00003210,
608 0x88d4, 0x0000001f, 0x00000010,
609 0x15c0, 0x000c0fc0, 0x000c0400
610 };
611
612 static const u32 hainan_golden_registers2[] =
613 {
614 0x98f8, 0xffffffff, 0x02010001
615 };
616
617 static const u32 tahiti_mgcg_cgcg_init[] =
618 {
619 0xc400, 0xffffffff, 0xfffffffc,
620 0x802c, 0xffffffff, 0xe0000000,
621 0x9a60, 0xffffffff, 0x00000100,
622 0x92a4, 0xffffffff, 0x00000100,
623 0xc164, 0xffffffff, 0x00000100,
624 0x9774, 0xffffffff, 0x00000100,
625 0x8984, 0xffffffff, 0x06000100,
626 0x8a18, 0xffffffff, 0x00000100,
627 0x92a0, 0xffffffff, 0x00000100,
628 0xc380, 0xffffffff, 0x00000100,
629 0x8b28, 0xffffffff, 0x00000100,
630 0x9144, 0xffffffff, 0x00000100,
631 0x8d88, 0xffffffff, 0x00000100,
632 0x8d8c, 0xffffffff, 0x00000100,
633 0x9030, 0xffffffff, 0x00000100,
634 0x9034, 0xffffffff, 0x00000100,
635 0x9038, 0xffffffff, 0x00000100,
636 0x903c, 0xffffffff, 0x00000100,
637 0xad80, 0xffffffff, 0x00000100,
638 0xac54, 0xffffffff, 0x00000100,
639 0x897c, 0xffffffff, 0x06000100,
640 0x9868, 0xffffffff, 0x00000100,
641 0x9510, 0xffffffff, 0x00000100,
642 0xaf04, 0xffffffff, 0x00000100,
643 0xae04, 0xffffffff, 0x00000100,
644 0x949c, 0xffffffff, 0x00000100,
645 0x802c, 0xffffffff, 0xe0000000,
646 0x9160, 0xffffffff, 0x00010000,
647 0x9164, 0xffffffff, 0x00030002,
648 0x9168, 0xffffffff, 0x00040007,
649 0x916c, 0xffffffff, 0x00060005,
650 0x9170, 0xffffffff, 0x00090008,
651 0x9174, 0xffffffff, 0x00020001,
652 0x9178, 0xffffffff, 0x00040003,
653 0x917c, 0xffffffff, 0x00000007,
654 0x9180, 0xffffffff, 0x00060005,
655 0x9184, 0xffffffff, 0x00090008,
656 0x9188, 0xffffffff, 0x00030002,
657 0x918c, 0xffffffff, 0x00050004,
658 0x9190, 0xffffffff, 0x00000008,
659 0x9194, 0xffffffff, 0x00070006,
660 0x9198, 0xffffffff, 0x000a0009,
661 0x919c, 0xffffffff, 0x00040003,
662 0x91a0, 0xffffffff, 0x00060005,
663 0x91a4, 0xffffffff, 0x00000009,
664 0x91a8, 0xffffffff, 0x00080007,
665 0x91ac, 0xffffffff, 0x000b000a,
666 0x91b0, 0xffffffff, 0x00050004,
667 0x91b4, 0xffffffff, 0x00070006,
668 0x91b8, 0xffffffff, 0x0008000b,
669 0x91bc, 0xffffffff, 0x000a0009,
670 0x91c0, 0xffffffff, 0x000d000c,
671 0x91c4, 0xffffffff, 0x00060005,
672 0x91c8, 0xffffffff, 0x00080007,
673 0x91cc, 0xffffffff, 0x0000000b,
674 0x91d0, 0xffffffff, 0x000a0009,
675 0x91d4, 0xffffffff, 0x000d000c,
676 0x91d8, 0xffffffff, 0x00070006,
677 0x91dc, 0xffffffff, 0x00090008,
678 0x91e0, 0xffffffff, 0x0000000c,
679 0x91e4, 0xffffffff, 0x000b000a,
680 0x91e8, 0xffffffff, 0x000e000d,
681 0x91ec, 0xffffffff, 0x00080007,
682 0x91f0, 0xffffffff, 0x000a0009,
683 0x91f4, 0xffffffff, 0x0000000d,
684 0x91f8, 0xffffffff, 0x000c000b,
685 0x91fc, 0xffffffff, 0x000f000e,
686 0x9200, 0xffffffff, 0x00090008,
687 0x9204, 0xffffffff, 0x000b000a,
688 0x9208, 0xffffffff, 0x000c000f,
689 0x920c, 0xffffffff, 0x000e000d,
690 0x9210, 0xffffffff, 0x00110010,
691 0x9214, 0xffffffff, 0x000a0009,
692 0x9218, 0xffffffff, 0x000c000b,
693 0x921c, 0xffffffff, 0x0000000f,
694 0x9220, 0xffffffff, 0x000e000d,
695 0x9224, 0xffffffff, 0x00110010,
696 0x9228, 0xffffffff, 0x000b000a,
697 0x922c, 0xffffffff, 0x000d000c,
698 0x9230, 0xffffffff, 0x00000010,
699 0x9234, 0xffffffff, 0x000f000e,
700 0x9238, 0xffffffff, 0x00120011,
701 0x923c, 0xffffffff, 0x000c000b,
702 0x9240, 0xffffffff, 0x000e000d,
703 0x9244, 0xffffffff, 0x00000011,
704 0x9248, 0xffffffff, 0x0010000f,
705 0x924c, 0xffffffff, 0x00130012,
706 0x9250, 0xffffffff, 0x000d000c,
707 0x9254, 0xffffffff, 0x000f000e,
708 0x9258, 0xffffffff, 0x00100013,
709 0x925c, 0xffffffff, 0x00120011,
710 0x9260, 0xffffffff, 0x00150014,
711 0x9264, 0xffffffff, 0x000e000d,
712 0x9268, 0xffffffff, 0x0010000f,
713 0x926c, 0xffffffff, 0x00000013,
714 0x9270, 0xffffffff, 0x00120011,
715 0x9274, 0xffffffff, 0x00150014,
716 0x9278, 0xffffffff, 0x000f000e,
717 0x927c, 0xffffffff, 0x00110010,
718 0x9280, 0xffffffff, 0x00000014,
719 0x9284, 0xffffffff, 0x00130012,
720 0x9288, 0xffffffff, 0x00160015,
721 0x928c, 0xffffffff, 0x0010000f,
722 0x9290, 0xffffffff, 0x00120011,
723 0x9294, 0xffffffff, 0x00000015,
724 0x9298, 0xffffffff, 0x00140013,
725 0x929c, 0xffffffff, 0x00170016,
726 0x9150, 0xffffffff, 0x96940200,
727 0x8708, 0xffffffff, 0x00900100,
728 0xc478, 0xffffffff, 0x00000080,
729 0xc404, 0xffffffff, 0x0020003f,
730 0x30, 0xffffffff, 0x0000001c,
731 0x34, 0x000f0000, 0x000f0000,
732 0x160c, 0xffffffff, 0x00000100,
733 0x1024, 0xffffffff, 0x00000100,
734 0x102c, 0x00000101, 0x00000000,
735 0x20a8, 0xffffffff, 0x00000104,
736 0x264c, 0x000c0000, 0x000c0000,
737 0x2648, 0x000c0000, 0x000c0000,
738 0x55e4, 0xff000fff, 0x00000100,
739 0x55e8, 0x00000001, 0x00000001,
740 0x2f50, 0x00000001, 0x00000001,
741 0x30cc, 0xc0000fff, 0x00000104,
742 0xc1e4, 0x00000001, 0x00000001,
743 0xd0c0, 0xfffffff0, 0x00000100,
744 0xd8c0, 0xfffffff0, 0x00000100
745 };
746
747 static const u32 pitcairn_mgcg_cgcg_init[] =
748 {
749 0xc400, 0xffffffff, 0xfffffffc,
750 0x802c, 0xffffffff, 0xe0000000,
751 0x9a60, 0xffffffff, 0x00000100,
752 0x92a4, 0xffffffff, 0x00000100,
753 0xc164, 0xffffffff, 0x00000100,
754 0x9774, 0xffffffff, 0x00000100,
755 0x8984, 0xffffffff, 0x06000100,
756 0x8a18, 0xffffffff, 0x00000100,
757 0x92a0, 0xffffffff, 0x00000100,
758 0xc380, 0xffffffff, 0x00000100,
759 0x8b28, 0xffffffff, 0x00000100,
760 0x9144, 0xffffffff, 0x00000100,
761 0x8d88, 0xffffffff, 0x00000100,
762 0x8d8c, 0xffffffff, 0x00000100,
763 0x9030, 0xffffffff, 0x00000100,
764 0x9034, 0xffffffff, 0x00000100,
765 0x9038, 0xffffffff, 0x00000100,
766 0x903c, 0xffffffff, 0x00000100,
767 0xad80, 0xffffffff, 0x00000100,
768 0xac54, 0xffffffff, 0x00000100,
769 0x897c, 0xffffffff, 0x06000100,
770 0x9868, 0xffffffff, 0x00000100,
771 0x9510, 0xffffffff, 0x00000100,
772 0xaf04, 0xffffffff, 0x00000100,
773 0xae04, 0xffffffff, 0x00000100,
774 0x949c, 0xffffffff, 0x00000100,
775 0x802c, 0xffffffff, 0xe0000000,
776 0x9160, 0xffffffff, 0x00010000,
777 0x9164, 0xffffffff, 0x00030002,
778 0x9168, 0xffffffff, 0x00040007,
779 0x916c, 0xffffffff, 0x00060005,
780 0x9170, 0xffffffff, 0x00090008,
781 0x9174, 0xffffffff, 0x00020001,
782 0x9178, 0xffffffff, 0x00040003,
783 0x917c, 0xffffffff, 0x00000007,
784 0x9180, 0xffffffff, 0x00060005,
785 0x9184, 0xffffffff, 0x00090008,
786 0x9188, 0xffffffff, 0x00030002,
787 0x918c, 0xffffffff, 0x00050004,
788 0x9190, 0xffffffff, 0x00000008,
789 0x9194, 0xffffffff, 0x00070006,
790 0x9198, 0xffffffff, 0x000a0009,
791 0x919c, 0xffffffff, 0x00040003,
792 0x91a0, 0xffffffff, 0x00060005,
793 0x91a4, 0xffffffff, 0x00000009,
794 0x91a8, 0xffffffff, 0x00080007,
795 0x91ac, 0xffffffff, 0x000b000a,
796 0x91b0, 0xffffffff, 0x00050004,
797 0x91b4, 0xffffffff, 0x00070006,
798 0x91b8, 0xffffffff, 0x0008000b,
799 0x91bc, 0xffffffff, 0x000a0009,
800 0x91c0, 0xffffffff, 0x000d000c,
801 0x9200, 0xffffffff, 0x00090008,
802 0x9204, 0xffffffff, 0x000b000a,
803 0x9208, 0xffffffff, 0x000c000f,
804 0x920c, 0xffffffff, 0x000e000d,
805 0x9210, 0xffffffff, 0x00110010,
806 0x9214, 0xffffffff, 0x000a0009,
807 0x9218, 0xffffffff, 0x000c000b,
808 0x921c, 0xffffffff, 0x0000000f,
809 0x9220, 0xffffffff, 0x000e000d,
810 0x9224, 0xffffffff, 0x00110010,
811 0x9228, 0xffffffff, 0x000b000a,
812 0x922c, 0xffffffff, 0x000d000c,
813 0x9230, 0xffffffff, 0x00000010,
814 0x9234, 0xffffffff, 0x000f000e,
815 0x9238, 0xffffffff, 0x00120011,
816 0x923c, 0xffffffff, 0x000c000b,
817 0x9240, 0xffffffff, 0x000e000d,
818 0x9244, 0xffffffff, 0x00000011,
819 0x9248, 0xffffffff, 0x0010000f,
820 0x924c, 0xffffffff, 0x00130012,
821 0x9250, 0xffffffff, 0x000d000c,
822 0x9254, 0xffffffff, 0x000f000e,
823 0x9258, 0xffffffff, 0x00100013,
824 0x925c, 0xffffffff, 0x00120011,
825 0x9260, 0xffffffff, 0x00150014,
826 0x9150, 0xffffffff, 0x96940200,
827 0x8708, 0xffffffff, 0x00900100,
828 0xc478, 0xffffffff, 0x00000080,
829 0xc404, 0xffffffff, 0x0020003f,
830 0x30, 0xffffffff, 0x0000001c,
831 0x34, 0x000f0000, 0x000f0000,
832 0x160c, 0xffffffff, 0x00000100,
833 0x1024, 0xffffffff, 0x00000100,
834 0x102c, 0x00000101, 0x00000000,
835 0x20a8, 0xffffffff, 0x00000104,
836 0x55e4, 0xff000fff, 0x00000100,
837 0x55e8, 0x00000001, 0x00000001,
838 0x2f50, 0x00000001, 0x00000001,
839 0x30cc, 0xc0000fff, 0x00000104,
840 0xc1e4, 0x00000001, 0x00000001,
841 0xd0c0, 0xfffffff0, 0x00000100,
842 0xd8c0, 0xfffffff0, 0x00000100
843 };
844
845 static const u32 verde_mgcg_cgcg_init[] =
846 {
847 0xc400, 0xffffffff, 0xfffffffc,
848 0x802c, 0xffffffff, 0xe0000000,
849 0x9a60, 0xffffffff, 0x00000100,
850 0x92a4, 0xffffffff, 0x00000100,
851 0xc164, 0xffffffff, 0x00000100,
852 0x9774, 0xffffffff, 0x00000100,
853 0x8984, 0xffffffff, 0x06000100,
854 0x8a18, 0xffffffff, 0x00000100,
855 0x92a0, 0xffffffff, 0x00000100,
856 0xc380, 0xffffffff, 0x00000100,
857 0x8b28, 0xffffffff, 0x00000100,
858 0x9144, 0xffffffff, 0x00000100,
859 0x8d88, 0xffffffff, 0x00000100,
860 0x8d8c, 0xffffffff, 0x00000100,
861 0x9030, 0xffffffff, 0x00000100,
862 0x9034, 0xffffffff, 0x00000100,
863 0x9038, 0xffffffff, 0x00000100,
864 0x903c, 0xffffffff, 0x00000100,
865 0xad80, 0xffffffff, 0x00000100,
866 0xac54, 0xffffffff, 0x00000100,
867 0x897c, 0xffffffff, 0x06000100,
868 0x9868, 0xffffffff, 0x00000100,
869 0x9510, 0xffffffff, 0x00000100,
870 0xaf04, 0xffffffff, 0x00000100,
871 0xae04, 0xffffffff, 0x00000100,
872 0x949c, 0xffffffff, 0x00000100,
873 0x802c, 0xffffffff, 0xe0000000,
874 0x9160, 0xffffffff, 0x00010000,
875 0x9164, 0xffffffff, 0x00030002,
876 0x9168, 0xffffffff, 0x00040007,
877 0x916c, 0xffffffff, 0x00060005,
878 0x9170, 0xffffffff, 0x00090008,
879 0x9174, 0xffffffff, 0x00020001,
880 0x9178, 0xffffffff, 0x00040003,
881 0x917c, 0xffffffff, 0x00000007,
882 0x9180, 0xffffffff, 0x00060005,
883 0x9184, 0xffffffff, 0x00090008,
884 0x9188, 0xffffffff, 0x00030002,
885 0x918c, 0xffffffff, 0x00050004,
886 0x9190, 0xffffffff, 0x00000008,
887 0x9194, 0xffffffff, 0x00070006,
888 0x9198, 0xffffffff, 0x000a0009,
889 0x919c, 0xffffffff, 0x00040003,
890 0x91a0, 0xffffffff, 0x00060005,
891 0x91a4, 0xffffffff, 0x00000009,
892 0x91a8, 0xffffffff, 0x00080007,
893 0x91ac, 0xffffffff, 0x000b000a,
894 0x91b0, 0xffffffff, 0x00050004,
895 0x91b4, 0xffffffff, 0x00070006,
896 0x91b8, 0xffffffff, 0x0008000b,
897 0x91bc, 0xffffffff, 0x000a0009,
898 0x91c0, 0xffffffff, 0x000d000c,
899 0x9200, 0xffffffff, 0x00090008,
900 0x9204, 0xffffffff, 0x000b000a,
901 0x9208, 0xffffffff, 0x000c000f,
902 0x920c, 0xffffffff, 0x000e000d,
903 0x9210, 0xffffffff, 0x00110010,
904 0x9214, 0xffffffff, 0x000a0009,
905 0x9218, 0xffffffff, 0x000c000b,
906 0x921c, 0xffffffff, 0x0000000f,
907 0x9220, 0xffffffff, 0x000e000d,
908 0x9224, 0xffffffff, 0x00110010,
909 0x9228, 0xffffffff, 0x000b000a,
910 0x922c, 0xffffffff, 0x000d000c,
911 0x9230, 0xffffffff, 0x00000010,
912 0x9234, 0xffffffff, 0x000f000e,
913 0x9238, 0xffffffff, 0x00120011,
914 0x923c, 0xffffffff, 0x000c000b,
915 0x9240, 0xffffffff, 0x000e000d,
916 0x9244, 0xffffffff, 0x00000011,
917 0x9248, 0xffffffff, 0x0010000f,
918 0x924c, 0xffffffff, 0x00130012,
919 0x9250, 0xffffffff, 0x000d000c,
920 0x9254, 0xffffffff, 0x000f000e,
921 0x9258, 0xffffffff, 0x00100013,
922 0x925c, 0xffffffff, 0x00120011,
923 0x9260, 0xffffffff, 0x00150014,
924 0x9150, 0xffffffff, 0x96940200,
925 0x8708, 0xffffffff, 0x00900100,
926 0xc478, 0xffffffff, 0x00000080,
927 0xc404, 0xffffffff, 0x0020003f,
928 0x30, 0xffffffff, 0x0000001c,
929 0x34, 0x000f0000, 0x000f0000,
930 0x160c, 0xffffffff, 0x00000100,
931 0x1024, 0xffffffff, 0x00000100,
932 0x102c, 0x00000101, 0x00000000,
933 0x20a8, 0xffffffff, 0x00000104,
934 0x264c, 0x000c0000, 0x000c0000,
935 0x2648, 0x000c0000, 0x000c0000,
936 0x55e4, 0xff000fff, 0x00000100,
937 0x55e8, 0x00000001, 0x00000001,
938 0x2f50, 0x00000001, 0x00000001,
939 0x30cc, 0xc0000fff, 0x00000104,
940 0xc1e4, 0x00000001, 0x00000001,
941 0xd0c0, 0xfffffff0, 0x00000100,
942 0xd8c0, 0xfffffff0, 0x00000100
943 };
944
945 static const u32 oland_mgcg_cgcg_init[] =
946 {
947 0xc400, 0xffffffff, 0xfffffffc,
948 0x802c, 0xffffffff, 0xe0000000,
949 0x9a60, 0xffffffff, 0x00000100,
950 0x92a4, 0xffffffff, 0x00000100,
951 0xc164, 0xffffffff, 0x00000100,
952 0x9774, 0xffffffff, 0x00000100,
953 0x8984, 0xffffffff, 0x06000100,
954 0x8a18, 0xffffffff, 0x00000100,
955 0x92a0, 0xffffffff, 0x00000100,
956 0xc380, 0xffffffff, 0x00000100,
957 0x8b28, 0xffffffff, 0x00000100,
958 0x9144, 0xffffffff, 0x00000100,
959 0x8d88, 0xffffffff, 0x00000100,
960 0x8d8c, 0xffffffff, 0x00000100,
961 0x9030, 0xffffffff, 0x00000100,
962 0x9034, 0xffffffff, 0x00000100,
963 0x9038, 0xffffffff, 0x00000100,
964 0x903c, 0xffffffff, 0x00000100,
965 0xad80, 0xffffffff, 0x00000100,
966 0xac54, 0xffffffff, 0x00000100,
967 0x897c, 0xffffffff, 0x06000100,
968 0x9868, 0xffffffff, 0x00000100,
969 0x9510, 0xffffffff, 0x00000100,
970 0xaf04, 0xffffffff, 0x00000100,
971 0xae04, 0xffffffff, 0x00000100,
972 0x949c, 0xffffffff, 0x00000100,
973 0x802c, 0xffffffff, 0xe0000000,
974 0x9160, 0xffffffff, 0x00010000,
975 0x9164, 0xffffffff, 0x00030002,
976 0x9168, 0xffffffff, 0x00040007,
977 0x916c, 0xffffffff, 0x00060005,
978 0x9170, 0xffffffff, 0x00090008,
979 0x9174, 0xffffffff, 0x00020001,
980 0x9178, 0xffffffff, 0x00040003,
981 0x917c, 0xffffffff, 0x00000007,
982 0x9180, 0xffffffff, 0x00060005,
983 0x9184, 0xffffffff, 0x00090008,
984 0x9188, 0xffffffff, 0x00030002,
985 0x918c, 0xffffffff, 0x00050004,
986 0x9190, 0xffffffff, 0x00000008,
987 0x9194, 0xffffffff, 0x00070006,
988 0x9198, 0xffffffff, 0x000a0009,
989 0x919c, 0xffffffff, 0x00040003,
990 0x91a0, 0xffffffff, 0x00060005,
991 0x91a4, 0xffffffff, 0x00000009,
992 0x91a8, 0xffffffff, 0x00080007,
993 0x91ac, 0xffffffff, 0x000b000a,
994 0x91b0, 0xffffffff, 0x00050004,
995 0x91b4, 0xffffffff, 0x00070006,
996 0x91b8, 0xffffffff, 0x0008000b,
997 0x91bc, 0xffffffff, 0x000a0009,
998 0x91c0, 0xffffffff, 0x000d000c,
999 0x91c4, 0xffffffff, 0x00060005,
1000 0x91c8, 0xffffffff, 0x00080007,
1001 0x91cc, 0xffffffff, 0x0000000b,
1002 0x91d0, 0xffffffff, 0x000a0009,
1003 0x91d4, 0xffffffff, 0x000d000c,
1004 0x9150, 0xffffffff, 0x96940200,
1005 0x8708, 0xffffffff, 0x00900100,
1006 0xc478, 0xffffffff, 0x00000080,
1007 0xc404, 0xffffffff, 0x0020003f,
1008 0x30, 0xffffffff, 0x0000001c,
1009 0x34, 0x000f0000, 0x000f0000,
1010 0x160c, 0xffffffff, 0x00000100,
1011 0x1024, 0xffffffff, 0x00000100,
1012 0x102c, 0x00000101, 0x00000000,
1013 0x20a8, 0xffffffff, 0x00000104,
1014 0x264c, 0x000c0000, 0x000c0000,
1015 0x2648, 0x000c0000, 0x000c0000,
1016 0x55e4, 0xff000fff, 0x00000100,
1017 0x55e8, 0x00000001, 0x00000001,
1018 0x2f50, 0x00000001, 0x00000001,
1019 0x30cc, 0xc0000fff, 0x00000104,
1020 0xc1e4, 0x00000001, 0x00000001,
1021 0xd0c0, 0xfffffff0, 0x00000100,
1022 0xd8c0, 0xfffffff0, 0x00000100
1023 };
1024
1025 static const u32 hainan_mgcg_cgcg_init[] =
1026 {
1027 0xc400, 0xffffffff, 0xfffffffc,
1028 0x802c, 0xffffffff, 0xe0000000,
1029 0x9a60, 0xffffffff, 0x00000100,
1030 0x92a4, 0xffffffff, 0x00000100,
1031 0xc164, 0xffffffff, 0x00000100,
1032 0x9774, 0xffffffff, 0x00000100,
1033 0x8984, 0xffffffff, 0x06000100,
1034 0x8a18, 0xffffffff, 0x00000100,
1035 0x92a0, 0xffffffff, 0x00000100,
1036 0xc380, 0xffffffff, 0x00000100,
1037 0x8b28, 0xffffffff, 0x00000100,
1038 0x9144, 0xffffffff, 0x00000100,
1039 0x8d88, 0xffffffff, 0x00000100,
1040 0x8d8c, 0xffffffff, 0x00000100,
1041 0x9030, 0xffffffff, 0x00000100,
1042 0x9034, 0xffffffff, 0x00000100,
1043 0x9038, 0xffffffff, 0x00000100,
1044 0x903c, 0xffffffff, 0x00000100,
1045 0xad80, 0xffffffff, 0x00000100,
1046 0xac54, 0xffffffff, 0x00000100,
1047 0x897c, 0xffffffff, 0x06000100,
1048 0x9868, 0xffffffff, 0x00000100,
1049 0x9510, 0xffffffff, 0x00000100,
1050 0xaf04, 0xffffffff, 0x00000100,
1051 0xae04, 0xffffffff, 0x00000100,
1052 0x949c, 0xffffffff, 0x00000100,
1053 0x802c, 0xffffffff, 0xe0000000,
1054 0x9160, 0xffffffff, 0x00010000,
1055 0x9164, 0xffffffff, 0x00030002,
1056 0x9168, 0xffffffff, 0x00040007,
1057 0x916c, 0xffffffff, 0x00060005,
1058 0x9170, 0xffffffff, 0x00090008,
1059 0x9174, 0xffffffff, 0x00020001,
1060 0x9178, 0xffffffff, 0x00040003,
1061 0x917c, 0xffffffff, 0x00000007,
1062 0x9180, 0xffffffff, 0x00060005,
1063 0x9184, 0xffffffff, 0x00090008,
1064 0x9188, 0xffffffff, 0x00030002,
1065 0x918c, 0xffffffff, 0x00050004,
1066 0x9190, 0xffffffff, 0x00000008,
1067 0x9194, 0xffffffff, 0x00070006,
1068 0x9198, 0xffffffff, 0x000a0009,
1069 0x919c, 0xffffffff, 0x00040003,
1070 0x91a0, 0xffffffff, 0x00060005,
1071 0x91a4, 0xffffffff, 0x00000009,
1072 0x91a8, 0xffffffff, 0x00080007,
1073 0x91ac, 0xffffffff, 0x000b000a,
1074 0x91b0, 0xffffffff, 0x00050004,
1075 0x91b4, 0xffffffff, 0x00070006,
1076 0x91b8, 0xffffffff, 0x0008000b,
1077 0x91bc, 0xffffffff, 0x000a0009,
1078 0x91c0, 0xffffffff, 0x000d000c,
1079 0x91c4, 0xffffffff, 0x00060005,
1080 0x91c8, 0xffffffff, 0x00080007,
1081 0x91cc, 0xffffffff, 0x0000000b,
1082 0x91d0, 0xffffffff, 0x000a0009,
1083 0x91d4, 0xffffffff, 0x000d000c,
1084 0x9150, 0xffffffff, 0x96940200,
1085 0x8708, 0xffffffff, 0x00900100,
1086 0xc478, 0xffffffff, 0x00000080,
1087 0xc404, 0xffffffff, 0x0020003f,
1088 0x30, 0xffffffff, 0x0000001c,
1089 0x34, 0x000f0000, 0x000f0000,
1090 0x160c, 0xffffffff, 0x00000100,
1091 0x1024, 0xffffffff, 0x00000100,
1092 0x20a8, 0xffffffff, 0x00000104,
1093 0x264c, 0x000c0000, 0x000c0000,
1094 0x2648, 0x000c0000, 0x000c0000,
1095 0x2f50, 0x00000001, 0x00000001,
1096 0x30cc, 0xc0000fff, 0x00000104,
1097 0xc1e4, 0x00000001, 0x00000001,
1098 0xd0c0, 0xfffffff0, 0x00000100,
1099 0xd8c0, 0xfffffff0, 0x00000100
1100 };
1101
1102 static u32 verde_pg_init[] =
1103 {
1104 0x353c, 0xffffffff, 0x40000,
1105 0x3538, 0xffffffff, 0x200010ff,
1106 0x353c, 0xffffffff, 0x0,
1107 0x353c, 0xffffffff, 0x0,
1108 0x353c, 0xffffffff, 0x0,
1109 0x353c, 0xffffffff, 0x0,
1110 0x353c, 0xffffffff, 0x0,
1111 0x353c, 0xffffffff, 0x7007,
1112 0x3538, 0xffffffff, 0x300010ff,
1113 0x353c, 0xffffffff, 0x0,
1114 0x353c, 0xffffffff, 0x0,
1115 0x353c, 0xffffffff, 0x0,
1116 0x353c, 0xffffffff, 0x0,
1117 0x353c, 0xffffffff, 0x0,
1118 0x353c, 0xffffffff, 0x400000,
1119 0x3538, 0xffffffff, 0x100010ff,
1120 0x353c, 0xffffffff, 0x0,
1121 0x353c, 0xffffffff, 0x0,
1122 0x353c, 0xffffffff, 0x0,
1123 0x353c, 0xffffffff, 0x0,
1124 0x353c, 0xffffffff, 0x0,
1125 0x353c, 0xffffffff, 0x120200,
1126 0x3538, 0xffffffff, 0x500010ff,
1127 0x353c, 0xffffffff, 0x0,
1128 0x353c, 0xffffffff, 0x0,
1129 0x353c, 0xffffffff, 0x0,
1130 0x353c, 0xffffffff, 0x0,
1131 0x353c, 0xffffffff, 0x0,
1132 0x353c, 0xffffffff, 0x1e1e16,
1133 0x3538, 0xffffffff, 0x600010ff,
1134 0x353c, 0xffffffff, 0x0,
1135 0x353c, 0xffffffff, 0x0,
1136 0x353c, 0xffffffff, 0x0,
1137 0x353c, 0xffffffff, 0x0,
1138 0x353c, 0xffffffff, 0x0,
1139 0x353c, 0xffffffff, 0x171f1e,
1140 0x3538, 0xffffffff, 0x700010ff,
1141 0x353c, 0xffffffff, 0x0,
1142 0x353c, 0xffffffff, 0x0,
1143 0x353c, 0xffffffff, 0x0,
1144 0x353c, 0xffffffff, 0x0,
1145 0x353c, 0xffffffff, 0x0,
1146 0x353c, 0xffffffff, 0x0,
1147 0x3538, 0xffffffff, 0x9ff,
1148 0x3500, 0xffffffff, 0x0,
1149 0x3504, 0xffffffff, 0x10000800,
1150 0x3504, 0xffffffff, 0xf,
1151 0x3504, 0xffffffff, 0xf,
1152 0x3500, 0xffffffff, 0x4,
1153 0x3504, 0xffffffff, 0x1000051e,
1154 0x3504, 0xffffffff, 0xffff,
1155 0x3504, 0xffffffff, 0xffff,
1156 0x3500, 0xffffffff, 0x8,
1157 0x3504, 0xffffffff, 0x80500,
1158 0x3500, 0xffffffff, 0x12,
1159 0x3504, 0xffffffff, 0x9050c,
1160 0x3500, 0xffffffff, 0x1d,
1161 0x3504, 0xffffffff, 0xb052c,
1162 0x3500, 0xffffffff, 0x2a,
1163 0x3504, 0xffffffff, 0x1053e,
1164 0x3500, 0xffffffff, 0x2d,
1165 0x3504, 0xffffffff, 0x10546,
1166 0x3500, 0xffffffff, 0x30,
1167 0x3504, 0xffffffff, 0xa054e,
1168 0x3500, 0xffffffff, 0x3c,
1169 0x3504, 0xffffffff, 0x1055f,
1170 0x3500, 0xffffffff, 0x3f,
1171 0x3504, 0xffffffff, 0x10567,
1172 0x3500, 0xffffffff, 0x42,
1173 0x3504, 0xffffffff, 0x1056f,
1174 0x3500, 0xffffffff, 0x45,
1175 0x3504, 0xffffffff, 0x10572,
1176 0x3500, 0xffffffff, 0x48,
1177 0x3504, 0xffffffff, 0x20575,
1178 0x3500, 0xffffffff, 0x4c,
1179 0x3504, 0xffffffff, 0x190801,
1180 0x3500, 0xffffffff, 0x67,
1181 0x3504, 0xffffffff, 0x1082a,
1182 0x3500, 0xffffffff, 0x6a,
1183 0x3504, 0xffffffff, 0x1b082d,
1184 0x3500, 0xffffffff, 0x87,
1185 0x3504, 0xffffffff, 0x310851,
1186 0x3500, 0xffffffff, 0xba,
1187 0x3504, 0xffffffff, 0x891,
1188 0x3500, 0xffffffff, 0xbc,
1189 0x3504, 0xffffffff, 0x893,
1190 0x3500, 0xffffffff, 0xbe,
1191 0x3504, 0xffffffff, 0x20895,
1192 0x3500, 0xffffffff, 0xc2,
1193 0x3504, 0xffffffff, 0x20899,
1194 0x3500, 0xffffffff, 0xc6,
1195 0x3504, 0xffffffff, 0x2089d,
1196 0x3500, 0xffffffff, 0xca,
1197 0x3504, 0xffffffff, 0x8a1,
1198 0x3500, 0xffffffff, 0xcc,
1199 0x3504, 0xffffffff, 0x8a3,
1200 0x3500, 0xffffffff, 0xce,
1201 0x3504, 0xffffffff, 0x308a5,
1202 0x3500, 0xffffffff, 0xd3,
1203 0x3504, 0xffffffff, 0x6d08cd,
1204 0x3500, 0xffffffff, 0x142,
1205 0x3504, 0xffffffff, 0x2000095a,
1206 0x3504, 0xffffffff, 0x1,
1207 0x3500, 0xffffffff, 0x144,
1208 0x3504, 0xffffffff, 0x301f095b,
1209 0x3500, 0xffffffff, 0x165,
1210 0x3504, 0xffffffff, 0xc094d,
1211 0x3500, 0xffffffff, 0x173,
1212 0x3504, 0xffffffff, 0xf096d,
1213 0x3500, 0xffffffff, 0x184,
1214 0x3504, 0xffffffff, 0x15097f,
1215 0x3500, 0xffffffff, 0x19b,
1216 0x3504, 0xffffffff, 0xc0998,
1217 0x3500, 0xffffffff, 0x1a9,
1218 0x3504, 0xffffffff, 0x409a7,
1219 0x3500, 0xffffffff, 0x1af,
1220 0x3504, 0xffffffff, 0xcdc,
1221 0x3500, 0xffffffff, 0x1b1,
1222 0x3504, 0xffffffff, 0x800,
1223 0x3508, 0xffffffff, 0x6c9b2000,
1224 0x3510, 0xfc00, 0x2000,
1225 0x3544, 0xffffffff, 0xfc0,
1226 0x28d4, 0x00000100, 0x100
1227 };
1228
1229 static void si_init_golden_registers(struct radeon_device *rdev)
1230 {
1231 switch (rdev->family) {
1232 case CHIP_TAHITI:
1233 radeon_program_register_sequence(rdev,
1234 tahiti_golden_registers,
1235 (const u32)ARRAY_SIZE(tahiti_golden_registers));
1236 radeon_program_register_sequence(rdev,
1237 tahiti_golden_rlc_registers,
1238 (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
1239 radeon_program_register_sequence(rdev,
1240 tahiti_mgcg_cgcg_init,
1241 (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1242 radeon_program_register_sequence(rdev,
1243 tahiti_golden_registers2,
1244 (const u32)ARRAY_SIZE(tahiti_golden_registers2));
1245 break;
1246 case CHIP_PITCAIRN:
1247 radeon_program_register_sequence(rdev,
1248 pitcairn_golden_registers,
1249 (const u32)ARRAY_SIZE(pitcairn_golden_registers));
1250 radeon_program_register_sequence(rdev,
1251 pitcairn_golden_rlc_registers,
1252 (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
1253 radeon_program_register_sequence(rdev,
1254 pitcairn_mgcg_cgcg_init,
1255 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1256 break;
1257 case CHIP_VERDE:
1258 radeon_program_register_sequence(rdev,
1259 verde_golden_registers,
1260 (const u32)ARRAY_SIZE(verde_golden_registers));
1261 radeon_program_register_sequence(rdev,
1262 verde_golden_rlc_registers,
1263 (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
1264 radeon_program_register_sequence(rdev,
1265 verde_mgcg_cgcg_init,
1266 (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
1267 radeon_program_register_sequence(rdev,
1268 verde_pg_init,
1269 (const u32)ARRAY_SIZE(verde_pg_init));
1270 break;
1271 case CHIP_OLAND:
1272 radeon_program_register_sequence(rdev,
1273 oland_golden_registers,
1274 (const u32)ARRAY_SIZE(oland_golden_registers));
1275 radeon_program_register_sequence(rdev,
1276 oland_golden_rlc_registers,
1277 (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
1278 radeon_program_register_sequence(rdev,
1279 oland_mgcg_cgcg_init,
1280 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
1281 break;
1282 case CHIP_HAINAN:
1283 radeon_program_register_sequence(rdev,
1284 hainan_golden_registers,
1285 (const u32)ARRAY_SIZE(hainan_golden_registers));
1286 radeon_program_register_sequence(rdev,
1287 hainan_golden_registers2,
1288 (const u32)ARRAY_SIZE(hainan_golden_registers2));
1289 radeon_program_register_sequence(rdev,
1290 hainan_mgcg_cgcg_init,
1291 (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
1292 break;
1293 default:
1294 break;
1295 }
1296 }
1297
1298 /**
1299 * si_get_allowed_info_register - fetch the register for the info ioctl
1300 *
1301 * @rdev: radeon_device pointer
1302 * @reg: register offset in bytes
1303 * @val: register value
1304 *
1305 * Returns 0 for success or -EINVAL for an invalid register
1306 *
1307 */
1308 int si_get_allowed_info_register(struct radeon_device *rdev,
1309 u32 reg, u32 *val)
1310 {
1311 switch (reg) {
1312 case GRBM_STATUS:
1313 case GRBM_STATUS2:
1314 case GRBM_STATUS_SE0:
1315 case GRBM_STATUS_SE1:
1316 case SRBM_STATUS:
1317 case SRBM_STATUS2:
1318 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
1319 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):
1320 case UVD_STATUS:
1321 *val = RREG32(reg);
1322 return 0;
1323 default:
1324 return -EINVAL;
1325 }
1326 }
1327
1328 #define PCIE_BUS_CLK 10000
1329 #define TCLK (PCIE_BUS_CLK / 10)
1330
1331 /**
1332 * si_get_xclk - get the xclk
1333 *
1334 * @rdev: radeon_device pointer
1335 *
1336 * Returns the reference clock used by the gfx engine
1337 * (SI).
1338 */
1339 u32 si_get_xclk(struct radeon_device *rdev)
1340 {
1341 u32 reference_clock = rdev->clock.spll.reference_freq;
1342 u32 tmp;
1343
1344 tmp = RREG32(CG_CLKPIN_CNTL_2);
1345 if (tmp & MUX_TCLK_TO_XCLK)
1346 return TCLK;
1347
1348 tmp = RREG32(CG_CLKPIN_CNTL);
1349 if (tmp & XTALIN_DIVIDE)
1350 return reference_clock / 4;
1351
1352 return reference_clock;
1353 }
1354
1355 /* get temperature in millidegrees */
1356 int si_get_temp(struct radeon_device *rdev)
1357 {
1358 u32 temp;
1359 int actual_temp = 0;
1360
1361 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
1362 CTF_TEMP_SHIFT;
1363
1364 if (temp & 0x200)
1365 actual_temp = 255;
1366 else
1367 actual_temp = temp & 0x1ff;
1368
1369 actual_temp = (actual_temp * 1000);
1370
1371 return actual_temp;
1372 }
1373
1374 #define TAHITI_IO_MC_REGS_SIZE 36
1375
1376 static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1377 {0x0000006f, 0x03044000},
1378 {0x00000070, 0x0480c018},
1379 {0x00000071, 0x00000040},
1380 {0x00000072, 0x01000000},
1381 {0x00000074, 0x000000ff},
1382 {0x00000075, 0x00143400},
1383 {0x00000076, 0x08ec0800},
1384 {0x00000077, 0x040000cc},
1385 {0x00000079, 0x00000000},
1386 {0x0000007a, 0x21000409},
1387 {0x0000007c, 0x00000000},
1388 {0x0000007d, 0xe8000000},
1389 {0x0000007e, 0x044408a8},
1390 {0x0000007f, 0x00000003},
1391 {0x00000080, 0x00000000},
1392 {0x00000081, 0x01000000},
1393 {0x00000082, 0x02000000},
1394 {0x00000083, 0x00000000},
1395 {0x00000084, 0xe3f3e4f4},
1396 {0x00000085, 0x00052024},
1397 {0x00000087, 0x00000000},
1398 {0x00000088, 0x66036603},
1399 {0x00000089, 0x01000000},
1400 {0x0000008b, 0x1c0a0000},
1401 {0x0000008c, 0xff010000},
1402 {0x0000008e, 0xffffefff},
1403 {0x0000008f, 0xfff3efff},
1404 {0x00000090, 0xfff3efbf},
1405 {0x00000094, 0x00101101},
1406 {0x00000095, 0x00000fff},
1407 {0x00000096, 0x00116fff},
1408 {0x00000097, 0x60010000},
1409 {0x00000098, 0x10010000},
1410 {0x00000099, 0x00006000},
1411 {0x0000009a, 0x00001000},
1412 {0x0000009f, 0x00a77400}
1413 };
1414
1415 static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1416 {0x0000006f, 0x03044000},
1417 {0x00000070, 0x0480c018},
1418 {0x00000071, 0x00000040},
1419 {0x00000072, 0x01000000},
1420 {0x00000074, 0x000000ff},
1421 {0x00000075, 0x00143400},
1422 {0x00000076, 0x08ec0800},
1423 {0x00000077, 0x040000cc},
1424 {0x00000079, 0x00000000},
1425 {0x0000007a, 0x21000409},
1426 {0x0000007c, 0x00000000},
1427 {0x0000007d, 0xe8000000},
1428 {0x0000007e, 0x044408a8},
1429 {0x0000007f, 0x00000003},
1430 {0x00000080, 0x00000000},
1431 {0x00000081, 0x01000000},
1432 {0x00000082, 0x02000000},
1433 {0x00000083, 0x00000000},
1434 {0x00000084, 0xe3f3e4f4},
1435 {0x00000085, 0x00052024},
1436 {0x00000087, 0x00000000},
1437 {0x00000088, 0x66036603},
1438 {0x00000089, 0x01000000},
1439 {0x0000008b, 0x1c0a0000},
1440 {0x0000008c, 0xff010000},
1441 {0x0000008e, 0xffffefff},
1442 {0x0000008f, 0xfff3efff},
1443 {0x00000090, 0xfff3efbf},
1444 {0x00000094, 0x00101101},
1445 {0x00000095, 0x00000fff},
1446 {0x00000096, 0x00116fff},
1447 {0x00000097, 0x60010000},
1448 {0x00000098, 0x10010000},
1449 {0x00000099, 0x00006000},
1450 {0x0000009a, 0x00001000},
1451 {0x0000009f, 0x00a47400}
1452 };
1453
1454 static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1455 {0x0000006f, 0x03044000},
1456 {0x00000070, 0x0480c018},
1457 {0x00000071, 0x00000040},
1458 {0x00000072, 0x01000000},
1459 {0x00000074, 0x000000ff},
1460 {0x00000075, 0x00143400},
1461 {0x00000076, 0x08ec0800},
1462 {0x00000077, 0x040000cc},
1463 {0x00000079, 0x00000000},
1464 {0x0000007a, 0x21000409},
1465 {0x0000007c, 0x00000000},
1466 {0x0000007d, 0xe8000000},
1467 {0x0000007e, 0x044408a8},
1468 {0x0000007f, 0x00000003},
1469 {0x00000080, 0x00000000},
1470 {0x00000081, 0x01000000},
1471 {0x00000082, 0x02000000},
1472 {0x00000083, 0x00000000},
1473 {0x00000084, 0xe3f3e4f4},
1474 {0x00000085, 0x00052024},
1475 {0x00000087, 0x00000000},
1476 {0x00000088, 0x66036603},
1477 {0x00000089, 0x01000000},
1478 {0x0000008b, 0x1c0a0000},
1479 {0x0000008c, 0xff010000},
1480 {0x0000008e, 0xffffefff},
1481 {0x0000008f, 0xfff3efff},
1482 {0x00000090, 0xfff3efbf},
1483 {0x00000094, 0x00101101},
1484 {0x00000095, 0x00000fff},
1485 {0x00000096, 0x00116fff},
1486 {0x00000097, 0x60010000},
1487 {0x00000098, 0x10010000},
1488 {0x00000099, 0x00006000},
1489 {0x0000009a, 0x00001000},
1490 {0x0000009f, 0x00a37400}
1491 };
1492
1493 static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1494 {0x0000006f, 0x03044000},
1495 {0x00000070, 0x0480c018},
1496 {0x00000071, 0x00000040},
1497 {0x00000072, 0x01000000},
1498 {0x00000074, 0x000000ff},
1499 {0x00000075, 0x00143400},
1500 {0x00000076, 0x08ec0800},
1501 {0x00000077, 0x040000cc},
1502 {0x00000079, 0x00000000},
1503 {0x0000007a, 0x21000409},
1504 {0x0000007c, 0x00000000},
1505 {0x0000007d, 0xe8000000},
1506 {0x0000007e, 0x044408a8},
1507 {0x0000007f, 0x00000003},
1508 {0x00000080, 0x00000000},
1509 {0x00000081, 0x01000000},
1510 {0x00000082, 0x02000000},
1511 {0x00000083, 0x00000000},
1512 {0x00000084, 0xe3f3e4f4},
1513 {0x00000085, 0x00052024},
1514 {0x00000087, 0x00000000},
1515 {0x00000088, 0x66036603},
1516 {0x00000089, 0x01000000},
1517 {0x0000008b, 0x1c0a0000},
1518 {0x0000008c, 0xff010000},
1519 {0x0000008e, 0xffffefff},
1520 {0x0000008f, 0xfff3efff},
1521 {0x00000090, 0xfff3efbf},
1522 {0x00000094, 0x00101101},
1523 {0x00000095, 0x00000fff},
1524 {0x00000096, 0x00116fff},
1525 {0x00000097, 0x60010000},
1526 {0x00000098, 0x10010000},
1527 {0x00000099, 0x00006000},
1528 {0x0000009a, 0x00001000},
1529 {0x0000009f, 0x00a17730}
1530 };
1531
1532 static const u32 hainan_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1533 {0x0000006f, 0x03044000},
1534 {0x00000070, 0x0480c018},
1535 {0x00000071, 0x00000040},
1536 {0x00000072, 0x01000000},
1537 {0x00000074, 0x000000ff},
1538 {0x00000075, 0x00143400},
1539 {0x00000076, 0x08ec0800},
1540 {0x00000077, 0x040000cc},
1541 {0x00000079, 0x00000000},
1542 {0x0000007a, 0x21000409},
1543 {0x0000007c, 0x00000000},
1544 {0x0000007d, 0xe8000000},
1545 {0x0000007e, 0x044408a8},
1546 {0x0000007f, 0x00000003},
1547 {0x00000080, 0x00000000},
1548 {0x00000081, 0x01000000},
1549 {0x00000082, 0x02000000},
1550 {0x00000083, 0x00000000},
1551 {0x00000084, 0xe3f3e4f4},
1552 {0x00000085, 0x00052024},
1553 {0x00000087, 0x00000000},
1554 {0x00000088, 0x66036603},
1555 {0x00000089, 0x01000000},
1556 {0x0000008b, 0x1c0a0000},
1557 {0x0000008c, 0xff010000},
1558 {0x0000008e, 0xffffefff},
1559 {0x0000008f, 0xfff3efff},
1560 {0x00000090, 0xfff3efbf},
1561 {0x00000094, 0x00101101},
1562 {0x00000095, 0x00000fff},
1563 {0x00000096, 0x00116fff},
1564 {0x00000097, 0x60010000},
1565 {0x00000098, 0x10010000},
1566 {0x00000099, 0x00006000},
1567 {0x0000009a, 0x00001000},
1568 {0x0000009f, 0x00a07730}
1569 };
1570
1571 /* ucode loading */
1572 int si_mc_load_microcode(struct radeon_device *rdev)
1573 {
1574 const __be32 *fw_data = NULL;
1575 const __le32 *new_fw_data = NULL;
1576 u32 running;
1577 u32 *io_mc_regs = NULL;
1578 const __le32 *new_io_mc_regs = NULL;
1579 int i, regs_size, ucode_size;
1580
1581 if (!rdev->mc_fw)
1582 return -EINVAL;
1583
1584 if (rdev->new_fw) {
1585 const struct mc_firmware_header_v1_0 *hdr =
1586 (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data;
1587
1588 radeon_ucode_print_mc_hdr(&hdr->header);
1589 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
1590 new_io_mc_regs = (const __le32 *)
1591 (rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
1592 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1593 new_fw_data = (const __le32 *)
1594 (rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1595 } else {
1596 ucode_size = rdev->mc_fw->size / 4;
1597
1598 switch (rdev->family) {
1599 case CHIP_TAHITI:
1600 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
1601 regs_size = TAHITI_IO_MC_REGS_SIZE;
1602 break;
1603 case CHIP_PITCAIRN:
1604 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
1605 regs_size = TAHITI_IO_MC_REGS_SIZE;
1606 break;
1607 case CHIP_VERDE:
1608 default:
1609 io_mc_regs = (u32 *)&verde_io_mc_regs;
1610 regs_size = TAHITI_IO_MC_REGS_SIZE;
1611 break;
1612 case CHIP_OLAND:
1613 io_mc_regs = (u32 *)&oland_io_mc_regs;
1614 regs_size = TAHITI_IO_MC_REGS_SIZE;
1615 break;
1616 case CHIP_HAINAN:
1617 io_mc_regs = (u32 *)&hainan_io_mc_regs;
1618 regs_size = TAHITI_IO_MC_REGS_SIZE;
1619 break;
1620 }
1621 fw_data = (const __be32 *)rdev->mc_fw->data;
1622 }
1623
1624 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
1625
1626 if (running == 0) {
1627 /* reset the engine and set to writable */
1628 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1629 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
1630
1631 /* load mc io regs */
1632 for (i = 0; i < regs_size; i++) {
1633 if (rdev->new_fw) {
1634 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
1635 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
1636 } else {
1637 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
1638 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
1639 }
1640 }
1641 /* load the MC ucode */
1642 for (i = 0; i < ucode_size; i++) {
1643 if (rdev->new_fw)
1644 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
1645 else
1646 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
1647 }
1648
1649 /* put the engine back into the active state */
1650 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1651 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
1652 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
1653
1654 /* wait for training to complete */
1655 for (i = 0; i < rdev->usec_timeout; i++) {
1656 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
1657 break;
1658 udelay(1);
1659 }
1660 for (i = 0; i < rdev->usec_timeout; i++) {
1661 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
1662 break;
1663 udelay(1);
1664 }
1665 }
1666
1667 return 0;
1668 }
1669
1670 static int si_init_microcode(struct radeon_device *rdev)
1671 {
1672 const char *chip_name;
1673 const char *new_chip_name;
1674 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
1675 size_t smc_req_size, mc2_req_size;
1676 char fw_name[30];
1677 int err;
1678 int new_fw = 0;
1679 bool new_smc = false;
1680 bool si58_fw = false;
1681 bool banks2_fw = false;
1682
1683 DRM_DEBUG("\n");
1684
1685 switch (rdev->family) {
1686 case CHIP_TAHITI:
1687 chip_name = "TAHITI";
1688 new_chip_name = "tahiti";
1689 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1690 me_req_size = SI_PM4_UCODE_SIZE * 4;
1691 ce_req_size = SI_CE_UCODE_SIZE * 4;
1692 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1693 mc_req_size = SI_MC_UCODE_SIZE * 4;
1694 mc2_req_size = TAHITI_MC_UCODE_SIZE * 4;
1695 smc_req_size = ALIGN(TAHITI_SMC_UCODE_SIZE, 4);
1696 break;
1697 case CHIP_PITCAIRN:
1698 chip_name = "PITCAIRN";
1699 if ((rdev->pdev->revision == 0x81) &&
1700 ((rdev->pdev->device == 0x6810) ||
1701 (rdev->pdev->device == 0x6811)))
1702 new_smc = true;
1703 new_chip_name = "pitcairn";
1704 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1705 me_req_size = SI_PM4_UCODE_SIZE * 4;
1706 ce_req_size = SI_CE_UCODE_SIZE * 4;
1707 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1708 mc_req_size = SI_MC_UCODE_SIZE * 4;
1709 mc2_req_size = PITCAIRN_MC_UCODE_SIZE * 4;
1710 smc_req_size = ALIGN(PITCAIRN_SMC_UCODE_SIZE, 4);
1711 break;
1712 case CHIP_VERDE:
1713 chip_name = "VERDE";
1714 if (((rdev->pdev->device == 0x6820) &&
1715 ((rdev->pdev->revision == 0x81) ||
1716 (rdev->pdev->revision == 0x83))) ||
1717 ((rdev->pdev->device == 0x6821) &&
1718 ((rdev->pdev->revision == 0x83) ||
1719 (rdev->pdev->revision == 0x87))) ||
1720 ((rdev->pdev->revision == 0x87) &&
1721 ((rdev->pdev->device == 0x6823) ||
1722 (rdev->pdev->device == 0x682b))))
1723 new_smc = true;
1724 new_chip_name = "verde";
1725 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1726 me_req_size = SI_PM4_UCODE_SIZE * 4;
1727 ce_req_size = SI_CE_UCODE_SIZE * 4;
1728 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1729 mc_req_size = SI_MC_UCODE_SIZE * 4;
1730 mc2_req_size = VERDE_MC_UCODE_SIZE * 4;
1731 smc_req_size = ALIGN(VERDE_SMC_UCODE_SIZE, 4);
1732 break;
1733 case CHIP_OLAND:
1734 chip_name = "OLAND";
1735 if (((rdev->pdev->revision == 0x81) &&
1736 ((rdev->pdev->device == 0x6600) ||
1737 (rdev->pdev->device == 0x6604) ||
1738 (rdev->pdev->device == 0x6605) ||
1739 (rdev->pdev->device == 0x6610))) ||
1740 ((rdev->pdev->revision == 0x83) &&
1741 (rdev->pdev->device == 0x6610)))
1742 new_smc = true;
1743 new_chip_name = "oland";
1744 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1745 me_req_size = SI_PM4_UCODE_SIZE * 4;
1746 ce_req_size = SI_CE_UCODE_SIZE * 4;
1747 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1748 mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
1749 smc_req_size = ALIGN(OLAND_SMC_UCODE_SIZE, 4);
1750 break;
1751 case CHIP_HAINAN:
1752 chip_name = "HAINAN";
1753 if (((rdev->pdev->revision == 0x81) &&
1754 (rdev->pdev->device == 0x6660)) ||
1755 ((rdev->pdev->revision == 0x83) &&
1756 ((rdev->pdev->device == 0x6660) ||
1757 (rdev->pdev->device == 0x6663) ||
1758 (rdev->pdev->device == 0x6665) ||
1759 (rdev->pdev->device == 0x6667))))
1760 new_smc = true;
1761 else if ((rdev->pdev->revision == 0xc3) &&
1762 (rdev->pdev->device == 0x6665))
1763 banks2_fw = true;
1764 new_chip_name = "hainan";
1765 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1766 me_req_size = SI_PM4_UCODE_SIZE * 4;
1767 ce_req_size = SI_CE_UCODE_SIZE * 4;
1768 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1769 mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
1770 smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4);
1771 break;
1772 default: BUG();
1773 }
1774
1775 /* this memory configuration requires special firmware */
1776 if (((RREG32(MC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
1777 si58_fw = true;
1778
1779 DRM_INFO("Loading %s Microcode\n", new_chip_name);
1780
1781 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", new_chip_name);
1782 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
1783 if (err) {
1784 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1785 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
1786 if (err)
1787 goto out;
1788 if (rdev->pfp_fw->size != pfp_req_size) {
1789 pr_err("si_cp: Bogus length %zu in firmware \"%s\"\n",
1790 rdev->pfp_fw->size, fw_name);
1791 err = -EINVAL;
1792 goto out;
1793 }
1794 } else {
1795 err = radeon_ucode_validate(rdev->pfp_fw);
1796 if (err) {
1797 pr_err("si_cp: validation failed for firmware \"%s\"\n",
1798 fw_name);
1799 goto out;
1800 } else {
1801 new_fw++;
1802 }
1803 }
1804
1805 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", new_chip_name);
1806 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1807 if (err) {
1808 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1809 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1810 if (err)
1811 goto out;
1812 if (rdev->me_fw->size != me_req_size) {
1813 pr_err("si_cp: Bogus length %zu in firmware \"%s\"\n",
1814 rdev->me_fw->size, fw_name);
1815 err = -EINVAL;
1816 }
1817 } else {
1818 err = radeon_ucode_validate(rdev->me_fw);
1819 if (err) {
1820 pr_err("si_cp: validation failed for firmware \"%s\"\n",
1821 fw_name);
1822 goto out;
1823 } else {
1824 new_fw++;
1825 }
1826 }
1827
1828 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", new_chip_name);
1829 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
1830 if (err) {
1831 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
1832 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
1833 if (err)
1834 goto out;
1835 if (rdev->ce_fw->size != ce_req_size) {
1836 pr_err("si_cp: Bogus length %zu in firmware \"%s\"\n",
1837 rdev->ce_fw->size, fw_name);
1838 err = -EINVAL;
1839 }
1840 } else {
1841 err = radeon_ucode_validate(rdev->ce_fw);
1842 if (err) {
1843 pr_err("si_cp: validation failed for firmware \"%s\"\n",
1844 fw_name);
1845 goto out;
1846 } else {
1847 new_fw++;
1848 }
1849 }
1850
1851 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", new_chip_name);
1852 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
1853 if (err) {
1854 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
1855 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
1856 if (err)
1857 goto out;
1858 if (rdev->rlc_fw->size != rlc_req_size) {
1859 pr_err("si_rlc: Bogus length %zu in firmware \"%s\"\n",
1860 rdev->rlc_fw->size, fw_name);
1861 err = -EINVAL;
1862 }
1863 } else {
1864 err = radeon_ucode_validate(rdev->rlc_fw);
1865 if (err) {
1866 pr_err("si_cp: validation failed for firmware \"%s\"\n",
1867 fw_name);
1868 goto out;
1869 } else {
1870 new_fw++;
1871 }
1872 }
1873
1874 if (si58_fw)
1875 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin");
1876 else
1877 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", new_chip_name);
1878 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1879 if (err) {
1880 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name);
1881 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1882 if (err) {
1883 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
1884 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1885 if (err)
1886 goto out;
1887 }
1888 if ((rdev->mc_fw->size != mc_req_size) &&
1889 (rdev->mc_fw->size != mc2_req_size)) {
1890 pr_err("si_mc: Bogus length %zu in firmware \"%s\"\n",
1891 rdev->mc_fw->size, fw_name);
1892 err = -EINVAL;
1893 }
1894 DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
1895 } else {
1896 err = radeon_ucode_validate(rdev->mc_fw);
1897 if (err) {
1898 pr_err("si_cp: validation failed for firmware \"%s\"\n",
1899 fw_name);
1900 goto out;
1901 } else {
1902 new_fw++;
1903 }
1904 }
1905
1906 if (banks2_fw)
1907 snprintf(fw_name, sizeof(fw_name), "radeon/banks_k_2_smc.bin");
1908 else if (new_smc)
1909 snprintf(fw_name, sizeof(fw_name), "radeon/%s_k_smc.bin", new_chip_name);
1910 else
1911 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", new_chip_name);
1912 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
1913 if (err) {
1914 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
1915 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
1916 if (err) {
1917 pr_err("smc: error loading firmware \"%s\"\n", fw_name);
1918 release_firmware(rdev->smc_fw);
1919 rdev->smc_fw = NULL;
1920 err = 0;
1921 } else if (rdev->smc_fw->size != smc_req_size) {
1922 pr_err("si_smc: Bogus length %zu in firmware \"%s\"\n",
1923 rdev->smc_fw->size, fw_name);
1924 err = -EINVAL;
1925 }
1926 } else {
1927 err = radeon_ucode_validate(rdev->smc_fw);
1928 if (err) {
1929 pr_err("si_cp: validation failed for firmware \"%s\"\n",
1930 fw_name);
1931 goto out;
1932 } else {
1933 new_fw++;
1934 }
1935 }
1936
1937 if (new_fw == 0) {
1938 rdev->new_fw = false;
1939 } else if (new_fw < 6) {
1940 pr_err("si_fw: mixing new and old firmware!\n");
1941 err = -EINVAL;
1942 } else {
1943 rdev->new_fw = true;
1944 }
1945 out:
1946 if (err) {
1947 if (err != -EINVAL)
1948 pr_err("si_cp: Failed to load firmware \"%s\"\n",
1949 fw_name);
1950 release_firmware(rdev->pfp_fw);
1951 rdev->pfp_fw = NULL;
1952 release_firmware(rdev->me_fw);
1953 rdev->me_fw = NULL;
1954 release_firmware(rdev->ce_fw);
1955 rdev->ce_fw = NULL;
1956 release_firmware(rdev->rlc_fw);
1957 rdev->rlc_fw = NULL;
1958 release_firmware(rdev->mc_fw);
1959 rdev->mc_fw = NULL;
1960 release_firmware(rdev->smc_fw);
1961 rdev->smc_fw = NULL;
1962 }
1963 return err;
1964 }
1965
1966 /* watermark setup */
1967 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
1968 struct radeon_crtc *radeon_crtc,
1969 struct drm_display_mode *mode,
1970 struct drm_display_mode *other_mode)
1971 {
1972 u32 tmp, buffer_alloc, i;
1973 u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
1974 /*
1975 * Line Buffer Setup
1976 * There are 3 line buffers, each one shared by 2 display controllers.
1977 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1978 * the display controllers. The paritioning is done via one of four
1979 * preset allocations specified in bits 21:20:
1980 * 0 - half lb
1981 * 2 - whole lb, other crtc must be disabled
1982 */
1983 /* this can get tricky if we have two large displays on a paired group
1984 * of crtcs. Ideally for multiple large displays we'd assign them to
1985 * non-linked crtcs for maximum line buffer allocation.
1986 */
1987 if (radeon_crtc->base.enabled && mode) {
1988 if (other_mode) {
1989 tmp = 0; /* 1/2 */
1990 buffer_alloc = 1;
1991 } else {
1992 tmp = 2; /* whole */
1993 buffer_alloc = 2;
1994 }
1995 } else {
1996 tmp = 0;
1997 buffer_alloc = 0;
1998 }
1999
2000 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
2001 DC_LB_MEMORY_CONFIG(tmp));
2002
2003 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
2004 DMIF_BUFFERS_ALLOCATED(buffer_alloc));
2005 for (i = 0; i < rdev->usec_timeout; i++) {
2006 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
2007 DMIF_BUFFERS_ALLOCATED_COMPLETED)
2008 break;
2009 udelay(1);
2010 }
2011
2012 if (radeon_crtc->base.enabled && mode) {
2013 switch (tmp) {
2014 case 0:
2015 default:
2016 return 4096 * 2;
2017 case 2:
2018 return 8192 * 2;
2019 }
2020 }
2021
2022 /* controller not enabled, so no lb used */
2023 return 0;
2024 }
2025
2026 static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
2027 {
2028 u32 tmp = RREG32(MC_SHARED_CHMAP);
2029
2030 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2031 case 0:
2032 default:
2033 return 1;
2034 case 1:
2035 return 2;
2036 case 2:
2037 return 4;
2038 case 3:
2039 return 8;
2040 case 4:
2041 return 3;
2042 case 5:
2043 return 6;
2044 case 6:
2045 return 10;
2046 case 7:
2047 return 12;
2048 case 8:
2049 return 16;
2050 }
2051 }
2052
2053 struct dce6_wm_params {
2054 u32 dram_channels; /* number of dram channels */
2055 u32 yclk; /* bandwidth per dram data pin in kHz */
2056 u32 sclk; /* engine clock in kHz */
2057 u32 disp_clk; /* display clock in kHz */
2058 u32 src_width; /* viewport width */
2059 u32 active_time; /* active display time in ns */
2060 u32 blank_time; /* blank time in ns */
2061 bool interlaced; /* mode is interlaced */
2062 fixed20_12 vsc; /* vertical scale ratio */
2063 u32 num_heads; /* number of active crtcs */
2064 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
2065 u32 lb_size; /* line buffer allocated to pipe */
2066 u32 vtaps; /* vertical scaler taps */
2067 };
2068
2069 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
2070 {
2071 /* Calculate raw DRAM Bandwidth */
2072 fixed20_12 dram_efficiency; /* 0.7 */
2073 fixed20_12 yclk, dram_channels, bandwidth;
2074 fixed20_12 a;
2075
2076 a.full = dfixed_const(1000);
2077 yclk.full = dfixed_const(wm->yclk);
2078 yclk.full = dfixed_div(yclk, a);
2079 dram_channels.full = dfixed_const(wm->dram_channels * 4);
2080 a.full = dfixed_const(10);
2081 dram_efficiency.full = dfixed_const(7);
2082 dram_efficiency.full = dfixed_div(dram_efficiency, a);
2083 bandwidth.full = dfixed_mul(dram_channels, yclk);
2084 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
2085
2086 return dfixed_trunc(bandwidth);
2087 }
2088
2089 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
2090 {
2091 /* Calculate DRAM Bandwidth and the part allocated to display. */
2092 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
2093 fixed20_12 yclk, dram_channels, bandwidth;
2094 fixed20_12 a;
2095
2096 a.full = dfixed_const(1000);
2097 yclk.full = dfixed_const(wm->yclk);
2098 yclk.full = dfixed_div(yclk, a);
2099 dram_channels.full = dfixed_const(wm->dram_channels * 4);
2100 a.full = dfixed_const(10);
2101 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
2102 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
2103 bandwidth.full = dfixed_mul(dram_channels, yclk);
2104 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
2105
2106 return dfixed_trunc(bandwidth);
2107 }
2108
2109 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
2110 {
2111 /* Calculate the display Data return Bandwidth */
2112 fixed20_12 return_efficiency; /* 0.8 */
2113 fixed20_12 sclk, bandwidth;
2114 fixed20_12 a;
2115
2116 a.full = dfixed_const(1000);
2117 sclk.full = dfixed_const(wm->sclk);
2118 sclk.full = dfixed_div(sclk, a);
2119 a.full = dfixed_const(10);
2120 return_efficiency.full = dfixed_const(8);
2121 return_efficiency.full = dfixed_div(return_efficiency, a);
2122 a.full = dfixed_const(32);
2123 bandwidth.full = dfixed_mul(a, sclk);
2124 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
2125
2126 return dfixed_trunc(bandwidth);
2127 }
2128
2129 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
2130 {
2131 return 32;
2132 }
2133
2134 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
2135 {
2136 /* Calculate the DMIF Request Bandwidth */
2137 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
2138 fixed20_12 disp_clk, sclk, bandwidth;
2139 fixed20_12 a, b1, b2;
2140 u32 min_bandwidth;
2141
2142 a.full = dfixed_const(1000);
2143 disp_clk.full = dfixed_const(wm->disp_clk);
2144 disp_clk.full = dfixed_div(disp_clk, a);
2145 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
2146 b1.full = dfixed_mul(a, disp_clk);
2147
2148 a.full = dfixed_const(1000);
2149 sclk.full = dfixed_const(wm->sclk);
2150 sclk.full = dfixed_div(sclk, a);
2151 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
2152 b2.full = dfixed_mul(a, sclk);
2153
2154 a.full = dfixed_const(10);
2155 disp_clk_request_efficiency.full = dfixed_const(8);
2156 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
2157
2158 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
2159
2160 a.full = dfixed_const(min_bandwidth);
2161 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
2162
2163 return dfixed_trunc(bandwidth);
2164 }
2165
2166 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
2167 {
2168 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
2169 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
2170 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
2171 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
2172
2173 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
2174 }
2175
2176 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
2177 {
2178 /* Calculate the display mode Average Bandwidth
2179 * DisplayMode should contain the source and destination dimensions,
2180 * timing, etc.
2181 */
2182 fixed20_12 bpp;
2183 fixed20_12 line_time;
2184 fixed20_12 src_width;
2185 fixed20_12 bandwidth;
2186 fixed20_12 a;
2187
2188 a.full = dfixed_const(1000);
2189 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
2190 line_time.full = dfixed_div(line_time, a);
2191 bpp.full = dfixed_const(wm->bytes_per_pixel);
2192 src_width.full = dfixed_const(wm->src_width);
2193 bandwidth.full = dfixed_mul(src_width, bpp);
2194 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
2195 bandwidth.full = dfixed_div(bandwidth, line_time);
2196
2197 return dfixed_trunc(bandwidth);
2198 }
2199
2200 static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
2201 {
2202 /* First calcualte the latency in ns */
2203 u32 mc_latency = 2000; /* 2000 ns. */
2204 u32 available_bandwidth = dce6_available_bandwidth(wm);
2205 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
2206 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
2207 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
2208 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
2209 (wm->num_heads * cursor_line_pair_return_time);
2210 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
2211 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
2212 u32 tmp, dmif_size = 12288;
2213 fixed20_12 a, b, c;
2214
2215 if (wm->num_heads == 0)
2216 return 0;
2217
2218 a.full = dfixed_const(2);
2219 b.full = dfixed_const(1);
2220 if ((wm->vsc.full > a.full) ||
2221 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
2222 (wm->vtaps >= 5) ||
2223 ((wm->vsc.full >= a.full) && wm->interlaced))
2224 max_src_lines_per_dst_line = 4;
2225 else
2226 max_src_lines_per_dst_line = 2;
2227
2228 a.full = dfixed_const(available_bandwidth);
2229 b.full = dfixed_const(wm->num_heads);
2230 a.full = dfixed_div(a, b);
2231 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
2232 tmp = min(dfixed_trunc(a), tmp);
2233
2234 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
2235
2236 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
2237 b.full = dfixed_const(1000);
2238 c.full = dfixed_const(lb_fill_bw);
2239 b.full = dfixed_div(c, b);
2240 a.full = dfixed_div(a, b);
2241 line_fill_time = dfixed_trunc(a);
2242
2243 if (line_fill_time < wm->active_time)
2244 return latency;
2245 else
2246 return latency + (line_fill_time - wm->active_time);
2247
2248 }
2249
2250 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
2251 {
2252 if (dce6_average_bandwidth(wm) <=
2253 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
2254 return true;
2255 else
2256 return false;
2257 };
2258
2259 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
2260 {
2261 if (dce6_average_bandwidth(wm) <=
2262 (dce6_available_bandwidth(wm) / wm->num_heads))
2263 return true;
2264 else
2265 return false;
2266 };
2267
2268 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
2269 {
2270 u32 lb_partitions = wm->lb_size / wm->src_width;
2271 u32 line_time = wm->active_time + wm->blank_time;
2272 u32 latency_tolerant_lines;
2273 u32 latency_hiding;
2274 fixed20_12 a;
2275
2276 a.full = dfixed_const(1);
2277 if (wm->vsc.full > a.full)
2278 latency_tolerant_lines = 1;
2279 else {
2280 if (lb_partitions <= (wm->vtaps + 1))
2281 latency_tolerant_lines = 1;
2282 else
2283 latency_tolerant_lines = 2;
2284 }
2285
2286 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
2287
2288 if (dce6_latency_watermark(wm) <= latency_hiding)
2289 return true;
2290 else
2291 return false;
2292 }
2293
2294 static void dce6_program_watermarks(struct radeon_device *rdev,
2295 struct radeon_crtc *radeon_crtc,
2296 u32 lb_size, u32 num_heads)
2297 {
2298 struct drm_display_mode *mode = &radeon_crtc->base.mode;
2299 struct dce6_wm_params wm_low, wm_high;
2300 u32 dram_channels;
2301 u32 active_time;
2302 u32 line_time = 0;
2303 u32 latency_watermark_a = 0, latency_watermark_b = 0;
2304 u32 priority_a_mark = 0, priority_b_mark = 0;
2305 u32 priority_a_cnt = PRIORITY_OFF;
2306 u32 priority_b_cnt = PRIORITY_OFF;
2307 u32 tmp, arb_control3;
2308 fixed20_12 a, b, c;
2309
2310 if (radeon_crtc->base.enabled && num_heads && mode) {
2311 active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
2312 line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
2313 priority_a_cnt = 0;
2314 priority_b_cnt = 0;
2315
2316 if (rdev->family == CHIP_ARUBA)
2317 dram_channels = evergreen_get_number_of_dram_channels(rdev);
2318 else
2319 dram_channels = si_get_number_of_dram_channels(rdev);
2320
2321 /* watermark for high clocks */
2322 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2323 wm_high.yclk =
2324 radeon_dpm_get_mclk(rdev, false) * 10;
2325 wm_high.sclk =
2326 radeon_dpm_get_sclk(rdev, false) * 10;
2327 } else {
2328 wm_high.yclk = rdev->pm.current_mclk * 10;
2329 wm_high.sclk = rdev->pm.current_sclk * 10;
2330 }
2331
2332 wm_high.disp_clk = mode->clock;
2333 wm_high.src_width = mode->crtc_hdisplay;
2334 wm_high.active_time = active_time;
2335 wm_high.blank_time = line_time - wm_high.active_time;
2336 wm_high.interlaced = false;
2337 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2338 wm_high.interlaced = true;
2339 wm_high.vsc = radeon_crtc->vsc;
2340 wm_high.vtaps = 1;
2341 if (radeon_crtc->rmx_type != RMX_OFF)
2342 wm_high.vtaps = 2;
2343 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
2344 wm_high.lb_size = lb_size;
2345 wm_high.dram_channels = dram_channels;
2346 wm_high.num_heads = num_heads;
2347
2348 /* watermark for low clocks */
2349 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2350 wm_low.yclk =
2351 radeon_dpm_get_mclk(rdev, true) * 10;
2352 wm_low.sclk =
2353 radeon_dpm_get_sclk(rdev, true) * 10;
2354 } else {
2355 wm_low.yclk = rdev->pm.current_mclk * 10;
2356 wm_low.sclk = rdev->pm.current_sclk * 10;
2357 }
2358
2359 wm_low.disp_clk = mode->clock;
2360 wm_low.src_width = mode->crtc_hdisplay;
2361 wm_low.active_time = active_time;
2362 wm_low.blank_time = line_time - wm_low.active_time;
2363 wm_low.interlaced = false;
2364 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2365 wm_low.interlaced = true;
2366 wm_low.vsc = radeon_crtc->vsc;
2367 wm_low.vtaps = 1;
2368 if (radeon_crtc->rmx_type != RMX_OFF)
2369 wm_low.vtaps = 2;
2370 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
2371 wm_low.lb_size = lb_size;
2372 wm_low.dram_channels = dram_channels;
2373 wm_low.num_heads = num_heads;
2374
2375 /* set for high clocks */
2376 latency_watermark_a = min(dce6_latency_watermark(&wm_high), (u32)65535);
2377 /* set for low clocks */
2378 latency_watermark_b = min(dce6_latency_watermark(&wm_low), (u32)65535);
2379
2380 /* possibly force display priority to high */
2381 /* should really do this at mode validation time... */
2382 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
2383 !dce6_average_bandwidth_vs_available_bandwidth(&wm_high) ||
2384 !dce6_check_latency_hiding(&wm_high) ||
2385 (rdev->disp_priority == 2)) {
2386 DRM_DEBUG_KMS("force priority to high\n");
2387 priority_a_cnt |= PRIORITY_ALWAYS_ON;
2388 priority_b_cnt |= PRIORITY_ALWAYS_ON;
2389 }
2390 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
2391 !dce6_average_bandwidth_vs_available_bandwidth(&wm_low) ||
2392 !dce6_check_latency_hiding(&wm_low) ||
2393 (rdev->disp_priority == 2)) {
2394 DRM_DEBUG_KMS("force priority to high\n");
2395 priority_a_cnt |= PRIORITY_ALWAYS_ON;
2396 priority_b_cnt |= PRIORITY_ALWAYS_ON;
2397 }
2398
2399 a.full = dfixed_const(1000);
2400 b.full = dfixed_const(mode->clock);
2401 b.full = dfixed_div(b, a);
2402 c.full = dfixed_const(latency_watermark_a);
2403 c.full = dfixed_mul(c, b);
2404 c.full = dfixed_mul(c, radeon_crtc->hsc);
2405 c.full = dfixed_div(c, a);
2406 a.full = dfixed_const(16);
2407 c.full = dfixed_div(c, a);
2408 priority_a_mark = dfixed_trunc(c);
2409 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
2410
2411 a.full = dfixed_const(1000);
2412 b.full = dfixed_const(mode->clock);
2413 b.full = dfixed_div(b, a);
2414 c.full = dfixed_const(latency_watermark_b);
2415 c.full = dfixed_mul(c, b);
2416 c.full = dfixed_mul(c, radeon_crtc->hsc);
2417 c.full = dfixed_div(c, a);
2418 a.full = dfixed_const(16);
2419 c.full = dfixed_div(c, a);
2420 priority_b_mark = dfixed_trunc(c);
2421 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
2422
2423 /* Save number of lines the linebuffer leads before the scanout */
2424 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
2425 }
2426
2427 /* select wm A */
2428 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2429 tmp = arb_control3;
2430 tmp &= ~LATENCY_WATERMARK_MASK(3);
2431 tmp |= LATENCY_WATERMARK_MASK(1);
2432 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2433 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
2434 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
2435 LATENCY_HIGH_WATERMARK(line_time)));
2436 /* select wm B */
2437 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2438 tmp &= ~LATENCY_WATERMARK_MASK(3);
2439 tmp |= LATENCY_WATERMARK_MASK(2);
2440 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2441 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
2442 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
2443 LATENCY_HIGH_WATERMARK(line_time)));
2444 /* restore original selection */
2445 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
2446
2447 /* write the priority marks */
2448 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
2449 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
2450
2451 /* save values for DPM */
2452 radeon_crtc->line_time = line_time;
2453 radeon_crtc->wm_high = latency_watermark_a;
2454 radeon_crtc->wm_low = latency_watermark_b;
2455 }
2456
2457 void dce6_bandwidth_update(struct radeon_device *rdev)
2458 {
2459 struct drm_display_mode *mode0 = NULL;
2460 struct drm_display_mode *mode1 = NULL;
2461 u32 num_heads = 0, lb_size;
2462 int i;
2463
2464 if (!rdev->mode_info.mode_config_initialized)
2465 return;
2466
2467 radeon_update_display_priority(rdev);
2468
2469 for (i = 0; i < rdev->num_crtc; i++) {
2470 if (rdev->mode_info.crtcs[i]->base.enabled)
2471 num_heads++;
2472 }
2473 for (i = 0; i < rdev->num_crtc; i += 2) {
2474 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
2475 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
2476 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
2477 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
2478 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
2479 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
2480 }
2481 }
2482
2483 /*
2484 * Core functions
2485 */
2486 static void si_tiling_mode_table_init(struct radeon_device *rdev)
2487 {
2488 u32 *tile = rdev->config.si.tile_mode_array;
2489 const u32 num_tile_mode_states =
2490 ARRAY_SIZE(rdev->config.si.tile_mode_array);
2491 u32 reg_offset, split_equal_to_row_size;
2492
2493 switch (rdev->config.si.mem_row_size_in_kb) {
2494 case 1:
2495 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
2496 break;
2497 case 2:
2498 default:
2499 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
2500 break;
2501 case 4:
2502 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
2503 break;
2504 }
2505
2506 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2507 tile[reg_offset] = 0;
2508
2509 switch(rdev->family) {
2510 case CHIP_TAHITI:
2511 case CHIP_PITCAIRN:
2512 /* non-AA compressed depth or any compressed stencil */
2513 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2514 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2515 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2516 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2517 NUM_BANKS(ADDR_SURF_16_BANK) |
2518 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2519 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2520 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2521 /* 2xAA/4xAA compressed depth only */
2522 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2523 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2524 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2525 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2526 NUM_BANKS(ADDR_SURF_16_BANK) |
2527 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2528 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2529 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2530 /* 8xAA compressed depth only */
2531 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2532 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2533 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2534 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2535 NUM_BANKS(ADDR_SURF_16_BANK) |
2536 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2537 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2538 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2539 /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
2540 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2541 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2542 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2543 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2544 NUM_BANKS(ADDR_SURF_16_BANK) |
2545 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2548 /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2549 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2550 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2551 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2552 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2553 NUM_BANKS(ADDR_SURF_16_BANK) |
2554 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2555 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2556 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2557 /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
2558 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2559 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2560 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2561 TILE_SPLIT(split_equal_to_row_size) |
2562 NUM_BANKS(ADDR_SURF_16_BANK) |
2563 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2564 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2565 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2566 /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
2567 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2568 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2569 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2570 TILE_SPLIT(split_equal_to_row_size) |
2571 NUM_BANKS(ADDR_SURF_16_BANK) |
2572 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2573 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2574 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2575 /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
2576 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2577 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2578 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2579 TILE_SPLIT(split_equal_to_row_size) |
2580 NUM_BANKS(ADDR_SURF_16_BANK) |
2581 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2582 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2583 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2584 /* 1D and 1D Array Surfaces */
2585 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2586 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2587 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2588 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2589 NUM_BANKS(ADDR_SURF_16_BANK) |
2590 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2591 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2592 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2593 /* Displayable maps. */
2594 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2595 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2596 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2597 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2598 NUM_BANKS(ADDR_SURF_16_BANK) |
2599 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2600 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2601 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2602 /* Display 8bpp. */
2603 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2604 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2605 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2606 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2607 NUM_BANKS(ADDR_SURF_16_BANK) |
2608 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2609 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2610 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2611 /* Display 16bpp. */
2612 tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2613 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2614 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2615 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2616 NUM_BANKS(ADDR_SURF_16_BANK) |
2617 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2618 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2619 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2620 /* Display 32bpp. */
2621 tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2622 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2623 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2624 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2625 NUM_BANKS(ADDR_SURF_16_BANK) |
2626 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2627 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2628 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2629 /* Thin. */
2630 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2631 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2632 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2633 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2634 NUM_BANKS(ADDR_SURF_16_BANK) |
2635 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2636 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2637 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2638 /* Thin 8 bpp. */
2639 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2640 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2641 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2642 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2643 NUM_BANKS(ADDR_SURF_16_BANK) |
2644 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2645 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2646 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2647 /* Thin 16 bpp. */
2648 tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2649 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2650 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2651 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2652 NUM_BANKS(ADDR_SURF_16_BANK) |
2653 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2654 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2655 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2656 /* Thin 32 bpp. */
2657 tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2658 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2659 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2660 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2661 NUM_BANKS(ADDR_SURF_16_BANK) |
2662 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2663 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2664 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2665 /* Thin 64 bpp. */
2666 tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2667 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2668 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2669 TILE_SPLIT(split_equal_to_row_size) |
2670 NUM_BANKS(ADDR_SURF_16_BANK) |
2671 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2672 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2673 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2674 /* 8 bpp PRT. */
2675 tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2676 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2677 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2678 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2679 NUM_BANKS(ADDR_SURF_16_BANK) |
2680 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2681 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2682 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2683 /* 16 bpp PRT */
2684 tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2685 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2686 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2687 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2688 NUM_BANKS(ADDR_SURF_16_BANK) |
2689 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2690 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2691 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2692 /* 32 bpp PRT */
2693 tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2694 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2695 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2696 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2697 NUM_BANKS(ADDR_SURF_16_BANK) |
2698 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2699 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2700 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2701 /* 64 bpp PRT */
2702 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2703 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2704 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2705 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2706 NUM_BANKS(ADDR_SURF_16_BANK) |
2707 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2708 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2709 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2710 /* 128 bpp PRT */
2711 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2712 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2713 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2714 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2715 NUM_BANKS(ADDR_SURF_8_BANK) |
2716 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2717 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2718 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2719
2720 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2721 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2722 break;
2723
2724 case CHIP_VERDE:
2725 case CHIP_OLAND:
2726 case CHIP_HAINAN:
2727 /* non-AA compressed depth or any compressed stencil */
2728 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2729 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2730 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2731 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2732 NUM_BANKS(ADDR_SURF_16_BANK) |
2733 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2734 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2735 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2736 /* 2xAA/4xAA compressed depth only */
2737 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2738 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2739 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2740 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2741 NUM_BANKS(ADDR_SURF_16_BANK) |
2742 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2743 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2744 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2745 /* 8xAA compressed depth only */
2746 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2747 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2748 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2749 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2750 NUM_BANKS(ADDR_SURF_16_BANK) |
2751 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2752 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2753 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2754 /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
2755 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2756 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2757 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2758 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2759 NUM_BANKS(ADDR_SURF_16_BANK) |
2760 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2761 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2762 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2763 /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2764 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2765 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2766 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2767 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2768 NUM_BANKS(ADDR_SURF_16_BANK) |
2769 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2770 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2771 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2772 /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
2773 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2774 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2775 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2776 TILE_SPLIT(split_equal_to_row_size) |
2777 NUM_BANKS(ADDR_SURF_16_BANK) |
2778 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2779 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2780 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2781 /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
2782 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2783 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2784 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2785 TILE_SPLIT(split_equal_to_row_size) |
2786 NUM_BANKS(ADDR_SURF_16_BANK) |
2787 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2788 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2789 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2790 /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
2791 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2792 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2793 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2794 TILE_SPLIT(split_equal_to_row_size) |
2795 NUM_BANKS(ADDR_SURF_16_BANK) |
2796 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2797 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2798 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2799 /* 1D and 1D Array Surfaces */
2800 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2801 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2802 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2803 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2804 NUM_BANKS(ADDR_SURF_16_BANK) |
2805 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2806 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2807 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2808 /* Displayable maps. */
2809 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2810 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2811 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2812 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2813 NUM_BANKS(ADDR_SURF_16_BANK) |
2814 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2815 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2816 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2817 /* Display 8bpp. */
2818 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2819 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2820 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2821 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2822 NUM_BANKS(ADDR_SURF_16_BANK) |
2823 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2824 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2825 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2826 /* Display 16bpp. */
2827 tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2828 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2829 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2830 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2831 NUM_BANKS(ADDR_SURF_16_BANK) |
2832 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2833 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2834 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2835 /* Display 32bpp. */
2836 tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2837 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2838 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2839 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2840 NUM_BANKS(ADDR_SURF_16_BANK) |
2841 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2842 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2843 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2844 /* Thin. */
2845 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2846 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2847 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2848 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2849 NUM_BANKS(ADDR_SURF_16_BANK) |
2850 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2851 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2852 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2853 /* Thin 8 bpp. */
2854 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2855 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2856 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2857 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2858 NUM_BANKS(ADDR_SURF_16_BANK) |
2859 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2860 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2861 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2862 /* Thin 16 bpp. */
2863 tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2864 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2865 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2866 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2867 NUM_BANKS(ADDR_SURF_16_BANK) |
2868 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2869 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2870 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2871 /* Thin 32 bpp. */
2872 tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2873 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2874 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2875 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2876 NUM_BANKS(ADDR_SURF_16_BANK) |
2877 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2878 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2879 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2880 /* Thin 64 bpp. */
2881 tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2882 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2883 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2884 TILE_SPLIT(split_equal_to_row_size) |
2885 NUM_BANKS(ADDR_SURF_16_BANK) |
2886 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2887 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2888 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2889 /* 8 bpp PRT. */
2890 tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2891 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2892 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2893 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2894 NUM_BANKS(ADDR_SURF_16_BANK) |
2895 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2896 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2897 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2898 /* 16 bpp PRT */
2899 tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2900 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2901 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2902 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2903 NUM_BANKS(ADDR_SURF_16_BANK) |
2904 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2905 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2906 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2907 /* 32 bpp PRT */
2908 tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2909 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2910 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2911 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2912 NUM_BANKS(ADDR_SURF_16_BANK) |
2913 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2914 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2915 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2916 /* 64 bpp PRT */
2917 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2918 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2919 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2920 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2921 NUM_BANKS(ADDR_SURF_16_BANK) |
2922 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2923 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2924 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2925 /* 128 bpp PRT */
2926 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2927 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2928 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2929 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2930 NUM_BANKS(ADDR_SURF_8_BANK) |
2931 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2932 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2933 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2934
2935 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2936 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2937 break;
2938
2939 default:
2940 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
2941 }
2942 }
2943
2944 static void si_select_se_sh(struct radeon_device *rdev,
2945 u32 se_num, u32 sh_num)
2946 {
2947 u32 data = INSTANCE_BROADCAST_WRITES;
2948
2949 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
2950 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
2951 else if (se_num == 0xffffffff)
2952 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
2953 else if (sh_num == 0xffffffff)
2954 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
2955 else
2956 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
2957 WREG32(GRBM_GFX_INDEX, data);
2958 }
2959
2960 static u32 si_create_bitmask(u32 bit_width)
2961 {
2962 u32 i, mask = 0;
2963
2964 for (i = 0; i < bit_width; i++) {
2965 mask <<= 1;
2966 mask |= 1;
2967 }
2968 return mask;
2969 }
2970
2971 static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
2972 {
2973 u32 data, mask;
2974
2975 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
2976 if (data & 1)
2977 data &= INACTIVE_CUS_MASK;
2978 else
2979 data = 0;
2980 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
2981
2982 data >>= INACTIVE_CUS_SHIFT;
2983
2984 mask = si_create_bitmask(cu_per_sh);
2985
2986 return ~data & mask;
2987 }
2988
2989 static void si_setup_spi(struct radeon_device *rdev,
2990 u32 se_num, u32 sh_per_se,
2991 u32 cu_per_sh)
2992 {
2993 int i, j, k;
2994 u32 data, mask, active_cu;
2995
2996 for (i = 0; i < se_num; i++) {
2997 for (j = 0; j < sh_per_se; j++) {
2998 si_select_se_sh(rdev, i, j);
2999 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
3000 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
3001
3002 mask = 1;
3003 for (k = 0; k < 16; k++) {
3004 mask <<= k;
3005 if (active_cu & mask) {
3006 data &= ~mask;
3007 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
3008 break;
3009 }
3010 }
3011 }
3012 }
3013 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3014 }
3015
3016 static u32 si_get_rb_disabled(struct radeon_device *rdev,
3017 u32 max_rb_num_per_se,
3018 u32 sh_per_se)
3019 {
3020 u32 data, mask;
3021
3022 data = RREG32(CC_RB_BACKEND_DISABLE);
3023 if (data & 1)
3024 data &= BACKEND_DISABLE_MASK;
3025 else
3026 data = 0;
3027 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
3028
3029 data >>= BACKEND_DISABLE_SHIFT;
3030
3031 mask = si_create_bitmask(max_rb_num_per_se / sh_per_se);
3032
3033 return data & mask;
3034 }
3035
3036 static void si_setup_rb(struct radeon_device *rdev,
3037 u32 se_num, u32 sh_per_se,
3038 u32 max_rb_num_per_se)
3039 {
3040 int i, j;
3041 u32 data, mask;
3042 u32 disabled_rbs = 0;
3043 u32 enabled_rbs = 0;
3044
3045 for (i = 0; i < se_num; i++) {
3046 for (j = 0; j < sh_per_se; j++) {
3047 si_select_se_sh(rdev, i, j);
3048 data = si_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
3049 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
3050 }
3051 }
3052 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3053
3054 mask = 1;
3055 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
3056 if (!(disabled_rbs & mask))
3057 enabled_rbs |= mask;
3058 mask <<= 1;
3059 }
3060
3061 rdev->config.si.backend_enable_mask = enabled_rbs;
3062
3063 for (i = 0; i < se_num; i++) {
3064 si_select_se_sh(rdev, i, 0xffffffff);
3065 data = 0;
3066 for (j = 0; j < sh_per_se; j++) {
3067 switch (enabled_rbs & 3) {
3068 case 1:
3069 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
3070 break;
3071 case 2:
3072 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
3073 break;
3074 case 3:
3075 default:
3076 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
3077 break;
3078 }
3079 enabled_rbs >>= 2;
3080 }
3081 WREG32(PA_SC_RASTER_CONFIG, data);
3082 }
3083 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3084 }
3085
3086 static void si_gpu_init(struct radeon_device *rdev)
3087 {
3088 u32 gb_addr_config = 0;
3089 u32 mc_shared_chmap, mc_arb_ramcfg;
3090 u32 sx_debug_1;
3091 u32 hdp_host_path_cntl;
3092 u32 tmp;
3093 int i, j;
3094
3095 switch (rdev->family) {
3096 case CHIP_TAHITI:
3097 rdev->config.si.max_shader_engines = 2;
3098 rdev->config.si.max_tile_pipes = 12;
3099 rdev->config.si.max_cu_per_sh = 8;
3100 rdev->config.si.max_sh_per_se = 2;
3101 rdev->config.si.max_backends_per_se = 4;
3102 rdev->config.si.max_texture_channel_caches = 12;
3103 rdev->config.si.max_gprs = 256;
3104 rdev->config.si.max_gs_threads = 32;
3105 rdev->config.si.max_hw_contexts = 8;
3106
3107 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3108 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
3109 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3110 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3111 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
3112 break;
3113 case CHIP_PITCAIRN:
3114 rdev->config.si.max_shader_engines = 2;
3115 rdev->config.si.max_tile_pipes = 8;
3116 rdev->config.si.max_cu_per_sh = 5;
3117 rdev->config.si.max_sh_per_se = 2;
3118 rdev->config.si.max_backends_per_se = 4;
3119 rdev->config.si.max_texture_channel_caches = 8;
3120 rdev->config.si.max_gprs = 256;
3121 rdev->config.si.max_gs_threads = 32;
3122 rdev->config.si.max_hw_contexts = 8;
3123
3124 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3125 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
3126 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3127 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3128 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
3129 break;
3130 case CHIP_VERDE:
3131 default:
3132 rdev->config.si.max_shader_engines = 1;
3133 rdev->config.si.max_tile_pipes = 4;
3134 rdev->config.si.max_cu_per_sh = 5;
3135 rdev->config.si.max_sh_per_se = 2;
3136 rdev->config.si.max_backends_per_se = 4;
3137 rdev->config.si.max_texture_channel_caches = 4;
3138 rdev->config.si.max_gprs = 256;
3139 rdev->config.si.max_gs_threads = 32;
3140 rdev->config.si.max_hw_contexts = 8;
3141
3142 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3143 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3144 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3145 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3146 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
3147 break;
3148 case CHIP_OLAND:
3149 rdev->config.si.max_shader_engines = 1;
3150 rdev->config.si.max_tile_pipes = 4;
3151 rdev->config.si.max_cu_per_sh = 6;
3152 rdev->config.si.max_sh_per_se = 1;
3153 rdev->config.si.max_backends_per_se = 2;
3154 rdev->config.si.max_texture_channel_caches = 4;
3155 rdev->config.si.max_gprs = 256;
3156 rdev->config.si.max_gs_threads = 16;
3157 rdev->config.si.max_hw_contexts = 8;
3158
3159 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3160 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3161 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3162 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3163 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
3164 break;
3165 case CHIP_HAINAN:
3166 rdev->config.si.max_shader_engines = 1;
3167 rdev->config.si.max_tile_pipes = 4;
3168 rdev->config.si.max_cu_per_sh = 5;
3169 rdev->config.si.max_sh_per_se = 1;
3170 rdev->config.si.max_backends_per_se = 1;
3171 rdev->config.si.max_texture_channel_caches = 2;
3172 rdev->config.si.max_gprs = 256;
3173 rdev->config.si.max_gs_threads = 16;
3174 rdev->config.si.max_hw_contexts = 8;
3175
3176 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3177 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3178 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3179 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3180 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
3181 break;
3182 }
3183
3184 /* Initialize HDP */
3185 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
3186 WREG32((0x2c14 + j), 0x00000000);
3187 WREG32((0x2c18 + j), 0x00000000);
3188 WREG32((0x2c1c + j), 0x00000000);
3189 WREG32((0x2c20 + j), 0x00000000);
3190 WREG32((0x2c24 + j), 0x00000000);
3191 }
3192
3193 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3194 WREG32(SRBM_INT_CNTL, 1);
3195 WREG32(SRBM_INT_ACK, 1);
3196
3197 evergreen_fix_pci_max_read_req_size(rdev);
3198
3199 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
3200
3201 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
3202 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3203
3204 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
3205 rdev->config.si.mem_max_burst_length_bytes = 256;
3206 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3207 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3208 if (rdev->config.si.mem_row_size_in_kb > 4)
3209 rdev->config.si.mem_row_size_in_kb = 4;
3210 /* XXX use MC settings? */
3211 rdev->config.si.shader_engine_tile_size = 32;
3212 rdev->config.si.num_gpus = 1;
3213 rdev->config.si.multi_gpu_tile_size = 64;
3214
3215 /* fix up row size */
3216 gb_addr_config &= ~ROW_SIZE_MASK;
3217 switch (rdev->config.si.mem_row_size_in_kb) {
3218 case 1:
3219 default:
3220 gb_addr_config |= ROW_SIZE(0);
3221 break;
3222 case 2:
3223 gb_addr_config |= ROW_SIZE(1);
3224 break;
3225 case 4:
3226 gb_addr_config |= ROW_SIZE(2);
3227 break;
3228 }
3229
3230 /* setup tiling info dword. gb_addr_config is not adequate since it does
3231 * not have bank info, so create a custom tiling dword.
3232 * bits 3:0 num_pipes
3233 * bits 7:4 num_banks
3234 * bits 11:8 group_size
3235 * bits 15:12 row_size
3236 */
3237 rdev->config.si.tile_config = 0;
3238 switch (rdev->config.si.num_tile_pipes) {
3239 case 1:
3240 rdev->config.si.tile_config |= (0 << 0);
3241 break;
3242 case 2:
3243 rdev->config.si.tile_config |= (1 << 0);
3244 break;
3245 case 4:
3246 rdev->config.si.tile_config |= (2 << 0);
3247 break;
3248 case 8:
3249 default:
3250 /* XXX what about 12? */
3251 rdev->config.si.tile_config |= (3 << 0);
3252 break;
3253 }
3254 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
3255 case 0: /* four banks */
3256 rdev->config.si.tile_config |= 0 << 4;
3257 break;
3258 case 1: /* eight banks */
3259 rdev->config.si.tile_config |= 1 << 4;
3260 break;
3261 case 2: /* sixteen banks */
3262 default:
3263 rdev->config.si.tile_config |= 2 << 4;
3264 break;
3265 }
3266 rdev->config.si.tile_config |=
3267 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
3268 rdev->config.si.tile_config |=
3269 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
3270
3271 WREG32(GB_ADDR_CONFIG, gb_addr_config);
3272 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
3273 WREG32(DMIF_ADDR_CALC, gb_addr_config);
3274 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
3275 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
3276 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
3277 if (rdev->has_uvd) {
3278 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3279 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3280 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
3281 }
3282
3283 si_tiling_mode_table_init(rdev);
3284
3285 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
3286 rdev->config.si.max_sh_per_se,
3287 rdev->config.si.max_backends_per_se);
3288
3289 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
3290 rdev->config.si.max_sh_per_se,
3291 rdev->config.si.max_cu_per_sh);
3292
3293 rdev->config.si.active_cus = 0;
3294 for (i = 0; i < rdev->config.si.max_shader_engines; i++) {
3295 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {
3296 rdev->config.si.active_cus +=
3297 hweight32(si_get_cu_active_bitmap(rdev, i, j));
3298 }
3299 }
3300
3301 /* set HW defaults for 3D engine */
3302 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
3303 ROQ_IB2_START(0x2b)));
3304 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
3305
3306 sx_debug_1 = RREG32(SX_DEBUG_1);
3307 WREG32(SX_DEBUG_1, sx_debug_1);
3308
3309 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
3310
3311 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
3312 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
3313 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
3314 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
3315
3316 WREG32(VGT_NUM_INSTANCES, 1);
3317
3318 WREG32(CP_PERFMON_CNTL, 0);
3319
3320 WREG32(SQ_CONFIG, 0);
3321
3322 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
3323 FORCE_EOV_MAX_REZ_CNT(255)));
3324
3325 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
3326 AUTO_INVLD_EN(ES_AND_GS_AUTO));
3327
3328 WREG32(VGT_GS_VERTEX_REUSE, 16);
3329 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
3330
3331 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
3332 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
3333 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
3334 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
3335 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
3336 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
3337 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
3338 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
3339
3340 tmp = RREG32(HDP_MISC_CNTL);
3341 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3342 WREG32(HDP_MISC_CNTL, tmp);
3343
3344 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3345 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3346
3347 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3348
3349 udelay(50);
3350 }
3351
3352 /*
3353 * GPU scratch registers helpers function.
3354 */
3355 static void si_scratch_init(struct radeon_device *rdev)
3356 {
3357 int i;
3358
3359 rdev->scratch.num_reg = 7;
3360 rdev->scratch.reg_base = SCRATCH_REG0;
3361 for (i = 0; i < rdev->scratch.num_reg; i++) {
3362 rdev->scratch.free[i] = true;
3363 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3364 }
3365 }
3366
3367 void si_fence_ring_emit(struct radeon_device *rdev,
3368 struct radeon_fence *fence)
3369 {
3370 struct radeon_ring *ring = &rdev->ring[fence->ring];
3371 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3372
3373 /* flush read cache over gart */
3374 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3375 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3376 radeon_ring_write(ring, 0);
3377 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3378 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3379 PACKET3_TC_ACTION_ENA |
3380 PACKET3_SH_KCACHE_ACTION_ENA |
3381 PACKET3_SH_ICACHE_ACTION_ENA);
3382 radeon_ring_write(ring, 0xFFFFFFFF);
3383 radeon_ring_write(ring, 0);
3384 radeon_ring_write(ring, 10); /* poll interval */
3385 /* EVENT_WRITE_EOP - flush caches, send int */
3386 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3387 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
3388 radeon_ring_write(ring, lower_32_bits(addr));
3389 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
3390 radeon_ring_write(ring, fence->seq);
3391 radeon_ring_write(ring, 0);
3392 }
3393
3394 /*
3395 * IB stuff
3396 */
3397 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3398 {
3399 struct radeon_ring *ring = &rdev->ring[ib->ring];
3400 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
3401 u32 header;
3402
3403 if (ib->is_const_ib) {
3404 /* set switch buffer packet before const IB */
3405 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3406 radeon_ring_write(ring, 0);
3407
3408 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3409 } else {
3410 u32 next_rptr;
3411 if (ring->rptr_save_reg) {
3412 next_rptr = ring->wptr + 3 + 4 + 8;
3413 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3414 radeon_ring_write(ring, ((ring->rptr_save_reg -
3415 PACKET3_SET_CONFIG_REG_START) >> 2));
3416 radeon_ring_write(ring, next_rptr);
3417 } else if (rdev->wb.enabled) {
3418 next_rptr = ring->wptr + 5 + 4 + 8;
3419 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3420 radeon_ring_write(ring, (1 << 8));
3421 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3422 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
3423 radeon_ring_write(ring, next_rptr);
3424 }
3425
3426 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3427 }
3428
3429 radeon_ring_write(ring, header);
3430 radeon_ring_write(ring,
3431 #ifdef __BIG_ENDIAN
3432 (2 << 0) |
3433 #endif
3434 (ib->gpu_addr & 0xFFFFFFFC));
3435 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3436 radeon_ring_write(ring, ib->length_dw | (vm_id << 24));
3437
3438 if (!ib->is_const_ib) {
3439 /* flush read cache over gart for this vmid */
3440 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3441 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3442 radeon_ring_write(ring, vm_id);
3443 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3444 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3445 PACKET3_TC_ACTION_ENA |
3446 PACKET3_SH_KCACHE_ACTION_ENA |
3447 PACKET3_SH_ICACHE_ACTION_ENA);
3448 radeon_ring_write(ring, 0xFFFFFFFF);
3449 radeon_ring_write(ring, 0);
3450 radeon_ring_write(ring, 10); /* poll interval */
3451 }
3452 }
3453
3454 /*
3455 * CP.
3456 */
3457 static void si_cp_enable(struct radeon_device *rdev, bool enable)
3458 {
3459 if (enable)
3460 WREG32(CP_ME_CNTL, 0);
3461 else {
3462 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3463 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3464 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
3465 WREG32(SCRATCH_UMSK, 0);
3466 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3467 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3468 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3469 }
3470 udelay(50);
3471 }
3472
3473 static int si_cp_load_microcode(struct radeon_device *rdev)
3474 {
3475 int i;
3476
3477 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw)
3478 return -EINVAL;
3479
3480 si_cp_enable(rdev, false);
3481
3482 if (rdev->new_fw) {
3483 const struct gfx_firmware_header_v1_0 *pfp_hdr =
3484 (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
3485 const struct gfx_firmware_header_v1_0 *ce_hdr =
3486 (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
3487 const struct gfx_firmware_header_v1_0 *me_hdr =
3488 (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
3489 const __le32 *fw_data;
3490 u32 fw_size;
3491
3492 radeon_ucode_print_gfx_hdr(&pfp_hdr->header);
3493 radeon_ucode_print_gfx_hdr(&ce_hdr->header);
3494 radeon_ucode_print_gfx_hdr(&me_hdr->header);
3495
3496 /* PFP */
3497 fw_data = (const __le32 *)
3498 (rdev->pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3499 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
3500 WREG32(CP_PFP_UCODE_ADDR, 0);
3501 for (i = 0; i < fw_size; i++)
3502 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3503 WREG32(CP_PFP_UCODE_ADDR, 0);
3504
3505 /* CE */
3506 fw_data = (const __le32 *)
3507 (rdev->ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
3508 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
3509 WREG32(CP_CE_UCODE_ADDR, 0);
3510 for (i = 0; i < fw_size; i++)
3511 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3512 WREG32(CP_CE_UCODE_ADDR, 0);
3513
3514 /* ME */
3515 fw_data = (const __be32 *)
3516 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
3517 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
3518 WREG32(CP_ME_RAM_WADDR, 0);
3519 for (i = 0; i < fw_size; i++)
3520 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
3521 WREG32(CP_ME_RAM_WADDR, 0);
3522 } else {
3523 const __be32 *fw_data;
3524
3525 /* PFP */
3526 fw_data = (const __be32 *)rdev->pfp_fw->data;
3527 WREG32(CP_PFP_UCODE_ADDR, 0);
3528 for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
3529 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
3530 WREG32(CP_PFP_UCODE_ADDR, 0);
3531
3532 /* CE */
3533 fw_data = (const __be32 *)rdev->ce_fw->data;
3534 WREG32(CP_CE_UCODE_ADDR, 0);
3535 for (i = 0; i < SI_CE_UCODE_SIZE; i++)
3536 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
3537 WREG32(CP_CE_UCODE_ADDR, 0);
3538
3539 /* ME */
3540 fw_data = (const __be32 *)rdev->me_fw->data;
3541 WREG32(CP_ME_RAM_WADDR, 0);
3542 for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
3543 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
3544 WREG32(CP_ME_RAM_WADDR, 0);
3545 }
3546
3547 WREG32(CP_PFP_UCODE_ADDR, 0);
3548 WREG32(CP_CE_UCODE_ADDR, 0);
3549 WREG32(CP_ME_RAM_WADDR, 0);
3550 WREG32(CP_ME_RAM_RADDR, 0);
3551 return 0;
3552 }
3553
3554 static int si_cp_start(struct radeon_device *rdev)
3555 {
3556 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3557 int r, i;
3558
3559 r = radeon_ring_lock(rdev, ring, 7 + 4);
3560 if (r) {
3561 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3562 return r;
3563 }
3564 /* init the CP */
3565 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
3566 radeon_ring_write(ring, 0x1);
3567 radeon_ring_write(ring, 0x0);
3568 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
3569 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
3570 radeon_ring_write(ring, 0);
3571 radeon_ring_write(ring, 0);
3572
3573 /* init the CE partitions */
3574 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3575 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3576 radeon_ring_write(ring, 0xc000);
3577 radeon_ring_write(ring, 0xe000);
3578 radeon_ring_unlock_commit(rdev, ring, false);
3579
3580 si_cp_enable(rdev, true);
3581
3582 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
3583 if (r) {
3584 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3585 return r;
3586 }
3587
3588 /* setup clear context state */
3589 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3590 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3591
3592 for (i = 0; i < si_default_size; i++)
3593 radeon_ring_write(ring, si_default_state[i]);
3594
3595 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3596 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3597
3598 /* set clear context state */
3599 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3600 radeon_ring_write(ring, 0);
3601
3602 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3603 radeon_ring_write(ring, 0x00000316);
3604 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
3605 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
3606
3607 radeon_ring_unlock_commit(rdev, ring, false);
3608
3609 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
3610 ring = &rdev->ring[i];
3611 r = radeon_ring_lock(rdev, ring, 2);
3612
3613 /* clear the compute context state */
3614 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
3615 radeon_ring_write(ring, 0);
3616
3617 radeon_ring_unlock_commit(rdev, ring, false);
3618 }
3619
3620 return 0;
3621 }
3622
3623 static void si_cp_fini(struct radeon_device *rdev)
3624 {
3625 struct radeon_ring *ring;
3626 si_cp_enable(rdev, false);
3627
3628 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3629 radeon_ring_fini(rdev, ring);
3630 radeon_scratch_free(rdev, ring->rptr_save_reg);
3631
3632 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3633 radeon_ring_fini(rdev, ring);
3634 radeon_scratch_free(rdev, ring->rptr_save_reg);
3635
3636 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3637 radeon_ring_fini(rdev, ring);
3638 radeon_scratch_free(rdev, ring->rptr_save_reg);
3639 }
3640
3641 static int si_cp_resume(struct radeon_device *rdev)
3642 {
3643 struct radeon_ring *ring;
3644 u32 tmp;
3645 u32 rb_bufsz;
3646 int r;
3647
3648 si_enable_gui_idle_interrupt(rdev, false);
3649
3650 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3651 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
3652
3653 /* Set the write pointer delay */
3654 WREG32(CP_RB_WPTR_DELAY, 0);
3655
3656 WREG32(CP_DEBUG, 0);
3657 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
3658
3659 /* ring 0 - compute and gfx */
3660 /* Set ring buffer size */
3661 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3662 rb_bufsz = order_base_2(ring->ring_size / 8);
3663 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3664 #ifdef __BIG_ENDIAN
3665 tmp |= BUF_SWAP_32BIT;
3666 #endif
3667 WREG32(CP_RB0_CNTL, tmp);
3668
3669 /* Initialize the ring buffer's read and write pointers */
3670 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
3671 ring->wptr = 0;
3672 WREG32(CP_RB0_WPTR, ring->wptr);
3673
3674 /* set the wb address whether it's enabled or not */
3675 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
3676 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
3677
3678 if (rdev->wb.enabled)
3679 WREG32(SCRATCH_UMSK, 0xff);
3680 else {
3681 tmp |= RB_NO_UPDATE;
3682 WREG32(SCRATCH_UMSK, 0);
3683 }
3684
3685 mdelay(1);
3686 WREG32(CP_RB0_CNTL, tmp);
3687
3688 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
3689
3690 /* ring1 - compute only */
3691 /* Set ring buffer size */
3692 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3693 rb_bufsz = order_base_2(ring->ring_size / 8);
3694 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3695 #ifdef __BIG_ENDIAN
3696 tmp |= BUF_SWAP_32BIT;
3697 #endif
3698 WREG32(CP_RB1_CNTL, tmp);
3699
3700 /* Initialize the ring buffer's read and write pointers */
3701 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
3702 ring->wptr = 0;
3703 WREG32(CP_RB1_WPTR, ring->wptr);
3704
3705 /* set the wb address whether it's enabled or not */
3706 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
3707 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
3708
3709 mdelay(1);
3710 WREG32(CP_RB1_CNTL, tmp);
3711
3712 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
3713
3714 /* ring2 - compute only */
3715 /* Set ring buffer size */
3716 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3717 rb_bufsz = order_base_2(ring->ring_size / 8);
3718 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3719 #ifdef __BIG_ENDIAN
3720 tmp |= BUF_SWAP_32BIT;
3721 #endif
3722 WREG32(CP_RB2_CNTL, tmp);
3723
3724 /* Initialize the ring buffer's read and write pointers */
3725 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
3726 ring->wptr = 0;
3727 WREG32(CP_RB2_WPTR, ring->wptr);
3728
3729 /* set the wb address whether it's enabled or not */
3730 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
3731 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
3732
3733 mdelay(1);
3734 WREG32(CP_RB2_CNTL, tmp);
3735
3736 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
3737
3738 /* start the rings */
3739 si_cp_start(rdev);
3740 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
3741 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
3742 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
3743 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3744 if (r) {
3745 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3746 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3747 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3748 return r;
3749 }
3750 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
3751 if (r) {
3752 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3753 }
3754 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
3755 if (r) {
3756 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3757 }
3758
3759 si_enable_gui_idle_interrupt(rdev, true);
3760
3761 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3762 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
3763
3764 return 0;
3765 }
3766
3767 u32 si_gpu_check_soft_reset(struct radeon_device *rdev)
3768 {
3769 u32 reset_mask = 0;
3770 u32 tmp;
3771
3772 /* GRBM_STATUS */
3773 tmp = RREG32(GRBM_STATUS);
3774 if (tmp & (PA_BUSY | SC_BUSY |
3775 BCI_BUSY | SX_BUSY |
3776 TA_BUSY | VGT_BUSY |
3777 DB_BUSY | CB_BUSY |
3778 GDS_BUSY | SPI_BUSY |
3779 IA_BUSY | IA_BUSY_NO_DMA))
3780 reset_mask |= RADEON_RESET_GFX;
3781
3782 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
3783 CP_BUSY | CP_COHERENCY_BUSY))
3784 reset_mask |= RADEON_RESET_CP;
3785
3786 if (tmp & GRBM_EE_BUSY)
3787 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
3788
3789 /* GRBM_STATUS2 */
3790 tmp = RREG32(GRBM_STATUS2);
3791 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
3792 reset_mask |= RADEON_RESET_RLC;
3793
3794 /* DMA_STATUS_REG 0 */
3795 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
3796 if (!(tmp & DMA_IDLE))
3797 reset_mask |= RADEON_RESET_DMA;
3798
3799 /* DMA_STATUS_REG 1 */
3800 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
3801 if (!(tmp & DMA_IDLE))
3802 reset_mask |= RADEON_RESET_DMA1;
3803
3804 /* SRBM_STATUS2 */
3805 tmp = RREG32(SRBM_STATUS2);
3806 if (tmp & DMA_BUSY)
3807 reset_mask |= RADEON_RESET_DMA;
3808
3809 if (tmp & DMA1_BUSY)
3810 reset_mask |= RADEON_RESET_DMA1;
3811
3812 /* SRBM_STATUS */
3813 tmp = RREG32(SRBM_STATUS);
3814
3815 if (tmp & IH_BUSY)
3816 reset_mask |= RADEON_RESET_IH;
3817
3818 if (tmp & SEM_BUSY)
3819 reset_mask |= RADEON_RESET_SEM;
3820
3821 if (tmp & GRBM_RQ_PENDING)
3822 reset_mask |= RADEON_RESET_GRBM;
3823
3824 if (tmp & VMC_BUSY)
3825 reset_mask |= RADEON_RESET_VMC;
3826
3827 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
3828 MCC_BUSY | MCD_BUSY))
3829 reset_mask |= RADEON_RESET_MC;
3830
3831 if (evergreen_is_display_hung(rdev))
3832 reset_mask |= RADEON_RESET_DISPLAY;
3833
3834 /* VM_L2_STATUS */
3835 tmp = RREG32(VM_L2_STATUS);
3836 if (tmp & L2_BUSY)
3837 reset_mask |= RADEON_RESET_VMC;
3838
3839 /* Skip MC reset as it's mostly likely not hung, just busy */
3840 if (reset_mask & RADEON_RESET_MC) {
3841 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
3842 reset_mask &= ~RADEON_RESET_MC;
3843 }
3844
3845 return reset_mask;
3846 }
3847
3848 static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
3849 {
3850 struct evergreen_mc_save save;
3851 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3852 u32 tmp;
3853
3854 if (reset_mask == 0)
3855 return;
3856
3857 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
3858
3859 evergreen_print_gpu_status_regs(rdev);
3860 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
3861 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3862 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3863 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3864
3865 /* disable PG/CG */
3866 si_fini_pg(rdev);
3867 si_fini_cg(rdev);
3868
3869 /* stop the rlc */
3870 si_rlc_stop(rdev);
3871
3872 /* Disable CP parsing/prefetching */
3873 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
3874
3875 if (reset_mask & RADEON_RESET_DMA) {
3876 /* dma0 */
3877 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
3878 tmp &= ~DMA_RB_ENABLE;
3879 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
3880 }
3881 if (reset_mask & RADEON_RESET_DMA1) {
3882 /* dma1 */
3883 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
3884 tmp &= ~DMA_RB_ENABLE;
3885 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
3886 }
3887
3888 udelay(50);
3889
3890 evergreen_mc_stop(rdev, &save);
3891 if (evergreen_mc_wait_for_idle(rdev)) {
3892 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3893 }
3894
3895 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
3896 grbm_soft_reset = SOFT_RESET_CB |
3897 SOFT_RESET_DB |
3898 SOFT_RESET_GDS |
3899 SOFT_RESET_PA |
3900 SOFT_RESET_SC |
3901 SOFT_RESET_BCI |
3902 SOFT_RESET_SPI |
3903 SOFT_RESET_SX |
3904 SOFT_RESET_TC |
3905 SOFT_RESET_TA |
3906 SOFT_RESET_VGT |
3907 SOFT_RESET_IA;
3908 }
3909
3910 if (reset_mask & RADEON_RESET_CP) {
3911 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
3912
3913 srbm_soft_reset |= SOFT_RESET_GRBM;
3914 }
3915
3916 if (reset_mask & RADEON_RESET_DMA)
3917 srbm_soft_reset |= SOFT_RESET_DMA;
3918
3919 if (reset_mask & RADEON_RESET_DMA1)
3920 srbm_soft_reset |= SOFT_RESET_DMA1;
3921
3922 if (reset_mask & RADEON_RESET_DISPLAY)
3923 srbm_soft_reset |= SOFT_RESET_DC;
3924
3925 if (reset_mask & RADEON_RESET_RLC)
3926 grbm_soft_reset |= SOFT_RESET_RLC;
3927
3928 if (reset_mask & RADEON_RESET_SEM)
3929 srbm_soft_reset |= SOFT_RESET_SEM;
3930
3931 if (reset_mask & RADEON_RESET_IH)
3932 srbm_soft_reset |= SOFT_RESET_IH;
3933
3934 if (reset_mask & RADEON_RESET_GRBM)
3935 srbm_soft_reset |= SOFT_RESET_GRBM;
3936
3937 if (reset_mask & RADEON_RESET_VMC)
3938 srbm_soft_reset |= SOFT_RESET_VMC;
3939
3940 if (reset_mask & RADEON_RESET_MC)
3941 srbm_soft_reset |= SOFT_RESET_MC;
3942
3943 if (grbm_soft_reset) {
3944 tmp = RREG32(GRBM_SOFT_RESET);
3945 tmp |= grbm_soft_reset;
3946 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3947 WREG32(GRBM_SOFT_RESET, tmp);
3948 tmp = RREG32(GRBM_SOFT_RESET);
3949
3950 udelay(50);
3951
3952 tmp &= ~grbm_soft_reset;
3953 WREG32(GRBM_SOFT_RESET, tmp);
3954 tmp = RREG32(GRBM_SOFT_RESET);
3955 }
3956
3957 if (srbm_soft_reset) {
3958 tmp = RREG32(SRBM_SOFT_RESET);
3959 tmp |= srbm_soft_reset;
3960 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3961 WREG32(SRBM_SOFT_RESET, tmp);
3962 tmp = RREG32(SRBM_SOFT_RESET);
3963
3964 udelay(50);
3965
3966 tmp &= ~srbm_soft_reset;
3967 WREG32(SRBM_SOFT_RESET, tmp);
3968 tmp = RREG32(SRBM_SOFT_RESET);
3969 }
3970
3971 /* Wait a little for things to settle down */
3972 udelay(50);
3973
3974 evergreen_mc_resume(rdev, &save);
3975 udelay(50);
3976
3977 evergreen_print_gpu_status_regs(rdev);
3978 }
3979
3980 static void si_set_clk_bypass_mode(struct radeon_device *rdev)
3981 {
3982 u32 tmp, i;
3983
3984 tmp = RREG32(CG_SPLL_FUNC_CNTL);
3985 tmp |= SPLL_BYPASS_EN;
3986 WREG32(CG_SPLL_FUNC_CNTL, tmp);
3987
3988 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
3989 tmp |= SPLL_CTLREQ_CHG;
3990 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
3991
3992 for (i = 0; i < rdev->usec_timeout; i++) {
3993 if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS)
3994 break;
3995 udelay(1);
3996 }
3997
3998 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
3999 tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE);
4000 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
4001
4002 tmp = RREG32(MPLL_CNTL_MODE);
4003 tmp &= ~MPLL_MCLK_SEL;
4004 WREG32(MPLL_CNTL_MODE, tmp);
4005 }
4006
4007 static void si_spll_powerdown(struct radeon_device *rdev)
4008 {
4009 u32 tmp;
4010
4011 tmp = RREG32(SPLL_CNTL_MODE);
4012 tmp |= SPLL_SW_DIR_CONTROL;
4013 WREG32(SPLL_CNTL_MODE, tmp);
4014
4015 tmp = RREG32(CG_SPLL_FUNC_CNTL);
4016 tmp |= SPLL_RESET;
4017 WREG32(CG_SPLL_FUNC_CNTL, tmp);
4018
4019 tmp = RREG32(CG_SPLL_FUNC_CNTL);
4020 tmp |= SPLL_SLEEP;
4021 WREG32(CG_SPLL_FUNC_CNTL, tmp);
4022
4023 tmp = RREG32(SPLL_CNTL_MODE);
4024 tmp &= ~SPLL_SW_DIR_CONTROL;
4025 WREG32(SPLL_CNTL_MODE, tmp);
4026 }
4027
4028 static void si_gpu_pci_config_reset(struct radeon_device *rdev)
4029 {
4030 struct evergreen_mc_save save;
4031 u32 tmp, i;
4032
4033 dev_info(rdev->dev, "GPU pci config reset\n");
4034
4035 /* disable dpm? */
4036
4037 /* disable cg/pg */
4038 si_fini_pg(rdev);
4039 si_fini_cg(rdev);
4040
4041 /* Disable CP parsing/prefetching */
4042 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
4043 /* dma0 */
4044 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
4045 tmp &= ~DMA_RB_ENABLE;
4046 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
4047 /* dma1 */
4048 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
4049 tmp &= ~DMA_RB_ENABLE;
4050 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
4051 /* XXX other engines? */
4052
4053 /* halt the rlc, disable cp internal ints */
4054 si_rlc_stop(rdev);
4055
4056 udelay(50);
4057
4058 /* disable mem access */
4059 evergreen_mc_stop(rdev, &save);
4060 if (evergreen_mc_wait_for_idle(rdev)) {
4061 dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
4062 }
4063
4064 /* set mclk/sclk to bypass */
4065 si_set_clk_bypass_mode(rdev);
4066 /* powerdown spll */
4067 si_spll_powerdown(rdev);
4068 /* disable BM */
4069 pci_clear_master(rdev->pdev);
4070 /* reset */
4071 radeon_pci_config_reset(rdev);
4072 /* wait for asic to come out of reset */
4073 for (i = 0; i < rdev->usec_timeout; i++) {
4074 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
4075 break;
4076 udelay(1);
4077 }
4078 }
4079
4080 int si_asic_reset(struct radeon_device *rdev, bool hard)
4081 {
4082 u32 reset_mask;
4083
4084 if (hard) {
4085 si_gpu_pci_config_reset(rdev);
4086 return 0;
4087 }
4088
4089 reset_mask = si_gpu_check_soft_reset(rdev);
4090
4091 if (reset_mask)
4092 r600_set_bios_scratch_engine_hung(rdev, true);
4093
4094 /* try soft reset */
4095 si_gpu_soft_reset(rdev, reset_mask);
4096
4097 reset_mask = si_gpu_check_soft_reset(rdev);
4098
4099 /* try pci config reset */
4100 if (reset_mask && radeon_hard_reset)
4101 si_gpu_pci_config_reset(rdev);
4102
4103 reset_mask = si_gpu_check_soft_reset(rdev);
4104
4105 if (!reset_mask)
4106 r600_set_bios_scratch_engine_hung(rdev, false);
4107
4108 return 0;
4109 }
4110
4111 /**
4112 * si_gfx_is_lockup - Check if the GFX engine is locked up
4113 *
4114 * @rdev: radeon_device pointer
4115 * @ring: radeon_ring structure holding ring information
4116 *
4117 * Check if the GFX engine is locked up.
4118 * Returns true if the engine appears to be locked up, false if not.
4119 */
4120 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
4121 {
4122 u32 reset_mask = si_gpu_check_soft_reset(rdev);
4123
4124 if (!(reset_mask & (RADEON_RESET_GFX |
4125 RADEON_RESET_COMPUTE |
4126 RADEON_RESET_CP))) {
4127 radeon_ring_lockup_update(rdev, ring);
4128 return false;
4129 }
4130 return radeon_ring_test_lockup(rdev, ring);
4131 }
4132
4133 /* MC */
4134 static void si_mc_program(struct radeon_device *rdev)
4135 {
4136 struct evergreen_mc_save save;
4137 u32 tmp;
4138 int i, j;
4139
4140 /* Initialize HDP */
4141 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
4142 WREG32((0x2c14 + j), 0x00000000);
4143 WREG32((0x2c18 + j), 0x00000000);
4144 WREG32((0x2c1c + j), 0x00000000);
4145 WREG32((0x2c20 + j), 0x00000000);
4146 WREG32((0x2c24 + j), 0x00000000);
4147 }
4148 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
4149
4150 evergreen_mc_stop(rdev, &save);
4151 if (radeon_mc_wait_for_idle(rdev)) {
4152 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
4153 }
4154 if (!ASIC_IS_NODCE(rdev))
4155 /* Lockout access through VGA aperture*/
4156 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
4157 /* Update configuration */
4158 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
4159 rdev->mc.vram_start >> 12);
4160 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
4161 rdev->mc.vram_end >> 12);
4162 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
4163 rdev->vram_scratch.gpu_addr >> 12);
4164 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
4165 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
4166 WREG32(MC_VM_FB_LOCATION, tmp);
4167 /* XXX double check these! */
4168 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
4169 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
4170 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
4171 WREG32(MC_VM_AGP_BASE, 0);
4172 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
4173 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
4174 if (radeon_mc_wait_for_idle(rdev)) {
4175 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
4176 }
4177 evergreen_mc_resume(rdev, &save);
4178 if (!ASIC_IS_NODCE(rdev)) {
4179 /* we need to own VRAM, so turn off the VGA renderer here
4180 * to stop it overwriting our objects */
4181 rv515_vga_render_disable(rdev);
4182 }
4183 }
4184
4185 void si_vram_gtt_location(struct radeon_device *rdev,
4186 struct radeon_mc *mc)
4187 {
4188 if (mc->mc_vram_size > 0xFFC0000000ULL) {
4189 /* leave room for at least 1024M GTT */
4190 dev_warn(rdev->dev, "limiting VRAM\n");
4191 mc->real_vram_size = 0xFFC0000000ULL;
4192 mc->mc_vram_size = 0xFFC0000000ULL;
4193 }
4194 radeon_vram_location(rdev, &rdev->mc, 0);
4195 rdev->mc.gtt_base_align = 0;
4196 radeon_gtt_location(rdev, mc);
4197 }
4198
4199 static int si_mc_init(struct radeon_device *rdev)
4200 {
4201 u32 tmp;
4202 int chansize, numchan;
4203
4204 /* Get VRAM informations */
4205 rdev->mc.vram_is_ddr = true;
4206 tmp = RREG32(MC_ARB_RAMCFG);
4207 if (tmp & CHANSIZE_OVERRIDE) {
4208 chansize = 16;
4209 } else if (tmp & CHANSIZE_MASK) {
4210 chansize = 64;
4211 } else {
4212 chansize = 32;
4213 }
4214 tmp = RREG32(MC_SHARED_CHMAP);
4215 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
4216 case 0:
4217 default:
4218 numchan = 1;
4219 break;
4220 case 1:
4221 numchan = 2;
4222 break;
4223 case 2:
4224 numchan = 4;
4225 break;
4226 case 3:
4227 numchan = 8;
4228 break;
4229 case 4:
4230 numchan = 3;
4231 break;
4232 case 5:
4233 numchan = 6;
4234 break;
4235 case 6:
4236 numchan = 10;
4237 break;
4238 case 7:
4239 numchan = 12;
4240 break;
4241 case 8:
4242 numchan = 16;
4243 break;
4244 }
4245 rdev->mc.vram_width = numchan * chansize;
4246 /* Could aper size report 0 ? */
4247 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
4248 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
4249 /* size in MB on si */
4250 tmp = RREG32(CONFIG_MEMSIZE);
4251 /* some boards may have garbage in the upper 16 bits */
4252 if (tmp & 0xffff0000) {
4253 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
4254 if (tmp & 0xffff)
4255 tmp &= 0xffff;
4256 }
4257 rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL;
4258 rdev->mc.real_vram_size = rdev->mc.mc_vram_size;
4259 rdev->mc.visible_vram_size = rdev->mc.aper_size;
4260 si_vram_gtt_location(rdev, &rdev->mc);
4261 radeon_update_bandwidth_info(rdev);
4262
4263 return 0;
4264 }
4265
4266 /*
4267 * GART
4268 */
4269 void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
4270 {
4271 /* flush hdp cache */
4272 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4273
4274 /* bits 0-15 are the VM contexts0-15 */
4275 WREG32(VM_INVALIDATE_REQUEST, 1);
4276 }
4277
4278 static int si_pcie_gart_enable(struct radeon_device *rdev)
4279 {
4280 int r, i;
4281
4282 if (rdev->gart.robj == NULL) {
4283 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
4284 return -EINVAL;
4285 }
4286 r = radeon_gart_table_vram_pin(rdev);
4287 if (r)
4288 return r;
4289 /* Setup TLB control */
4290 WREG32(MC_VM_MX_L1_TLB_CNTL,
4291 (0xA << 7) |
4292 ENABLE_L1_TLB |
4293 ENABLE_L1_FRAGMENT_PROCESSING |
4294 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
4295 ENABLE_ADVANCED_DRIVER_MODEL |
4296 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
4297 /* Setup L2 cache */
4298 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
4299 ENABLE_L2_FRAGMENT_PROCESSING |
4300 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
4301 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
4302 EFFECTIVE_L2_QUEUE_SIZE(7) |
4303 CONTEXT1_IDENTITY_ACCESS_MODE(1));
4304 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
4305 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
4306 BANK_SELECT(4) |
4307 L2_CACHE_BIGK_FRAGMENT_SIZE(4));
4308 /* setup context0 */
4309 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
4310 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
4311 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
4312 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
4313 (u32)(rdev->dummy_page.addr >> 12));
4314 WREG32(VM_CONTEXT0_CNTL2, 0);
4315 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
4316 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
4317
4318 WREG32(0x15D4, 0);
4319 WREG32(0x15D8, 0);
4320 WREG32(0x15DC, 0);
4321
4322 /* empty context1-15 */
4323 /* set vm size, must be a multiple of 4 */
4324 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
4325 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);
4326 /* Assign the pt base to something valid for now; the pts used for
4327 * the VMs are determined by the application and setup and assigned
4328 * on the fly in the vm part of radeon_gart.c
4329 */
4330 for (i = 1; i < 16; i++) {
4331 if (i < 8)
4332 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
4333 rdev->vm_manager.saved_table_addr[i]);
4334 else
4335 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
4336 rdev->vm_manager.saved_table_addr[i]);
4337 }
4338
4339 /* enable context1-15 */
4340 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
4341 (u32)(rdev->dummy_page.addr >> 12));
4342 WREG32(VM_CONTEXT1_CNTL2, 4);
4343 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
4344 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
4345 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4346 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
4347 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4348 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
4349 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
4350 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
4351 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
4352 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
4353 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
4354 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
4355 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4356 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
4357
4358 si_pcie_gart_tlb_flush(rdev);
4359 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
4360 (unsigned)(rdev->mc.gtt_size >> 20),
4361 (unsigned long long)rdev->gart.table_addr);
4362 rdev->gart.ready = true;
4363 return 0;
4364 }
4365
4366 static void si_pcie_gart_disable(struct radeon_device *rdev)
4367 {
4368 unsigned i;
4369
4370 for (i = 1; i < 16; ++i) {
4371 uint32_t reg;
4372 if (i < 8)
4373 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2);
4374 else
4375 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2);
4376 rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
4377 }
4378
4379 /* Disable all tables */
4380 WREG32(VM_CONTEXT0_CNTL, 0);
4381 WREG32(VM_CONTEXT1_CNTL, 0);
4382 /* Setup TLB control */
4383 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
4384 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
4385 /* Setup L2 cache */
4386 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
4387 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
4388 EFFECTIVE_L2_QUEUE_SIZE(7) |
4389 CONTEXT1_IDENTITY_ACCESS_MODE(1));
4390 WREG32(VM_L2_CNTL2, 0);
4391 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
4392 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
4393 radeon_gart_table_vram_unpin(rdev);
4394 }
4395
4396 static void si_pcie_gart_fini(struct radeon_device *rdev)
4397 {
4398 si_pcie_gart_disable(rdev);
4399 radeon_gart_table_vram_free(rdev);
4400 radeon_gart_fini(rdev);
4401 }
4402
4403 /* vm parser */
4404 static bool si_vm_reg_valid(u32 reg)
4405 {
4406 /* context regs are fine */
4407 if (reg >= 0x28000)
4408 return true;
4409
4410 /* shader regs are also fine */
4411 if (reg >= 0xB000 && reg < 0xC000)
4412 return true;
4413
4414 /* check config regs */
4415 switch (reg) {
4416 case GRBM_GFX_INDEX:
4417 case CP_STRMOUT_CNTL:
4418 case VGT_VTX_VECT_EJECT_REG:
4419 case VGT_CACHE_INVALIDATION:
4420 case VGT_ESGS_RING_SIZE:
4421 case VGT_GSVS_RING_SIZE:
4422 case VGT_GS_VERTEX_REUSE:
4423 case VGT_PRIMITIVE_TYPE:
4424 case VGT_INDEX_TYPE:
4425 case VGT_NUM_INDICES:
4426 case VGT_NUM_INSTANCES:
4427 case VGT_TF_RING_SIZE:
4428 case VGT_HS_OFFCHIP_PARAM:
4429 case VGT_TF_MEMORY_BASE:
4430 case PA_CL_ENHANCE:
4431 case PA_SU_LINE_STIPPLE_VALUE:
4432 case PA_SC_LINE_STIPPLE_STATE:
4433 case PA_SC_ENHANCE:
4434 case SQC_CACHES:
4435 case SPI_STATIC_THREAD_MGMT_1:
4436 case SPI_STATIC_THREAD_MGMT_2:
4437 case SPI_STATIC_THREAD_MGMT_3:
4438 case SPI_PS_MAX_WAVE_ID:
4439 case SPI_CONFIG_CNTL:
4440 case SPI_CONFIG_CNTL_1:
4441 case TA_CNTL_AUX:
4442 case TA_CS_BC_BASE_ADDR:
4443 return true;
4444 default:
4445 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
4446 return false;
4447 }
4448 }
4449
4450 static int si_vm_packet3_ce_check(struct radeon_device *rdev,
4451 u32 *ib, struct radeon_cs_packet *pkt)
4452 {
4453 switch (pkt->opcode) {
4454 case PACKET3_NOP:
4455 case PACKET3_SET_BASE:
4456 case PACKET3_SET_CE_DE_COUNTERS:
4457 case PACKET3_LOAD_CONST_RAM:
4458 case PACKET3_WRITE_CONST_RAM:
4459 case PACKET3_WRITE_CONST_RAM_OFFSET:
4460 case PACKET3_DUMP_CONST_RAM:
4461 case PACKET3_INCREMENT_CE_COUNTER:
4462 case PACKET3_WAIT_ON_DE_COUNTER:
4463 case PACKET3_CE_WRITE:
4464 break;
4465 default:
4466 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
4467 return -EINVAL;
4468 }
4469 return 0;
4470 }
4471
4472 static int si_vm_packet3_cp_dma_check(u32 *ib, u32 idx)
4473 {
4474 u32 start_reg, reg, i;
4475 u32 command = ib[idx + 4];
4476 u32 info = ib[idx + 1];
4477 u32 idx_value = ib[idx];
4478 if (command & PACKET3_CP_DMA_CMD_SAS) {
4479 /* src address space is register */
4480 if (((info & 0x60000000) >> 29) == 0) {
4481 start_reg = idx_value << 2;
4482 if (command & PACKET3_CP_DMA_CMD_SAIC) {
4483 reg = start_reg;
4484 if (!si_vm_reg_valid(reg)) {
4485 DRM_ERROR("CP DMA Bad SRC register\n");
4486 return -EINVAL;
4487 }
4488 } else {
4489 for (i = 0; i < (command & 0x1fffff); i++) {
4490 reg = start_reg + (4 * i);
4491 if (!si_vm_reg_valid(reg)) {
4492 DRM_ERROR("CP DMA Bad SRC register\n");
4493 return -EINVAL;
4494 }
4495 }
4496 }
4497 }
4498 }
4499 if (command & PACKET3_CP_DMA_CMD_DAS) {
4500 /* dst address space is register */
4501 if (((info & 0x00300000) >> 20) == 0) {
4502 start_reg = ib[idx + 2];
4503 if (command & PACKET3_CP_DMA_CMD_DAIC) {
4504 reg = start_reg;
4505 if (!si_vm_reg_valid(reg)) {
4506 DRM_ERROR("CP DMA Bad DST register\n");
4507 return -EINVAL;
4508 }
4509 } else {
4510 for (i = 0; i < (command & 0x1fffff); i++) {
4511 reg = start_reg + (4 * i);
4512 if (!si_vm_reg_valid(reg)) {
4513 DRM_ERROR("CP DMA Bad DST register\n");
4514 return -EINVAL;
4515 }
4516 }
4517 }
4518 }
4519 }
4520 return 0;
4521 }
4522
4523 static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
4524 u32 *ib, struct radeon_cs_packet *pkt)
4525 {
4526 int r;
4527 u32 idx = pkt->idx + 1;
4528 u32 idx_value = ib[idx];
4529 u32 start_reg, end_reg, reg, i;
4530
4531 switch (pkt->opcode) {
4532 case PACKET3_NOP:
4533 case PACKET3_SET_BASE:
4534 case PACKET3_CLEAR_STATE:
4535 case PACKET3_INDEX_BUFFER_SIZE:
4536 case PACKET3_DISPATCH_DIRECT:
4537 case PACKET3_DISPATCH_INDIRECT:
4538 case PACKET3_ALLOC_GDS:
4539 case PACKET3_WRITE_GDS_RAM:
4540 case PACKET3_ATOMIC_GDS:
4541 case PACKET3_ATOMIC:
4542 case PACKET3_OCCLUSION_QUERY:
4543 case PACKET3_SET_PREDICATION:
4544 case PACKET3_COND_EXEC:
4545 case PACKET3_PRED_EXEC:
4546 case PACKET3_DRAW_INDIRECT:
4547 case PACKET3_DRAW_INDEX_INDIRECT:
4548 case PACKET3_INDEX_BASE:
4549 case PACKET3_DRAW_INDEX_2:
4550 case PACKET3_CONTEXT_CONTROL:
4551 case PACKET3_INDEX_TYPE:
4552 case PACKET3_DRAW_INDIRECT_MULTI:
4553 case PACKET3_DRAW_INDEX_AUTO:
4554 case PACKET3_DRAW_INDEX_IMMD:
4555 case PACKET3_NUM_INSTANCES:
4556 case PACKET3_DRAW_INDEX_MULTI_AUTO:
4557 case PACKET3_STRMOUT_BUFFER_UPDATE:
4558 case PACKET3_DRAW_INDEX_OFFSET_2:
4559 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
4560 case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
4561 case PACKET3_MPEG_INDEX:
4562 case PACKET3_WAIT_REG_MEM:
4563 case PACKET3_MEM_WRITE:
4564 case PACKET3_PFP_SYNC_ME:
4565 case PACKET3_SURFACE_SYNC:
4566 case PACKET3_EVENT_WRITE:
4567 case PACKET3_EVENT_WRITE_EOP:
4568 case PACKET3_EVENT_WRITE_EOS:
4569 case PACKET3_SET_CONTEXT_REG:
4570 case PACKET3_SET_CONTEXT_REG_INDIRECT:
4571 case PACKET3_SET_SH_REG:
4572 case PACKET3_SET_SH_REG_OFFSET:
4573 case PACKET3_INCREMENT_DE_COUNTER:
4574 case PACKET3_WAIT_ON_CE_COUNTER:
4575 case PACKET3_WAIT_ON_AVAIL_BUFFER:
4576 case PACKET3_ME_WRITE:
4577 break;
4578 case PACKET3_COPY_DATA:
4579 if ((idx_value & 0xf00) == 0) {
4580 reg = ib[idx + 3] * 4;
4581 if (!si_vm_reg_valid(reg))
4582 return -EINVAL;
4583 }
4584 break;
4585 case PACKET3_WRITE_DATA:
4586 if ((idx_value & 0xf00) == 0) {
4587 start_reg = ib[idx + 1] * 4;
4588 if (idx_value & 0x10000) {
4589 if (!si_vm_reg_valid(start_reg))
4590 return -EINVAL;
4591 } else {
4592 for (i = 0; i < (pkt->count - 2); i++) {
4593 reg = start_reg + (4 * i);
4594 if (!si_vm_reg_valid(reg))
4595 return -EINVAL;
4596 }
4597 }
4598 }
4599 break;
4600 case PACKET3_COND_WRITE:
4601 if (idx_value & 0x100) {
4602 reg = ib[idx + 5] * 4;
4603 if (!si_vm_reg_valid(reg))
4604 return -EINVAL;
4605 }
4606 break;
4607 case PACKET3_COPY_DW:
4608 if (idx_value & 0x2) {
4609 reg = ib[idx + 3] * 4;
4610 if (!si_vm_reg_valid(reg))
4611 return -EINVAL;
4612 }
4613 break;
4614 case PACKET3_SET_CONFIG_REG:
4615 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
4616 end_reg = 4 * pkt->count + start_reg - 4;
4617 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
4618 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
4619 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
4620 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
4621 return -EINVAL;
4622 }
4623 for (i = 0; i < pkt->count; i++) {
4624 reg = start_reg + (4 * i);
4625 if (!si_vm_reg_valid(reg))
4626 return -EINVAL;
4627 }
4628 break;
4629 case PACKET3_CP_DMA:
4630 r = si_vm_packet3_cp_dma_check(ib, idx);
4631 if (r)
4632 return r;
4633 break;
4634 default:
4635 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
4636 return -EINVAL;
4637 }
4638 return 0;
4639 }
4640
4641 static int si_vm_packet3_compute_check(struct radeon_device *rdev,
4642 u32 *ib, struct radeon_cs_packet *pkt)
4643 {
4644 int r;
4645 u32 idx = pkt->idx + 1;
4646 u32 idx_value = ib[idx];
4647 u32 start_reg, reg, i;
4648
4649 switch (pkt->opcode) {
4650 case PACKET3_NOP:
4651 case PACKET3_SET_BASE:
4652 case PACKET3_CLEAR_STATE:
4653 case PACKET3_DISPATCH_DIRECT:
4654 case PACKET3_DISPATCH_INDIRECT:
4655 case PACKET3_ALLOC_GDS:
4656 case PACKET3_WRITE_GDS_RAM:
4657 case PACKET3_ATOMIC_GDS:
4658 case PACKET3_ATOMIC:
4659 case PACKET3_OCCLUSION_QUERY:
4660 case PACKET3_SET_PREDICATION:
4661 case PACKET3_COND_EXEC:
4662 case PACKET3_PRED_EXEC:
4663 case PACKET3_CONTEXT_CONTROL:
4664 case PACKET3_STRMOUT_BUFFER_UPDATE:
4665 case PACKET3_WAIT_REG_MEM:
4666 case PACKET3_MEM_WRITE:
4667 case PACKET3_PFP_SYNC_ME:
4668 case PACKET3_SURFACE_SYNC:
4669 case PACKET3_EVENT_WRITE:
4670 case PACKET3_EVENT_WRITE_EOP:
4671 case PACKET3_EVENT_WRITE_EOS:
4672 case PACKET3_SET_CONTEXT_REG:
4673 case PACKET3_SET_CONTEXT_REG_INDIRECT:
4674 case PACKET3_SET_SH_REG:
4675 case PACKET3_SET_SH_REG_OFFSET:
4676 case PACKET3_INCREMENT_DE_COUNTER:
4677 case PACKET3_WAIT_ON_CE_COUNTER:
4678 case PACKET3_WAIT_ON_AVAIL_BUFFER:
4679 case PACKET3_ME_WRITE:
4680 break;
4681 case PACKET3_COPY_DATA:
4682 if ((idx_value & 0xf00) == 0) {
4683 reg = ib[idx + 3] * 4;
4684 if (!si_vm_reg_valid(reg))
4685 return -EINVAL;
4686 }
4687 break;
4688 case PACKET3_WRITE_DATA:
4689 if ((idx_value & 0xf00) == 0) {
4690 start_reg = ib[idx + 1] * 4;
4691 if (idx_value & 0x10000) {
4692 if (!si_vm_reg_valid(start_reg))
4693 return -EINVAL;
4694 } else {
4695 for (i = 0; i < (pkt->count - 2); i++) {
4696 reg = start_reg + (4 * i);
4697 if (!si_vm_reg_valid(reg))
4698 return -EINVAL;
4699 }
4700 }
4701 }
4702 break;
4703 case PACKET3_COND_WRITE:
4704 if (idx_value & 0x100) {
4705 reg = ib[idx + 5] * 4;
4706 if (!si_vm_reg_valid(reg))
4707 return -EINVAL;
4708 }
4709 break;
4710 case PACKET3_COPY_DW:
4711 if (idx_value & 0x2) {
4712 reg = ib[idx + 3] * 4;
4713 if (!si_vm_reg_valid(reg))
4714 return -EINVAL;
4715 }
4716 break;
4717 case PACKET3_CP_DMA:
4718 r = si_vm_packet3_cp_dma_check(ib, idx);
4719 if (r)
4720 return r;
4721 break;
4722 default:
4723 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
4724 return -EINVAL;
4725 }
4726 return 0;
4727 }
4728
4729 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
4730 {
4731 int ret = 0;
4732 u32 idx = 0, i;
4733 struct radeon_cs_packet pkt;
4734
4735 do {
4736 pkt.idx = idx;
4737 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
4738 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
4739 pkt.one_reg_wr = 0;
4740 switch (pkt.type) {
4741 case RADEON_PACKET_TYPE0:
4742 dev_err(rdev->dev, "Packet0 not allowed!\n");
4743 ret = -EINVAL;
4744 break;
4745 case RADEON_PACKET_TYPE2:
4746 idx += 1;
4747 break;
4748 case RADEON_PACKET_TYPE3:
4749 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
4750 if (ib->is_const_ib)
4751 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
4752 else {
4753 switch (ib->ring) {
4754 case RADEON_RING_TYPE_GFX_INDEX:
4755 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
4756 break;
4757 case CAYMAN_RING_TYPE_CP1_INDEX:
4758 case CAYMAN_RING_TYPE_CP2_INDEX:
4759 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
4760 break;
4761 default:
4762 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
4763 ret = -EINVAL;
4764 break;
4765 }
4766 }
4767 idx += pkt.count + 2;
4768 break;
4769 default:
4770 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
4771 ret = -EINVAL;
4772 break;
4773 }
4774 if (ret) {
4775 for (i = 0; i < ib->length_dw; i++) {
4776 if (i == idx)
4777 printk("\t0x%08x <---\n", ib->ptr[i]);
4778 else
4779 printk("\t0x%08x\n", ib->ptr[i]);
4780 }
4781 break;
4782 }
4783 } while (idx < ib->length_dw);
4784
4785 return ret;
4786 }
4787
4788 /*
4789 * vm
4790 */
4791 int si_vm_init(struct radeon_device *rdev)
4792 {
4793 /* number of VMs */
4794 rdev->vm_manager.nvm = 16;
4795 /* base offset of vram pages */
4796 rdev->vm_manager.vram_base_offset = 0;
4797
4798 return 0;
4799 }
4800
4801 void si_vm_fini(struct radeon_device *rdev)
4802 {
4803 }
4804
4805 /**
4806 * si_vm_decode_fault - print human readable fault info
4807 *
4808 * @rdev: radeon_device pointer
4809 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
4810 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
4811 *
4812 * Print human readable fault information (SI).
4813 */
4814 static void si_vm_decode_fault(struct radeon_device *rdev,
4815 u32 status, u32 addr)
4816 {
4817 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
4818 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
4819 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
4820 char *block;
4821
4822 if (rdev->family == CHIP_TAHITI) {
4823 switch (mc_id) {
4824 case 160:
4825 case 144:
4826 case 96:
4827 case 80:
4828 case 224:
4829 case 208:
4830 case 32:
4831 case 16:
4832 block = "CB";
4833 break;
4834 case 161:
4835 case 145:
4836 case 97:
4837 case 81:
4838 case 225:
4839 case 209:
4840 case 33:
4841 case 17:
4842 block = "CB_FMASK";
4843 break;
4844 case 162:
4845 case 146:
4846 case 98:
4847 case 82:
4848 case 226:
4849 case 210:
4850 case 34:
4851 case 18:
4852 block = "CB_CMASK";
4853 break;
4854 case 163:
4855 case 147:
4856 case 99:
4857 case 83:
4858 case 227:
4859 case 211:
4860 case 35:
4861 case 19:
4862 block = "CB_IMMED";
4863 break;
4864 case 164:
4865 case 148:
4866 case 100:
4867 case 84:
4868 case 228:
4869 case 212:
4870 case 36:
4871 case 20:
4872 block = "DB";
4873 break;
4874 case 165:
4875 case 149:
4876 case 101:
4877 case 85:
4878 case 229:
4879 case 213:
4880 case 37:
4881 case 21:
4882 block = "DB_HTILE";
4883 break;
4884 case 167:
4885 case 151:
4886 case 103:
4887 case 87:
4888 case 231:
4889 case 215:
4890 case 39:
4891 case 23:
4892 block = "DB_STEN";
4893 break;
4894 case 72:
4895 case 68:
4896 case 64:
4897 case 8:
4898 case 4:
4899 case 0:
4900 case 136:
4901 case 132:
4902 case 128:
4903 case 200:
4904 case 196:
4905 case 192:
4906 block = "TC";
4907 break;
4908 case 112:
4909 case 48:
4910 block = "CP";
4911 break;
4912 case 49:
4913 case 177:
4914 case 50:
4915 case 178:
4916 block = "SH";
4917 break;
4918 case 53:
4919 case 190:
4920 block = "VGT";
4921 break;
4922 case 117:
4923 block = "IH";
4924 break;
4925 case 51:
4926 case 115:
4927 block = "RLC";
4928 break;
4929 case 119:
4930 case 183:
4931 block = "DMA0";
4932 break;
4933 case 61:
4934 block = "DMA1";
4935 break;
4936 case 248:
4937 case 120:
4938 block = "HDP";
4939 break;
4940 default:
4941 block = "unknown";
4942 break;
4943 }
4944 } else {
4945 switch (mc_id) {
4946 case 32:
4947 case 16:
4948 case 96:
4949 case 80:
4950 case 160:
4951 case 144:
4952 case 224:
4953 case 208:
4954 block = "CB";
4955 break;
4956 case 33:
4957 case 17:
4958 case 97:
4959 case 81:
4960 case 161:
4961 case 145:
4962 case 225:
4963 case 209:
4964 block = "CB_FMASK";
4965 break;
4966 case 34:
4967 case 18:
4968 case 98:
4969 case 82:
4970 case 162:
4971 case 146:
4972 case 226:
4973 case 210:
4974 block = "CB_CMASK";
4975 break;
4976 case 35:
4977 case 19:
4978 case 99:
4979 case 83:
4980 case 163:
4981 case 147:
4982 case 227:
4983 case 211:
4984 block = "CB_IMMED";
4985 break;
4986 case 36:
4987 case 20:
4988 case 100:
4989 case 84:
4990 case 164:
4991 case 148:
4992 case 228:
4993 case 212:
4994 block = "DB";
4995 break;
4996 case 37:
4997 case 21:
4998 case 101:
4999 case 85:
5000 case 165:
5001 case 149:
5002 case 229:
5003 case 213:
5004 block = "DB_HTILE";
5005 break;
5006 case 39:
5007 case 23:
5008 case 103:
5009 case 87:
5010 case 167:
5011 case 151:
5012 case 231:
5013 case 215:
5014 block = "DB_STEN";
5015 break;
5016 case 72:
5017 case 68:
5018 case 8:
5019 case 4:
5020 case 136:
5021 case 132:
5022 case 200:
5023 case 196:
5024 block = "TC";
5025 break;
5026 case 112:
5027 case 48:
5028 block = "CP";
5029 break;
5030 case 49:
5031 case 177:
5032 case 50:
5033 case 178:
5034 block = "SH";
5035 break;
5036 case 53:
5037 block = "VGT";
5038 break;
5039 case 117:
5040 block = "IH";
5041 break;
5042 case 51:
5043 case 115:
5044 block = "RLC";
5045 break;
5046 case 119:
5047 case 183:
5048 block = "DMA0";
5049 break;
5050 case 61:
5051 block = "DMA1";
5052 break;
5053 case 248:
5054 case 120:
5055 block = "HDP";
5056 break;
5057 default:
5058 block = "unknown";
5059 break;
5060 }
5061 }
5062
5063 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
5064 protections, vmid, addr,
5065 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
5066 block, mc_id);
5067 }
5068
5069 void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
5070 unsigned vm_id, uint64_t pd_addr)
5071 {
5072 /* write new base address */
5073 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5074 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5075 WRITE_DATA_DST_SEL(0)));
5076
5077 if (vm_id < 8) {
5078 radeon_ring_write(ring,
5079 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
5080 } else {
5081 radeon_ring_write(ring,
5082 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
5083 }
5084 radeon_ring_write(ring, 0);
5085 radeon_ring_write(ring, pd_addr >> 12);
5086
5087 /* flush hdp cache */
5088 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5089 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5090 WRITE_DATA_DST_SEL(0)));
5091 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
5092 radeon_ring_write(ring, 0);
5093 radeon_ring_write(ring, 0x1);
5094
5095 /* bits 0-15 are the VM contexts0-15 */
5096 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5097 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5098 WRITE_DATA_DST_SEL(0)));
5099 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5100 radeon_ring_write(ring, 0);
5101 radeon_ring_write(ring, 1 << vm_id);
5102
5103 /* wait for the invalidate to complete */
5104 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
5105 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
5106 WAIT_REG_MEM_ENGINE(0))); /* me */
5107 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5108 radeon_ring_write(ring, 0);
5109 radeon_ring_write(ring, 0); /* ref */
5110 radeon_ring_write(ring, 0); /* mask */
5111 radeon_ring_write(ring, 0x20); /* poll interval */
5112
5113 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5114 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5115 radeon_ring_write(ring, 0x0);
5116 }
5117
5118 /*
5119 * Power and clock gating
5120 */
5121 static void si_wait_for_rlc_serdes(struct radeon_device *rdev)
5122 {
5123 int i;
5124
5125 for (i = 0; i < rdev->usec_timeout; i++) {
5126 if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0)
5127 break;
5128 udelay(1);
5129 }
5130
5131 for (i = 0; i < rdev->usec_timeout; i++) {
5132 if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0)
5133 break;
5134 udelay(1);
5135 }
5136 }
5137
5138 static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
5139 bool enable)
5140 {
5141 u32 tmp = RREG32(CP_INT_CNTL_RING0);
5142 u32 mask;
5143 int i;
5144
5145 if (enable)
5146 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5147 else
5148 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5149 WREG32(CP_INT_CNTL_RING0, tmp);
5150
5151 if (!enable) {
5152 /* read a gfx register */
5153 tmp = RREG32(DB_DEPTH_INFO);
5154
5155 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
5156 for (i = 0; i < rdev->usec_timeout; i++) {
5157 if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
5158 break;
5159 udelay(1);
5160 }
5161 }
5162 }
5163
5164 static void si_set_uvd_dcm(struct radeon_device *rdev,
5165 bool sw_mode)
5166 {
5167 u32 tmp, tmp2;
5168
5169 tmp = RREG32(UVD_CGC_CTRL);
5170 tmp &= ~(CLK_OD_MASK | CG_DT_MASK);
5171 tmp |= DCM | CG_DT(1) | CLK_OD(4);
5172
5173 if (sw_mode) {
5174 tmp &= ~0x7ffff800;
5175 tmp2 = DYN_OR_EN | DYN_RR_EN | G_DIV_ID(7);
5176 } else {
5177 tmp |= 0x7ffff800;
5178 tmp2 = 0;
5179 }
5180
5181 WREG32(UVD_CGC_CTRL, tmp);
5182 WREG32_UVD_CTX(UVD_CGC_CTRL2, tmp2);
5183 }
5184
5185 void si_init_uvd_internal_cg(struct radeon_device *rdev)
5186 {
5187 bool hw_mode = true;
5188
5189 if (hw_mode) {
5190 si_set_uvd_dcm(rdev, false);
5191 } else {
5192 u32 tmp = RREG32(UVD_CGC_CTRL);
5193 tmp &= ~DCM;
5194 WREG32(UVD_CGC_CTRL, tmp);
5195 }
5196 }
5197
5198 static u32 si_halt_rlc(struct radeon_device *rdev)
5199 {
5200 u32 data, orig;
5201
5202 orig = data = RREG32(RLC_CNTL);
5203
5204 if (data & RLC_ENABLE) {
5205 data &= ~RLC_ENABLE;
5206 WREG32(RLC_CNTL, data);
5207
5208 si_wait_for_rlc_serdes(rdev);
5209 }
5210
5211 return orig;
5212 }
5213
5214 static void si_update_rlc(struct radeon_device *rdev, u32 rlc)
5215 {
5216 u32 tmp;
5217
5218 tmp = RREG32(RLC_CNTL);
5219 if (tmp != rlc)
5220 WREG32(RLC_CNTL, rlc);
5221 }
5222
5223 static void si_enable_dma_pg(struct radeon_device *rdev, bool enable)
5224 {
5225 u32 data, orig;
5226
5227 orig = data = RREG32(DMA_PG);
5228 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA))
5229 data |= PG_CNTL_ENABLE;
5230 else
5231 data &= ~PG_CNTL_ENABLE;
5232 if (orig != data)
5233 WREG32(DMA_PG, data);
5234 }
5235
5236 static void si_init_dma_pg(struct radeon_device *rdev)
5237 {
5238 u32 tmp;
5239
5240 WREG32(DMA_PGFSM_WRITE, 0x00002000);
5241 WREG32(DMA_PGFSM_CONFIG, 0x100010ff);
5242
5243 for (tmp = 0; tmp < 5; tmp++)
5244 WREG32(DMA_PGFSM_WRITE, 0);
5245 }
5246
5247 static void si_enable_gfx_cgpg(struct radeon_device *rdev,
5248 bool enable)
5249 {
5250 u32 tmp;
5251
5252 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
5253 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
5254 WREG32(RLC_TTOP_D, tmp);
5255
5256 tmp = RREG32(RLC_PG_CNTL);
5257 tmp |= GFX_PG_ENABLE;
5258 WREG32(RLC_PG_CNTL, tmp);
5259
5260 tmp = RREG32(RLC_AUTO_PG_CTRL);
5261 tmp |= AUTO_PG_EN;
5262 WREG32(RLC_AUTO_PG_CTRL, tmp);
5263 } else {
5264 tmp = RREG32(RLC_AUTO_PG_CTRL);
5265 tmp &= ~AUTO_PG_EN;
5266 WREG32(RLC_AUTO_PG_CTRL, tmp);
5267
5268 tmp = RREG32(DB_RENDER_CONTROL);
5269 }
5270 }
5271
5272 static void si_init_gfx_cgpg(struct radeon_device *rdev)
5273 {
5274 u32 tmp;
5275
5276 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5277
5278 tmp = RREG32(RLC_PG_CNTL);
5279 tmp |= GFX_PG_SRC;
5280 WREG32(RLC_PG_CNTL, tmp);
5281
5282 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5283
5284 tmp = RREG32(RLC_AUTO_PG_CTRL);
5285
5286 tmp &= ~GRBM_REG_SGIT_MASK;
5287 tmp |= GRBM_REG_SGIT(0x700);
5288 tmp &= ~PG_AFTER_GRBM_REG_ST_MASK;
5289 WREG32(RLC_AUTO_PG_CTRL, tmp);
5290 }
5291
5292 static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)
5293 {
5294 u32 mask = 0, tmp, tmp1;
5295 int i;
5296
5297 si_select_se_sh(rdev, se, sh);
5298 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
5299 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
5300 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5301
5302 tmp &= 0xffff0000;
5303
5304 tmp |= tmp1;
5305 tmp >>= 16;
5306
5307 for (i = 0; i < rdev->config.si.max_cu_per_sh; i ++) {
5308 mask <<= 1;
5309 mask |= 1;
5310 }
5311
5312 return (~tmp) & mask;
5313 }
5314
5315 static void si_init_ao_cu_mask(struct radeon_device *rdev)
5316 {
5317 u32 i, j, k, active_cu_number = 0;
5318 u32 mask, counter, cu_bitmap;
5319 u32 tmp = 0;
5320
5321 for (i = 0; i < rdev->config.si.max_shader_engines; i++) {
5322 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {
5323 mask = 1;
5324 cu_bitmap = 0;
5325 counter = 0;
5326 for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) {
5327 if (si_get_cu_active_bitmap(rdev, i, j) & mask) {
5328 if (counter < 2)
5329 cu_bitmap |= mask;
5330 counter++;
5331 }
5332 mask <<= 1;
5333 }
5334
5335 active_cu_number += counter;
5336 tmp |= (cu_bitmap << (i * 16 + j * 8));
5337 }
5338 }
5339
5340 WREG32(RLC_PG_AO_CU_MASK, tmp);
5341
5342 tmp = RREG32(RLC_MAX_PG_CU);
5343 tmp &= ~MAX_PU_CU_MASK;
5344 tmp |= MAX_PU_CU(active_cu_number);
5345 WREG32(RLC_MAX_PG_CU, tmp);
5346 }
5347
5348 static void si_enable_cgcg(struct radeon_device *rdev,
5349 bool enable)
5350 {
5351 u32 data, orig, tmp;
5352
5353 orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
5354
5355 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
5356 si_enable_gui_idle_interrupt(rdev, true);
5357
5358 WREG32(RLC_GCPM_GENERAL_3, 0x00000080);
5359
5360 tmp = si_halt_rlc(rdev);
5361
5362 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
5363 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
5364 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
5365
5366 si_wait_for_rlc_serdes(rdev);
5367
5368 si_update_rlc(rdev, tmp);
5369
5370 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
5371
5372 data |= CGCG_EN | CGLS_EN;
5373 } else {
5374 si_enable_gui_idle_interrupt(rdev, false);
5375
5376 RREG32(CB_CGTT_SCLK_CTRL);
5377 RREG32(CB_CGTT_SCLK_CTRL);
5378 RREG32(CB_CGTT_SCLK_CTRL);
5379 RREG32(CB_CGTT_SCLK_CTRL);
5380
5381 data &= ~(CGCG_EN | CGLS_EN);
5382 }
5383
5384 if (orig != data)
5385 WREG32(RLC_CGCG_CGLS_CTRL, data);
5386 }
5387
5388 static void si_enable_mgcg(struct radeon_device *rdev,
5389 bool enable)
5390 {
5391 u32 data, orig, tmp = 0;
5392
5393 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {
5394 orig = data = RREG32(CGTS_SM_CTRL_REG);
5395 data = 0x96940200;
5396 if (orig != data)
5397 WREG32(CGTS_SM_CTRL_REG, data);
5398
5399 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CP_LS) {
5400 orig = data = RREG32(CP_MEM_SLP_CNTL);
5401 data |= CP_MEM_LS_EN;
5402 if (orig != data)
5403 WREG32(CP_MEM_SLP_CNTL, data);
5404 }
5405
5406 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
5407 data &= 0xffffffc0;
5408 if (orig != data)
5409 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
5410
5411 tmp = si_halt_rlc(rdev);
5412
5413 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
5414 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
5415 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff);
5416
5417 si_update_rlc(rdev, tmp);
5418 } else {
5419 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
5420 data |= 0x00000003;
5421 if (orig != data)
5422 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
5423
5424 data = RREG32(CP_MEM_SLP_CNTL);
5425 if (data & CP_MEM_LS_EN) {
5426 data &= ~CP_MEM_LS_EN;
5427 WREG32(CP_MEM_SLP_CNTL, data);
5428 }
5429 orig = data = RREG32(CGTS_SM_CTRL_REG);
5430 data |= LS_OVERRIDE | OVERRIDE;
5431 if (orig != data)
5432 WREG32(CGTS_SM_CTRL_REG, data);
5433
5434 tmp = si_halt_rlc(rdev);
5435
5436 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
5437 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
5438 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff);
5439
5440 si_update_rlc(rdev, tmp);
5441 }
5442 }
5443
5444 static void si_enable_uvd_mgcg(struct radeon_device *rdev,
5445 bool enable)
5446 {
5447 u32 orig, data, tmp;
5448
5449 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {
5450 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
5451 tmp |= 0x3fff;
5452 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
5453
5454 orig = data = RREG32(UVD_CGC_CTRL);
5455 data |= DCM;
5456 if (orig != data)
5457 WREG32(UVD_CGC_CTRL, data);
5458
5459 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0);
5460 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0);
5461 } else {
5462 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
5463 tmp &= ~0x3fff;
5464 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
5465
5466 orig = data = RREG32(UVD_CGC_CTRL);
5467 data &= ~DCM;
5468 if (orig != data)
5469 WREG32(UVD_CGC_CTRL, data);
5470
5471 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff);
5472 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff);
5473 }
5474 }
5475
5476 static const u32 mc_cg_registers[] =
5477 {
5478 MC_HUB_MISC_HUB_CG,
5479 MC_HUB_MISC_SIP_CG,
5480 MC_HUB_MISC_VM_CG,
5481 MC_XPB_CLK_GAT,
5482 ATC_MISC_CG,
5483 MC_CITF_MISC_WR_CG,
5484 MC_CITF_MISC_RD_CG,
5485 MC_CITF_MISC_VM_CG,
5486 VM_L2_CG,
5487 };
5488
5489 static void si_enable_mc_ls(struct radeon_device *rdev,
5490 bool enable)
5491 {
5492 int i;
5493 u32 orig, data;
5494
5495 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
5496 orig = data = RREG32(mc_cg_registers[i]);
5497 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
5498 data |= MC_LS_ENABLE;
5499 else
5500 data &= ~MC_LS_ENABLE;
5501 if (data != orig)
5502 WREG32(mc_cg_registers[i], data);
5503 }
5504 }
5505
5506 static void si_enable_mc_mgcg(struct radeon_device *rdev,
5507 bool enable)
5508 {
5509 int i;
5510 u32 orig, data;
5511
5512 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
5513 orig = data = RREG32(mc_cg_registers[i]);
5514 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))
5515 data |= MC_CG_ENABLE;
5516 else
5517 data &= ~MC_CG_ENABLE;
5518 if (data != orig)
5519 WREG32(mc_cg_registers[i], data);
5520 }
5521 }
5522
5523 static void si_enable_dma_mgcg(struct radeon_device *rdev,
5524 bool enable)
5525 {
5526 u32 orig, data, offset;
5527 int i;
5528
5529 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {
5530 for (i = 0; i < 2; i++) {
5531 if (i == 0)
5532 offset = DMA0_REGISTER_OFFSET;
5533 else
5534 offset = DMA1_REGISTER_OFFSET;
5535 orig = data = RREG32(DMA_POWER_CNTL + offset);
5536 data &= ~MEM_POWER_OVERRIDE;
5537 if (data != orig)
5538 WREG32(DMA_POWER_CNTL + offset, data);
5539 WREG32(DMA_CLK_CTRL + offset, 0x00000100);
5540 }
5541 } else {
5542 for (i = 0; i < 2; i++) {
5543 if (i == 0)
5544 offset = DMA0_REGISTER_OFFSET;
5545 else
5546 offset = DMA1_REGISTER_OFFSET;
5547 orig = data = RREG32(DMA_POWER_CNTL + offset);
5548 data |= MEM_POWER_OVERRIDE;
5549 if (data != orig)
5550 WREG32(DMA_POWER_CNTL + offset, data);
5551
5552 orig = data = RREG32(DMA_CLK_CTRL + offset);
5553 data = 0xff000000;
5554 if (data != orig)
5555 WREG32(DMA_CLK_CTRL + offset, data);
5556 }
5557 }
5558 }
5559
5560 static void si_enable_bif_mgls(struct radeon_device *rdev,
5561 bool enable)
5562 {
5563 u32 orig, data;
5564
5565 orig = data = RREG32_PCIE(PCIE_CNTL2);
5566
5567 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))
5568 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN |
5569 REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN;
5570 else
5571 data &= ~(SLV_MEM_LS_EN | MST_MEM_LS_EN |
5572 REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN);
5573
5574 if (orig != data)
5575 WREG32_PCIE(PCIE_CNTL2, data);
5576 }
5577
5578 static void si_enable_hdp_mgcg(struct radeon_device *rdev,
5579 bool enable)
5580 {
5581 u32 orig, data;
5582
5583 orig = data = RREG32(HDP_HOST_PATH_CNTL);
5584
5585 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))
5586 data &= ~CLOCK_GATING_DIS;
5587 else
5588 data |= CLOCK_GATING_DIS;
5589
5590 if (orig != data)
5591 WREG32(HDP_HOST_PATH_CNTL, data);
5592 }
5593
5594 static void si_enable_hdp_ls(struct radeon_device *rdev,
5595 bool enable)
5596 {
5597 u32 orig, data;
5598
5599 orig = data = RREG32(HDP_MEM_POWER_LS);
5600
5601 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))
5602 data |= HDP_LS_ENABLE;
5603 else
5604 data &= ~HDP_LS_ENABLE;
5605
5606 if (orig != data)
5607 WREG32(HDP_MEM_POWER_LS, data);
5608 }
5609
5610 static void si_update_cg(struct radeon_device *rdev,
5611 u32 block, bool enable)
5612 {
5613 if (block & RADEON_CG_BLOCK_GFX) {
5614 si_enable_gui_idle_interrupt(rdev, false);
5615 /* order matters! */
5616 if (enable) {
5617 si_enable_mgcg(rdev, true);
5618 si_enable_cgcg(rdev, true);
5619 } else {
5620 si_enable_cgcg(rdev, false);
5621 si_enable_mgcg(rdev, false);
5622 }
5623 si_enable_gui_idle_interrupt(rdev, true);
5624 }
5625
5626 if (block & RADEON_CG_BLOCK_MC) {
5627 si_enable_mc_mgcg(rdev, enable);
5628 si_enable_mc_ls(rdev, enable);
5629 }
5630
5631 if (block & RADEON_CG_BLOCK_SDMA) {
5632 si_enable_dma_mgcg(rdev, enable);
5633 }
5634
5635 if (block & RADEON_CG_BLOCK_BIF) {
5636 si_enable_bif_mgls(rdev, enable);
5637 }
5638
5639 if (block & RADEON_CG_BLOCK_UVD) {
5640 if (rdev->has_uvd) {
5641 si_enable_uvd_mgcg(rdev, enable);
5642 }
5643 }
5644
5645 if (block & RADEON_CG_BLOCK_HDP) {
5646 si_enable_hdp_mgcg(rdev, enable);
5647 si_enable_hdp_ls(rdev, enable);
5648 }
5649 }
5650
5651 static void si_init_cg(struct radeon_device *rdev)
5652 {
5653 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
5654 RADEON_CG_BLOCK_MC |
5655 RADEON_CG_BLOCK_SDMA |
5656 RADEON_CG_BLOCK_BIF |
5657 RADEON_CG_BLOCK_HDP), true);
5658 if (rdev->has_uvd) {
5659 si_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);
5660 si_init_uvd_internal_cg(rdev);
5661 }
5662 }
5663
5664 static void si_fini_cg(struct radeon_device *rdev)
5665 {
5666 if (rdev->has_uvd) {
5667 si_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
5668 }
5669 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
5670 RADEON_CG_BLOCK_MC |
5671 RADEON_CG_BLOCK_SDMA |
5672 RADEON_CG_BLOCK_BIF |
5673 RADEON_CG_BLOCK_HDP), false);
5674 }
5675
5676 u32 si_get_csb_size(struct radeon_device *rdev)
5677 {
5678 u32 count = 0;
5679 const struct cs_section_def *sect = NULL;
5680 const struct cs_extent_def *ext = NULL;
5681
5682 if (rdev->rlc.cs_data == NULL)
5683 return 0;
5684
5685 /* begin clear state */
5686 count += 2;
5687 /* context control state */
5688 count += 3;
5689
5690 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
5691 for (ext = sect->section; ext->extent != NULL; ++ext) {
5692 if (sect->id == SECT_CONTEXT)
5693 count += 2 + ext->reg_count;
5694 else
5695 return 0;
5696 }
5697 }
5698 /* pa_sc_raster_config */
5699 count += 3;
5700 /* end clear state */
5701 count += 2;
5702 /* clear state */
5703 count += 2;
5704
5705 return count;
5706 }
5707
5708 void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
5709 {
5710 u32 count = 0, i;
5711 const struct cs_section_def *sect = NULL;
5712 const struct cs_extent_def *ext = NULL;
5713
5714 if (rdev->rlc.cs_data == NULL)
5715 return;
5716 if (buffer == NULL)
5717 return;
5718
5719 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5720 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5721
5722 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5723 buffer[count++] = cpu_to_le32(0x80000000);
5724 buffer[count++] = cpu_to_le32(0x80000000);
5725
5726 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
5727 for (ext = sect->section; ext->extent != NULL; ++ext) {
5728 if (sect->id == SECT_CONTEXT) {
5729 buffer[count++] =
5730 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
5731 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
5732 for (i = 0; i < ext->reg_count; i++)
5733 buffer[count++] = cpu_to_le32(ext->extent[i]);
5734 } else {
5735 return;
5736 }
5737 }
5738 }
5739
5740 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5741 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
5742 switch (rdev->family) {
5743 case CHIP_TAHITI:
5744 case CHIP_PITCAIRN:
5745 buffer[count++] = cpu_to_le32(0x2a00126a);
5746 break;
5747 case CHIP_VERDE:
5748 buffer[count++] = cpu_to_le32(0x0000124a);
5749 break;
5750 case CHIP_OLAND:
5751 buffer[count++] = cpu_to_le32(0x00000082);
5752 break;
5753 case CHIP_HAINAN:
5754 buffer[count++] = cpu_to_le32(0x00000000);
5755 break;
5756 default:
5757 buffer[count++] = cpu_to_le32(0x00000000);
5758 break;
5759 }
5760
5761 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5762 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
5763
5764 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
5765 buffer[count++] = cpu_to_le32(0);
5766 }
5767
5768 static void si_init_pg(struct radeon_device *rdev)
5769 {
5770 if (rdev->pg_flags) {
5771 if (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA) {
5772 si_init_dma_pg(rdev);
5773 }
5774 si_init_ao_cu_mask(rdev);
5775 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
5776 si_init_gfx_cgpg(rdev);
5777 } else {
5778 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5779 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5780 }
5781 si_enable_dma_pg(rdev, true);
5782 si_enable_gfx_cgpg(rdev, true);
5783 } else {
5784 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5785 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5786 }
5787 }
5788
5789 static void si_fini_pg(struct radeon_device *rdev)
5790 {
5791 if (rdev->pg_flags) {
5792 si_enable_dma_pg(rdev, false);
5793 si_enable_gfx_cgpg(rdev, false);
5794 }
5795 }
5796
5797 /*
5798 * RLC
5799 */
5800 void si_rlc_reset(struct radeon_device *rdev)
5801 {
5802 u32 tmp = RREG32(GRBM_SOFT_RESET);
5803
5804 tmp |= SOFT_RESET_RLC;
5805 WREG32(GRBM_SOFT_RESET, tmp);
5806 udelay(50);
5807 tmp &= ~SOFT_RESET_RLC;
5808 WREG32(GRBM_SOFT_RESET, tmp);
5809 udelay(50);
5810 }
5811
5812 static void si_rlc_stop(struct radeon_device *rdev)
5813 {
5814 WREG32(RLC_CNTL, 0);
5815
5816 si_enable_gui_idle_interrupt(rdev, false);
5817
5818 si_wait_for_rlc_serdes(rdev);
5819 }
5820
5821 static void si_rlc_start(struct radeon_device *rdev)
5822 {
5823 WREG32(RLC_CNTL, RLC_ENABLE);
5824
5825 si_enable_gui_idle_interrupt(rdev, true);
5826
5827 udelay(50);
5828 }
5829
5830 static bool si_lbpw_supported(struct radeon_device *rdev)
5831 {
5832 u32 tmp;
5833
5834 /* Enable LBPW only for DDR3 */
5835 tmp = RREG32(MC_SEQ_MISC0);
5836 if ((tmp & 0xF0000000) == 0xB0000000)
5837 return true;
5838 return false;
5839 }
5840
5841 static void si_enable_lbpw(struct radeon_device *rdev, bool enable)
5842 {
5843 u32 tmp;
5844
5845 tmp = RREG32(RLC_LB_CNTL);
5846 if (enable)
5847 tmp |= LOAD_BALANCE_ENABLE;
5848 else
5849 tmp &= ~LOAD_BALANCE_ENABLE;
5850 WREG32(RLC_LB_CNTL, tmp);
5851
5852 if (!enable) {
5853 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5854 WREG32(SPI_LB_CU_MASK, 0x00ff);
5855 }
5856 }
5857
5858 static int si_rlc_resume(struct radeon_device *rdev)
5859 {
5860 u32 i;
5861
5862 if (!rdev->rlc_fw)
5863 return -EINVAL;
5864
5865 si_rlc_stop(rdev);
5866
5867 si_rlc_reset(rdev);
5868
5869 si_init_pg(rdev);
5870
5871 si_init_cg(rdev);
5872
5873 WREG32(RLC_RL_BASE, 0);
5874 WREG32(RLC_RL_SIZE, 0);
5875 WREG32(RLC_LB_CNTL, 0);
5876 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
5877 WREG32(RLC_LB_CNTR_INIT, 0);
5878 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
5879
5880 WREG32(RLC_MC_CNTL, 0);
5881 WREG32(RLC_UCODE_CNTL, 0);
5882
5883 if (rdev->new_fw) {
5884 const struct rlc_firmware_header_v1_0 *hdr =
5885 (const struct rlc_firmware_header_v1_0 *)rdev->rlc_fw->data;
5886 u32 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5887 const __le32 *fw_data = (const __le32 *)
5888 (rdev->rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5889
5890 radeon_ucode_print_rlc_hdr(&hdr->header);
5891
5892 for (i = 0; i < fw_size; i++) {
5893 WREG32(RLC_UCODE_ADDR, i);
5894 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++));
5895 }
5896 } else {
5897 const __be32 *fw_data =
5898 (const __be32 *)rdev->rlc_fw->data;
5899 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
5900 WREG32(RLC_UCODE_ADDR, i);
5901 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
5902 }
5903 }
5904 WREG32(RLC_UCODE_ADDR, 0);
5905
5906 si_enable_lbpw(rdev, si_lbpw_supported(rdev));
5907
5908 si_rlc_start(rdev);
5909
5910 return 0;
5911 }
5912
5913 static void si_enable_interrupts(struct radeon_device *rdev)
5914 {
5915 u32 ih_cntl = RREG32(IH_CNTL);
5916 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
5917
5918 ih_cntl |= ENABLE_INTR;
5919 ih_rb_cntl |= IH_RB_ENABLE;
5920 WREG32(IH_CNTL, ih_cntl);
5921 WREG32(IH_RB_CNTL, ih_rb_cntl);
5922 rdev->ih.enabled = true;
5923 }
5924
5925 static void si_disable_interrupts(struct radeon_device *rdev)
5926 {
5927 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
5928 u32 ih_cntl = RREG32(IH_CNTL);
5929
5930 ih_rb_cntl &= ~IH_RB_ENABLE;
5931 ih_cntl &= ~ENABLE_INTR;
5932 WREG32(IH_RB_CNTL, ih_rb_cntl);
5933 WREG32(IH_CNTL, ih_cntl);
5934 /* set rptr, wptr to 0 */
5935 WREG32(IH_RB_RPTR, 0);
5936 WREG32(IH_RB_WPTR, 0);
5937 rdev->ih.enabled = false;
5938 rdev->ih.rptr = 0;
5939 }
5940
5941 static void si_disable_interrupt_state(struct radeon_device *rdev)
5942 {
5943 int i;
5944 u32 tmp;
5945
5946 tmp = RREG32(CP_INT_CNTL_RING0) &
5947 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5948 WREG32(CP_INT_CNTL_RING0, tmp);
5949 WREG32(CP_INT_CNTL_RING1, 0);
5950 WREG32(CP_INT_CNTL_RING2, 0);
5951 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
5952 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
5953 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
5954 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
5955 WREG32(GRBM_INT_CNTL, 0);
5956 WREG32(SRBM_INT_CNTL, 0);
5957 for (i = 0; i < rdev->num_crtc; i++)
5958 WREG32(INT_MASK + crtc_offsets[i], 0);
5959 for (i = 0; i < rdev->num_crtc; i++)
5960 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);
5961
5962 if (!ASIC_IS_NODCE(rdev)) {
5963 WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
5964
5965 for (i = 0; i < 6; i++)
5966 WREG32_AND(DC_HPDx_INT_CONTROL(i),
5967 DC_HPDx_INT_POLARITY);
5968 }
5969 }
5970
5971 static int si_irq_init(struct radeon_device *rdev)
5972 {
5973 int ret = 0;
5974 int rb_bufsz;
5975 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
5976
5977 /* allocate ring */
5978 ret = r600_ih_ring_alloc(rdev);
5979 if (ret)
5980 return ret;
5981
5982 /* disable irqs */
5983 si_disable_interrupts(rdev);
5984
5985 /* init rlc */
5986 ret = si_rlc_resume(rdev);
5987 if (ret) {
5988 r600_ih_ring_fini(rdev);
5989 return ret;
5990 }
5991
5992 /* setup interrupt control */
5993 /* set dummy read address to ring address */
5994 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
5995 interrupt_cntl = RREG32(INTERRUPT_CNTL);
5996 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
5997 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
5998 */
5999 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
6000 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
6001 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
6002 WREG32(INTERRUPT_CNTL, interrupt_cntl);
6003
6004 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
6005 rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
6006
6007 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
6008 IH_WPTR_OVERFLOW_CLEAR |
6009 (rb_bufsz << 1));
6010
6011 if (rdev->wb.enabled)
6012 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
6013
6014 /* set the writeback address whether it's enabled or not */
6015 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
6016 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
6017
6018 WREG32(IH_RB_CNTL, ih_rb_cntl);
6019
6020 /* set rptr, wptr to 0 */
6021 WREG32(IH_RB_RPTR, 0);
6022 WREG32(IH_RB_WPTR, 0);
6023
6024 /* Default settings for IH_CNTL (disabled at first) */
6025 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
6026 /* RPTR_REARM only works if msi's are enabled */
6027 if (rdev->msi_enabled)
6028 ih_cntl |= RPTR_REARM;
6029 WREG32(IH_CNTL, ih_cntl);
6030
6031 /* force the active interrupt state to all disabled */
6032 si_disable_interrupt_state(rdev);
6033
6034 pci_set_master(rdev->pdev);
6035
6036 /* enable irqs */
6037 si_enable_interrupts(rdev);
6038
6039 return ret;
6040 }
6041
6042 /* The order we write back each register here is important */
6043 int si_irq_set(struct radeon_device *rdev)
6044 {
6045 int i;
6046 u32 cp_int_cntl;
6047 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
6048 u32 grbm_int_cntl = 0;
6049 u32 dma_cntl, dma_cntl1;
6050 u32 thermal_int = 0;
6051
6052 if (!rdev->irq.installed) {
6053 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
6054 return -EINVAL;
6055 }
6056 /* don't enable anything if the ih is disabled */
6057 if (!rdev->ih.enabled) {
6058 si_disable_interrupts(rdev);
6059 /* force the active interrupt state to all disabled */
6060 si_disable_interrupt_state(rdev);
6061 return 0;
6062 }
6063
6064 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
6065 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
6066
6067 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
6068 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
6069
6070 thermal_int = RREG32(CG_THERMAL_INT) &
6071 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6072
6073 /* enable CP interrupts on all rings */
6074 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
6075 DRM_DEBUG("si_irq_set: sw int gfx\n");
6076 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
6077 }
6078 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
6079 DRM_DEBUG("si_irq_set: sw int cp1\n");
6080 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
6081 }
6082 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
6083 DRM_DEBUG("si_irq_set: sw int cp2\n");
6084 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
6085 }
6086 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
6087 DRM_DEBUG("si_irq_set: sw int dma\n");
6088 dma_cntl |= TRAP_ENABLE;
6089 }
6090
6091 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
6092 DRM_DEBUG("si_irq_set: sw int dma1\n");
6093 dma_cntl1 |= TRAP_ENABLE;
6094 }
6095
6096 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
6097 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
6098 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
6099
6100 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
6101 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
6102
6103 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
6104
6105 if (rdev->irq.dpm_thermal) {
6106 DRM_DEBUG("dpm thermal\n");
6107 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6108 }
6109
6110 for (i = 0; i < rdev->num_crtc; i++) {
6111 radeon_irq_kms_set_irq_n_enabled(
6112 rdev, INT_MASK + crtc_offsets[i], VBLANK_INT_MASK,
6113 rdev->irq.crtc_vblank_int[i] ||
6114 atomic_read(&rdev->irq.pflip[i]), "vblank", i);
6115 }
6116
6117 for (i = 0; i < rdev->num_crtc; i++)
6118 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);
6119
6120 if (!ASIC_IS_NODCE(rdev)) {
6121 for (i = 0; i < 6; i++) {
6122 radeon_irq_kms_set_irq_n_enabled(
6123 rdev, DC_HPDx_INT_CONTROL(i),
6124 DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN,
6125 rdev->irq.hpd[i], "HPD", i);
6126 }
6127 }
6128
6129 WREG32(CG_THERMAL_INT, thermal_int);
6130
6131 /* posting read */
6132 RREG32(SRBM_STATUS);
6133
6134 return 0;
6135 }
6136
6137 /* The order we write back each register here is important */
6138 static inline void si_irq_ack(struct radeon_device *rdev)
6139 {
6140 int i, j;
6141 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;
6142 u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int;
6143
6144 if (ASIC_IS_NODCE(rdev))
6145 return;
6146
6147 for (i = 0; i < 6; i++) {
6148 disp_int[i] = RREG32(si_disp_int_status[i]);
6149 if (i < rdev->num_crtc)
6150 grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]);
6151 }
6152
6153 /* We write back each interrupt register in pairs of two */
6154 for (i = 0; i < rdev->num_crtc; i += 2) {
6155 for (j = i; j < (i + 2); j++) {
6156 if (grph_int[j] & GRPH_PFLIP_INT_OCCURRED)
6157 WREG32(GRPH_INT_STATUS + crtc_offsets[j],
6158 GRPH_PFLIP_INT_CLEAR);
6159 }
6160
6161 for (j = i; j < (i + 2); j++) {
6162 if (disp_int[j] & LB_D1_VBLANK_INTERRUPT)
6163 WREG32(VBLANK_STATUS + crtc_offsets[j],
6164 VBLANK_ACK);
6165 if (disp_int[j] & LB_D1_VLINE_INTERRUPT)
6166 WREG32(VLINE_STATUS + crtc_offsets[j],
6167 VLINE_ACK);
6168 }
6169 }
6170
6171 for (i = 0; i < 6; i++) {
6172 if (disp_int[i] & DC_HPD1_INTERRUPT)
6173 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_ACK);
6174 }
6175
6176 for (i = 0; i < 6; i++) {
6177 if (disp_int[i] & DC_HPD1_RX_INTERRUPT)
6178 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK);
6179 }
6180 }
6181
6182 static void si_irq_disable(struct radeon_device *rdev)
6183 {
6184 si_disable_interrupts(rdev);
6185 /* Wait and acknowledge irq */
6186 mdelay(1);
6187 si_irq_ack(rdev);
6188 si_disable_interrupt_state(rdev);
6189 }
6190
6191 static void si_irq_suspend(struct radeon_device *rdev)
6192 {
6193 si_irq_disable(rdev);
6194 si_rlc_stop(rdev);
6195 }
6196
6197 static void si_irq_fini(struct radeon_device *rdev)
6198 {
6199 si_irq_suspend(rdev);
6200 r600_ih_ring_fini(rdev);
6201 }
6202
6203 static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
6204 {
6205 u32 wptr, tmp;
6206
6207 if (rdev->wb.enabled)
6208 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
6209 else
6210 wptr = RREG32(IH_RB_WPTR);
6211
6212 if (wptr & RB_OVERFLOW) {
6213 wptr &= ~RB_OVERFLOW;
6214 /* When a ring buffer overflow happen start parsing interrupt
6215 * from the last not overwritten vector (wptr + 16). Hopefully
6216 * this should allow us to catchup.
6217 */
6218 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
6219 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
6220 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
6221 tmp = RREG32(IH_RB_CNTL);
6222 tmp |= IH_WPTR_OVERFLOW_CLEAR;
6223 WREG32(IH_RB_CNTL, tmp);
6224 }
6225 return (wptr & rdev->ih.ptr_mask);
6226 }
6227
6228 /* SI IV Ring
6229 * Each IV ring entry is 128 bits:
6230 * [7:0] - interrupt source id
6231 * [31:8] - reserved
6232 * [59:32] - interrupt source data
6233 * [63:60] - reserved
6234 * [71:64] - RINGID
6235 * [79:72] - VMID
6236 * [127:80] - reserved
6237 */
6238 int si_irq_process(struct radeon_device *rdev)
6239 {
6240 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;
6241 u32 crtc_idx, hpd_idx;
6242 u32 mask;
6243 u32 wptr;
6244 u32 rptr;
6245 u32 src_id, src_data, ring_id;
6246 u32 ring_index;
6247 bool queue_hotplug = false;
6248 bool queue_dp = false;
6249 bool queue_thermal = false;
6250 u32 status, addr;
6251 const char *event_name;
6252
6253 if (!rdev->ih.enabled || rdev->shutdown)
6254 return IRQ_NONE;
6255
6256 wptr = si_get_ih_wptr(rdev);
6257
6258 restart_ih:
6259 /* is somebody else already processing irqs? */
6260 if (atomic_xchg(&rdev->ih.lock, 1))
6261 return IRQ_NONE;
6262
6263 rptr = rdev->ih.rptr;
6264 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
6265
6266 /* Order reading of wptr vs. reading of IH ring data */
6267 rmb();
6268
6269 /* display interrupts */
6270 si_irq_ack(rdev);
6271
6272 while (rptr != wptr) {
6273 /* wptr/rptr are in bytes! */
6274 ring_index = rptr / 4;
6275 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
6276 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
6277 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
6278
6279 switch (src_id) {
6280 case 1: /* D1 vblank/vline */
6281 case 2: /* D2 vblank/vline */
6282 case 3: /* D3 vblank/vline */
6283 case 4: /* D4 vblank/vline */
6284 case 5: /* D5 vblank/vline */
6285 case 6: /* D6 vblank/vline */
6286 crtc_idx = src_id - 1;
6287
6288 if (src_data == 0) { /* vblank */
6289 mask = LB_D1_VBLANK_INTERRUPT;
6290 event_name = "vblank";
6291
6292 if (rdev->irq.crtc_vblank_int[crtc_idx]) {
6293 drm_handle_vblank(rdev->ddev, crtc_idx);
6294 rdev->pm.vblank_sync = true;
6295 wake_up(&rdev->irq.vblank_queue);
6296 }
6297 if (atomic_read(&rdev->irq.pflip[crtc_idx])) {
6298 radeon_crtc_handle_vblank(rdev,
6299 crtc_idx);
6300 }
6301
6302 } else if (src_data == 1) { /* vline */
6303 mask = LB_D1_VLINE_INTERRUPT;
6304 event_name = "vline";
6305 } else {
6306 DRM_DEBUG("Unhandled interrupt: %d %d\n",
6307 src_id, src_data);
6308 break;
6309 }
6310
6311 if (!(disp_int[crtc_idx] & mask)) {
6312 DRM_DEBUG("IH: D%d %s - IH event w/o asserted irq bit?\n",
6313 crtc_idx + 1, event_name);
6314 }
6315
6316 disp_int[crtc_idx] &= ~mask;
6317 DRM_DEBUG("IH: D%d %s\n", crtc_idx + 1, event_name);
6318
6319 break;
6320 case 8: /* D1 page flip */
6321 case 10: /* D2 page flip */
6322 case 12: /* D3 page flip */
6323 case 14: /* D4 page flip */
6324 case 16: /* D5 page flip */
6325 case 18: /* D6 page flip */
6326 DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
6327 if (radeon_use_pflipirq > 0)
6328 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
6329 break;
6330 case 42: /* HPD hotplug */
6331 if (src_data <= 5) {
6332 hpd_idx = src_data;
6333 mask = DC_HPD1_INTERRUPT;
6334 queue_hotplug = true;
6335 event_name = "HPD";
6336
6337 } else if (src_data <= 11) {
6338 hpd_idx = src_data - 6;
6339 mask = DC_HPD1_RX_INTERRUPT;
6340 queue_dp = true;
6341 event_name = "HPD_RX";
6342
6343 } else {
6344 DRM_DEBUG("Unhandled interrupt: %d %d\n",
6345 src_id, src_data);
6346 break;
6347 }
6348
6349 if (!(disp_int[hpd_idx] & mask))
6350 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6351
6352 disp_int[hpd_idx] &= ~mask;
6353 DRM_DEBUG("IH: %s%d\n", event_name, hpd_idx + 1);
6354 break;
6355 case 96:
6356 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
6357 WREG32(SRBM_INT_ACK, 0x1);
6358 break;
6359 case 124: /* UVD */
6360 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
6361 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
6362 break;
6363 case 146:
6364 case 147:
6365 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
6366 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
6367 /* reset addr and status */
6368 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
6369 if (addr == 0x0 && status == 0x0)
6370 break;
6371 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
6372 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
6373 addr);
6374 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
6375 status);
6376 si_vm_decode_fault(rdev, status, addr);
6377 break;
6378 case 176: /* RINGID0 CP_INT */
6379 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
6380 break;
6381 case 177: /* RINGID1 CP_INT */
6382 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
6383 break;
6384 case 178: /* RINGID2 CP_INT */
6385 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
6386 break;
6387 case 181: /* CP EOP event */
6388 DRM_DEBUG("IH: CP EOP\n");
6389 switch (ring_id) {
6390 case 0:
6391 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
6392 break;
6393 case 1:
6394 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
6395 break;
6396 case 2:
6397 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
6398 break;
6399 }
6400 break;
6401 case 224: /* DMA trap event */
6402 DRM_DEBUG("IH: DMA trap\n");
6403 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
6404 break;
6405 case 230: /* thermal low to high */
6406 DRM_DEBUG("IH: thermal low to high\n");
6407 rdev->pm.dpm.thermal.high_to_low = false;
6408 queue_thermal = true;
6409 break;
6410 case 231: /* thermal high to low */
6411 DRM_DEBUG("IH: thermal high to low\n");
6412 rdev->pm.dpm.thermal.high_to_low = true;
6413 queue_thermal = true;
6414 break;
6415 case 233: /* GUI IDLE */
6416 DRM_DEBUG("IH: GUI idle\n");
6417 break;
6418 case 244: /* DMA trap event */
6419 DRM_DEBUG("IH: DMA1 trap\n");
6420 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
6421 break;
6422 default:
6423 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6424 break;
6425 }
6426
6427 /* wptr/rptr are in bytes! */
6428 rptr += 16;
6429 rptr &= rdev->ih.ptr_mask;
6430 WREG32(IH_RB_RPTR, rptr);
6431 }
6432 if (queue_dp)
6433 schedule_work(&rdev->dp_work);
6434 if (queue_hotplug)
6435 schedule_delayed_work(&rdev->hotplug_work, 0);
6436 if (queue_thermal && rdev->pm.dpm_enabled)
6437 schedule_work(&rdev->pm.dpm.thermal.work);
6438 rdev->ih.rptr = rptr;
6439 atomic_set(&rdev->ih.lock, 0);
6440
6441 /* make sure wptr hasn't changed while processing */
6442 wptr = si_get_ih_wptr(rdev);
6443 if (wptr != rptr)
6444 goto restart_ih;
6445
6446 return IRQ_HANDLED;
6447 }
6448
6449 /*
6450 * startup/shutdown callbacks
6451 */
6452 static void si_uvd_init(struct radeon_device *rdev)
6453 {
6454 int r;
6455
6456 if (!rdev->has_uvd)
6457 return;
6458
6459 r = radeon_uvd_init(rdev);
6460 if (r) {
6461 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
6462 /*
6463 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
6464 * to early fails uvd_v2_2_resume() and thus nothing happens
6465 * there. So it is pointless to try to go through that code
6466 * hence why we disable uvd here.
6467 */
6468 rdev->has_uvd = 0;
6469 return;
6470 }
6471 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
6472 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
6473 }
6474
6475 static void si_uvd_start(struct radeon_device *rdev)
6476 {
6477 int r;
6478
6479 if (!rdev->has_uvd)
6480 return;
6481
6482 r = uvd_v2_2_resume(rdev);
6483 if (r) {
6484 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
6485 goto error;
6486 }
6487 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
6488 if (r) {
6489 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
6490 goto error;
6491 }
6492 return;
6493
6494 error:
6495 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
6496 }
6497
6498 static void si_uvd_resume(struct radeon_device *rdev)
6499 {
6500 struct radeon_ring *ring;
6501 int r;
6502
6503 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
6504 return;
6505
6506 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
6507 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
6508 if (r) {
6509 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
6510 return;
6511 }
6512 r = uvd_v1_0_init(rdev);
6513 if (r) {
6514 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
6515 return;
6516 }
6517 }
6518
6519 static void si_vce_init(struct radeon_device *rdev)
6520 {
6521 int r;
6522
6523 if (!rdev->has_vce)
6524 return;
6525
6526 r = radeon_vce_init(rdev);
6527 if (r) {
6528 dev_err(rdev->dev, "failed VCE (%d) init.\n", r);
6529 /*
6530 * At this point rdev->vce.vcpu_bo is NULL which trickles down
6531 * to early fails si_vce_start() and thus nothing happens
6532 * there. So it is pointless to try to go through that code
6533 * hence why we disable vce here.
6534 */
6535 rdev->has_vce = 0;
6536 return;
6537 }
6538 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL;
6539 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096);
6540 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL;
6541 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096);
6542 }
6543
6544 static void si_vce_start(struct radeon_device *rdev)
6545 {
6546 int r;
6547
6548 if (!rdev->has_vce)
6549 return;
6550
6551 r = radeon_vce_resume(rdev);
6552 if (r) {
6553 dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
6554 goto error;
6555 }
6556 r = vce_v1_0_resume(rdev);
6557 if (r) {
6558 dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
6559 goto error;
6560 }
6561 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE1_INDEX);
6562 if (r) {
6563 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r);
6564 goto error;
6565 }
6566 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE2_INDEX);
6567 if (r) {
6568 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r);
6569 goto error;
6570 }
6571 return;
6572
6573 error:
6574 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
6575 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
6576 }
6577
6578 static void si_vce_resume(struct radeon_device *rdev)
6579 {
6580 struct radeon_ring *ring;
6581 int r;
6582
6583 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size)
6584 return;
6585
6586 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
6587 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, VCE_CMD_NO_OP);
6588 if (r) {
6589 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
6590 return;
6591 }
6592 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
6593 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, VCE_CMD_NO_OP);
6594 if (r) {
6595 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
6596 return;
6597 }
6598 r = vce_v1_0_init(rdev);
6599 if (r) {
6600 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r);
6601 return;
6602 }
6603 }
6604
6605 static int si_startup(struct radeon_device *rdev)
6606 {
6607 struct radeon_ring *ring;
6608 int r;
6609
6610 /* enable pcie gen2/3 link */
6611 si_pcie_gen3_enable(rdev);
6612 /* enable aspm */
6613 si_program_aspm(rdev);
6614
6615 /* scratch needs to be initialized before MC */
6616 r = r600_vram_scratch_init(rdev);
6617 if (r)
6618 return r;
6619
6620 si_mc_program(rdev);
6621
6622 if (!rdev->pm.dpm_enabled) {
6623 r = si_mc_load_microcode(rdev);
6624 if (r) {
6625 DRM_ERROR("Failed to load MC firmware!\n");
6626 return r;
6627 }
6628 }
6629
6630 r = si_pcie_gart_enable(rdev);
6631 if (r)
6632 return r;
6633 si_gpu_init(rdev);
6634
6635 /* allocate rlc buffers */
6636 if (rdev->family == CHIP_VERDE) {
6637 rdev->rlc.reg_list = verde_rlc_save_restore_register_list;
6638 rdev->rlc.reg_list_size =
6639 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
6640 }
6641 rdev->rlc.cs_data = si_cs_data;
6642 r = sumo_rlc_init(rdev);
6643 if (r) {
6644 DRM_ERROR("Failed to init rlc BOs!\n");
6645 return r;
6646 }
6647
6648 /* allocate wb buffer */
6649 r = radeon_wb_init(rdev);
6650 if (r)
6651 return r;
6652
6653 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
6654 if (r) {
6655 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
6656 return r;
6657 }
6658
6659 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
6660 if (r) {
6661 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
6662 return r;
6663 }
6664
6665 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
6666 if (r) {
6667 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
6668 return r;
6669 }
6670
6671 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
6672 if (r) {
6673 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
6674 return r;
6675 }
6676
6677 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
6678 if (r) {
6679 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
6680 return r;
6681 }
6682
6683 si_uvd_start(rdev);
6684 si_vce_start(rdev);
6685
6686 /* Enable IRQ */
6687 if (!rdev->irq.installed) {
6688 r = radeon_irq_kms_init(rdev);
6689 if (r)
6690 return r;
6691 }
6692
6693 r = si_irq_init(rdev);
6694 if (r) {
6695 DRM_ERROR("radeon: IH init failed (%d).\n", r);
6696 radeon_irq_kms_fini(rdev);
6697 return r;
6698 }
6699 si_irq_set(rdev);
6700
6701 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
6702 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
6703 RADEON_CP_PACKET2);
6704 if (r)
6705 return r;
6706
6707 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
6708 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
6709 RADEON_CP_PACKET2);
6710 if (r)
6711 return r;
6712
6713 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
6714 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
6715 RADEON_CP_PACKET2);
6716 if (r)
6717 return r;
6718
6719 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
6720 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
6721 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
6722 if (r)
6723 return r;
6724
6725 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
6726 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
6727 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
6728 if (r)
6729 return r;
6730
6731 r = si_cp_load_microcode(rdev);
6732 if (r)
6733 return r;
6734 r = si_cp_resume(rdev);
6735 if (r)
6736 return r;
6737
6738 r = cayman_dma_resume(rdev);
6739 if (r)
6740 return r;
6741
6742 si_uvd_resume(rdev);
6743 si_vce_resume(rdev);
6744
6745 r = radeon_ib_pool_init(rdev);
6746 if (r) {
6747 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
6748 return r;
6749 }
6750
6751 r = radeon_vm_manager_init(rdev);
6752 if (r) {
6753 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
6754 return r;
6755 }
6756
6757 r = radeon_audio_init(rdev);
6758 if (r)
6759 return r;
6760
6761 return 0;
6762 }
6763
6764 int si_resume(struct radeon_device *rdev)
6765 {
6766 int r;
6767
6768 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
6769 * posting will perform necessary task to bring back GPU into good
6770 * shape.
6771 */
6772 /* post card */
6773 atom_asic_init(rdev->mode_info.atom_context);
6774
6775 /* init golden registers */
6776 si_init_golden_registers(rdev);
6777
6778 if (rdev->pm.pm_method == PM_METHOD_DPM)
6779 radeon_pm_resume(rdev);
6780
6781 rdev->accel_working = true;
6782 r = si_startup(rdev);
6783 if (r) {
6784 DRM_ERROR("si startup failed on resume\n");
6785 rdev->accel_working = false;
6786 return r;
6787 }
6788
6789 return r;
6790
6791 }
6792
6793 int si_suspend(struct radeon_device *rdev)
6794 {
6795 radeon_pm_suspend(rdev);
6796 radeon_audio_fini(rdev);
6797 radeon_vm_manager_fini(rdev);
6798 si_cp_enable(rdev, false);
6799 cayman_dma_stop(rdev);
6800 if (rdev->has_uvd) {
6801 uvd_v1_0_fini(rdev);
6802 radeon_uvd_suspend(rdev);
6803 }
6804 if (rdev->has_vce)
6805 radeon_vce_suspend(rdev);
6806 si_fini_pg(rdev);
6807 si_fini_cg(rdev);
6808 si_irq_suspend(rdev);
6809 radeon_wb_disable(rdev);
6810 si_pcie_gart_disable(rdev);
6811 return 0;
6812 }
6813
6814 /* Plan is to move initialization in that function and use
6815 * helper function so that radeon_device_init pretty much
6816 * do nothing more than calling asic specific function. This
6817 * should also allow to remove a bunch of callback function
6818 * like vram_info.
6819 */
6820 int si_init(struct radeon_device *rdev)
6821 {
6822 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
6823 int r;
6824
6825 /* Read BIOS */
6826 if (!radeon_get_bios(rdev)) {
6827 if (ASIC_IS_AVIVO(rdev))
6828 return -EINVAL;
6829 }
6830 /* Must be an ATOMBIOS */
6831 if (!rdev->is_atom_bios) {
6832 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
6833 return -EINVAL;
6834 }
6835 r = radeon_atombios_init(rdev);
6836 if (r)
6837 return r;
6838
6839 /* Post card if necessary */
6840 if (!radeon_card_posted(rdev)) {
6841 if (!rdev->bios) {
6842 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
6843 return -EINVAL;
6844 }
6845 DRM_INFO("GPU not posted. posting now...\n");
6846 atom_asic_init(rdev->mode_info.atom_context);
6847 }
6848 /* init golden registers */
6849 si_init_golden_registers(rdev);
6850 /* Initialize scratch registers */
6851 si_scratch_init(rdev);
6852 /* Initialize surface registers */
6853 radeon_surface_init(rdev);
6854 /* Initialize clocks */
6855 radeon_get_clock_info(rdev->ddev);
6856
6857 /* Fence driver */
6858 r = radeon_fence_driver_init(rdev);
6859 if (r)
6860 return r;
6861
6862 /* initialize memory controller */
6863 r = si_mc_init(rdev);
6864 if (r)
6865 return r;
6866 /* Memory manager */
6867 r = radeon_bo_init(rdev);
6868 if (r)
6869 return r;
6870
6871 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
6872 !rdev->rlc_fw || !rdev->mc_fw) {
6873 r = si_init_microcode(rdev);
6874 if (r) {
6875 DRM_ERROR("Failed to load firmware!\n");
6876 return r;
6877 }
6878 }
6879
6880 /* Initialize power management */
6881 radeon_pm_init(rdev);
6882
6883 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
6884 ring->ring_obj = NULL;
6885 r600_ring_init(rdev, ring, 1024 * 1024);
6886
6887 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
6888 ring->ring_obj = NULL;
6889 r600_ring_init(rdev, ring, 1024 * 1024);
6890
6891 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
6892 ring->ring_obj = NULL;
6893 r600_ring_init(rdev, ring, 1024 * 1024);
6894
6895 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
6896 ring->ring_obj = NULL;
6897 r600_ring_init(rdev, ring, 64 * 1024);
6898
6899 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
6900 ring->ring_obj = NULL;
6901 r600_ring_init(rdev, ring, 64 * 1024);
6902
6903 si_uvd_init(rdev);
6904 si_vce_init(rdev);
6905
6906 rdev->ih.ring_obj = NULL;
6907 r600_ih_ring_init(rdev, 64 * 1024);
6908
6909 r = r600_pcie_gart_init(rdev);
6910 if (r)
6911 return r;
6912
6913 rdev->accel_working = true;
6914 r = si_startup(rdev);
6915 if (r) {
6916 dev_err(rdev->dev, "disabling GPU acceleration\n");
6917 si_cp_fini(rdev);
6918 cayman_dma_fini(rdev);
6919 si_irq_fini(rdev);
6920 sumo_rlc_fini(rdev);
6921 radeon_wb_fini(rdev);
6922 radeon_ib_pool_fini(rdev);
6923 radeon_vm_manager_fini(rdev);
6924 radeon_irq_kms_fini(rdev);
6925 si_pcie_gart_fini(rdev);
6926 rdev->accel_working = false;
6927 }
6928
6929 /* Don't start up if the MC ucode is missing.
6930 * The default clocks and voltages before the MC ucode
6931 * is loaded are not suffient for advanced operations.
6932 */
6933 if (!rdev->mc_fw) {
6934 DRM_ERROR("radeon: MC ucode required for NI+.\n");
6935 return -EINVAL;
6936 }
6937
6938 return 0;
6939 }
6940
6941 void si_fini(struct radeon_device *rdev)
6942 {
6943 radeon_pm_fini(rdev);
6944 si_cp_fini(rdev);
6945 cayman_dma_fini(rdev);
6946 si_fini_pg(rdev);
6947 si_fini_cg(rdev);
6948 si_irq_fini(rdev);
6949 sumo_rlc_fini(rdev);
6950 radeon_wb_fini(rdev);
6951 radeon_vm_manager_fini(rdev);
6952 radeon_ib_pool_fini(rdev);
6953 radeon_irq_kms_fini(rdev);
6954 if (rdev->has_uvd) {
6955 uvd_v1_0_fini(rdev);
6956 radeon_uvd_fini(rdev);
6957 }
6958 if (rdev->has_vce)
6959 radeon_vce_fini(rdev);
6960 si_pcie_gart_fini(rdev);
6961 r600_vram_scratch_fini(rdev);
6962 radeon_gem_fini(rdev);
6963 radeon_fence_driver_fini(rdev);
6964 radeon_bo_fini(rdev);
6965 radeon_atombios_fini(rdev);
6966 kfree(rdev->bios);
6967 rdev->bios = NULL;
6968 }
6969
6970 /**
6971 * si_get_gpu_clock_counter - return GPU clock counter snapshot
6972 *
6973 * @rdev: radeon_device pointer
6974 *
6975 * Fetches a GPU clock counter snapshot (SI).
6976 * Returns the 64 bit clock counter snapshot.
6977 */
6978 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev)
6979 {
6980 uint64_t clock;
6981
6982 mutex_lock(&rdev->gpu_clock_mutex);
6983 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
6984 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
6985 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
6986 mutex_unlock(&rdev->gpu_clock_mutex);
6987 return clock;
6988 }
6989
6990 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
6991 {
6992 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
6993 int r;
6994
6995 /* bypass vclk and dclk with bclk */
6996 WREG32_P(CG_UPLL_FUNC_CNTL_2,
6997 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
6998 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
6999
7000 /* put PLL in bypass mode */
7001 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
7002
7003 if (!vclk || !dclk) {
7004 /* keep the Bypass mode */
7005 return 0;
7006 }
7007
7008 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
7009 16384, 0x03FFFFFF, 0, 128, 5,
7010 &fb_div, &vclk_div, &dclk_div);
7011 if (r)
7012 return r;
7013
7014 /* set RESET_ANTI_MUX to 0 */
7015 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
7016
7017 /* set VCO_MODE to 1 */
7018 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
7019
7020 /* disable sleep mode */
7021 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
7022
7023 /* deassert UPLL_RESET */
7024 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
7025
7026 mdelay(1);
7027
7028 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
7029 if (r)
7030 return r;
7031
7032 /* assert UPLL_RESET again */
7033 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
7034
7035 /* disable spread spectrum. */
7036 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
7037
7038 /* set feedback divider */
7039 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
7040
7041 /* set ref divider to 0 */
7042 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
7043
7044 if (fb_div < 307200)
7045 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
7046 else
7047 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
7048
7049 /* set PDIV_A and PDIV_B */
7050 WREG32_P(CG_UPLL_FUNC_CNTL_2,
7051 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
7052 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
7053
7054 /* give the PLL some time to settle */
7055 mdelay(15);
7056
7057 /* deassert PLL_RESET */
7058 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
7059
7060 mdelay(15);
7061
7062 /* switch from bypass mode to normal mode */
7063 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
7064
7065 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
7066 if (r)
7067 return r;
7068
7069 /* switch VCLK and DCLK selection */
7070 WREG32_P(CG_UPLL_FUNC_CNTL_2,
7071 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
7072 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
7073
7074 mdelay(100);
7075
7076 return 0;
7077 }
7078
7079 static void si_pcie_gen3_enable(struct radeon_device *rdev)
7080 {
7081 struct pci_dev *root = rdev->pdev->bus->self;
7082 int bridge_pos, gpu_pos;
7083 u32 speed_cntl, mask, current_data_rate;
7084 int ret, i;
7085 u16 tmp16;
7086
7087 if (pci_is_root_bus(rdev->pdev->bus))
7088 return;
7089
7090 if (radeon_pcie_gen2 == 0)
7091 return;
7092
7093 if (rdev->flags & RADEON_IS_IGP)
7094 return;
7095
7096 if (!(rdev->flags & RADEON_IS_PCIE))
7097 return;
7098
7099 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
7100 if (ret != 0)
7101 return;
7102
7103 if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
7104 return;
7105
7106 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
7107 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
7108 LC_CURRENT_DATA_RATE_SHIFT;
7109 if (mask & DRM_PCIE_SPEED_80) {
7110 if (current_data_rate == 2) {
7111 DRM_INFO("PCIE gen 3 link speeds already enabled\n");
7112 return;
7113 }
7114 DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
7115 } else if (mask & DRM_PCIE_SPEED_50) {
7116 if (current_data_rate == 1) {
7117 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
7118 return;
7119 }
7120 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
7121 }
7122
7123 bridge_pos = pci_pcie_cap(root);
7124 if (!bridge_pos)
7125 return;
7126
7127 gpu_pos = pci_pcie_cap(rdev->pdev);
7128 if (!gpu_pos)
7129 return;
7130
7131 if (mask & DRM_PCIE_SPEED_80) {
7132 /* re-try equalization if gen3 is not already enabled */
7133 if (current_data_rate != 2) {
7134 u16 bridge_cfg, gpu_cfg;
7135 u16 bridge_cfg2, gpu_cfg2;
7136 u32 max_lw, current_lw, tmp;
7137
7138 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
7139 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
7140
7141 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
7142 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
7143
7144 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
7145 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
7146
7147 tmp = RREG32_PCIE(PCIE_LC_STATUS1);
7148 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
7149 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
7150
7151 if (current_lw < max_lw) {
7152 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
7153 if (tmp & LC_RENEGOTIATION_SUPPORT) {
7154 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
7155 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
7156 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
7157 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
7158 }
7159 }
7160
7161 for (i = 0; i < 10; i++) {
7162 /* check status */
7163 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
7164 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
7165 break;
7166
7167 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
7168 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
7169
7170 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
7171 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
7172
7173 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7174 tmp |= LC_SET_QUIESCE;
7175 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7176
7177 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7178 tmp |= LC_REDO_EQ;
7179 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7180
7181 mdelay(100);
7182
7183 /* linkctl */
7184 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
7185 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
7186 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
7187 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
7188
7189 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
7190 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
7191 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
7192 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
7193
7194 /* linkctl2 */
7195 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
7196 tmp16 &= ~((1 << 4) | (7 << 9));
7197 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
7198 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
7199
7200 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
7201 tmp16 &= ~((1 << 4) | (7 << 9));
7202 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
7203 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
7204
7205 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7206 tmp &= ~LC_SET_QUIESCE;
7207 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7208 }
7209 }
7210 }
7211
7212 /* set the link speed */
7213 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
7214 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
7215 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
7216
7217 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
7218 tmp16 &= ~0xf;
7219 if (mask & DRM_PCIE_SPEED_80)
7220 tmp16 |= 3; /* gen3 */
7221 else if (mask & DRM_PCIE_SPEED_50)
7222 tmp16 |= 2; /* gen2 */
7223 else
7224 tmp16 |= 1; /* gen1 */
7225 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
7226
7227 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
7228 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
7229 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
7230
7231 for (i = 0; i < rdev->usec_timeout; i++) {
7232 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
7233 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
7234 break;
7235 udelay(1);
7236 }
7237 }
7238
7239 static void si_program_aspm(struct radeon_device *rdev)
7240 {
7241 u32 data, orig;
7242 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
7243 bool disable_clkreq = false;
7244
7245 if (radeon_aspm == 0)
7246 return;
7247
7248 if (!(rdev->flags & RADEON_IS_PCIE))
7249 return;
7250
7251 orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
7252 data &= ~LC_XMIT_N_FTS_MASK;
7253 data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
7254 if (orig != data)
7255 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
7256
7257 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
7258 data |= LC_GO_TO_RECOVERY;
7259 if (orig != data)
7260 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
7261
7262 orig = data = RREG32_PCIE(PCIE_P_CNTL);
7263 data |= P_IGNORE_EDB_ERR;
7264 if (orig != data)
7265 WREG32_PCIE(PCIE_P_CNTL, data);
7266
7267 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
7268 data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
7269 data |= LC_PMI_TO_L1_DIS;
7270 if (!disable_l0s)
7271 data |= LC_L0S_INACTIVITY(7);
7272
7273 if (!disable_l1) {
7274 data |= LC_L1_INACTIVITY(7);
7275 data &= ~LC_PMI_TO_L1_DIS;
7276 if (orig != data)
7277 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
7278
7279 if (!disable_plloff_in_l1) {
7280 bool clk_req_support;
7281
7282 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);
7283 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
7284 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
7285 if (orig != data)
7286 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);
7287
7288 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);
7289 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
7290 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
7291 if (orig != data)
7292 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);
7293
7294 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);
7295 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
7296 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
7297 if (orig != data)
7298 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);
7299
7300 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);
7301 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
7302 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
7303 if (orig != data)
7304 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);
7305
7306 if ((rdev->family != CHIP_OLAND) && (rdev->family != CHIP_HAINAN)) {
7307 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);
7308 data &= ~PLL_RAMP_UP_TIME_0_MASK;
7309 if (orig != data)
7310 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);
7311
7312 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);
7313 data &= ~PLL_RAMP_UP_TIME_1_MASK;
7314 if (orig != data)
7315 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);
7316
7317 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_2);
7318 data &= ~PLL_RAMP_UP_TIME_2_MASK;
7319 if (orig != data)
7320 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_2, data);
7321
7322 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_3);
7323 data &= ~PLL_RAMP_UP_TIME_3_MASK;
7324 if (orig != data)
7325 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_3, data);
7326
7327 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);
7328 data &= ~PLL_RAMP_UP_TIME_0_MASK;
7329 if (orig != data)
7330 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);
7331
7332 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);
7333 data &= ~PLL_RAMP_UP_TIME_1_MASK;
7334 if (orig != data)
7335 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);
7336
7337 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_2);
7338 data &= ~PLL_RAMP_UP_TIME_2_MASK;
7339 if (orig != data)
7340 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_2, data);
7341
7342 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_3);
7343 data &= ~PLL_RAMP_UP_TIME_3_MASK;
7344 if (orig != data)
7345 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_3, data);
7346 }
7347 orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
7348 data &= ~LC_DYN_LANES_PWR_STATE_MASK;
7349 data |= LC_DYN_LANES_PWR_STATE(3);
7350 if (orig != data)
7351 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
7352
7353 orig = data = RREG32_PIF_PHY0(PB0_PIF_CNTL);
7354 data &= ~LS2_EXIT_TIME_MASK;
7355 if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN))
7356 data |= LS2_EXIT_TIME(5);
7357 if (orig != data)
7358 WREG32_PIF_PHY0(PB0_PIF_CNTL, data);
7359
7360 orig = data = RREG32_PIF_PHY1(PB1_PIF_CNTL);
7361 data &= ~LS2_EXIT_TIME_MASK;
7362 if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN))
7363 data |= LS2_EXIT_TIME(5);
7364 if (orig != data)
7365 WREG32_PIF_PHY1(PB1_PIF_CNTL, data);
7366
7367 if (!disable_clkreq &&
7368 !pci_is_root_bus(rdev->pdev->bus)) {
7369 struct pci_dev *root = rdev->pdev->bus->self;
7370 u32 lnkcap;
7371
7372 clk_req_support = false;
7373 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
7374 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
7375 clk_req_support = true;
7376 } else {
7377 clk_req_support = false;
7378 }
7379
7380 if (clk_req_support) {
7381 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
7382 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
7383 if (orig != data)
7384 WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
7385
7386 orig = data = RREG32(THM_CLK_CNTL);
7387 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
7388 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
7389 if (orig != data)
7390 WREG32(THM_CLK_CNTL, data);
7391
7392 orig = data = RREG32(MISC_CLK_CNTL);
7393 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
7394 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
7395 if (orig != data)
7396 WREG32(MISC_CLK_CNTL, data);
7397
7398 orig = data = RREG32(CG_CLKPIN_CNTL);
7399 data &= ~BCLK_AS_XCLK;
7400 if (orig != data)
7401 WREG32(CG_CLKPIN_CNTL, data);
7402
7403 orig = data = RREG32(CG_CLKPIN_CNTL_2);
7404 data &= ~FORCE_BIF_REFCLK_EN;
7405 if (orig != data)
7406 WREG32(CG_CLKPIN_CNTL_2, data);
7407
7408 orig = data = RREG32(MPLL_BYPASSCLK_SEL);
7409 data &= ~MPLL_CLKOUT_SEL_MASK;
7410 data |= MPLL_CLKOUT_SEL(4);
7411 if (orig != data)
7412 WREG32(MPLL_BYPASSCLK_SEL, data);
7413
7414 orig = data = RREG32(SPLL_CNTL_MODE);
7415 data &= ~SPLL_REFCLK_SEL_MASK;
7416 if (orig != data)
7417 WREG32(SPLL_CNTL_MODE, data);
7418 }
7419 }
7420 } else {
7421 if (orig != data)
7422 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
7423 }
7424
7425 orig = data = RREG32_PCIE(PCIE_CNTL2);
7426 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
7427 if (orig != data)
7428 WREG32_PCIE(PCIE_CNTL2, data);
7429
7430 if (!disable_l0s) {
7431 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
7432 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
7433 data = RREG32_PCIE(PCIE_LC_STATUS1);
7434 if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
7435 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
7436 data &= ~LC_L0S_INACTIVITY_MASK;
7437 if (orig != data)
7438 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
7439 }
7440 }
7441 }
7442 }
7443
7444 static int si_vce_send_vcepll_ctlreq(struct radeon_device *rdev)
7445 {
7446 unsigned i;
7447
7448 /* make sure VCEPLL_CTLREQ is deasserted */
7449 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
7450
7451 mdelay(10);
7452
7453 /* assert UPLL_CTLREQ */
7454 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
7455
7456 /* wait for CTLACK and CTLACK2 to get asserted */
7457 for (i = 0; i < 100; ++i) {
7458 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
7459 if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask)
7460 break;
7461 mdelay(10);
7462 }
7463
7464 /* deassert UPLL_CTLREQ */
7465 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
7466
7467 if (i == 100) {
7468 DRM_ERROR("Timeout setting UVD clocks!\n");
7469 return -ETIMEDOUT;
7470 }
7471
7472 return 0;
7473 }
7474
7475 int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
7476 {
7477 unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0;
7478 int r;
7479
7480 /* bypass evclk and ecclk with bclk */
7481 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
7482 EVCLK_SRC_SEL(1) | ECCLK_SRC_SEL(1),
7483 ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK));
7484
7485 /* put PLL in bypass mode */
7486 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK,
7487 ~VCEPLL_BYPASS_EN_MASK);
7488
7489 if (!evclk || !ecclk) {
7490 /* keep the Bypass mode, put PLL to sleep */
7491 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,
7492 ~VCEPLL_SLEEP_MASK);
7493 return 0;
7494 }
7495
7496 r = radeon_uvd_calc_upll_dividers(rdev, evclk, ecclk, 125000, 250000,
7497 16384, 0x03FFFFFF, 0, 128, 5,
7498 &fb_div, &evclk_div, &ecclk_div);
7499 if (r)
7500 return r;
7501
7502 /* set RESET_ANTI_MUX to 0 */
7503 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
7504
7505 /* set VCO_MODE to 1 */
7506 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK,
7507 ~VCEPLL_VCO_MODE_MASK);
7508
7509 /* toggle VCEPLL_SLEEP to 1 then back to 0 */
7510 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,
7511 ~VCEPLL_SLEEP_MASK);
7512 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK);
7513
7514 /* deassert VCEPLL_RESET */
7515 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);
7516
7517 mdelay(1);
7518
7519 r = si_vce_send_vcepll_ctlreq(rdev);
7520 if (r)
7521 return r;
7522
7523 /* assert VCEPLL_RESET again */
7524 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK);
7525
7526 /* disable spread spectrum. */
7527 WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
7528
7529 /* set feedback divider */
7530 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK);
7531
7532 /* set ref divider to 0 */
7533 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK);
7534
7535 /* set PDIV_A and PDIV_B */
7536 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
7537 VCEPLL_PDIV_A(evclk_div) | VCEPLL_PDIV_B(ecclk_div),
7538 ~(VCEPLL_PDIV_A_MASK | VCEPLL_PDIV_B_MASK));
7539
7540 /* give the PLL some time to settle */
7541 mdelay(15);
7542
7543 /* deassert PLL_RESET */
7544 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);
7545
7546 mdelay(15);
7547
7548 /* switch from bypass mode to normal mode */
7549 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK);
7550
7551 r = si_vce_send_vcepll_ctlreq(rdev);
7552 if (r)
7553 return r;
7554
7555 /* switch VCLK and DCLK selection */
7556 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
7557 EVCLK_SRC_SEL(16) | ECCLK_SRC_SEL(16),
7558 ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK));
7559
7560 mdelay(100);
7561
7562 return 0;
7563 }
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