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spi-imx: Implements handling of the SPI_READY mode flag.
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / radeon / si_dpm.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "drmP.h"
25 #include "radeon.h"
26 #include "radeon_asic.h"
27 #include "sid.h"
28 #include "r600_dpm.h"
29 #include "si_dpm.h"
30 #include "atom.h"
31 #include <linux/math64.h>
32 #include <linux/seq_file.h>
33
34 #define MC_CG_ARB_FREQ_F0 0x0a
35 #define MC_CG_ARB_FREQ_F1 0x0b
36 #define MC_CG_ARB_FREQ_F2 0x0c
37 #define MC_CG_ARB_FREQ_F3 0x0d
38
39 #define SMC_RAM_END 0x20000
40
41 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
42
43 static const struct si_cac_config_reg cac_weights_tahiti[] =
44 {
45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
105 { 0xFFFFFFFF }
106 };
107
108 static const struct si_cac_config_reg lcac_tahiti[] =
109 {
110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
196 { 0xFFFFFFFF }
197
198 };
199
200 static const struct si_cac_config_reg cac_override_tahiti[] =
201 {
202 { 0xFFFFFFFF }
203 };
204
205 static const struct si_powertune_data powertune_data_tahiti =
206 {
207 ((1 << 16) | 27027),
208 6,
209 0,
210 4,
211 95,
212 {
213 0UL,
214 0UL,
215 4521550UL,
216 309631529UL,
217 -1270850L,
218 4513710L,
219 40
220 },
221 595000000UL,
222 12,
223 {
224 0,
225 0,
226 0,
227 0,
228 0,
229 0,
230 0,
231 0
232 },
233 true
234 };
235
236 static const struct si_dte_data dte_data_tahiti =
237 {
238 { 1159409, 0, 0, 0, 0 },
239 { 777, 0, 0, 0, 0 },
240 2,
241 54000,
242 127000,
243 25,
244 2,
245 10,
246 13,
247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
250 85,
251 false
252 };
253
254 static const struct si_dte_data dte_data_tahiti_le =
255 {
256 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
257 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
258 0x5,
259 0xAFC8,
260 0x64,
261 0x32,
262 1,
263 0,
264 0x10,
265 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
266 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
267 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
268 85,
269 true
270 };
271
272 static const struct si_dte_data dte_data_tahiti_pro =
273 {
274 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
275 { 0x0, 0x0, 0x0, 0x0, 0x0 },
276 5,
277 45000,
278 100,
279 0xA,
280 1,
281 0,
282 0x10,
283 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
284 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
285 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
286 90,
287 true
288 };
289
290 static const struct si_dte_data dte_data_new_zealand =
291 {
292 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
293 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
294 0x5,
295 0xAFC8,
296 0x69,
297 0x32,
298 1,
299 0,
300 0x10,
301 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
302 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
303 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
304 85,
305 true
306 };
307
308 static const struct si_dte_data dte_data_aruba_pro =
309 {
310 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
311 { 0x0, 0x0, 0x0, 0x0, 0x0 },
312 5,
313 45000,
314 100,
315 0xA,
316 1,
317 0,
318 0x10,
319 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
320 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
321 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
322 90,
323 true
324 };
325
326 static const struct si_dte_data dte_data_malta =
327 {
328 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
329 { 0x0, 0x0, 0x0, 0x0, 0x0 },
330 5,
331 45000,
332 100,
333 0xA,
334 1,
335 0,
336 0x10,
337 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
338 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
339 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
340 90,
341 true
342 };
343
344 struct si_cac_config_reg cac_weights_pitcairn[] =
345 {
346 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
347 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
348 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
349 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
350 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
351 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
352 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
353 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
354 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
355 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
356 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
357 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
358 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
359 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
360 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
361 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
362 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
363 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
364 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
365 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
366 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
367 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
368 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
369 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
370 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
371 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
372 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
373 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
374 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
375 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
376 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
377 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
378 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
379 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
380 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
381 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
382 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
383 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
384 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
385 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
386 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
387 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
388 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
389 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
390 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
391 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
392 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
393 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
394 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
395 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
396 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
397 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
398 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
399 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
400 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
401 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
402 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
403 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
404 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
405 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
406 { 0xFFFFFFFF }
407 };
408
409 static const struct si_cac_config_reg lcac_pitcairn[] =
410 {
411 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
412 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
413 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
414 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
415 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
416 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
417 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
418 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
419 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
420 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
421 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
422 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
423 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
424 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
425 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
426 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
427 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
428 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
429 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
430 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
431 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
432 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
433 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
434 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
435 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
436 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
437 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
438 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
439 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
440 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
441 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
442 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
443 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
444 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
445 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
446 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
447 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
448 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
449 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
450 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
451 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
452 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
453 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
454 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
455 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
456 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
457 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
458 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
459 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
460 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
461 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
462 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
463 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
464 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
465 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
466 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
467 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
468 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
469 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
470 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
471 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
472 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
473 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
474 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
475 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
476 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
477 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
478 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
479 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
480 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
481 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
482 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
483 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
484 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
485 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
486 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
487 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
488 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
489 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
490 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
491 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
492 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
493 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
494 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
495 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
496 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
497 { 0xFFFFFFFF }
498 };
499
500 static const struct si_cac_config_reg cac_override_pitcairn[] =
501 {
502 { 0xFFFFFFFF }
503 };
504
505 static const struct si_powertune_data powertune_data_pitcairn =
506 {
507 ((1 << 16) | 27027),
508 5,
509 0,
510 6,
511 100,
512 {
513 51600000UL,
514 1800000UL,
515 7194395UL,
516 309631529UL,
517 -1270850L,
518 4513710L,
519 100
520 },
521 117830498UL,
522 12,
523 {
524 0,
525 0,
526 0,
527 0,
528 0,
529 0,
530 0,
531 0
532 },
533 true
534 };
535
536 static const struct si_dte_data dte_data_pitcairn =
537 {
538 { 0, 0, 0, 0, 0 },
539 { 0, 0, 0, 0, 0 },
540 0,
541 0,
542 0,
543 0,
544 0,
545 0,
546 0,
547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
550 0,
551 false
552 };
553
554 static const struct si_dte_data dte_data_curacao_xt =
555 {
556 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
557 { 0x0, 0x0, 0x0, 0x0, 0x0 },
558 5,
559 45000,
560 100,
561 0xA,
562 1,
563 0,
564 0x10,
565 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
566 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
567 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
568 90,
569 true
570 };
571
572 static const struct si_dte_data dte_data_curacao_pro =
573 {
574 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
575 { 0x0, 0x0, 0x0, 0x0, 0x0 },
576 5,
577 45000,
578 100,
579 0xA,
580 1,
581 0,
582 0x10,
583 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
584 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
585 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
586 90,
587 true
588 };
589
590 static const struct si_dte_data dte_data_neptune_xt =
591 {
592 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
593 { 0x0, 0x0, 0x0, 0x0, 0x0 },
594 5,
595 45000,
596 100,
597 0xA,
598 1,
599 0,
600 0x10,
601 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
602 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
603 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
604 90,
605 true
606 };
607
608 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
609 {
610 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
611 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
612 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
613 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
614 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
615 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
616 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
617 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
618 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
619 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
620 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
621 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
622 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
623 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
624 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
625 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
626 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
627 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
628 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
629 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
630 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
631 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
632 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
633 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
634 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
635 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
636 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
637 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
638 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
639 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
640 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
641 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
642 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
643 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
644 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
645 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
646 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
647 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
648 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
649 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
650 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
651 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
652 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
653 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
654 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
655 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
656 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
657 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
658 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
659 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
660 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
661 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
662 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
663 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
664 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
665 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
666 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
667 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
668 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
669 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
670 { 0xFFFFFFFF }
671 };
672
673 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
674 {
675 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
676 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
677 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
678 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
679 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
680 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
681 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
682 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
683 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
684 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
685 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
686 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
687 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
688 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
689 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
690 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
691 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
692 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
693 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
694 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
695 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
696 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
697 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
698 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
699 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
700 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
701 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
702 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
703 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
704 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
705 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
706 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
707 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
708 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
709 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
710 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
711 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
712 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
713 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
714 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
715 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
716 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
717 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
718 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
719 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
720 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
721 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
722 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
723 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
724 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
725 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
726 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
727 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
728 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
729 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
730 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
731 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
732 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
733 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
734 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
735 { 0xFFFFFFFF }
736 };
737
738 static const struct si_cac_config_reg cac_weights_heathrow[] =
739 {
740 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
741 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
742 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
743 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
744 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
746 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
747 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
748 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
749 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
750 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
751 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
752 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
753 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
754 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
755 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
756 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
757 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
758 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
759 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
760 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
761 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
762 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
763 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
764 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
765 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
766 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
767 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
768 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
769 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
770 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
771 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
772 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
773 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
774 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
775 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
776 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
777 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
778 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
779 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
780 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
781 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
782 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
783 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
784 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
785 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
786 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
787 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
788 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
789 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
790 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
791 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
792 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
793 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
794 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
795 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
796 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
797 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
798 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
799 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
800 { 0xFFFFFFFF }
801 };
802
803 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
804 {
805 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
806 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
807 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
808 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
809 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
811 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
812 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
813 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
814 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
815 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
816 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
817 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
818 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
819 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
820 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
821 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
822 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
823 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
824 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
825 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
826 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
827 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
828 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
829 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
830 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
831 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
832 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
833 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
834 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
835 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
836 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
837 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
838 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
839 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
840 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
841 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
842 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
843 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
844 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
845 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
846 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
847 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
848 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
849 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
850 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
851 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
852 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
853 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
854 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
855 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
856 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
857 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
858 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
859 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
860 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
861 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
862 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
863 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
864 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
865 { 0xFFFFFFFF }
866 };
867
868 static const struct si_cac_config_reg cac_weights_cape_verde[] =
869 {
870 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
871 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
872 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
873 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
874 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
876 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
877 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
878 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
879 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
880 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
881 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
882 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
883 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
884 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
885 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
886 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
887 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
888 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
889 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
890 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
891 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
892 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
893 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
894 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
895 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
896 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
897 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
898 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
899 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
900 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
901 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
902 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
903 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
904 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
905 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
906 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
907 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
908 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
909 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
910 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
911 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
912 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
913 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
914 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
915 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
916 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
917 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
918 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
919 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
920 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
921 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
922 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
923 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
924 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
925 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
926 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
927 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
928 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
929 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
930 { 0xFFFFFFFF }
931 };
932
933 static const struct si_cac_config_reg lcac_cape_verde[] =
934 {
935 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
936 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
937 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
938 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
939 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
940 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
941 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
942 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
943 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
944 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
945 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
946 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
947 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
948 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
949 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
950 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
951 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
952 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
953 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
954 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
955 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
956 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
957 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
958 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
959 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
960 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
961 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
962 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
963 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
964 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
965 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
966 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
967 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
968 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
969 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
970 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
971 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
972 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
973 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
974 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
975 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
976 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
977 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
978 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
979 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
980 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
981 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
982 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
983 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
984 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
985 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
986 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
987 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
988 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
989 { 0xFFFFFFFF }
990 };
991
992 static const struct si_cac_config_reg cac_override_cape_verde[] =
993 {
994 { 0xFFFFFFFF }
995 };
996
997 static const struct si_powertune_data powertune_data_cape_verde =
998 {
999 ((1 << 16) | 0x6993),
1000 5,
1001 0,
1002 7,
1003 105,
1004 {
1005 0UL,
1006 0UL,
1007 7194395UL,
1008 309631529UL,
1009 -1270850L,
1010 4513710L,
1011 100
1012 },
1013 117830498UL,
1014 12,
1015 {
1016 0,
1017 0,
1018 0,
1019 0,
1020 0,
1021 0,
1022 0,
1023 0
1024 },
1025 true
1026 };
1027
1028 static const struct si_dte_data dte_data_cape_verde =
1029 {
1030 { 0, 0, 0, 0, 0 },
1031 { 0, 0, 0, 0, 0 },
1032 0,
1033 0,
1034 0,
1035 0,
1036 0,
1037 0,
1038 0,
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1042 0,
1043 false
1044 };
1045
1046 static const struct si_dte_data dte_data_venus_xtx =
1047 {
1048 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1049 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1050 5,
1051 55000,
1052 0x69,
1053 0xA,
1054 1,
1055 0,
1056 0x3,
1057 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060 90,
1061 true
1062 };
1063
1064 static const struct si_dte_data dte_data_venus_xt =
1065 {
1066 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1067 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1068 5,
1069 55000,
1070 0x69,
1071 0xA,
1072 1,
1073 0,
1074 0x3,
1075 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078 90,
1079 true
1080 };
1081
1082 static const struct si_dte_data dte_data_venus_pro =
1083 {
1084 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1085 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1086 5,
1087 55000,
1088 0x69,
1089 0xA,
1090 1,
1091 0,
1092 0x3,
1093 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1096 90,
1097 true
1098 };
1099
1100 struct si_cac_config_reg cac_weights_oland[] =
1101 {
1102 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1103 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1104 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1105 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1106 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1107 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1109 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1110 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1111 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1112 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1113 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1114 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1115 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1116 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1117 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1118 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1119 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1120 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1121 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1122 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1123 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1124 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1125 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1126 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1127 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1128 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1129 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1130 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1131 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1132 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1133 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1134 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1135 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1136 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1137 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1138 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1140 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1141 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1142 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1143 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1147 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1148 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1160 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1161 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1162 { 0xFFFFFFFF }
1163 };
1164
1165 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1166 {
1167 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1168 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1169 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1170 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1171 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1172 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1174 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1175 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1176 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1177 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1178 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1179 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1180 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1181 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1182 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1183 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1184 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1185 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1186 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1187 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1188 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1189 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1190 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1191 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1192 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1193 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1194 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1195 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1196 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1197 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1198 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1199 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1200 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1201 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1202 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1203 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1205 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1206 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1207 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1208 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1212 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1214 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1215 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1216 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1218 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1219 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1225 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1226 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1227 { 0xFFFFFFFF }
1228 };
1229
1230 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1231 {
1232 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1233 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1235 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1236 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1239 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1241 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1242 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1243 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1244 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1245 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1246 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1247 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1248 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1249 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1250 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1251 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1252 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1253 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1254 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1255 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1256 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1257 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1258 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1259 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1260 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1261 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1262 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1263 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1264 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1265 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1266 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1267 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1268 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1270 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1271 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1272 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1273 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1277 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1278 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1279 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1280 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1281 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1282 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1283 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1284 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1286 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1290 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1291 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1292 { 0xFFFFFFFF }
1293 };
1294
1295 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1296 {
1297 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1298 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1300 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1301 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1304 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1305 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1306 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1307 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1308 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1309 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1310 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1311 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1312 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1313 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1314 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1315 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1316 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1317 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1318 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1319 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1320 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1321 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1322 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1323 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1324 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1325 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1326 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1327 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1328 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1329 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1330 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1331 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1332 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1333 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1335 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1336 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1337 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1338 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1342 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1343 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1344 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1345 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1346 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1347 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1348 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1349 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1351 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1355 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1356 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1357 { 0xFFFFFFFF }
1358 };
1359
1360 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1361 {
1362 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1363 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1365 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1366 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1369 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1370 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1371 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1372 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1373 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1374 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1375 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1376 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1377 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1378 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1379 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1380 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1381 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1382 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1383 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1384 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1385 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1386 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1387 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1388 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1389 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1390 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1391 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1392 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1393 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1394 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1395 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1396 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1397 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1398 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1400 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1401 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1402 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1403 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1407 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1408 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1409 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1410 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1411 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1412 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1413 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1414 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1416 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1420 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1421 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1422 { 0xFFFFFFFF }
1423 };
1424
1425 static const struct si_cac_config_reg lcac_oland[] =
1426 {
1427 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1430 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1436 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1438 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1442 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1456 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1468 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1469 { 0xFFFFFFFF }
1470 };
1471
1472 static const struct si_cac_config_reg lcac_mars_pro[] =
1473 {
1474 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1477 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1483 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1489 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1501 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1503 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1515 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516 { 0xFFFFFFFF }
1517 };
1518
1519 static const struct si_cac_config_reg cac_override_oland[] =
1520 {
1521 { 0xFFFFFFFF }
1522 };
1523
1524 static const struct si_powertune_data powertune_data_oland =
1525 {
1526 ((1 << 16) | 0x6993),
1527 5,
1528 0,
1529 7,
1530 105,
1531 {
1532 0UL,
1533 0UL,
1534 7194395UL,
1535 309631529UL,
1536 -1270850L,
1537 4513710L,
1538 100
1539 },
1540 117830498UL,
1541 12,
1542 {
1543 0,
1544 0,
1545 0,
1546 0,
1547 0,
1548 0,
1549 0,
1550 0
1551 },
1552 true
1553 };
1554
1555 static const struct si_powertune_data powertune_data_mars_pro =
1556 {
1557 ((1 << 16) | 0x6993),
1558 5,
1559 0,
1560 7,
1561 105,
1562 {
1563 0UL,
1564 0UL,
1565 7194395UL,
1566 309631529UL,
1567 -1270850L,
1568 4513710L,
1569 100
1570 },
1571 117830498UL,
1572 12,
1573 {
1574 0,
1575 0,
1576 0,
1577 0,
1578 0,
1579 0,
1580 0,
1581 0
1582 },
1583 true
1584 };
1585
1586 static const struct si_dte_data dte_data_oland =
1587 {
1588 { 0, 0, 0, 0, 0 },
1589 { 0, 0, 0, 0, 0 },
1590 0,
1591 0,
1592 0,
1593 0,
1594 0,
1595 0,
1596 0,
1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1600 0,
1601 false
1602 };
1603
1604 static const struct si_dte_data dte_data_mars_pro =
1605 {
1606 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1607 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1608 5,
1609 55000,
1610 105,
1611 0xA,
1612 1,
1613 0,
1614 0x10,
1615 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1616 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1617 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1618 90,
1619 true
1620 };
1621
1622 static const struct si_dte_data dte_data_sun_xt =
1623 {
1624 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1625 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1626 5,
1627 55000,
1628 105,
1629 0xA,
1630 1,
1631 0,
1632 0x10,
1633 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1634 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1635 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1636 90,
1637 true
1638 };
1639
1640
1641 static const struct si_cac_config_reg cac_weights_hainan[] =
1642 {
1643 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1644 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1645 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1646 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1647 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1648 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1649 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1651 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1652 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1653 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1654 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1655 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1656 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1657 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1658 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1659 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1660 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1661 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1662 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1663 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1664 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1665 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1666 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1667 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1668 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1669 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1670 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1672 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1674 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1678 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1679 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1680 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1681 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1682 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1683 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1684 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1685 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1688 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1689 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1701 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1702 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1703 { 0xFFFFFFFF }
1704 };
1705
1706 static const struct si_powertune_data powertune_data_hainan =
1707 {
1708 ((1 << 16) | 0x6993),
1709 5,
1710 0,
1711 9,
1712 105,
1713 {
1714 0UL,
1715 0UL,
1716 7194395UL,
1717 309631529UL,
1718 -1270850L,
1719 4513710L,
1720 100
1721 },
1722 117830498UL,
1723 12,
1724 {
1725 0,
1726 0,
1727 0,
1728 0,
1729 0,
1730 0,
1731 0,
1732 0
1733 },
1734 true
1735 };
1736
1737 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1738 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1739 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1741
1742 extern int si_mc_load_microcode(struct radeon_device *rdev);
1743 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
1744
1745 static int si_populate_voltage_value(struct radeon_device *rdev,
1746 const struct atom_voltage_table *table,
1747 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1748 static int si_get_std_voltage_value(struct radeon_device *rdev,
1749 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1750 u16 *std_voltage);
1751 static int si_write_smc_soft_register(struct radeon_device *rdev,
1752 u16 reg_offset, u32 value);
1753 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1754 struct rv7xx_pl *pl,
1755 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1756 static int si_calculate_sclk_params(struct radeon_device *rdev,
1757 u32 engine_clock,
1758 SISLANDS_SMC_SCLK_VALUE *sclk);
1759
1760 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1761 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1762
1763 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1764 {
1765 struct si_power_info *pi = rdev->pm.dpm.priv;
1766
1767 return pi;
1768 }
1769
1770 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1771 u16 v, s32 t, u32 ileakage, u32 *leakage)
1772 {
1773 s64 kt, kv, leakage_w, i_leakage, vddc;
1774 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1775 s64 tmp;
1776
1777 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1778 vddc = div64_s64(drm_int2fixp(v), 1000);
1779 temperature = div64_s64(drm_int2fixp(t), 1000);
1780
1781 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1782 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1783 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1784 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1785 t_ref = drm_int2fixp(coeff->t_ref);
1786
1787 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1788 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1789 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1790 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1791
1792 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1793
1794 *leakage = drm_fixp2int(leakage_w * 1000);
1795 }
1796
1797 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1798 const struct ni_leakage_coeffients *coeff,
1799 u16 v,
1800 s32 t,
1801 u32 i_leakage,
1802 u32 *leakage)
1803 {
1804 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1805 }
1806
1807 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1808 const u32 fixed_kt, u16 v,
1809 u32 ileakage, u32 *leakage)
1810 {
1811 s64 kt, kv, leakage_w, i_leakage, vddc;
1812
1813 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1814 vddc = div64_s64(drm_int2fixp(v), 1000);
1815
1816 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1817 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1818 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1819
1820 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1821
1822 *leakage = drm_fixp2int(leakage_w * 1000);
1823 }
1824
1825 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1826 const struct ni_leakage_coeffients *coeff,
1827 const u32 fixed_kt,
1828 u16 v,
1829 u32 i_leakage,
1830 u32 *leakage)
1831 {
1832 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1833 }
1834
1835
1836 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1837 struct si_dte_data *dte_data)
1838 {
1839 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1840 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1841 u32 k = dte_data->k;
1842 u32 t_max = dte_data->max_t;
1843 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1844 u32 t_0 = dte_data->t0;
1845 u32 i;
1846
1847 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1848 dte_data->tdep_count = 3;
1849
1850 for (i = 0; i < k; i++) {
1851 dte_data->r[i] =
1852 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1853 (p_limit2 * (u32)100);
1854 }
1855
1856 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1857
1858 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1859 dte_data->tdep_r[i] = dte_data->r[4];
1860 }
1861 } else {
1862 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1863 }
1864 }
1865
1866 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1867 {
1868 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1869 struct si_power_info *si_pi = si_get_pi(rdev);
1870 bool update_dte_from_pl2 = false;
1871
1872 if (rdev->family == CHIP_TAHITI) {
1873 si_pi->cac_weights = cac_weights_tahiti;
1874 si_pi->lcac_config = lcac_tahiti;
1875 si_pi->cac_override = cac_override_tahiti;
1876 si_pi->powertune_data = &powertune_data_tahiti;
1877 si_pi->dte_data = dte_data_tahiti;
1878
1879 switch (rdev->pdev->device) {
1880 case 0x6798:
1881 si_pi->dte_data.enable_dte_by_default = true;
1882 break;
1883 case 0x6799:
1884 si_pi->dte_data = dte_data_new_zealand;
1885 break;
1886 case 0x6790:
1887 case 0x6791:
1888 case 0x6792:
1889 case 0x679E:
1890 si_pi->dte_data = dte_data_aruba_pro;
1891 update_dte_from_pl2 = true;
1892 break;
1893 case 0x679B:
1894 si_pi->dte_data = dte_data_malta;
1895 update_dte_from_pl2 = true;
1896 break;
1897 case 0x679A:
1898 si_pi->dte_data = dte_data_tahiti_pro;
1899 update_dte_from_pl2 = true;
1900 break;
1901 default:
1902 if (si_pi->dte_data.enable_dte_by_default == true)
1903 DRM_ERROR("DTE is not enabled!\n");
1904 break;
1905 }
1906 } else if (rdev->family == CHIP_PITCAIRN) {
1907 switch (rdev->pdev->device) {
1908 case 0x6810:
1909 case 0x6818:
1910 si_pi->cac_weights = cac_weights_pitcairn;
1911 si_pi->lcac_config = lcac_pitcairn;
1912 si_pi->cac_override = cac_override_pitcairn;
1913 si_pi->powertune_data = &powertune_data_pitcairn;
1914 si_pi->dte_data = dte_data_curacao_xt;
1915 update_dte_from_pl2 = true;
1916 break;
1917 case 0x6819:
1918 case 0x6811:
1919 si_pi->cac_weights = cac_weights_pitcairn;
1920 si_pi->lcac_config = lcac_pitcairn;
1921 si_pi->cac_override = cac_override_pitcairn;
1922 si_pi->powertune_data = &powertune_data_pitcairn;
1923 si_pi->dte_data = dte_data_curacao_pro;
1924 update_dte_from_pl2 = true;
1925 break;
1926 case 0x6800:
1927 case 0x6806:
1928 si_pi->cac_weights = cac_weights_pitcairn;
1929 si_pi->lcac_config = lcac_pitcairn;
1930 si_pi->cac_override = cac_override_pitcairn;
1931 si_pi->powertune_data = &powertune_data_pitcairn;
1932 si_pi->dte_data = dte_data_neptune_xt;
1933 update_dte_from_pl2 = true;
1934 break;
1935 default:
1936 si_pi->cac_weights = cac_weights_pitcairn;
1937 si_pi->lcac_config = lcac_pitcairn;
1938 si_pi->cac_override = cac_override_pitcairn;
1939 si_pi->powertune_data = &powertune_data_pitcairn;
1940 si_pi->dte_data = dte_data_pitcairn;
1941 break;
1942 }
1943 } else if (rdev->family == CHIP_VERDE) {
1944 si_pi->lcac_config = lcac_cape_verde;
1945 si_pi->cac_override = cac_override_cape_verde;
1946 si_pi->powertune_data = &powertune_data_cape_verde;
1947
1948 switch (rdev->pdev->device) {
1949 case 0x683B:
1950 case 0x683F:
1951 case 0x6829:
1952 case 0x6835:
1953 si_pi->cac_weights = cac_weights_cape_verde_pro;
1954 si_pi->dte_data = dte_data_cape_verde;
1955 break;
1956 case 0x682C:
1957 si_pi->cac_weights = cac_weights_cape_verde_pro;
1958 si_pi->dte_data = dte_data_sun_xt;
1959 break;
1960 case 0x6825:
1961 case 0x6827:
1962 si_pi->cac_weights = cac_weights_heathrow;
1963 si_pi->dte_data = dte_data_cape_verde;
1964 break;
1965 case 0x6824:
1966 case 0x682D:
1967 si_pi->cac_weights = cac_weights_chelsea_xt;
1968 si_pi->dte_data = dte_data_cape_verde;
1969 break;
1970 case 0x682F:
1971 si_pi->cac_weights = cac_weights_chelsea_pro;
1972 si_pi->dte_data = dte_data_cape_verde;
1973 break;
1974 case 0x6820:
1975 si_pi->cac_weights = cac_weights_heathrow;
1976 si_pi->dte_data = dte_data_venus_xtx;
1977 break;
1978 case 0x6821:
1979 si_pi->cac_weights = cac_weights_heathrow;
1980 si_pi->dte_data = dte_data_venus_xt;
1981 break;
1982 case 0x6823:
1983 case 0x682B:
1984 case 0x6822:
1985 case 0x682A:
1986 si_pi->cac_weights = cac_weights_chelsea_pro;
1987 si_pi->dte_data = dte_data_venus_pro;
1988 break;
1989 default:
1990 si_pi->cac_weights = cac_weights_cape_verde;
1991 si_pi->dte_data = dte_data_cape_verde;
1992 break;
1993 }
1994 } else if (rdev->family == CHIP_OLAND) {
1995 switch (rdev->pdev->device) {
1996 case 0x6601:
1997 case 0x6621:
1998 case 0x6603:
1999 case 0x6605:
2000 si_pi->cac_weights = cac_weights_mars_pro;
2001 si_pi->lcac_config = lcac_mars_pro;
2002 si_pi->cac_override = cac_override_oland;
2003 si_pi->powertune_data = &powertune_data_mars_pro;
2004 si_pi->dte_data = dte_data_mars_pro;
2005 update_dte_from_pl2 = true;
2006 break;
2007 case 0x6600:
2008 case 0x6606:
2009 case 0x6620:
2010 case 0x6604:
2011 si_pi->cac_weights = cac_weights_mars_xt;
2012 si_pi->lcac_config = lcac_mars_pro;
2013 si_pi->cac_override = cac_override_oland;
2014 si_pi->powertune_data = &powertune_data_mars_pro;
2015 si_pi->dte_data = dte_data_mars_pro;
2016 update_dte_from_pl2 = true;
2017 break;
2018 case 0x6611:
2019 case 0x6613:
2020 case 0x6608:
2021 si_pi->cac_weights = cac_weights_oland_pro;
2022 si_pi->lcac_config = lcac_mars_pro;
2023 si_pi->cac_override = cac_override_oland;
2024 si_pi->powertune_data = &powertune_data_mars_pro;
2025 si_pi->dte_data = dte_data_mars_pro;
2026 update_dte_from_pl2 = true;
2027 break;
2028 case 0x6610:
2029 si_pi->cac_weights = cac_weights_oland_xt;
2030 si_pi->lcac_config = lcac_mars_pro;
2031 si_pi->cac_override = cac_override_oland;
2032 si_pi->powertune_data = &powertune_data_mars_pro;
2033 si_pi->dte_data = dte_data_mars_pro;
2034 update_dte_from_pl2 = true;
2035 break;
2036 default:
2037 si_pi->cac_weights = cac_weights_oland;
2038 si_pi->lcac_config = lcac_oland;
2039 si_pi->cac_override = cac_override_oland;
2040 si_pi->powertune_data = &powertune_data_oland;
2041 si_pi->dte_data = dte_data_oland;
2042 break;
2043 }
2044 } else if (rdev->family == CHIP_HAINAN) {
2045 si_pi->cac_weights = cac_weights_hainan;
2046 si_pi->lcac_config = lcac_oland;
2047 si_pi->cac_override = cac_override_oland;
2048 si_pi->powertune_data = &powertune_data_hainan;
2049 si_pi->dte_data = dte_data_sun_xt;
2050 update_dte_from_pl2 = true;
2051 } else {
2052 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2053 return;
2054 }
2055
2056 ni_pi->enable_power_containment = false;
2057 ni_pi->enable_cac = false;
2058 ni_pi->enable_sq_ramping = false;
2059 si_pi->enable_dte = false;
2060
2061 if (si_pi->powertune_data->enable_powertune_by_default) {
2062 ni_pi->enable_power_containment= true;
2063 ni_pi->enable_cac = true;
2064 if (si_pi->dte_data.enable_dte_by_default) {
2065 si_pi->enable_dte = true;
2066 if (update_dte_from_pl2)
2067 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2068
2069 }
2070 ni_pi->enable_sq_ramping = true;
2071 }
2072
2073 ni_pi->driver_calculate_cac_leakage = true;
2074 ni_pi->cac_configuration_required = true;
2075
2076 if (ni_pi->cac_configuration_required) {
2077 ni_pi->support_cac_long_term_average = true;
2078 si_pi->dyn_powertune_data.l2_lta_window_size =
2079 si_pi->powertune_data->l2_lta_window_size_default;
2080 si_pi->dyn_powertune_data.lts_truncate =
2081 si_pi->powertune_data->lts_truncate_default;
2082 } else {
2083 ni_pi->support_cac_long_term_average = false;
2084 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2085 si_pi->dyn_powertune_data.lts_truncate = 0;
2086 }
2087
2088 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2089 }
2090
2091 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2092 {
2093 return 1;
2094 }
2095
2096 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2097 {
2098 u32 xclk;
2099 u32 wintime;
2100 u32 cac_window;
2101 u32 cac_window_size;
2102
2103 xclk = radeon_get_xclk(rdev);
2104
2105 if (xclk == 0)
2106 return 0;
2107
2108 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2109 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2110
2111 wintime = (cac_window_size * 100) / xclk;
2112
2113 return wintime;
2114 }
2115
2116 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2117 {
2118 return power_in_watts;
2119 }
2120
2121 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2122 bool adjust_polarity,
2123 u32 tdp_adjustment,
2124 u32 *tdp_limit,
2125 u32 *near_tdp_limit)
2126 {
2127 u32 adjustment_delta, max_tdp_limit;
2128
2129 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2130 return -EINVAL;
2131
2132 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2133
2134 if (adjust_polarity) {
2135 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2136 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2137 } else {
2138 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2139 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2140 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2141 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2142 else
2143 *near_tdp_limit = 0;
2144 }
2145
2146 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2147 return -EINVAL;
2148 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2149 return -EINVAL;
2150
2151 return 0;
2152 }
2153
2154 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2155 struct radeon_ps *radeon_state)
2156 {
2157 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2158 struct si_power_info *si_pi = si_get_pi(rdev);
2159
2160 if (ni_pi->enable_power_containment) {
2161 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2162 PP_SIslands_PAPMParameters *papm_parm;
2163 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2164 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2165 u32 tdp_limit;
2166 u32 near_tdp_limit;
2167 int ret;
2168
2169 if (scaling_factor == 0)
2170 return -EINVAL;
2171
2172 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2173
2174 ret = si_calculate_adjusted_tdp_limits(rdev,
2175 false, /* ??? */
2176 rdev->pm.dpm.tdp_adjustment,
2177 &tdp_limit,
2178 &near_tdp_limit);
2179 if (ret)
2180 return ret;
2181
2182 smc_table->dpm2Params.TDPLimit =
2183 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2184 smc_table->dpm2Params.NearTDPLimit =
2185 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2186 smc_table->dpm2Params.SafePowerLimit =
2187 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2188
2189 ret = si_copy_bytes_to_smc(rdev,
2190 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2191 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2192 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2193 sizeof(u32) * 3,
2194 si_pi->sram_end);
2195 if (ret)
2196 return ret;
2197
2198 if (si_pi->enable_ppm) {
2199 papm_parm = &si_pi->papm_parm;
2200 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2201 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2202 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2203 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2204 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2205 papm_parm->PlatformPowerLimit = 0xffffffff;
2206 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2207
2208 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2209 (u8 *)papm_parm,
2210 sizeof(PP_SIslands_PAPMParameters),
2211 si_pi->sram_end);
2212 if (ret)
2213 return ret;
2214 }
2215 }
2216 return 0;
2217 }
2218
2219 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2220 struct radeon_ps *radeon_state)
2221 {
2222 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2223 struct si_power_info *si_pi = si_get_pi(rdev);
2224
2225 if (ni_pi->enable_power_containment) {
2226 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2227 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2228 int ret;
2229
2230 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2231
2232 smc_table->dpm2Params.NearTDPLimit =
2233 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2234 smc_table->dpm2Params.SafePowerLimit =
2235 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2236
2237 ret = si_copy_bytes_to_smc(rdev,
2238 (si_pi->state_table_start +
2239 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2240 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2241 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2242 sizeof(u32) * 2,
2243 si_pi->sram_end);
2244 if (ret)
2245 return ret;
2246 }
2247
2248 return 0;
2249 }
2250
2251 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2252 const u16 prev_std_vddc,
2253 const u16 curr_std_vddc)
2254 {
2255 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2256 u64 prev_vddc = (u64)prev_std_vddc;
2257 u64 curr_vddc = (u64)curr_std_vddc;
2258 u64 pwr_efficiency_ratio, n, d;
2259
2260 if ((prev_vddc == 0) || (curr_vddc == 0))
2261 return 0;
2262
2263 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2264 d = prev_vddc * prev_vddc;
2265 pwr_efficiency_ratio = div64_u64(n, d);
2266
2267 if (pwr_efficiency_ratio > (u64)0xFFFF)
2268 return 0;
2269
2270 return (u16)pwr_efficiency_ratio;
2271 }
2272
2273 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2274 struct radeon_ps *radeon_state)
2275 {
2276 struct si_power_info *si_pi = si_get_pi(rdev);
2277
2278 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2279 radeon_state->vclk && radeon_state->dclk)
2280 return true;
2281
2282 return false;
2283 }
2284
2285 static int si_populate_power_containment_values(struct radeon_device *rdev,
2286 struct radeon_ps *radeon_state,
2287 SISLANDS_SMC_SWSTATE *smc_state)
2288 {
2289 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2290 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2291 struct ni_ps *state = ni_get_ps(radeon_state);
2292 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2293 u32 prev_sclk;
2294 u32 max_sclk;
2295 u32 min_sclk;
2296 u16 prev_std_vddc;
2297 u16 curr_std_vddc;
2298 int i;
2299 u16 pwr_efficiency_ratio;
2300 u8 max_ps_percent;
2301 bool disable_uvd_power_tune;
2302 int ret;
2303
2304 if (ni_pi->enable_power_containment == false)
2305 return 0;
2306
2307 if (state->performance_level_count == 0)
2308 return -EINVAL;
2309
2310 if (smc_state->levelCount != state->performance_level_count)
2311 return -EINVAL;
2312
2313 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2314
2315 smc_state->levels[0].dpm2.MaxPS = 0;
2316 smc_state->levels[0].dpm2.NearTDPDec = 0;
2317 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2318 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2319 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2320
2321 for (i = 1; i < state->performance_level_count; i++) {
2322 prev_sclk = state->performance_levels[i-1].sclk;
2323 max_sclk = state->performance_levels[i].sclk;
2324 if (i == 1)
2325 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2326 else
2327 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2328
2329 if (prev_sclk > max_sclk)
2330 return -EINVAL;
2331
2332 if ((max_ps_percent == 0) ||
2333 (prev_sclk == max_sclk) ||
2334 disable_uvd_power_tune) {
2335 min_sclk = max_sclk;
2336 } else if (i == 1) {
2337 min_sclk = prev_sclk;
2338 } else {
2339 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2340 }
2341
2342 if (min_sclk < state->performance_levels[0].sclk)
2343 min_sclk = state->performance_levels[0].sclk;
2344
2345 if (min_sclk == 0)
2346 return -EINVAL;
2347
2348 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2349 state->performance_levels[i-1].vddc, &vddc);
2350 if (ret)
2351 return ret;
2352
2353 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2354 if (ret)
2355 return ret;
2356
2357 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2358 state->performance_levels[i].vddc, &vddc);
2359 if (ret)
2360 return ret;
2361
2362 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2363 if (ret)
2364 return ret;
2365
2366 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2367 prev_std_vddc, curr_std_vddc);
2368
2369 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2370 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2371 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2372 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2373 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2374 }
2375
2376 return 0;
2377 }
2378
2379 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2380 struct radeon_ps *radeon_state,
2381 SISLANDS_SMC_SWSTATE *smc_state)
2382 {
2383 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2384 struct ni_ps *state = ni_get_ps(radeon_state);
2385 u32 sq_power_throttle, sq_power_throttle2;
2386 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2387 int i;
2388
2389 if (state->performance_level_count == 0)
2390 return -EINVAL;
2391
2392 if (smc_state->levelCount != state->performance_level_count)
2393 return -EINVAL;
2394
2395 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2396 return -EINVAL;
2397
2398 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2399 enable_sq_ramping = false;
2400
2401 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2402 enable_sq_ramping = false;
2403
2404 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2405 enable_sq_ramping = false;
2406
2407 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2408 enable_sq_ramping = false;
2409
2410 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2411 enable_sq_ramping = false;
2412
2413 for (i = 0; i < state->performance_level_count; i++) {
2414 sq_power_throttle = 0;
2415 sq_power_throttle2 = 0;
2416
2417 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2418 enable_sq_ramping) {
2419 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2420 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2421 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2422 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2423 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2424 } else {
2425 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2426 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2427 }
2428
2429 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2430 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2431 }
2432
2433 return 0;
2434 }
2435
2436 static int si_enable_power_containment(struct radeon_device *rdev,
2437 struct radeon_ps *radeon_new_state,
2438 bool enable)
2439 {
2440 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2441 PPSMC_Result smc_result;
2442 int ret = 0;
2443
2444 if (ni_pi->enable_power_containment) {
2445 if (enable) {
2446 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2447 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2448 if (smc_result != PPSMC_Result_OK) {
2449 ret = -EINVAL;
2450 ni_pi->pc_enabled = false;
2451 } else {
2452 ni_pi->pc_enabled = true;
2453 }
2454 }
2455 } else {
2456 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2457 if (smc_result != PPSMC_Result_OK)
2458 ret = -EINVAL;
2459 ni_pi->pc_enabled = false;
2460 }
2461 }
2462
2463 return ret;
2464 }
2465
2466 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2467 {
2468 struct si_power_info *si_pi = si_get_pi(rdev);
2469 int ret = 0;
2470 struct si_dte_data *dte_data = &si_pi->dte_data;
2471 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2472 u32 table_size;
2473 u8 tdep_count;
2474 u32 i;
2475
2476 if (dte_data == NULL)
2477 si_pi->enable_dte = false;
2478
2479 if (si_pi->enable_dte == false)
2480 return 0;
2481
2482 if (dte_data->k <= 0)
2483 return -EINVAL;
2484
2485 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2486 if (dte_tables == NULL) {
2487 si_pi->enable_dte = false;
2488 return -ENOMEM;
2489 }
2490
2491 table_size = dte_data->k;
2492
2493 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2494 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2495
2496 tdep_count = dte_data->tdep_count;
2497 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2498 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2499
2500 dte_tables->K = cpu_to_be32(table_size);
2501 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2502 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2503 dte_tables->WindowSize = dte_data->window_size;
2504 dte_tables->temp_select = dte_data->temp_select;
2505 dte_tables->DTE_mode = dte_data->dte_mode;
2506 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2507
2508 if (tdep_count > 0)
2509 table_size--;
2510
2511 for (i = 0; i < table_size; i++) {
2512 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2513 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2514 }
2515
2516 dte_tables->Tdep_count = tdep_count;
2517
2518 for (i = 0; i < (u32)tdep_count; i++) {
2519 dte_tables->T_limits[i] = dte_data->t_limits[i];
2520 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2521 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2522 }
2523
2524 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2525 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2526 kfree(dte_tables);
2527
2528 return ret;
2529 }
2530
2531 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2532 u16 *max, u16 *min)
2533 {
2534 struct si_power_info *si_pi = si_get_pi(rdev);
2535 struct radeon_cac_leakage_table *table =
2536 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2537 u32 i;
2538 u32 v0_loadline;
2539
2540
2541 if (table == NULL)
2542 return -EINVAL;
2543
2544 *max = 0;
2545 *min = 0xFFFF;
2546
2547 for (i = 0; i < table->count; i++) {
2548 if (table->entries[i].vddc > *max)
2549 *max = table->entries[i].vddc;
2550 if (table->entries[i].vddc < *min)
2551 *min = table->entries[i].vddc;
2552 }
2553
2554 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2555 return -EINVAL;
2556
2557 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2558
2559 if (v0_loadline > 0xFFFFUL)
2560 return -EINVAL;
2561
2562 *min = (u16)v0_loadline;
2563
2564 if ((*min > *max) || (*max == 0) || (*min == 0))
2565 return -EINVAL;
2566
2567 return 0;
2568 }
2569
2570 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2571 {
2572 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2573 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2574 }
2575
2576 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2577 PP_SIslands_CacConfig *cac_tables,
2578 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2579 u16 t0, u16 t_step)
2580 {
2581 struct si_power_info *si_pi = si_get_pi(rdev);
2582 u32 leakage;
2583 unsigned int i, j;
2584 s32 t;
2585 u32 smc_leakage;
2586 u32 scaling_factor;
2587 u16 voltage;
2588
2589 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2590
2591 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2592 t = (1000 * (i * t_step + t0));
2593
2594 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2595 voltage = vddc_max - (vddc_step * j);
2596
2597 si_calculate_leakage_for_v_and_t(rdev,
2598 &si_pi->powertune_data->leakage_coefficients,
2599 voltage,
2600 t,
2601 si_pi->dyn_powertune_data.cac_leakage,
2602 &leakage);
2603
2604 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2605
2606 if (smc_leakage > 0xFFFF)
2607 smc_leakage = 0xFFFF;
2608
2609 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2610 cpu_to_be16((u16)smc_leakage);
2611 }
2612 }
2613 return 0;
2614 }
2615
2616 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2617 PP_SIslands_CacConfig *cac_tables,
2618 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2619 {
2620 struct si_power_info *si_pi = si_get_pi(rdev);
2621 u32 leakage;
2622 unsigned int i, j;
2623 u32 smc_leakage;
2624 u32 scaling_factor;
2625 u16 voltage;
2626
2627 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2628
2629 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2630 voltage = vddc_max - (vddc_step * j);
2631
2632 si_calculate_leakage_for_v(rdev,
2633 &si_pi->powertune_data->leakage_coefficients,
2634 si_pi->powertune_data->fixed_kt,
2635 voltage,
2636 si_pi->dyn_powertune_data.cac_leakage,
2637 &leakage);
2638
2639 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2640
2641 if (smc_leakage > 0xFFFF)
2642 smc_leakage = 0xFFFF;
2643
2644 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2645 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2646 cpu_to_be16((u16)smc_leakage);
2647 }
2648 return 0;
2649 }
2650
2651 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2652 {
2653 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2654 struct si_power_info *si_pi = si_get_pi(rdev);
2655 PP_SIslands_CacConfig *cac_tables = NULL;
2656 u16 vddc_max, vddc_min, vddc_step;
2657 u16 t0, t_step;
2658 u32 load_line_slope, reg;
2659 int ret = 0;
2660 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2661
2662 if (ni_pi->enable_cac == false)
2663 return 0;
2664
2665 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2666 if (!cac_tables)
2667 return -ENOMEM;
2668
2669 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2670 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2671 WREG32(CG_CAC_CTRL, reg);
2672
2673 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2674 si_pi->dyn_powertune_data.dc_pwr_value =
2675 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2676 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2677 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2678
2679 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2680
2681 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2682 if (ret)
2683 goto done_free;
2684
2685 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2686 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2687 t_step = 4;
2688 t0 = 60;
2689
2690 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2691 ret = si_init_dte_leakage_table(rdev, cac_tables,
2692 vddc_max, vddc_min, vddc_step,
2693 t0, t_step);
2694 else
2695 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2696 vddc_max, vddc_min, vddc_step);
2697 if (ret)
2698 goto done_free;
2699
2700 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2701
2702 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2703 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2704 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2705 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2706 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2707 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2708 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2709 cac_tables->calculation_repeats = cpu_to_be32(2);
2710 cac_tables->dc_cac = cpu_to_be32(0);
2711 cac_tables->log2_PG_LKG_SCALE = 12;
2712 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2713 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2714 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2715
2716 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2717 sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2718
2719 if (ret)
2720 goto done_free;
2721
2722 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2723
2724 done_free:
2725 if (ret) {
2726 ni_pi->enable_cac = false;
2727 ni_pi->enable_power_containment = false;
2728 }
2729
2730 kfree(cac_tables);
2731
2732 return 0;
2733 }
2734
2735 static int si_program_cac_config_registers(struct radeon_device *rdev,
2736 const struct si_cac_config_reg *cac_config_regs)
2737 {
2738 const struct si_cac_config_reg *config_regs = cac_config_regs;
2739 u32 data = 0, offset;
2740
2741 if (!config_regs)
2742 return -EINVAL;
2743
2744 while (config_regs->offset != 0xFFFFFFFF) {
2745 switch (config_regs->type) {
2746 case SISLANDS_CACCONFIG_CGIND:
2747 offset = SMC_CG_IND_START + config_regs->offset;
2748 if (offset < SMC_CG_IND_END)
2749 data = RREG32_SMC(offset);
2750 break;
2751 default:
2752 data = RREG32(config_regs->offset << 2);
2753 break;
2754 }
2755
2756 data &= ~config_regs->mask;
2757 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2758
2759 switch (config_regs->type) {
2760 case SISLANDS_CACCONFIG_CGIND:
2761 offset = SMC_CG_IND_START + config_regs->offset;
2762 if (offset < SMC_CG_IND_END)
2763 WREG32_SMC(offset, data);
2764 break;
2765 default:
2766 WREG32(config_regs->offset << 2, data);
2767 break;
2768 }
2769 config_regs++;
2770 }
2771 return 0;
2772 }
2773
2774 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2775 {
2776 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2777 struct si_power_info *si_pi = si_get_pi(rdev);
2778 int ret;
2779
2780 if ((ni_pi->enable_cac == false) ||
2781 (ni_pi->cac_configuration_required == false))
2782 return 0;
2783
2784 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2785 if (ret)
2786 return ret;
2787 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2788 if (ret)
2789 return ret;
2790 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2791 if (ret)
2792 return ret;
2793
2794 return 0;
2795 }
2796
2797 static int si_enable_smc_cac(struct radeon_device *rdev,
2798 struct radeon_ps *radeon_new_state,
2799 bool enable)
2800 {
2801 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2802 struct si_power_info *si_pi = si_get_pi(rdev);
2803 PPSMC_Result smc_result;
2804 int ret = 0;
2805
2806 if (ni_pi->enable_cac) {
2807 if (enable) {
2808 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2809 if (ni_pi->support_cac_long_term_average) {
2810 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2811 if (smc_result != PPSMC_Result_OK)
2812 ni_pi->support_cac_long_term_average = false;
2813 }
2814
2815 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2816 if (smc_result != PPSMC_Result_OK) {
2817 ret = -EINVAL;
2818 ni_pi->cac_enabled = false;
2819 } else {
2820 ni_pi->cac_enabled = true;
2821 }
2822
2823 if (si_pi->enable_dte) {
2824 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2825 if (smc_result != PPSMC_Result_OK)
2826 ret = -EINVAL;
2827 }
2828 }
2829 } else if (ni_pi->cac_enabled) {
2830 if (si_pi->enable_dte)
2831 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2832
2833 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2834
2835 ni_pi->cac_enabled = false;
2836
2837 if (ni_pi->support_cac_long_term_average)
2838 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2839 }
2840 }
2841 return ret;
2842 }
2843
2844 static int si_init_smc_spll_table(struct radeon_device *rdev)
2845 {
2846 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2847 struct si_power_info *si_pi = si_get_pi(rdev);
2848 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2849 SISLANDS_SMC_SCLK_VALUE sclk_params;
2850 u32 fb_div, p_div;
2851 u32 clk_s, clk_v;
2852 u32 sclk = 0;
2853 int ret = 0;
2854 u32 tmp;
2855 int i;
2856
2857 if (si_pi->spll_table_start == 0)
2858 return -EINVAL;
2859
2860 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2861 if (spll_table == NULL)
2862 return -ENOMEM;
2863
2864 for (i = 0; i < 256; i++) {
2865 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2866 if (ret)
2867 break;
2868
2869 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2870 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2871 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2872 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2873
2874 fb_div &= ~0x00001FFF;
2875 fb_div >>= 1;
2876 clk_v >>= 6;
2877
2878 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2879 ret = -EINVAL;
2880 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2881 ret = -EINVAL;
2882 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2883 ret = -EINVAL;
2884 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2885 ret = -EINVAL;
2886
2887 if (ret)
2888 break;
2889
2890 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2891 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2892 spll_table->freq[i] = cpu_to_be32(tmp);
2893
2894 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2895 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2896 spll_table->ss[i] = cpu_to_be32(tmp);
2897
2898 sclk += 512;
2899 }
2900
2901
2902 if (!ret)
2903 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2904 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2905 si_pi->sram_end);
2906
2907 if (ret)
2908 ni_pi->enable_power_containment = false;
2909
2910 kfree(spll_table);
2911
2912 return ret;
2913 }
2914
2915 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2916 u16 vce_voltage)
2917 {
2918 u16 highest_leakage = 0;
2919 struct si_power_info *si_pi = si_get_pi(rdev);
2920 int i;
2921
2922 for (i = 0; i < si_pi->leakage_voltage.count; i++){
2923 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
2924 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
2925 }
2926
2927 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
2928 return highest_leakage;
2929
2930 return vce_voltage;
2931 }
2932
2933 static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2934 u32 evclk, u32 ecclk, u16 *voltage)
2935 {
2936 u32 i;
2937 int ret = -EINVAL;
2938 struct radeon_vce_clock_voltage_dependency_table *table =
2939 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2940
2941 if (((evclk == 0) && (ecclk == 0)) ||
2942 (table && (table->count == 0))) {
2943 *voltage = 0;
2944 return 0;
2945 }
2946
2947 for (i = 0; i < table->count; i++) {
2948 if ((evclk <= table->entries[i].evclk) &&
2949 (ecclk <= table->entries[i].ecclk)) {
2950 *voltage = table->entries[i].v;
2951 ret = 0;
2952 break;
2953 }
2954 }
2955
2956 /* if no match return the highest voltage */
2957 if (ret)
2958 *voltage = table->entries[table->count - 1].v;
2959
2960 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2961
2962 return ret;
2963 }
2964
2965 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2966 struct radeon_ps *rps)
2967 {
2968 struct ni_ps *ps = ni_get_ps(rps);
2969 struct radeon_clock_and_voltage_limits *max_limits;
2970 bool disable_mclk_switching = false;
2971 bool disable_sclk_switching = false;
2972 u32 mclk, sclk;
2973 u16 vddc, vddci, min_vce_voltage = 0;
2974 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2975 u32 max_sclk = 0, max_mclk = 0;
2976 int i;
2977
2978 if (rdev->family == CHIP_HAINAN) {
2979 if ((rdev->pdev->revision == 0x81) ||
2980 (rdev->pdev->revision == 0x83) ||
2981 (rdev->pdev->revision == 0xC3) ||
2982 (rdev->pdev->device == 0x6664) ||
2983 (rdev->pdev->device == 0x6665) ||
2984 (rdev->pdev->device == 0x6667)) {
2985 max_sclk = 75000;
2986 }
2987 }
2988
2989 if (rps->vce_active) {
2990 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
2991 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
2992 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
2993 &min_vce_voltage);
2994 } else {
2995 rps->evclk = 0;
2996 rps->ecclk = 0;
2997 }
2998
2999 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
3000 ni_dpm_vblank_too_short(rdev))
3001 disable_mclk_switching = true;
3002
3003 if (rps->vclk || rps->dclk) {
3004 disable_mclk_switching = true;
3005 disable_sclk_switching = true;
3006 }
3007
3008 if (rdev->pm.dpm.ac_power)
3009 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3010 else
3011 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3012
3013 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3014 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3015 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3016 }
3017 if (rdev->pm.dpm.ac_power == false) {
3018 for (i = 0; i < ps->performance_level_count; i++) {
3019 if (ps->performance_levels[i].mclk > max_limits->mclk)
3020 ps->performance_levels[i].mclk = max_limits->mclk;
3021 if (ps->performance_levels[i].sclk > max_limits->sclk)
3022 ps->performance_levels[i].sclk = max_limits->sclk;
3023 if (ps->performance_levels[i].vddc > max_limits->vddc)
3024 ps->performance_levels[i].vddc = max_limits->vddc;
3025 if (ps->performance_levels[i].vddci > max_limits->vddci)
3026 ps->performance_levels[i].vddci = max_limits->vddci;
3027 }
3028 }
3029
3030 /* limit clocks to max supported clocks based on voltage dependency tables */
3031 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3032 &max_sclk_vddc);
3033 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3034 &max_mclk_vddci);
3035 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3036 &max_mclk_vddc);
3037
3038 for (i = 0; i < ps->performance_level_count; i++) {
3039 if (max_sclk_vddc) {
3040 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3041 ps->performance_levels[i].sclk = max_sclk_vddc;
3042 }
3043 if (max_mclk_vddci) {
3044 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3045 ps->performance_levels[i].mclk = max_mclk_vddci;
3046 }
3047 if (max_mclk_vddc) {
3048 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3049 ps->performance_levels[i].mclk = max_mclk_vddc;
3050 }
3051 if (max_mclk) {
3052 if (ps->performance_levels[i].mclk > max_mclk)
3053 ps->performance_levels[i].mclk = max_mclk;
3054 }
3055 if (max_sclk) {
3056 if (ps->performance_levels[i].sclk > max_sclk)
3057 ps->performance_levels[i].sclk = max_sclk;
3058 }
3059 }
3060
3061 /* XXX validate the min clocks required for display */
3062
3063 if (disable_mclk_switching) {
3064 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3065 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3066 } else {
3067 mclk = ps->performance_levels[0].mclk;
3068 vddci = ps->performance_levels[0].vddci;
3069 }
3070
3071 if (disable_sclk_switching) {
3072 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3073 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3074 } else {
3075 sclk = ps->performance_levels[0].sclk;
3076 vddc = ps->performance_levels[0].vddc;
3077 }
3078
3079 if (rps->vce_active) {
3080 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3081 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3082 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3083 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3084 }
3085
3086 /* adjusted low state */
3087 ps->performance_levels[0].sclk = sclk;
3088 ps->performance_levels[0].mclk = mclk;
3089 ps->performance_levels[0].vddc = vddc;
3090 ps->performance_levels[0].vddci = vddci;
3091
3092 if (disable_sclk_switching) {
3093 sclk = ps->performance_levels[0].sclk;
3094 for (i = 1; i < ps->performance_level_count; i++) {
3095 if (sclk < ps->performance_levels[i].sclk)
3096 sclk = ps->performance_levels[i].sclk;
3097 }
3098 for (i = 0; i < ps->performance_level_count; i++) {
3099 ps->performance_levels[i].sclk = sclk;
3100 ps->performance_levels[i].vddc = vddc;
3101 }
3102 } else {
3103 for (i = 1; i < ps->performance_level_count; i++) {
3104 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3105 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3106 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3107 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3108 }
3109 }
3110
3111 if (disable_mclk_switching) {
3112 mclk = ps->performance_levels[0].mclk;
3113 for (i = 1; i < ps->performance_level_count; i++) {
3114 if (mclk < ps->performance_levels[i].mclk)
3115 mclk = ps->performance_levels[i].mclk;
3116 }
3117 for (i = 0; i < ps->performance_level_count; i++) {
3118 ps->performance_levels[i].mclk = mclk;
3119 ps->performance_levels[i].vddci = vddci;
3120 }
3121 } else {
3122 for (i = 1; i < ps->performance_level_count; i++) {
3123 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3124 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3125 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3126 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3127 }
3128 }
3129
3130 for (i = 0; i < ps->performance_level_count; i++)
3131 btc_adjust_clock_combinations(rdev, max_limits,
3132 &ps->performance_levels[i]);
3133
3134 for (i = 0; i < ps->performance_level_count; i++) {
3135 if (ps->performance_levels[i].vddc < min_vce_voltage)
3136 ps->performance_levels[i].vddc = min_vce_voltage;
3137 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3138 ps->performance_levels[i].sclk,
3139 max_limits->vddc, &ps->performance_levels[i].vddc);
3140 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3141 ps->performance_levels[i].mclk,
3142 max_limits->vddci, &ps->performance_levels[i].vddci);
3143 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3144 ps->performance_levels[i].mclk,
3145 max_limits->vddc, &ps->performance_levels[i].vddc);
3146 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3147 rdev->clock.current_dispclk,
3148 max_limits->vddc, &ps->performance_levels[i].vddc);
3149 }
3150
3151 for (i = 0; i < ps->performance_level_count; i++) {
3152 btc_apply_voltage_delta_rules(rdev,
3153 max_limits->vddc, max_limits->vddci,
3154 &ps->performance_levels[i].vddc,
3155 &ps->performance_levels[i].vddci);
3156 }
3157
3158 ps->dc_compatible = true;
3159 for (i = 0; i < ps->performance_level_count; i++) {
3160 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3161 ps->dc_compatible = false;
3162 }
3163 }
3164
3165 #if 0
3166 static int si_read_smc_soft_register(struct radeon_device *rdev,
3167 u16 reg_offset, u32 *value)
3168 {
3169 struct si_power_info *si_pi = si_get_pi(rdev);
3170
3171 return si_read_smc_sram_dword(rdev,
3172 si_pi->soft_regs_start + reg_offset, value,
3173 si_pi->sram_end);
3174 }
3175 #endif
3176
3177 static int si_write_smc_soft_register(struct radeon_device *rdev,
3178 u16 reg_offset, u32 value)
3179 {
3180 struct si_power_info *si_pi = si_get_pi(rdev);
3181
3182 return si_write_smc_sram_dword(rdev,
3183 si_pi->soft_regs_start + reg_offset,
3184 value, si_pi->sram_end);
3185 }
3186
3187 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3188 {
3189 bool ret = false;
3190 u32 tmp, width, row, column, bank, density;
3191 bool is_memory_gddr5, is_special;
3192
3193 tmp = RREG32(MC_SEQ_MISC0);
3194 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3195 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3196 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3197
3198 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3199 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3200
3201 tmp = RREG32(MC_ARB_RAMCFG);
3202 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3203 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3204 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3205
3206 density = (1 << (row + column - 20 + bank)) * width;
3207
3208 if ((rdev->pdev->device == 0x6819) &&
3209 is_memory_gddr5 && is_special && (density == 0x400))
3210 ret = true;
3211
3212 return ret;
3213 }
3214
3215 static void si_get_leakage_vddc(struct radeon_device *rdev)
3216 {
3217 struct si_power_info *si_pi = si_get_pi(rdev);
3218 u16 vddc, count = 0;
3219 int i, ret;
3220
3221 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3222 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3223
3224 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3225 si_pi->leakage_voltage.entries[count].voltage = vddc;
3226 si_pi->leakage_voltage.entries[count].leakage_index =
3227 SISLANDS_LEAKAGE_INDEX0 + i;
3228 count++;
3229 }
3230 }
3231 si_pi->leakage_voltage.count = count;
3232 }
3233
3234 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3235 u32 index, u16 *leakage_voltage)
3236 {
3237 struct si_power_info *si_pi = si_get_pi(rdev);
3238 int i;
3239
3240 if (leakage_voltage == NULL)
3241 return -EINVAL;
3242
3243 if ((index & 0xff00) != 0xff00)
3244 return -EINVAL;
3245
3246 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3247 return -EINVAL;
3248
3249 if (index < SISLANDS_LEAKAGE_INDEX0)
3250 return -EINVAL;
3251
3252 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3253 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3254 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3255 return 0;
3256 }
3257 }
3258 return -EAGAIN;
3259 }
3260
3261 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3262 {
3263 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3264 bool want_thermal_protection;
3265 enum radeon_dpm_event_src dpm_event_src;
3266
3267 switch (sources) {
3268 case 0:
3269 default:
3270 want_thermal_protection = false;
3271 break;
3272 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3273 want_thermal_protection = true;
3274 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3275 break;
3276 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3277 want_thermal_protection = true;
3278 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3279 break;
3280 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3281 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3282 want_thermal_protection = true;
3283 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3284 break;
3285 }
3286
3287 if (want_thermal_protection) {
3288 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3289 if (pi->thermal_protection)
3290 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3291 } else {
3292 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3293 }
3294 }
3295
3296 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3297 enum radeon_dpm_auto_throttle_src source,
3298 bool enable)
3299 {
3300 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3301
3302 if (enable) {
3303 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3304 pi->active_auto_throttle_sources |= 1 << source;
3305 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3306 }
3307 } else {
3308 if (pi->active_auto_throttle_sources & (1 << source)) {
3309 pi->active_auto_throttle_sources &= ~(1 << source);
3310 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3311 }
3312 }
3313 }
3314
3315 static void si_start_dpm(struct radeon_device *rdev)
3316 {
3317 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3318 }
3319
3320 static void si_stop_dpm(struct radeon_device *rdev)
3321 {
3322 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3323 }
3324
3325 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3326 {
3327 if (enable)
3328 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3329 else
3330 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3331
3332 }
3333
3334 #if 0
3335 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3336 u32 thermal_level)
3337 {
3338 PPSMC_Result ret;
3339
3340 if (thermal_level == 0) {
3341 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3342 if (ret == PPSMC_Result_OK)
3343 return 0;
3344 else
3345 return -EINVAL;
3346 }
3347 return 0;
3348 }
3349
3350 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3351 {
3352 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3353 }
3354 #endif
3355
3356 #if 0
3357 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3358 {
3359 if (ac_power)
3360 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3361 0 : -EINVAL;
3362
3363 return 0;
3364 }
3365 #endif
3366
3367 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3368 PPSMC_Msg msg, u32 parameter)
3369 {
3370 WREG32(SMC_SCRATCH0, parameter);
3371 return si_send_msg_to_smc(rdev, msg);
3372 }
3373
3374 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3375 {
3376 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3377 return -EINVAL;
3378
3379 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3380 0 : -EINVAL;
3381 }
3382
3383 int si_dpm_force_performance_level(struct radeon_device *rdev,
3384 enum radeon_dpm_forced_level level)
3385 {
3386 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3387 struct ni_ps *ps = ni_get_ps(rps);
3388 u32 levels = ps->performance_level_count;
3389
3390 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3391 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3392 return -EINVAL;
3393
3394 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3395 return -EINVAL;
3396 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3397 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3398 return -EINVAL;
3399
3400 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3401 return -EINVAL;
3402 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3403 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3404 return -EINVAL;
3405
3406 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3407 return -EINVAL;
3408 }
3409
3410 rdev->pm.dpm.forced_level = level;
3411
3412 return 0;
3413 }
3414
3415 #if 0
3416 static int si_set_boot_state(struct radeon_device *rdev)
3417 {
3418 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3419 0 : -EINVAL;
3420 }
3421 #endif
3422
3423 static int si_set_sw_state(struct radeon_device *rdev)
3424 {
3425 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3426 0 : -EINVAL;
3427 }
3428
3429 static int si_halt_smc(struct radeon_device *rdev)
3430 {
3431 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3432 return -EINVAL;
3433
3434 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3435 0 : -EINVAL;
3436 }
3437
3438 static int si_resume_smc(struct radeon_device *rdev)
3439 {
3440 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3441 return -EINVAL;
3442
3443 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3444 0 : -EINVAL;
3445 }
3446
3447 static void si_dpm_start_smc(struct radeon_device *rdev)
3448 {
3449 si_program_jump_on_start(rdev);
3450 si_start_smc(rdev);
3451 si_start_smc_clock(rdev);
3452 }
3453
3454 static void si_dpm_stop_smc(struct radeon_device *rdev)
3455 {
3456 si_reset_smc(rdev);
3457 si_stop_smc_clock(rdev);
3458 }
3459
3460 static int si_process_firmware_header(struct radeon_device *rdev)
3461 {
3462 struct si_power_info *si_pi = si_get_pi(rdev);
3463 u32 tmp;
3464 int ret;
3465
3466 ret = si_read_smc_sram_dword(rdev,
3467 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3468 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3469 &tmp, si_pi->sram_end);
3470 if (ret)
3471 return ret;
3472
3473 si_pi->state_table_start = tmp;
3474
3475 ret = si_read_smc_sram_dword(rdev,
3476 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3477 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3478 &tmp, si_pi->sram_end);
3479 if (ret)
3480 return ret;
3481
3482 si_pi->soft_regs_start = tmp;
3483
3484 ret = si_read_smc_sram_dword(rdev,
3485 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3486 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3487 &tmp, si_pi->sram_end);
3488 if (ret)
3489 return ret;
3490
3491 si_pi->mc_reg_table_start = tmp;
3492
3493 ret = si_read_smc_sram_dword(rdev,
3494 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3495 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3496 &tmp, si_pi->sram_end);
3497 if (ret)
3498 return ret;
3499
3500 si_pi->fan_table_start = tmp;
3501
3502 ret = si_read_smc_sram_dword(rdev,
3503 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3504 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3505 &tmp, si_pi->sram_end);
3506 if (ret)
3507 return ret;
3508
3509 si_pi->arb_table_start = tmp;
3510
3511 ret = si_read_smc_sram_dword(rdev,
3512 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3513 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3514 &tmp, si_pi->sram_end);
3515 if (ret)
3516 return ret;
3517
3518 si_pi->cac_table_start = tmp;
3519
3520 ret = si_read_smc_sram_dword(rdev,
3521 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3522 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3523 &tmp, si_pi->sram_end);
3524 if (ret)
3525 return ret;
3526
3527 si_pi->dte_table_start = tmp;
3528
3529 ret = si_read_smc_sram_dword(rdev,
3530 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3531 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3532 &tmp, si_pi->sram_end);
3533 if (ret)
3534 return ret;
3535
3536 si_pi->spll_table_start = tmp;
3537
3538 ret = si_read_smc_sram_dword(rdev,
3539 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3540 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3541 &tmp, si_pi->sram_end);
3542 if (ret)
3543 return ret;
3544
3545 si_pi->papm_cfg_table_start = tmp;
3546
3547 return ret;
3548 }
3549
3550 static void si_read_clock_registers(struct radeon_device *rdev)
3551 {
3552 struct si_power_info *si_pi = si_get_pi(rdev);
3553
3554 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3555 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3556 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3557 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3558 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3559 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3560 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3561 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3562 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3563 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3564 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3565 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3566 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3567 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3568 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3569 }
3570
3571 static void si_enable_thermal_protection(struct radeon_device *rdev,
3572 bool enable)
3573 {
3574 if (enable)
3575 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3576 else
3577 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3578 }
3579
3580 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3581 {
3582 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3583 }
3584
3585 #if 0
3586 static int si_enter_ulp_state(struct radeon_device *rdev)
3587 {
3588 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3589
3590 udelay(25000);
3591
3592 return 0;
3593 }
3594
3595 static int si_exit_ulp_state(struct radeon_device *rdev)
3596 {
3597 int i;
3598
3599 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3600
3601 udelay(7000);
3602
3603 for (i = 0; i < rdev->usec_timeout; i++) {
3604 if (RREG32(SMC_RESP_0) == 1)
3605 break;
3606 udelay(1000);
3607 }
3608
3609 return 0;
3610 }
3611 #endif
3612
3613 static int si_notify_smc_display_change(struct radeon_device *rdev,
3614 bool has_display)
3615 {
3616 PPSMC_Msg msg = has_display ?
3617 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3618
3619 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3620 0 : -EINVAL;
3621 }
3622
3623 static void si_program_response_times(struct radeon_device *rdev)
3624 {
3625 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3626 u32 vddc_dly, acpi_dly, vbi_dly;
3627 u32 reference_clock;
3628
3629 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3630
3631 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3632 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3633
3634 if (voltage_response_time == 0)
3635 voltage_response_time = 1000;
3636
3637 acpi_delay_time = 15000;
3638 vbi_time_out = 100000;
3639
3640 reference_clock = radeon_get_xclk(rdev);
3641
3642 vddc_dly = (voltage_response_time * reference_clock) / 100;
3643 acpi_dly = (acpi_delay_time * reference_clock) / 100;
3644 vbi_dly = (vbi_time_out * reference_clock) / 100;
3645
3646 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3647 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3648 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3649 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3650 }
3651
3652 static void si_program_ds_registers(struct radeon_device *rdev)
3653 {
3654 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3655 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3656
3657 if (eg_pi->sclk_deep_sleep) {
3658 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3659 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3660 ~AUTOSCALE_ON_SS_CLEAR);
3661 }
3662 }
3663
3664 static void si_program_display_gap(struct radeon_device *rdev)
3665 {
3666 u32 tmp, pipe;
3667 int i;
3668
3669 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3670 if (rdev->pm.dpm.new_active_crtc_count > 0)
3671 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3672 else
3673 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3674
3675 if (rdev->pm.dpm.new_active_crtc_count > 1)
3676 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3677 else
3678 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3679
3680 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3681
3682 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3683 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3684
3685 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3686 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3687 /* find the first active crtc */
3688 for (i = 0; i < rdev->num_crtc; i++) {
3689 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3690 break;
3691 }
3692 if (i == rdev->num_crtc)
3693 pipe = 0;
3694 else
3695 pipe = i;
3696
3697 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3698 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3699 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3700 }
3701
3702 /* Setting this to false forces the performance state to low if the crtcs are disabled.
3703 * This can be a problem on PowerXpress systems or if you want to use the card
3704 * for offscreen rendering or compute if there are no crtcs enabled.
3705 */
3706 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3707 }
3708
3709 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3710 {
3711 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3712
3713 if (enable) {
3714 if (pi->sclk_ss)
3715 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3716 } else {
3717 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3718 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3719 }
3720 }
3721
3722 static void si_setup_bsp(struct radeon_device *rdev)
3723 {
3724 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3725 u32 xclk = radeon_get_xclk(rdev);
3726
3727 r600_calculate_u_and_p(pi->asi,
3728 xclk,
3729 16,
3730 &pi->bsp,
3731 &pi->bsu);
3732
3733 r600_calculate_u_and_p(pi->pasi,
3734 xclk,
3735 16,
3736 &pi->pbsp,
3737 &pi->pbsu);
3738
3739
3740 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3741 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3742
3743 WREG32(CG_BSP, pi->dsp);
3744 }
3745
3746 static void si_program_git(struct radeon_device *rdev)
3747 {
3748 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3749 }
3750
3751 static void si_program_tp(struct radeon_device *rdev)
3752 {
3753 int i;
3754 enum r600_td td = R600_TD_DFLT;
3755
3756 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3757 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3758
3759 if (td == R600_TD_AUTO)
3760 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3761 else
3762 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3763
3764 if (td == R600_TD_UP)
3765 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3766
3767 if (td == R600_TD_DOWN)
3768 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3769 }
3770
3771 static void si_program_tpp(struct radeon_device *rdev)
3772 {
3773 WREG32(CG_TPC, R600_TPC_DFLT);
3774 }
3775
3776 static void si_program_sstp(struct radeon_device *rdev)
3777 {
3778 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3779 }
3780
3781 static void si_enable_display_gap(struct radeon_device *rdev)
3782 {
3783 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3784
3785 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3786 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3787 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3788
3789 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3790 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3791 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3792 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3793 }
3794
3795 static void si_program_vc(struct radeon_device *rdev)
3796 {
3797 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3798
3799 WREG32(CG_FTV, pi->vrc);
3800 }
3801
3802 static void si_clear_vc(struct radeon_device *rdev)
3803 {
3804 WREG32(CG_FTV, 0);
3805 }
3806
3807 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3808 {
3809 u8 mc_para_index;
3810
3811 if (memory_clock < 10000)
3812 mc_para_index = 0;
3813 else if (memory_clock >= 80000)
3814 mc_para_index = 0x0f;
3815 else
3816 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3817 return mc_para_index;
3818 }
3819
3820 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3821 {
3822 u8 mc_para_index;
3823
3824 if (strobe_mode) {
3825 if (memory_clock < 12500)
3826 mc_para_index = 0x00;
3827 else if (memory_clock > 47500)
3828 mc_para_index = 0x0f;
3829 else
3830 mc_para_index = (u8)((memory_clock - 10000) / 2500);
3831 } else {
3832 if (memory_clock < 65000)
3833 mc_para_index = 0x00;
3834 else if (memory_clock > 135000)
3835 mc_para_index = 0x0f;
3836 else
3837 mc_para_index = (u8)((memory_clock - 60000) / 5000);
3838 }
3839 return mc_para_index;
3840 }
3841
3842 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3843 {
3844 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3845 bool strobe_mode = false;
3846 u8 result = 0;
3847
3848 if (mclk <= pi->mclk_strobe_mode_threshold)
3849 strobe_mode = true;
3850
3851 if (pi->mem_gddr5)
3852 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3853 else
3854 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3855
3856 if (strobe_mode)
3857 result |= SISLANDS_SMC_STROBE_ENABLE;
3858
3859 return result;
3860 }
3861
3862 static int si_upload_firmware(struct radeon_device *rdev)
3863 {
3864 struct si_power_info *si_pi = si_get_pi(rdev);
3865 int ret;
3866
3867 si_reset_smc(rdev);
3868 si_stop_smc_clock(rdev);
3869
3870 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3871
3872 return ret;
3873 }
3874
3875 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3876 const struct atom_voltage_table *table,
3877 const struct radeon_phase_shedding_limits_table *limits)
3878 {
3879 u32 data, num_bits, num_levels;
3880
3881 if ((table == NULL) || (limits == NULL))
3882 return false;
3883
3884 data = table->mask_low;
3885
3886 num_bits = hweight32(data);
3887
3888 if (num_bits == 0)
3889 return false;
3890
3891 num_levels = (1 << num_bits);
3892
3893 if (table->count != num_levels)
3894 return false;
3895
3896 if (limits->count != (num_levels - 1))
3897 return false;
3898
3899 return true;
3900 }
3901
3902 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3903 u32 max_voltage_steps,
3904 struct atom_voltage_table *voltage_table)
3905 {
3906 unsigned int i, diff;
3907
3908 if (voltage_table->count <= max_voltage_steps)
3909 return;
3910
3911 diff = voltage_table->count - max_voltage_steps;
3912
3913 for (i= 0; i < max_voltage_steps; i++)
3914 voltage_table->entries[i] = voltage_table->entries[i + diff];
3915
3916 voltage_table->count = max_voltage_steps;
3917 }
3918
3919 static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3920 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3921 struct atom_voltage_table *voltage_table)
3922 {
3923 u32 i;
3924
3925 if (voltage_dependency_table == NULL)
3926 return -EINVAL;
3927
3928 voltage_table->mask_low = 0;
3929 voltage_table->phase_delay = 0;
3930
3931 voltage_table->count = voltage_dependency_table->count;
3932 for (i = 0; i < voltage_table->count; i++) {
3933 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
3934 voltage_table->entries[i].smio_low = 0;
3935 }
3936
3937 return 0;
3938 }
3939
3940 static int si_construct_voltage_tables(struct radeon_device *rdev)
3941 {
3942 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3943 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3944 struct si_power_info *si_pi = si_get_pi(rdev);
3945 int ret;
3946
3947 if (pi->voltage_control) {
3948 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3949 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3950 if (ret)
3951 return ret;
3952
3953 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3954 si_trim_voltage_table_to_fit_state_table(rdev,
3955 SISLANDS_MAX_NO_VREG_STEPS,
3956 &eg_pi->vddc_voltage_table);
3957 } else if (si_pi->voltage_control_svi2) {
3958 ret = si_get_svi2_voltage_table(rdev,
3959 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3960 &eg_pi->vddc_voltage_table);
3961 if (ret)
3962 return ret;
3963 } else {
3964 return -EINVAL;
3965 }
3966
3967 if (eg_pi->vddci_control) {
3968 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3969 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3970 if (ret)
3971 return ret;
3972
3973 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3974 si_trim_voltage_table_to_fit_state_table(rdev,
3975 SISLANDS_MAX_NO_VREG_STEPS,
3976 &eg_pi->vddci_voltage_table);
3977 }
3978 if (si_pi->vddci_control_svi2) {
3979 ret = si_get_svi2_voltage_table(rdev,
3980 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3981 &eg_pi->vddci_voltage_table);
3982 if (ret)
3983 return ret;
3984 }
3985
3986 if (pi->mvdd_control) {
3987 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3988 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3989
3990 if (ret) {
3991 pi->mvdd_control = false;
3992 return ret;
3993 }
3994
3995 if (si_pi->mvdd_voltage_table.count == 0) {
3996 pi->mvdd_control = false;
3997 return -EINVAL;
3998 }
3999
4000 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4001 si_trim_voltage_table_to_fit_state_table(rdev,
4002 SISLANDS_MAX_NO_VREG_STEPS,
4003 &si_pi->mvdd_voltage_table);
4004 }
4005
4006 if (si_pi->vddc_phase_shed_control) {
4007 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4008 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4009 if (ret)
4010 si_pi->vddc_phase_shed_control = false;
4011
4012 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4013 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4014 si_pi->vddc_phase_shed_control = false;
4015 }
4016
4017 return 0;
4018 }
4019
4020 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4021 const struct atom_voltage_table *voltage_table,
4022 SISLANDS_SMC_STATETABLE *table)
4023 {
4024 unsigned int i;
4025
4026 for (i = 0; i < voltage_table->count; i++)
4027 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4028 }
4029
4030 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4031 SISLANDS_SMC_STATETABLE *table)
4032 {
4033 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4034 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4035 struct si_power_info *si_pi = si_get_pi(rdev);
4036 u8 i;
4037
4038 if (si_pi->voltage_control_svi2) {
4039 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4040 si_pi->svc_gpio_id);
4041 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4042 si_pi->svd_gpio_id);
4043 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4044 2);
4045 } else {
4046 if (eg_pi->vddc_voltage_table.count) {
4047 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4048 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4049 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4050
4051 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4052 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4053 table->maxVDDCIndexInPPTable = i;
4054 break;
4055 }
4056 }
4057 }
4058
4059 if (eg_pi->vddci_voltage_table.count) {
4060 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4061
4062 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4063 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4064 }
4065
4066
4067 if (si_pi->mvdd_voltage_table.count) {
4068 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4069
4070 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4071 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4072 }
4073
4074 if (si_pi->vddc_phase_shed_control) {
4075 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4076 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4077 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4078
4079 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4080 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4081
4082 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4083 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4084 } else {
4085 si_pi->vddc_phase_shed_control = false;
4086 }
4087 }
4088 }
4089
4090 return 0;
4091 }
4092
4093 static int si_populate_voltage_value(struct radeon_device *rdev,
4094 const struct atom_voltage_table *table,
4095 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4096 {
4097 unsigned int i;
4098
4099 for (i = 0; i < table->count; i++) {
4100 if (value <= table->entries[i].value) {
4101 voltage->index = (u8)i;
4102 voltage->value = cpu_to_be16(table->entries[i].value);
4103 break;
4104 }
4105 }
4106
4107 if (i >= table->count)
4108 return -EINVAL;
4109
4110 return 0;
4111 }
4112
4113 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4114 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4115 {
4116 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4117 struct si_power_info *si_pi = si_get_pi(rdev);
4118
4119 if (pi->mvdd_control) {
4120 if (mclk <= pi->mvdd_split_frequency)
4121 voltage->index = 0;
4122 else
4123 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4124
4125 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4126 }
4127 return 0;
4128 }
4129
4130 static int si_get_std_voltage_value(struct radeon_device *rdev,
4131 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4132 u16 *std_voltage)
4133 {
4134 u16 v_index;
4135 bool voltage_found = false;
4136 *std_voltage = be16_to_cpu(voltage->value);
4137
4138 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4139 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4140 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4141 return -EINVAL;
4142
4143 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4144 if (be16_to_cpu(voltage->value) ==
4145 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4146 voltage_found = true;
4147 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4148 *std_voltage =
4149 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4150 else
4151 *std_voltage =
4152 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4153 break;
4154 }
4155 }
4156
4157 if (!voltage_found) {
4158 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4159 if (be16_to_cpu(voltage->value) <=
4160 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4161 voltage_found = true;
4162 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4163 *std_voltage =
4164 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4165 else
4166 *std_voltage =
4167 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4168 break;
4169 }
4170 }
4171 }
4172 } else {
4173 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4174 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4175 }
4176 }
4177
4178 return 0;
4179 }
4180
4181 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4182 u16 value, u8 index,
4183 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4184 {
4185 voltage->index = index;
4186 voltage->value = cpu_to_be16(value);
4187
4188 return 0;
4189 }
4190
4191 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4192 const struct radeon_phase_shedding_limits_table *limits,
4193 u16 voltage, u32 sclk, u32 mclk,
4194 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4195 {
4196 unsigned int i;
4197
4198 for (i = 0; i < limits->count; i++) {
4199 if ((voltage <= limits->entries[i].voltage) &&
4200 (sclk <= limits->entries[i].sclk) &&
4201 (mclk <= limits->entries[i].mclk))
4202 break;
4203 }
4204
4205 smc_voltage->phase_settings = (u8)i;
4206
4207 return 0;
4208 }
4209
4210 static int si_init_arb_table_index(struct radeon_device *rdev)
4211 {
4212 struct si_power_info *si_pi = si_get_pi(rdev);
4213 u32 tmp;
4214 int ret;
4215
4216 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4217 if (ret)
4218 return ret;
4219
4220 tmp &= 0x00FFFFFF;
4221 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4222
4223 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4224 }
4225
4226 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4227 {
4228 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4229 }
4230
4231 static int si_reset_to_default(struct radeon_device *rdev)
4232 {
4233 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4234 0 : -EINVAL;
4235 }
4236
4237 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4238 {
4239 struct si_power_info *si_pi = si_get_pi(rdev);
4240 u32 tmp;
4241 int ret;
4242
4243 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4244 &tmp, si_pi->sram_end);
4245 if (ret)
4246 return ret;
4247
4248 tmp = (tmp >> 24) & 0xff;
4249
4250 if (tmp == MC_CG_ARB_FREQ_F0)
4251 return 0;
4252
4253 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4254 }
4255
4256 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4257 u32 engine_clock)
4258 {
4259 u32 dram_rows;
4260 u32 dram_refresh_rate;
4261 u32 mc_arb_rfsh_rate;
4262 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4263
4264 if (tmp >= 4)
4265 dram_rows = 16384;
4266 else
4267 dram_rows = 1 << (tmp + 10);
4268
4269 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4270 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4271
4272 return mc_arb_rfsh_rate;
4273 }
4274
4275 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4276 struct rv7xx_pl *pl,
4277 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4278 {
4279 u32 dram_timing;
4280 u32 dram_timing2;
4281 u32 burst_time;
4282
4283 arb_regs->mc_arb_rfsh_rate =
4284 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4285
4286 radeon_atom_set_engine_dram_timings(rdev,
4287 pl->sclk,
4288 pl->mclk);
4289
4290 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4291 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4292 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4293
4294 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4295 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4296 arb_regs->mc_arb_burst_time = (u8)burst_time;
4297
4298 return 0;
4299 }
4300
4301 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4302 struct radeon_ps *radeon_state,
4303 unsigned int first_arb_set)
4304 {
4305 struct si_power_info *si_pi = si_get_pi(rdev);
4306 struct ni_ps *state = ni_get_ps(radeon_state);
4307 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4308 int i, ret = 0;
4309
4310 for (i = 0; i < state->performance_level_count; i++) {
4311 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4312 if (ret)
4313 break;
4314 ret = si_copy_bytes_to_smc(rdev,
4315 si_pi->arb_table_start +
4316 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4317 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4318 (u8 *)&arb_regs,
4319 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4320 si_pi->sram_end);
4321 if (ret)
4322 break;
4323 }
4324
4325 return ret;
4326 }
4327
4328 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4329 struct radeon_ps *radeon_new_state)
4330 {
4331 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4332 SISLANDS_DRIVER_STATE_ARB_INDEX);
4333 }
4334
4335 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4336 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4337 {
4338 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4339 struct si_power_info *si_pi = si_get_pi(rdev);
4340
4341 if (pi->mvdd_control)
4342 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4343 si_pi->mvdd_bootup_value, voltage);
4344
4345 return 0;
4346 }
4347
4348 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4349 struct radeon_ps *radeon_initial_state,
4350 SISLANDS_SMC_STATETABLE *table)
4351 {
4352 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4353 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4354 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4355 struct si_power_info *si_pi = si_get_pi(rdev);
4356 u32 reg;
4357 int ret;
4358
4359 table->initialState.levels[0].mclk.vDLL_CNTL =
4360 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4361 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4362 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4363 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4364 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4365 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4366 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4367 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4368 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4369 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4370 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4371 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4372 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4373 table->initialState.levels[0].mclk.vMPLL_SS =
4374 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4375 table->initialState.levels[0].mclk.vMPLL_SS2 =
4376 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4377
4378 table->initialState.levels[0].mclk.mclk_value =
4379 cpu_to_be32(initial_state->performance_levels[0].mclk);
4380
4381 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4382 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4383 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4384 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4385 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4386 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4387 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4388 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4389 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4390 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4391 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4392 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4393
4394 table->initialState.levels[0].sclk.sclk_value =
4395 cpu_to_be32(initial_state->performance_levels[0].sclk);
4396
4397 table->initialState.levels[0].arbRefreshState =
4398 SISLANDS_INITIAL_STATE_ARB_INDEX;
4399
4400 table->initialState.levels[0].ACIndex = 0;
4401
4402 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4403 initial_state->performance_levels[0].vddc,
4404 &table->initialState.levels[0].vddc);
4405
4406 if (!ret) {
4407 u16 std_vddc;
4408
4409 ret = si_get_std_voltage_value(rdev,
4410 &table->initialState.levels[0].vddc,
4411 &std_vddc);
4412 if (!ret)
4413 si_populate_std_voltage_value(rdev, std_vddc,
4414 table->initialState.levels[0].vddc.index,
4415 &table->initialState.levels[0].std_vddc);
4416 }
4417
4418 if (eg_pi->vddci_control)
4419 si_populate_voltage_value(rdev,
4420 &eg_pi->vddci_voltage_table,
4421 initial_state->performance_levels[0].vddci,
4422 &table->initialState.levels[0].vddci);
4423
4424 if (si_pi->vddc_phase_shed_control)
4425 si_populate_phase_shedding_value(rdev,
4426 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4427 initial_state->performance_levels[0].vddc,
4428 initial_state->performance_levels[0].sclk,
4429 initial_state->performance_levels[0].mclk,
4430 &table->initialState.levels[0].vddc);
4431
4432 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4433
4434 reg = CG_R(0xffff) | CG_L(0);
4435 table->initialState.levels[0].aT = cpu_to_be32(reg);
4436
4437 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4438
4439 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4440
4441 if (pi->mem_gddr5) {
4442 table->initialState.levels[0].strobeMode =
4443 si_get_strobe_mode_settings(rdev,
4444 initial_state->performance_levels[0].mclk);
4445
4446 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4447 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4448 else
4449 table->initialState.levels[0].mcFlags = 0;
4450 }
4451
4452 table->initialState.levelCount = 1;
4453
4454 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4455
4456 table->initialState.levels[0].dpm2.MaxPS = 0;
4457 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4458 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4459 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4460 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4461
4462 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4463 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4464
4465 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4466 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4467
4468 return 0;
4469 }
4470
4471 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4472 SISLANDS_SMC_STATETABLE *table)
4473 {
4474 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4475 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4476 struct si_power_info *si_pi = si_get_pi(rdev);
4477 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4478 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4479 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4480 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4481 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4482 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4483 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4484 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4485 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4486 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4487 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4488 u32 reg;
4489 int ret;
4490
4491 table->ACPIState = table->initialState;
4492
4493 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4494
4495 if (pi->acpi_vddc) {
4496 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4497 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4498 if (!ret) {
4499 u16 std_vddc;
4500
4501 ret = si_get_std_voltage_value(rdev,
4502 &table->ACPIState.levels[0].vddc, &std_vddc);
4503 if (!ret)
4504 si_populate_std_voltage_value(rdev, std_vddc,
4505 table->ACPIState.levels[0].vddc.index,
4506 &table->ACPIState.levels[0].std_vddc);
4507 }
4508 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4509
4510 if (si_pi->vddc_phase_shed_control) {
4511 si_populate_phase_shedding_value(rdev,
4512 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4513 pi->acpi_vddc,
4514 0,
4515 0,
4516 &table->ACPIState.levels[0].vddc);
4517 }
4518 } else {
4519 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4520 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4521 if (!ret) {
4522 u16 std_vddc;
4523
4524 ret = si_get_std_voltage_value(rdev,
4525 &table->ACPIState.levels[0].vddc, &std_vddc);
4526
4527 if (!ret)
4528 si_populate_std_voltage_value(rdev, std_vddc,
4529 table->ACPIState.levels[0].vddc.index,
4530 &table->ACPIState.levels[0].std_vddc);
4531 }
4532 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4533 si_pi->sys_pcie_mask,
4534 si_pi->boot_pcie_gen,
4535 RADEON_PCIE_GEN1);
4536
4537 if (si_pi->vddc_phase_shed_control)
4538 si_populate_phase_shedding_value(rdev,
4539 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4540 pi->min_vddc_in_table,
4541 0,
4542 0,
4543 &table->ACPIState.levels[0].vddc);
4544 }
4545
4546 if (pi->acpi_vddc) {
4547 if (eg_pi->acpi_vddci)
4548 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4549 eg_pi->acpi_vddci,
4550 &table->ACPIState.levels[0].vddci);
4551 }
4552
4553 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4554 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4555
4556 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4557
4558 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4559 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4560
4561 table->ACPIState.levels[0].mclk.vDLL_CNTL =
4562 cpu_to_be32(dll_cntl);
4563 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4564 cpu_to_be32(mclk_pwrmgt_cntl);
4565 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4566 cpu_to_be32(mpll_ad_func_cntl);
4567 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4568 cpu_to_be32(mpll_dq_func_cntl);
4569 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4570 cpu_to_be32(mpll_func_cntl);
4571 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4572 cpu_to_be32(mpll_func_cntl_1);
4573 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4574 cpu_to_be32(mpll_func_cntl_2);
4575 table->ACPIState.levels[0].mclk.vMPLL_SS =
4576 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4577 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4578 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4579
4580 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4581 cpu_to_be32(spll_func_cntl);
4582 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4583 cpu_to_be32(spll_func_cntl_2);
4584 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4585 cpu_to_be32(spll_func_cntl_3);
4586 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4587 cpu_to_be32(spll_func_cntl_4);
4588
4589 table->ACPIState.levels[0].mclk.mclk_value = 0;
4590 table->ACPIState.levels[0].sclk.sclk_value = 0;
4591
4592 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4593
4594 if (eg_pi->dynamic_ac_timing)
4595 table->ACPIState.levels[0].ACIndex = 0;
4596
4597 table->ACPIState.levels[0].dpm2.MaxPS = 0;
4598 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4599 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4600 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4601 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4602
4603 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4604 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4605
4606 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4607 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4608
4609 return 0;
4610 }
4611
4612 static int si_populate_ulv_state(struct radeon_device *rdev,
4613 SISLANDS_SMC_SWSTATE *state)
4614 {
4615 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4616 struct si_power_info *si_pi = si_get_pi(rdev);
4617 struct si_ulv_param *ulv = &si_pi->ulv;
4618 u32 sclk_in_sr = 1350; /* ??? */
4619 int ret;
4620
4621 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4622 &state->levels[0]);
4623 if (!ret) {
4624 if (eg_pi->sclk_deep_sleep) {
4625 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4626 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4627 else
4628 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4629 }
4630 if (ulv->one_pcie_lane_in_ulv)
4631 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4632 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4633 state->levels[0].ACIndex = 1;
4634 state->levels[0].std_vddc = state->levels[0].vddc;
4635 state->levelCount = 1;
4636
4637 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4638 }
4639
4640 return ret;
4641 }
4642
4643 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4644 {
4645 struct si_power_info *si_pi = si_get_pi(rdev);
4646 struct si_ulv_param *ulv = &si_pi->ulv;
4647 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4648 int ret;
4649
4650 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4651 &arb_regs);
4652 if (ret)
4653 return ret;
4654
4655 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4656 ulv->volt_change_delay);
4657
4658 ret = si_copy_bytes_to_smc(rdev,
4659 si_pi->arb_table_start +
4660 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4661 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4662 (u8 *)&arb_regs,
4663 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4664 si_pi->sram_end);
4665
4666 return ret;
4667 }
4668
4669 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4670 {
4671 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4672
4673 pi->mvdd_split_frequency = 30000;
4674 }
4675
4676 static int si_init_smc_table(struct radeon_device *rdev)
4677 {
4678 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4679 struct si_power_info *si_pi = si_get_pi(rdev);
4680 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4681 const struct si_ulv_param *ulv = &si_pi->ulv;
4682 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
4683 int ret;
4684 u32 lane_width;
4685 u32 vr_hot_gpio;
4686
4687 si_populate_smc_voltage_tables(rdev, table);
4688
4689 switch (rdev->pm.int_thermal_type) {
4690 case THERMAL_TYPE_SI:
4691 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4692 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4693 break;
4694 case THERMAL_TYPE_NONE:
4695 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4696 break;
4697 default:
4698 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4699 break;
4700 }
4701
4702 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4703 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4704
4705 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4706 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4707 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4708 }
4709
4710 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4711 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4712
4713 if (pi->mem_gddr5)
4714 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4715
4716 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4717 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4718
4719 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4720 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4721 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4722 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4723 vr_hot_gpio);
4724 }
4725
4726 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4727 if (ret)
4728 return ret;
4729
4730 ret = si_populate_smc_acpi_state(rdev, table);
4731 if (ret)
4732 return ret;
4733
4734 table->driverState = table->initialState;
4735
4736 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4737 SISLANDS_INITIAL_STATE_ARB_INDEX);
4738 if (ret)
4739 return ret;
4740
4741 if (ulv->supported && ulv->pl.vddc) {
4742 ret = si_populate_ulv_state(rdev, &table->ULVState);
4743 if (ret)
4744 return ret;
4745
4746 ret = si_program_ulv_memory_timing_parameters(rdev);
4747 if (ret)
4748 return ret;
4749
4750 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4751 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4752
4753 lane_width = radeon_get_pcie_lanes(rdev);
4754 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4755 } else {
4756 table->ULVState = table->initialState;
4757 }
4758
4759 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4760 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4761 si_pi->sram_end);
4762 }
4763
4764 static int si_calculate_sclk_params(struct radeon_device *rdev,
4765 u32 engine_clock,
4766 SISLANDS_SMC_SCLK_VALUE *sclk)
4767 {
4768 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4769 struct si_power_info *si_pi = si_get_pi(rdev);
4770 struct atom_clock_dividers dividers;
4771 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4772 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4773 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4774 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4775 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4776 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4777 u64 tmp;
4778 u32 reference_clock = rdev->clock.spll.reference_freq;
4779 u32 reference_divider;
4780 u32 fbdiv;
4781 int ret;
4782
4783 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4784 engine_clock, false, &dividers);
4785 if (ret)
4786 return ret;
4787
4788 reference_divider = 1 + dividers.ref_div;
4789
4790 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4791 do_div(tmp, reference_clock);
4792 fbdiv = (u32) tmp;
4793
4794 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4795 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4796 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4797
4798 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4799 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4800
4801 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4802 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4803 spll_func_cntl_3 |= SPLL_DITHEN;
4804
4805 if (pi->sclk_ss) {
4806 struct radeon_atom_ss ss;
4807 u32 vco_freq = engine_clock * dividers.post_div;
4808
4809 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4810 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4811 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4812 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4813
4814 cg_spll_spread_spectrum &= ~CLK_S_MASK;
4815 cg_spll_spread_spectrum |= CLK_S(clk_s);
4816 cg_spll_spread_spectrum |= SSEN;
4817
4818 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4819 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4820 }
4821 }
4822
4823 sclk->sclk_value = engine_clock;
4824 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4825 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4826 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4827 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4828 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4829 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4830
4831 return 0;
4832 }
4833
4834 static int si_populate_sclk_value(struct radeon_device *rdev,
4835 u32 engine_clock,
4836 SISLANDS_SMC_SCLK_VALUE *sclk)
4837 {
4838 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4839 int ret;
4840
4841 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4842 if (!ret) {
4843 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4844 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4845 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4846 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4847 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4848 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4849 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4850 }
4851
4852 return ret;
4853 }
4854
4855 static int si_populate_mclk_value(struct radeon_device *rdev,
4856 u32 engine_clock,
4857 u32 memory_clock,
4858 SISLANDS_SMC_MCLK_VALUE *mclk,
4859 bool strobe_mode,
4860 bool dll_state_on)
4861 {
4862 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4863 struct si_power_info *si_pi = si_get_pi(rdev);
4864 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4865 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4866 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4867 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4868 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4869 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4870 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4871 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4872 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4873 struct atom_mpll_param mpll_param;
4874 int ret;
4875
4876 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4877 if (ret)
4878 return ret;
4879
4880 mpll_func_cntl &= ~BWCTRL_MASK;
4881 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4882
4883 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4884 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4885 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4886
4887 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4888 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4889
4890 if (pi->mem_gddr5) {
4891 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4892 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4893 YCLK_POST_DIV(mpll_param.post_div);
4894 }
4895
4896 if (pi->mclk_ss) {
4897 struct radeon_atom_ss ss;
4898 u32 freq_nom;
4899 u32 tmp;
4900 u32 reference_clock = rdev->clock.mpll.reference_freq;
4901
4902 if (pi->mem_gddr5)
4903 freq_nom = memory_clock * 4;
4904 else
4905 freq_nom = memory_clock * 2;
4906
4907 tmp = freq_nom / reference_clock;
4908 tmp = tmp * tmp;
4909 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4910 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4911 u32 clks = reference_clock * 5 / ss.rate;
4912 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4913
4914 mpll_ss1 &= ~CLKV_MASK;
4915 mpll_ss1 |= CLKV(clkv);
4916
4917 mpll_ss2 &= ~CLKS_MASK;
4918 mpll_ss2 |= CLKS(clks);
4919 }
4920 }
4921
4922 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4923 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4924
4925 if (dll_state_on)
4926 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4927 else
4928 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4929
4930 mclk->mclk_value = cpu_to_be32(memory_clock);
4931 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4932 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4933 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4934 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4935 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4936 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4937 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4938 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4939 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4940
4941 return 0;
4942 }
4943
4944 static void si_populate_smc_sp(struct radeon_device *rdev,
4945 struct radeon_ps *radeon_state,
4946 SISLANDS_SMC_SWSTATE *smc_state)
4947 {
4948 struct ni_ps *ps = ni_get_ps(radeon_state);
4949 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4950 int i;
4951
4952 for (i = 0; i < ps->performance_level_count - 1; i++)
4953 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4954
4955 smc_state->levels[ps->performance_level_count - 1].bSP =
4956 cpu_to_be32(pi->psp);
4957 }
4958
4959 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4960 struct rv7xx_pl *pl,
4961 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4962 {
4963 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4964 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4965 struct si_power_info *si_pi = si_get_pi(rdev);
4966 int ret;
4967 bool dll_state_on;
4968 u16 std_vddc;
4969 bool gmc_pg = false;
4970
4971 if (eg_pi->pcie_performance_request &&
4972 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4973 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4974 else
4975 level->gen2PCIE = (u8)pl->pcie_gen;
4976
4977 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4978 if (ret)
4979 return ret;
4980
4981 level->mcFlags = 0;
4982
4983 if (pi->mclk_stutter_mode_threshold &&
4984 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4985 !eg_pi->uvd_enabled &&
4986 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4987 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4988 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4989
4990 if (gmc_pg)
4991 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4992 }
4993
4994 if (pi->mem_gddr5) {
4995 if (pl->mclk > pi->mclk_edc_enable_threshold)
4996 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4997
4998 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4999 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5000
5001 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5002
5003 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5004 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5005 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5006 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5007 else
5008 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5009 } else {
5010 dll_state_on = false;
5011 }
5012 } else {
5013 level->strobeMode = si_get_strobe_mode_settings(rdev,
5014 pl->mclk);
5015
5016 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5017 }
5018
5019 ret = si_populate_mclk_value(rdev,
5020 pl->sclk,
5021 pl->mclk,
5022 &level->mclk,
5023 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5024 if (ret)
5025 return ret;
5026
5027 ret = si_populate_voltage_value(rdev,
5028 &eg_pi->vddc_voltage_table,
5029 pl->vddc, &level->vddc);
5030 if (ret)
5031 return ret;
5032
5033
5034 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5035 if (ret)
5036 return ret;
5037
5038 ret = si_populate_std_voltage_value(rdev, std_vddc,
5039 level->vddc.index, &level->std_vddc);
5040 if (ret)
5041 return ret;
5042
5043 if (eg_pi->vddci_control) {
5044 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5045 pl->vddci, &level->vddci);
5046 if (ret)
5047 return ret;
5048 }
5049
5050 if (si_pi->vddc_phase_shed_control) {
5051 ret = si_populate_phase_shedding_value(rdev,
5052 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5053 pl->vddc,
5054 pl->sclk,
5055 pl->mclk,
5056 &level->vddc);
5057 if (ret)
5058 return ret;
5059 }
5060
5061 level->MaxPoweredUpCU = si_pi->max_cu;
5062
5063 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5064
5065 return ret;
5066 }
5067
5068 static int si_populate_smc_t(struct radeon_device *rdev,
5069 struct radeon_ps *radeon_state,
5070 SISLANDS_SMC_SWSTATE *smc_state)
5071 {
5072 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5073 struct ni_ps *state = ni_get_ps(radeon_state);
5074 u32 a_t;
5075 u32 t_l, t_h;
5076 u32 high_bsp;
5077 int i, ret;
5078
5079 if (state->performance_level_count >= 9)
5080 return -EINVAL;
5081
5082 if (state->performance_level_count < 2) {
5083 a_t = CG_R(0xffff) | CG_L(0);
5084 smc_state->levels[0].aT = cpu_to_be32(a_t);
5085 return 0;
5086 }
5087
5088 smc_state->levels[0].aT = cpu_to_be32(0);
5089
5090 for (i = 0; i <= state->performance_level_count - 2; i++) {
5091 ret = r600_calculate_at(
5092 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5093 100 * R600_AH_DFLT,
5094 state->performance_levels[i + 1].sclk,
5095 state->performance_levels[i].sclk,
5096 &t_l,
5097 &t_h);
5098
5099 if (ret) {
5100 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5101 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5102 }
5103
5104 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5105 a_t |= CG_R(t_l * pi->bsp / 20000);
5106 smc_state->levels[i].aT = cpu_to_be32(a_t);
5107
5108 high_bsp = (i == state->performance_level_count - 2) ?
5109 pi->pbsp : pi->bsp;
5110 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5111 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5112 }
5113
5114 return 0;
5115 }
5116
5117 static int si_disable_ulv(struct radeon_device *rdev)
5118 {
5119 struct si_power_info *si_pi = si_get_pi(rdev);
5120 struct si_ulv_param *ulv = &si_pi->ulv;
5121
5122 if (ulv->supported)
5123 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5124 0 : -EINVAL;
5125
5126 return 0;
5127 }
5128
5129 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5130 struct radeon_ps *radeon_state)
5131 {
5132 const struct si_power_info *si_pi = si_get_pi(rdev);
5133 const struct si_ulv_param *ulv = &si_pi->ulv;
5134 const struct ni_ps *state = ni_get_ps(radeon_state);
5135 int i;
5136
5137 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5138 return false;
5139
5140 /* XXX validate against display requirements! */
5141
5142 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5143 if (rdev->clock.current_dispclk <=
5144 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5145 if (ulv->pl.vddc <
5146 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5147 return false;
5148 }
5149 }
5150
5151 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5152 return false;
5153
5154 return true;
5155 }
5156
5157 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5158 struct radeon_ps *radeon_new_state)
5159 {
5160 const struct si_power_info *si_pi = si_get_pi(rdev);
5161 const struct si_ulv_param *ulv = &si_pi->ulv;
5162
5163 if (ulv->supported) {
5164 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5165 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5166 0 : -EINVAL;
5167 }
5168 return 0;
5169 }
5170
5171 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5172 struct radeon_ps *radeon_state,
5173 SISLANDS_SMC_SWSTATE *smc_state)
5174 {
5175 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5176 struct ni_power_info *ni_pi = ni_get_pi(rdev);
5177 struct si_power_info *si_pi = si_get_pi(rdev);
5178 struct ni_ps *state = ni_get_ps(radeon_state);
5179 int i, ret;
5180 u32 threshold;
5181 u32 sclk_in_sr = 1350; /* ??? */
5182
5183 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5184 return -EINVAL;
5185
5186 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5187
5188 if (radeon_state->vclk && radeon_state->dclk) {
5189 eg_pi->uvd_enabled = true;
5190 if (eg_pi->smu_uvd_hs)
5191 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5192 } else {
5193 eg_pi->uvd_enabled = false;
5194 }
5195
5196 if (state->dc_compatible)
5197 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5198
5199 smc_state->levelCount = 0;
5200 for (i = 0; i < state->performance_level_count; i++) {
5201 if (eg_pi->sclk_deep_sleep) {
5202 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5203 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5204 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5205 else
5206 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5207 }
5208 }
5209
5210 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5211 &smc_state->levels[i]);
5212 smc_state->levels[i].arbRefreshState =
5213 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5214
5215 if (ret)
5216 return ret;
5217
5218 if (ni_pi->enable_power_containment)
5219 smc_state->levels[i].displayWatermark =
5220 (state->performance_levels[i].sclk < threshold) ?
5221 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5222 else
5223 smc_state->levels[i].displayWatermark = (i < 2) ?
5224 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5225
5226 if (eg_pi->dynamic_ac_timing)
5227 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5228 else
5229 smc_state->levels[i].ACIndex = 0;
5230
5231 smc_state->levelCount++;
5232 }
5233
5234 si_write_smc_soft_register(rdev,
5235 SI_SMC_SOFT_REGISTER_watermark_threshold,
5236 threshold / 512);
5237
5238 si_populate_smc_sp(rdev, radeon_state, smc_state);
5239
5240 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5241 if (ret)
5242 ni_pi->enable_power_containment = false;
5243
5244 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5245 if (ret)
5246 ni_pi->enable_sq_ramping = false;
5247
5248 return si_populate_smc_t(rdev, radeon_state, smc_state);
5249 }
5250
5251 static int si_upload_sw_state(struct radeon_device *rdev,
5252 struct radeon_ps *radeon_new_state)
5253 {
5254 struct si_power_info *si_pi = si_get_pi(rdev);
5255 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5256 int ret;
5257 u32 address = si_pi->state_table_start +
5258 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5259 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5260 ((new_state->performance_level_count - 1) *
5261 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5262 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5263
5264 memset(smc_state, 0, state_size);
5265
5266 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5267 if (ret)
5268 return ret;
5269
5270 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5271 state_size, si_pi->sram_end);
5272
5273 return ret;
5274 }
5275
5276 static int si_upload_ulv_state(struct radeon_device *rdev)
5277 {
5278 struct si_power_info *si_pi = si_get_pi(rdev);
5279 struct si_ulv_param *ulv = &si_pi->ulv;
5280 int ret = 0;
5281
5282 if (ulv->supported && ulv->pl.vddc) {
5283 u32 address = si_pi->state_table_start +
5284 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5285 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5286 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5287
5288 memset(smc_state, 0, state_size);
5289
5290 ret = si_populate_ulv_state(rdev, smc_state);
5291 if (!ret)
5292 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5293 state_size, si_pi->sram_end);
5294 }
5295
5296 return ret;
5297 }
5298
5299 static int si_upload_smc_data(struct radeon_device *rdev)
5300 {
5301 struct radeon_crtc *radeon_crtc = NULL;
5302 int i;
5303
5304 if (rdev->pm.dpm.new_active_crtc_count == 0)
5305 return 0;
5306
5307 for (i = 0; i < rdev->num_crtc; i++) {
5308 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5309 radeon_crtc = rdev->mode_info.crtcs[i];
5310 break;
5311 }
5312 }
5313
5314 if (radeon_crtc == NULL)
5315 return 0;
5316
5317 if (radeon_crtc->line_time <= 0)
5318 return 0;
5319
5320 if (si_write_smc_soft_register(rdev,
5321 SI_SMC_SOFT_REGISTER_crtc_index,
5322 radeon_crtc->crtc_id) != PPSMC_Result_OK)
5323 return 0;
5324
5325 if (si_write_smc_soft_register(rdev,
5326 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5327 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5328 return 0;
5329
5330 if (si_write_smc_soft_register(rdev,
5331 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5332 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5333 return 0;
5334
5335 return 0;
5336 }
5337
5338 static int si_set_mc_special_registers(struct radeon_device *rdev,
5339 struct si_mc_reg_table *table)
5340 {
5341 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5342 u8 i, j, k;
5343 u32 temp_reg;
5344
5345 for (i = 0, j = table->last; i < table->last; i++) {
5346 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5347 return -EINVAL;
5348 switch (table->mc_reg_address[i].s1 << 2) {
5349 case MC_SEQ_MISC1:
5350 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5351 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5352 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5353 for (k = 0; k < table->num_entries; k++)
5354 table->mc_reg_table_entry[k].mc_data[j] =
5355 ((temp_reg & 0xffff0000)) |
5356 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5357 j++;
5358 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5359 return -EINVAL;
5360
5361 temp_reg = RREG32(MC_PMG_CMD_MRS);
5362 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5363 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5364 for (k = 0; k < table->num_entries; k++) {
5365 table->mc_reg_table_entry[k].mc_data[j] =
5366 (temp_reg & 0xffff0000) |
5367 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5368 if (!pi->mem_gddr5)
5369 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5370 }
5371 j++;
5372 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5373 return -EINVAL;
5374
5375 if (!pi->mem_gddr5) {
5376 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5377 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5378 for (k = 0; k < table->num_entries; k++)
5379 table->mc_reg_table_entry[k].mc_data[j] =
5380 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5381 j++;
5382 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5383 return -EINVAL;
5384 }
5385 break;
5386 case MC_SEQ_RESERVE_M:
5387 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5388 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5389 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5390 for(k = 0; k < table->num_entries; k++)
5391 table->mc_reg_table_entry[k].mc_data[j] =
5392 (temp_reg & 0xffff0000) |
5393 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5394 j++;
5395 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5396 return -EINVAL;
5397 break;
5398 default:
5399 break;
5400 }
5401 }
5402
5403 table->last = j;
5404
5405 return 0;
5406 }
5407
5408 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5409 {
5410 bool result = true;
5411
5412 switch (in_reg) {
5413 case MC_SEQ_RAS_TIMING >> 2:
5414 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5415 break;
5416 case MC_SEQ_CAS_TIMING >> 2:
5417 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5418 break;
5419 case MC_SEQ_MISC_TIMING >> 2:
5420 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5421 break;
5422 case MC_SEQ_MISC_TIMING2 >> 2:
5423 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5424 break;
5425 case MC_SEQ_RD_CTL_D0 >> 2:
5426 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5427 break;
5428 case MC_SEQ_RD_CTL_D1 >> 2:
5429 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5430 break;
5431 case MC_SEQ_WR_CTL_D0 >> 2:
5432 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5433 break;
5434 case MC_SEQ_WR_CTL_D1 >> 2:
5435 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5436 break;
5437 case MC_PMG_CMD_EMRS >> 2:
5438 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5439 break;
5440 case MC_PMG_CMD_MRS >> 2:
5441 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5442 break;
5443 case MC_PMG_CMD_MRS1 >> 2:
5444 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5445 break;
5446 case MC_SEQ_PMG_TIMING >> 2:
5447 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5448 break;
5449 case MC_PMG_CMD_MRS2 >> 2:
5450 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5451 break;
5452 case MC_SEQ_WR_CTL_2 >> 2:
5453 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5454 break;
5455 default:
5456 result = false;
5457 break;
5458 }
5459
5460 return result;
5461 }
5462
5463 static void si_set_valid_flag(struct si_mc_reg_table *table)
5464 {
5465 u8 i, j;
5466
5467 for (i = 0; i < table->last; i++) {
5468 for (j = 1; j < table->num_entries; j++) {
5469 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5470 table->valid_flag |= 1 << i;
5471 break;
5472 }
5473 }
5474 }
5475 }
5476
5477 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5478 {
5479 u32 i;
5480 u16 address;
5481
5482 for (i = 0; i < table->last; i++)
5483 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5484 address : table->mc_reg_address[i].s1;
5485
5486 }
5487
5488 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5489 struct si_mc_reg_table *si_table)
5490 {
5491 u8 i, j;
5492
5493 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5494 return -EINVAL;
5495 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5496 return -EINVAL;
5497
5498 for (i = 0; i < table->last; i++)
5499 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5500 si_table->last = table->last;
5501
5502 for (i = 0; i < table->num_entries; i++) {
5503 si_table->mc_reg_table_entry[i].mclk_max =
5504 table->mc_reg_table_entry[i].mclk_max;
5505 for (j = 0; j < table->last; j++) {
5506 si_table->mc_reg_table_entry[i].mc_data[j] =
5507 table->mc_reg_table_entry[i].mc_data[j];
5508 }
5509 }
5510 si_table->num_entries = table->num_entries;
5511
5512 return 0;
5513 }
5514
5515 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5516 {
5517 struct si_power_info *si_pi = si_get_pi(rdev);
5518 struct atom_mc_reg_table *table;
5519 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5520 u8 module_index = rv770_get_memory_module_index(rdev);
5521 int ret;
5522
5523 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5524 if (!table)
5525 return -ENOMEM;
5526
5527 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5528 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5529 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5530 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5531 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5532 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5533 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5534 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5535 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5536 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5537 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5538 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5539 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5540 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5541
5542 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5543 if (ret)
5544 goto init_mc_done;
5545
5546 ret = si_copy_vbios_mc_reg_table(table, si_table);
5547 if (ret)
5548 goto init_mc_done;
5549
5550 si_set_s0_mc_reg_index(si_table);
5551
5552 ret = si_set_mc_special_registers(rdev, si_table);
5553 if (ret)
5554 goto init_mc_done;
5555
5556 si_set_valid_flag(si_table);
5557
5558 init_mc_done:
5559 kfree(table);
5560
5561 return ret;
5562
5563 }
5564
5565 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5566 SMC_SIslands_MCRegisters *mc_reg_table)
5567 {
5568 struct si_power_info *si_pi = si_get_pi(rdev);
5569 u32 i, j;
5570
5571 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5572 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5573 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5574 break;
5575 mc_reg_table->address[i].s0 =
5576 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5577 mc_reg_table->address[i].s1 =
5578 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5579 i++;
5580 }
5581 }
5582 mc_reg_table->last = (u8)i;
5583 }
5584
5585 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5586 SMC_SIslands_MCRegisterSet *data,
5587 u32 num_entries, u32 valid_flag)
5588 {
5589 u32 i, j;
5590
5591 for(i = 0, j = 0; j < num_entries; j++) {
5592 if (valid_flag & (1 << j)) {
5593 data->value[i] = cpu_to_be32(entry->mc_data[j]);
5594 i++;
5595 }
5596 }
5597 }
5598
5599 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5600 struct rv7xx_pl *pl,
5601 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5602 {
5603 struct si_power_info *si_pi = si_get_pi(rdev);
5604 u32 i = 0;
5605
5606 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5607 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5608 break;
5609 }
5610
5611 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5612 --i;
5613
5614 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5615 mc_reg_table_data, si_pi->mc_reg_table.last,
5616 si_pi->mc_reg_table.valid_flag);
5617 }
5618
5619 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5620 struct radeon_ps *radeon_state,
5621 SMC_SIslands_MCRegisters *mc_reg_table)
5622 {
5623 struct ni_ps *state = ni_get_ps(radeon_state);
5624 int i;
5625
5626 for (i = 0; i < state->performance_level_count; i++) {
5627 si_convert_mc_reg_table_entry_to_smc(rdev,
5628 &state->performance_levels[i],
5629 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5630 }
5631 }
5632
5633 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5634 struct radeon_ps *radeon_boot_state)
5635 {
5636 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5637 struct si_power_info *si_pi = si_get_pi(rdev);
5638 struct si_ulv_param *ulv = &si_pi->ulv;
5639 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5640
5641 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5642
5643 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5644
5645 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5646
5647 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5648 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5649
5650 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5651 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5652 si_pi->mc_reg_table.last,
5653 si_pi->mc_reg_table.valid_flag);
5654
5655 if (ulv->supported && ulv->pl.vddc != 0)
5656 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5657 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5658 else
5659 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5660 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5661 si_pi->mc_reg_table.last,
5662 si_pi->mc_reg_table.valid_flag);
5663
5664 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5665
5666 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5667 (u8 *)smc_mc_reg_table,
5668 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5669 }
5670
5671 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5672 struct radeon_ps *radeon_new_state)
5673 {
5674 struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5675 struct si_power_info *si_pi = si_get_pi(rdev);
5676 u32 address = si_pi->mc_reg_table_start +
5677 offsetof(SMC_SIslands_MCRegisters,
5678 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5679 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5680
5681 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5682
5683 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5684
5685
5686 return si_copy_bytes_to_smc(rdev, address,
5687 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5688 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5689 si_pi->sram_end);
5690
5691 }
5692
5693 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5694 {
5695 if (enable)
5696 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5697 else
5698 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5699 }
5700
5701 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5702 struct radeon_ps *radeon_state)
5703 {
5704 struct ni_ps *state = ni_get_ps(radeon_state);
5705 int i;
5706 u16 pcie_speed, max_speed = 0;
5707
5708 for (i = 0; i < state->performance_level_count; i++) {
5709 pcie_speed = state->performance_levels[i].pcie_gen;
5710 if (max_speed < pcie_speed)
5711 max_speed = pcie_speed;
5712 }
5713 return max_speed;
5714 }
5715
5716 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5717 {
5718 u32 speed_cntl;
5719
5720 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5721 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5722
5723 return (u16)speed_cntl;
5724 }
5725
5726 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5727 struct radeon_ps *radeon_new_state,
5728 struct radeon_ps *radeon_current_state)
5729 {
5730 struct si_power_info *si_pi = si_get_pi(rdev);
5731 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5732 enum radeon_pcie_gen current_link_speed;
5733
5734 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5735 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5736 else
5737 current_link_speed = si_pi->force_pcie_gen;
5738
5739 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5740 si_pi->pspp_notify_required = false;
5741 if (target_link_speed > current_link_speed) {
5742 switch (target_link_speed) {
5743 #if defined(CONFIG_ACPI)
5744 case RADEON_PCIE_GEN3:
5745 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5746 break;
5747 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5748 if (current_link_speed == RADEON_PCIE_GEN2)
5749 break;
5750 case RADEON_PCIE_GEN2:
5751 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5752 break;
5753 #endif
5754 default:
5755 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5756 break;
5757 }
5758 } else {
5759 if (target_link_speed < current_link_speed)
5760 si_pi->pspp_notify_required = true;
5761 }
5762 }
5763
5764 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5765 struct radeon_ps *radeon_new_state,
5766 struct radeon_ps *radeon_current_state)
5767 {
5768 struct si_power_info *si_pi = si_get_pi(rdev);
5769 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5770 u8 request;
5771
5772 if (si_pi->pspp_notify_required) {
5773 if (target_link_speed == RADEON_PCIE_GEN3)
5774 request = PCIE_PERF_REQ_PECI_GEN3;
5775 else if (target_link_speed == RADEON_PCIE_GEN2)
5776 request = PCIE_PERF_REQ_PECI_GEN2;
5777 else
5778 request = PCIE_PERF_REQ_PECI_GEN1;
5779
5780 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5781 (si_get_current_pcie_speed(rdev) > 0))
5782 return;
5783
5784 #if defined(CONFIG_ACPI)
5785 radeon_acpi_pcie_performance_request(rdev, request, false);
5786 #endif
5787 }
5788 }
5789
5790 #if 0
5791 static int si_ds_request(struct radeon_device *rdev,
5792 bool ds_status_on, u32 count_write)
5793 {
5794 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5795
5796 if (eg_pi->sclk_deep_sleep) {
5797 if (ds_status_on)
5798 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5799 PPSMC_Result_OK) ?
5800 0 : -EINVAL;
5801 else
5802 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5803 PPSMC_Result_OK) ? 0 : -EINVAL;
5804 }
5805 return 0;
5806 }
5807 #endif
5808
5809 static void si_set_max_cu_value(struct radeon_device *rdev)
5810 {
5811 struct si_power_info *si_pi = si_get_pi(rdev);
5812
5813 if (rdev->family == CHIP_VERDE) {
5814 switch (rdev->pdev->device) {
5815 case 0x6820:
5816 case 0x6825:
5817 case 0x6821:
5818 case 0x6823:
5819 case 0x6827:
5820 si_pi->max_cu = 10;
5821 break;
5822 case 0x682D:
5823 case 0x6824:
5824 case 0x682F:
5825 case 0x6826:
5826 si_pi->max_cu = 8;
5827 break;
5828 case 0x6828:
5829 case 0x6830:
5830 case 0x6831:
5831 case 0x6838:
5832 case 0x6839:
5833 case 0x683D:
5834 si_pi->max_cu = 10;
5835 break;
5836 case 0x683B:
5837 case 0x683F:
5838 case 0x6829:
5839 si_pi->max_cu = 8;
5840 break;
5841 default:
5842 si_pi->max_cu = 0;
5843 break;
5844 }
5845 } else {
5846 si_pi->max_cu = 0;
5847 }
5848 }
5849
5850 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5851 struct radeon_clock_voltage_dependency_table *table)
5852 {
5853 u32 i;
5854 int j;
5855 u16 leakage_voltage;
5856
5857 if (table) {
5858 for (i = 0; i < table->count; i++) {
5859 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5860 table->entries[i].v,
5861 &leakage_voltage)) {
5862 case 0:
5863 table->entries[i].v = leakage_voltage;
5864 break;
5865 case -EAGAIN:
5866 return -EINVAL;
5867 case -EINVAL:
5868 default:
5869 break;
5870 }
5871 }
5872
5873 for (j = (table->count - 2); j >= 0; j--) {
5874 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5875 table->entries[j].v : table->entries[j + 1].v;
5876 }
5877 }
5878 return 0;
5879 }
5880
5881 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5882 {
5883 int ret = 0;
5884
5885 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5886 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5887 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5888 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5889 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5890 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5891 return ret;
5892 }
5893
5894 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5895 struct radeon_ps *radeon_new_state,
5896 struct radeon_ps *radeon_current_state)
5897 {
5898 u32 lane_width;
5899 u32 new_lane_width =
5900 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5901 u32 current_lane_width =
5902 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5903
5904 if (new_lane_width != current_lane_width) {
5905 radeon_set_pcie_lanes(rdev, new_lane_width);
5906 lane_width = radeon_get_pcie_lanes(rdev);
5907 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5908 }
5909 }
5910
5911 static void si_set_vce_clock(struct radeon_device *rdev,
5912 struct radeon_ps *new_rps,
5913 struct radeon_ps *old_rps)
5914 {
5915 if ((old_rps->evclk != new_rps->evclk) ||
5916 (old_rps->ecclk != new_rps->ecclk)) {
5917 /* turn the clocks on when encoding, off otherwise */
5918 if (new_rps->evclk || new_rps->ecclk)
5919 vce_v1_0_enable_mgcg(rdev, false);
5920 else
5921 vce_v1_0_enable_mgcg(rdev, true);
5922 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5923 }
5924 }
5925
5926 void si_dpm_setup_asic(struct radeon_device *rdev)
5927 {
5928 int r;
5929
5930 r = si_mc_load_microcode(rdev);
5931 if (r)
5932 DRM_ERROR("Failed to load MC firmware!\n");
5933 rv770_get_memory_type(rdev);
5934 si_read_clock_registers(rdev);
5935 si_enable_acpi_power_management(rdev);
5936 }
5937
5938 static int si_thermal_enable_alert(struct radeon_device *rdev,
5939 bool enable)
5940 {
5941 u32 thermal_int = RREG32(CG_THERMAL_INT);
5942
5943 if (enable) {
5944 PPSMC_Result result;
5945
5946 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
5947 WREG32(CG_THERMAL_INT, thermal_int);
5948 rdev->irq.dpm_thermal = false;
5949 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5950 if (result != PPSMC_Result_OK) {
5951 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5952 return -EINVAL;
5953 }
5954 } else {
5955 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
5956 WREG32(CG_THERMAL_INT, thermal_int);
5957 rdev->irq.dpm_thermal = true;
5958 }
5959
5960 return 0;
5961 }
5962
5963 static int si_thermal_set_temperature_range(struct radeon_device *rdev,
5964 int min_temp, int max_temp)
5965 {
5966 int low_temp = 0 * 1000;
5967 int high_temp = 255 * 1000;
5968
5969 if (low_temp < min_temp)
5970 low_temp = min_temp;
5971 if (high_temp > max_temp)
5972 high_temp = max_temp;
5973 if (high_temp < low_temp) {
5974 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5975 return -EINVAL;
5976 }
5977
5978 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5979 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5980 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5981
5982 rdev->pm.dpm.thermal.min_temp = low_temp;
5983 rdev->pm.dpm.thermal.max_temp = high_temp;
5984
5985 return 0;
5986 }
5987
5988 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
5989 {
5990 struct si_power_info *si_pi = si_get_pi(rdev);
5991 u32 tmp;
5992
5993 if (si_pi->fan_ctrl_is_in_default_mode) {
5994 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
5995 si_pi->fan_ctrl_default_mode = tmp;
5996 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
5997 si_pi->t_min = tmp;
5998 si_pi->fan_ctrl_is_in_default_mode = false;
5999 }
6000
6001 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6002 tmp |= TMIN(0);
6003 WREG32(CG_FDO_CTRL2, tmp);
6004
6005 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6006 tmp |= FDO_PWM_MODE(mode);
6007 WREG32(CG_FDO_CTRL2, tmp);
6008 }
6009
6010 static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6011 {
6012 struct si_power_info *si_pi = si_get_pi(rdev);
6013 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6014 u32 duty100;
6015 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6016 u16 fdo_min, slope1, slope2;
6017 u32 reference_clock, tmp;
6018 int ret;
6019 u64 tmp64;
6020
6021 if (!si_pi->fan_table_start) {
6022 rdev->pm.dpm.fan.ucode_fan_control = false;
6023 return 0;
6024 }
6025
6026 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6027
6028 if (duty100 == 0) {
6029 rdev->pm.dpm.fan.ucode_fan_control = false;
6030 return 0;
6031 }
6032
6033 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6034 do_div(tmp64, 10000);
6035 fdo_min = (u16)tmp64;
6036
6037 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6038 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6039
6040 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6041 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6042
6043 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6044 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6045
6046 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6047 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6048 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6049
6050 fan_table.slope1 = cpu_to_be16(slope1);
6051 fan_table.slope2 = cpu_to_be16(slope2);
6052
6053 fan_table.fdo_min = cpu_to_be16(fdo_min);
6054
6055 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6056
6057 fan_table.hys_up = cpu_to_be16(1);
6058
6059 fan_table.hys_slope = cpu_to_be16(1);
6060
6061 fan_table.temp_resp_lim = cpu_to_be16(5);
6062
6063 reference_clock = radeon_get_xclk(rdev);
6064
6065 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6066 reference_clock) / 1600);
6067
6068 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6069
6070 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6071 fan_table.temp_src = (uint8_t)tmp;
6072
6073 ret = si_copy_bytes_to_smc(rdev,
6074 si_pi->fan_table_start,
6075 (u8 *)(&fan_table),
6076 sizeof(fan_table),
6077 si_pi->sram_end);
6078
6079 if (ret) {
6080 DRM_ERROR("Failed to load fan table to the SMC.");
6081 rdev->pm.dpm.fan.ucode_fan_control = false;
6082 }
6083
6084 return 0;
6085 }
6086
6087 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6088 {
6089 struct si_power_info *si_pi = si_get_pi(rdev);
6090 PPSMC_Result ret;
6091
6092 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6093 if (ret == PPSMC_Result_OK) {
6094 si_pi->fan_is_controlled_by_smc = true;
6095 return 0;
6096 } else {
6097 return -EINVAL;
6098 }
6099 }
6100
6101 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6102 {
6103 struct si_power_info *si_pi = si_get_pi(rdev);
6104 PPSMC_Result ret;
6105
6106 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6107
6108 if (ret == PPSMC_Result_OK) {
6109 si_pi->fan_is_controlled_by_smc = false;
6110 return 0;
6111 } else {
6112 return -EINVAL;
6113 }
6114 }
6115
6116 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6117 u32 *speed)
6118 {
6119 u32 duty, duty100;
6120 u64 tmp64;
6121
6122 if (rdev->pm.no_fan)
6123 return -ENOENT;
6124
6125 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6126 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6127
6128 if (duty100 == 0)
6129 return -EINVAL;
6130
6131 tmp64 = (u64)duty * 100;
6132 do_div(tmp64, duty100);
6133 *speed = (u32)tmp64;
6134
6135 if (*speed > 100)
6136 *speed = 100;
6137
6138 return 0;
6139 }
6140
6141 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6142 u32 speed)
6143 {
6144 struct si_power_info *si_pi = si_get_pi(rdev);
6145 u32 tmp;
6146 u32 duty, duty100;
6147 u64 tmp64;
6148
6149 if (rdev->pm.no_fan)
6150 return -ENOENT;
6151
6152 if (si_pi->fan_is_controlled_by_smc)
6153 return -EINVAL;
6154
6155 if (speed > 100)
6156 return -EINVAL;
6157
6158 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6159
6160 if (duty100 == 0)
6161 return -EINVAL;
6162
6163 tmp64 = (u64)speed * duty100;
6164 do_div(tmp64, 100);
6165 duty = (u32)tmp64;
6166
6167 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6168 tmp |= FDO_STATIC_DUTY(duty);
6169 WREG32(CG_FDO_CTRL0, tmp);
6170
6171 return 0;
6172 }
6173
6174 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6175 {
6176 if (mode) {
6177 /* stop auto-manage */
6178 if (rdev->pm.dpm.fan.ucode_fan_control)
6179 si_fan_ctrl_stop_smc_fan_control(rdev);
6180 si_fan_ctrl_set_static_mode(rdev, mode);
6181 } else {
6182 /* restart auto-manage */
6183 if (rdev->pm.dpm.fan.ucode_fan_control)
6184 si_thermal_start_smc_fan_control(rdev);
6185 else
6186 si_fan_ctrl_set_default_mode(rdev);
6187 }
6188 }
6189
6190 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6191 {
6192 struct si_power_info *si_pi = si_get_pi(rdev);
6193 u32 tmp;
6194
6195 if (si_pi->fan_is_controlled_by_smc)
6196 return 0;
6197
6198 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6199 return (tmp >> FDO_PWM_MODE_SHIFT);
6200 }
6201
6202 #if 0
6203 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6204 u32 *speed)
6205 {
6206 u32 tach_period;
6207 u32 xclk = radeon_get_xclk(rdev);
6208
6209 if (rdev->pm.no_fan)
6210 return -ENOENT;
6211
6212 if (rdev->pm.fan_pulses_per_revolution == 0)
6213 return -ENOENT;
6214
6215 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6216 if (tach_period == 0)
6217 return -ENOENT;
6218
6219 *speed = 60 * xclk * 10000 / tach_period;
6220
6221 return 0;
6222 }
6223
6224 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6225 u32 speed)
6226 {
6227 u32 tach_period, tmp;
6228 u32 xclk = radeon_get_xclk(rdev);
6229
6230 if (rdev->pm.no_fan)
6231 return -ENOENT;
6232
6233 if (rdev->pm.fan_pulses_per_revolution == 0)
6234 return -ENOENT;
6235
6236 if ((speed < rdev->pm.fan_min_rpm) ||
6237 (speed > rdev->pm.fan_max_rpm))
6238 return -EINVAL;
6239
6240 if (rdev->pm.dpm.fan.ucode_fan_control)
6241 si_fan_ctrl_stop_smc_fan_control(rdev);
6242
6243 tach_period = 60 * xclk * 10000 / (8 * speed);
6244 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6245 tmp |= TARGET_PERIOD(tach_period);
6246 WREG32(CG_TACH_CTRL, tmp);
6247
6248 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6249
6250 return 0;
6251 }
6252 #endif
6253
6254 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6255 {
6256 struct si_power_info *si_pi = si_get_pi(rdev);
6257 u32 tmp;
6258
6259 if (!si_pi->fan_ctrl_is_in_default_mode) {
6260 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6261 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6262 WREG32(CG_FDO_CTRL2, tmp);
6263
6264 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6265 tmp |= TMIN(si_pi->t_min);
6266 WREG32(CG_FDO_CTRL2, tmp);
6267 si_pi->fan_ctrl_is_in_default_mode = true;
6268 }
6269 }
6270
6271 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6272 {
6273 if (rdev->pm.dpm.fan.ucode_fan_control) {
6274 si_fan_ctrl_start_smc_fan_control(rdev);
6275 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6276 }
6277 }
6278
6279 static void si_thermal_initialize(struct radeon_device *rdev)
6280 {
6281 u32 tmp;
6282
6283 if (rdev->pm.fan_pulses_per_revolution) {
6284 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6285 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6286 WREG32(CG_TACH_CTRL, tmp);
6287 }
6288
6289 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6290 tmp |= TACH_PWM_RESP_RATE(0x28);
6291 WREG32(CG_FDO_CTRL2, tmp);
6292 }
6293
6294 static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6295 {
6296 int ret;
6297
6298 si_thermal_initialize(rdev);
6299 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6300 if (ret)
6301 return ret;
6302 ret = si_thermal_enable_alert(rdev, true);
6303 if (ret)
6304 return ret;
6305 if (rdev->pm.dpm.fan.ucode_fan_control) {
6306 ret = si_halt_smc(rdev);
6307 if (ret)
6308 return ret;
6309 ret = si_thermal_setup_fan_table(rdev);
6310 if (ret)
6311 return ret;
6312 ret = si_resume_smc(rdev);
6313 if (ret)
6314 return ret;
6315 si_thermal_start_smc_fan_control(rdev);
6316 }
6317
6318 return 0;
6319 }
6320
6321 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6322 {
6323 if (!rdev->pm.no_fan) {
6324 si_fan_ctrl_set_default_mode(rdev);
6325 si_fan_ctrl_stop_smc_fan_control(rdev);
6326 }
6327 }
6328
6329 int si_dpm_enable(struct radeon_device *rdev)
6330 {
6331 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6332 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6333 struct si_power_info *si_pi = si_get_pi(rdev);
6334 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6335 int ret;
6336
6337 if (si_is_smc_running(rdev))
6338 return -EINVAL;
6339 if (pi->voltage_control || si_pi->voltage_control_svi2)
6340 si_enable_voltage_control(rdev, true);
6341 if (pi->mvdd_control)
6342 si_get_mvdd_configuration(rdev);
6343 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6344 ret = si_construct_voltage_tables(rdev);
6345 if (ret) {
6346 DRM_ERROR("si_construct_voltage_tables failed\n");
6347 return ret;
6348 }
6349 }
6350 if (eg_pi->dynamic_ac_timing) {
6351 ret = si_initialize_mc_reg_table(rdev);
6352 if (ret)
6353 eg_pi->dynamic_ac_timing = false;
6354 }
6355 if (pi->dynamic_ss)
6356 si_enable_spread_spectrum(rdev, true);
6357 if (pi->thermal_protection)
6358 si_enable_thermal_protection(rdev, true);
6359 si_setup_bsp(rdev);
6360 si_program_git(rdev);
6361 si_program_tp(rdev);
6362 si_program_tpp(rdev);
6363 si_program_sstp(rdev);
6364 si_enable_display_gap(rdev);
6365 si_program_vc(rdev);
6366 ret = si_upload_firmware(rdev);
6367 if (ret) {
6368 DRM_ERROR("si_upload_firmware failed\n");
6369 return ret;
6370 }
6371 ret = si_process_firmware_header(rdev);
6372 if (ret) {
6373 DRM_ERROR("si_process_firmware_header failed\n");
6374 return ret;
6375 }
6376 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6377 if (ret) {
6378 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6379 return ret;
6380 }
6381 ret = si_init_smc_table(rdev);
6382 if (ret) {
6383 DRM_ERROR("si_init_smc_table failed\n");
6384 return ret;
6385 }
6386 ret = si_init_smc_spll_table(rdev);
6387 if (ret) {
6388 DRM_ERROR("si_init_smc_spll_table failed\n");
6389 return ret;
6390 }
6391 ret = si_init_arb_table_index(rdev);
6392 if (ret) {
6393 DRM_ERROR("si_init_arb_table_index failed\n");
6394 return ret;
6395 }
6396 if (eg_pi->dynamic_ac_timing) {
6397 ret = si_populate_mc_reg_table(rdev, boot_ps);
6398 if (ret) {
6399 DRM_ERROR("si_populate_mc_reg_table failed\n");
6400 return ret;
6401 }
6402 }
6403 ret = si_initialize_smc_cac_tables(rdev);
6404 if (ret) {
6405 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6406 return ret;
6407 }
6408 ret = si_initialize_hardware_cac_manager(rdev);
6409 if (ret) {
6410 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6411 return ret;
6412 }
6413 ret = si_initialize_smc_dte_tables(rdev);
6414 if (ret) {
6415 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6416 return ret;
6417 }
6418 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6419 if (ret) {
6420 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6421 return ret;
6422 }
6423 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6424 if (ret) {
6425 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6426 return ret;
6427 }
6428 si_program_response_times(rdev);
6429 si_program_ds_registers(rdev);
6430 si_dpm_start_smc(rdev);
6431 ret = si_notify_smc_display_change(rdev, false);
6432 if (ret) {
6433 DRM_ERROR("si_notify_smc_display_change failed\n");
6434 return ret;
6435 }
6436 si_enable_sclk_control(rdev, true);
6437 si_start_dpm(rdev);
6438
6439 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6440
6441 si_thermal_start_thermal_controller(rdev);
6442
6443 ni_update_current_ps(rdev, boot_ps);
6444
6445 return 0;
6446 }
6447
6448 static int si_set_temperature_range(struct radeon_device *rdev)
6449 {
6450 int ret;
6451
6452 ret = si_thermal_enable_alert(rdev, false);
6453 if (ret)
6454 return ret;
6455 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6456 if (ret)
6457 return ret;
6458 ret = si_thermal_enable_alert(rdev, true);
6459 if (ret)
6460 return ret;
6461
6462 return ret;
6463 }
6464
6465 int si_dpm_late_enable(struct radeon_device *rdev)
6466 {
6467 int ret;
6468
6469 ret = si_set_temperature_range(rdev);
6470 if (ret)
6471 return ret;
6472
6473 return ret;
6474 }
6475
6476 void si_dpm_disable(struct radeon_device *rdev)
6477 {
6478 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6479 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6480
6481 if (!si_is_smc_running(rdev))
6482 return;
6483 si_thermal_stop_thermal_controller(rdev);
6484 si_disable_ulv(rdev);
6485 si_clear_vc(rdev);
6486 if (pi->thermal_protection)
6487 si_enable_thermal_protection(rdev, false);
6488 si_enable_power_containment(rdev, boot_ps, false);
6489 si_enable_smc_cac(rdev, boot_ps, false);
6490 si_enable_spread_spectrum(rdev, false);
6491 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6492 si_stop_dpm(rdev);
6493 si_reset_to_default(rdev);
6494 si_dpm_stop_smc(rdev);
6495 si_force_switch_to_arb_f0(rdev);
6496
6497 ni_update_current_ps(rdev, boot_ps);
6498 }
6499
6500 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6501 {
6502 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6503 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6504 struct radeon_ps *new_ps = &requested_ps;
6505
6506 ni_update_requested_ps(rdev, new_ps);
6507
6508 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6509
6510 return 0;
6511 }
6512
6513 static int si_power_control_set_level(struct radeon_device *rdev)
6514 {
6515 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6516 int ret;
6517
6518 ret = si_restrict_performance_levels_before_switch(rdev);
6519 if (ret)
6520 return ret;
6521 ret = si_halt_smc(rdev);
6522 if (ret)
6523 return ret;
6524 ret = si_populate_smc_tdp_limits(rdev, new_ps);
6525 if (ret)
6526 return ret;
6527 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6528 if (ret)
6529 return ret;
6530 ret = si_resume_smc(rdev);
6531 if (ret)
6532 return ret;
6533 ret = si_set_sw_state(rdev);
6534 if (ret)
6535 return ret;
6536 return 0;
6537 }
6538
6539 int si_dpm_set_power_state(struct radeon_device *rdev)
6540 {
6541 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6542 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6543 struct radeon_ps *old_ps = &eg_pi->current_rps;
6544 int ret;
6545
6546 ret = si_disable_ulv(rdev);
6547 if (ret) {
6548 DRM_ERROR("si_disable_ulv failed\n");
6549 return ret;
6550 }
6551 ret = si_restrict_performance_levels_before_switch(rdev);
6552 if (ret) {
6553 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6554 return ret;
6555 }
6556 if (eg_pi->pcie_performance_request)
6557 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6558 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6559 ret = si_enable_power_containment(rdev, new_ps, false);
6560 if (ret) {
6561 DRM_ERROR("si_enable_power_containment failed\n");
6562 return ret;
6563 }
6564 ret = si_enable_smc_cac(rdev, new_ps, false);
6565 if (ret) {
6566 DRM_ERROR("si_enable_smc_cac failed\n");
6567 return ret;
6568 }
6569 ret = si_halt_smc(rdev);
6570 if (ret) {
6571 DRM_ERROR("si_halt_smc failed\n");
6572 return ret;
6573 }
6574 ret = si_upload_sw_state(rdev, new_ps);
6575 if (ret) {
6576 DRM_ERROR("si_upload_sw_state failed\n");
6577 return ret;
6578 }
6579 ret = si_upload_smc_data(rdev);
6580 if (ret) {
6581 DRM_ERROR("si_upload_smc_data failed\n");
6582 return ret;
6583 }
6584 ret = si_upload_ulv_state(rdev);
6585 if (ret) {
6586 DRM_ERROR("si_upload_ulv_state failed\n");
6587 return ret;
6588 }
6589 if (eg_pi->dynamic_ac_timing) {
6590 ret = si_upload_mc_reg_table(rdev, new_ps);
6591 if (ret) {
6592 DRM_ERROR("si_upload_mc_reg_table failed\n");
6593 return ret;
6594 }
6595 }
6596 ret = si_program_memory_timing_parameters(rdev, new_ps);
6597 if (ret) {
6598 DRM_ERROR("si_program_memory_timing_parameters failed\n");
6599 return ret;
6600 }
6601 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6602
6603 ret = si_resume_smc(rdev);
6604 if (ret) {
6605 DRM_ERROR("si_resume_smc failed\n");
6606 return ret;
6607 }
6608 ret = si_set_sw_state(rdev);
6609 if (ret) {
6610 DRM_ERROR("si_set_sw_state failed\n");
6611 return ret;
6612 }
6613 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6614 si_set_vce_clock(rdev, new_ps, old_ps);
6615 if (eg_pi->pcie_performance_request)
6616 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6617 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6618 if (ret) {
6619 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6620 return ret;
6621 }
6622 ret = si_enable_smc_cac(rdev, new_ps, true);
6623 if (ret) {
6624 DRM_ERROR("si_enable_smc_cac failed\n");
6625 return ret;
6626 }
6627 ret = si_enable_power_containment(rdev, new_ps, true);
6628 if (ret) {
6629 DRM_ERROR("si_enable_power_containment failed\n");
6630 return ret;
6631 }
6632
6633 ret = si_power_control_set_level(rdev);
6634 if (ret) {
6635 DRM_ERROR("si_power_control_set_level failed\n");
6636 return ret;
6637 }
6638
6639 return 0;
6640 }
6641
6642 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6643 {
6644 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6645 struct radeon_ps *new_ps = &eg_pi->requested_rps;
6646
6647 ni_update_current_ps(rdev, new_ps);
6648 }
6649
6650 #if 0
6651 void si_dpm_reset_asic(struct radeon_device *rdev)
6652 {
6653 si_restrict_performance_levels_before_switch(rdev);
6654 si_disable_ulv(rdev);
6655 si_set_boot_state(rdev);
6656 }
6657 #endif
6658
6659 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6660 {
6661 si_program_display_gap(rdev);
6662 }
6663
6664 union power_info {
6665 struct _ATOM_POWERPLAY_INFO info;
6666 struct _ATOM_POWERPLAY_INFO_V2 info_2;
6667 struct _ATOM_POWERPLAY_INFO_V3 info_3;
6668 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6669 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6670 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6671 };
6672
6673 union pplib_clock_info {
6674 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6675 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6676 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6677 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6678 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6679 };
6680
6681 union pplib_power_state {
6682 struct _ATOM_PPLIB_STATE v1;
6683 struct _ATOM_PPLIB_STATE_V2 v2;
6684 };
6685
6686 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6687 struct radeon_ps *rps,
6688 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6689 u8 table_rev)
6690 {
6691 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6692 rps->class = le16_to_cpu(non_clock_info->usClassification);
6693 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6694
6695 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6696 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6697 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6698 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6699 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6700 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6701 } else {
6702 rps->vclk = 0;
6703 rps->dclk = 0;
6704 }
6705
6706 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6707 rdev->pm.dpm.boot_ps = rps;
6708 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6709 rdev->pm.dpm.uvd_ps = rps;
6710 }
6711
6712 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6713 struct radeon_ps *rps, int index,
6714 union pplib_clock_info *clock_info)
6715 {
6716 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6717 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6718 struct si_power_info *si_pi = si_get_pi(rdev);
6719 struct ni_ps *ps = ni_get_ps(rps);
6720 u16 leakage_voltage;
6721 struct rv7xx_pl *pl = &ps->performance_levels[index];
6722 int ret;
6723
6724 ps->performance_level_count = index + 1;
6725
6726 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6727 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6728 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6729 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6730
6731 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6732 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6733 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6734 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6735 si_pi->sys_pcie_mask,
6736 si_pi->boot_pcie_gen,
6737 clock_info->si.ucPCIEGen);
6738
6739 /* patch up vddc if necessary */
6740 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6741 &leakage_voltage);
6742 if (ret == 0)
6743 pl->vddc = leakage_voltage;
6744
6745 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6746 pi->acpi_vddc = pl->vddc;
6747 eg_pi->acpi_vddci = pl->vddci;
6748 si_pi->acpi_pcie_gen = pl->pcie_gen;
6749 }
6750
6751 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6752 index == 0) {
6753 /* XXX disable for A0 tahiti */
6754 si_pi->ulv.supported = false;
6755 si_pi->ulv.pl = *pl;
6756 si_pi->ulv.one_pcie_lane_in_ulv = false;
6757 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6758 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6759 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6760 }
6761
6762 if (pi->min_vddc_in_table > pl->vddc)
6763 pi->min_vddc_in_table = pl->vddc;
6764
6765 if (pi->max_vddc_in_table < pl->vddc)
6766 pi->max_vddc_in_table = pl->vddc;
6767
6768 /* patch up boot state */
6769 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6770 u16 vddc, vddci, mvdd;
6771 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6772 pl->mclk = rdev->clock.default_mclk;
6773 pl->sclk = rdev->clock.default_sclk;
6774 pl->vddc = vddc;
6775 pl->vddci = vddci;
6776 si_pi->mvdd_bootup_value = mvdd;
6777 }
6778
6779 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6780 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6781 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6782 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6783 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6784 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6785 }
6786 }
6787
6788 static int si_parse_power_table(struct radeon_device *rdev)
6789 {
6790 struct radeon_mode_info *mode_info = &rdev->mode_info;
6791 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6792 union pplib_power_state *power_state;
6793 int i, j, k, non_clock_array_index, clock_array_index;
6794 union pplib_clock_info *clock_info;
6795 struct _StateArray *state_array;
6796 struct _ClockInfoArray *clock_info_array;
6797 struct _NonClockInfoArray *non_clock_info_array;
6798 union power_info *power_info;
6799 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6800 u16 data_offset;
6801 u8 frev, crev;
6802 u8 *power_state_offset;
6803 struct ni_ps *ps;
6804
6805 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6806 &frev, &crev, &data_offset))
6807 return -EINVAL;
6808 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6809
6810 state_array = (struct _StateArray *)
6811 (mode_info->atom_context->bios + data_offset +
6812 le16_to_cpu(power_info->pplib.usStateArrayOffset));
6813 clock_info_array = (struct _ClockInfoArray *)
6814 (mode_info->atom_context->bios + data_offset +
6815 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6816 non_clock_info_array = (struct _NonClockInfoArray *)
6817 (mode_info->atom_context->bios + data_offset +
6818 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6819
6820 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6821 state_array->ucNumEntries, GFP_KERNEL);
6822 if (!rdev->pm.dpm.ps)
6823 return -ENOMEM;
6824 power_state_offset = (u8 *)state_array->states;
6825 for (i = 0; i < state_array->ucNumEntries; i++) {
6826 u8 *idx;
6827 power_state = (union pplib_power_state *)power_state_offset;
6828 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6829 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6830 &non_clock_info_array->nonClockInfo[non_clock_array_index];
6831 if (!rdev->pm.power_state[i].clock_info)
6832 return -EINVAL;
6833 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6834 if (ps == NULL) {
6835 kfree(rdev->pm.dpm.ps);
6836 return -ENOMEM;
6837 }
6838 rdev->pm.dpm.ps[i].ps_priv = ps;
6839 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6840 non_clock_info,
6841 non_clock_info_array->ucEntrySize);
6842 k = 0;
6843 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6844 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6845 clock_array_index = idx[j];
6846 if (clock_array_index >= clock_info_array->ucNumEntries)
6847 continue;
6848 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6849 break;
6850 clock_info = (union pplib_clock_info *)
6851 ((u8 *)&clock_info_array->clockInfo[0] +
6852 (clock_array_index * clock_info_array->ucEntrySize));
6853 si_parse_pplib_clock_info(rdev,
6854 &rdev->pm.dpm.ps[i], k,
6855 clock_info);
6856 k++;
6857 }
6858 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6859 }
6860 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6861
6862 /* fill in the vce power states */
6863 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
6864 u32 sclk, mclk;
6865 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6866 clock_info = (union pplib_clock_info *)
6867 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6868 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6869 sclk |= clock_info->si.ucEngineClockHigh << 16;
6870 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6871 mclk |= clock_info->si.ucMemoryClockHigh << 16;
6872 rdev->pm.dpm.vce_states[i].sclk = sclk;
6873 rdev->pm.dpm.vce_states[i].mclk = mclk;
6874 }
6875
6876 return 0;
6877 }
6878
6879 int si_dpm_init(struct radeon_device *rdev)
6880 {
6881 struct rv7xx_power_info *pi;
6882 struct evergreen_power_info *eg_pi;
6883 struct ni_power_info *ni_pi;
6884 struct si_power_info *si_pi;
6885 struct atom_clock_dividers dividers;
6886 int ret;
6887 u32 mask;
6888
6889 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6890 if (si_pi == NULL)
6891 return -ENOMEM;
6892 rdev->pm.dpm.priv = si_pi;
6893 ni_pi = &si_pi->ni;
6894 eg_pi = &ni_pi->eg;
6895 pi = &eg_pi->rv7xx;
6896
6897 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6898 if (ret)
6899 si_pi->sys_pcie_mask = 0;
6900 else
6901 si_pi->sys_pcie_mask = mask;
6902 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6903 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6904
6905 si_set_max_cu_value(rdev);
6906
6907 rv770_get_max_vddc(rdev);
6908 si_get_leakage_vddc(rdev);
6909 si_patch_dependency_tables_based_on_leakage(rdev);
6910
6911 pi->acpi_vddc = 0;
6912 eg_pi->acpi_vddci = 0;
6913 pi->min_vddc_in_table = 0;
6914 pi->max_vddc_in_table = 0;
6915
6916 ret = r600_get_platform_caps(rdev);
6917 if (ret)
6918 return ret;
6919
6920 ret = r600_parse_extended_power_table(rdev);
6921 if (ret)
6922 return ret;
6923
6924 ret = si_parse_power_table(rdev);
6925 if (ret)
6926 return ret;
6927
6928 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6929 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6930 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6931 r600_free_extended_power_table(rdev);
6932 return -ENOMEM;
6933 }
6934 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6935 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6936 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6937 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6938 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6939 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6940 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6941 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6942 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6943
6944 if (rdev->pm.dpm.voltage_response_time == 0)
6945 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6946 if (rdev->pm.dpm.backbias_response_time == 0)
6947 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6948
6949 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6950 0, false, &dividers);
6951 if (ret)
6952 pi->ref_div = dividers.ref_div + 1;
6953 else
6954 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6955
6956 eg_pi->smu_uvd_hs = false;
6957
6958 pi->mclk_strobe_mode_threshold = 40000;
6959 if (si_is_special_1gb_platform(rdev))
6960 pi->mclk_stutter_mode_threshold = 0;
6961 else
6962 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6963 pi->mclk_edc_enable_threshold = 40000;
6964 eg_pi->mclk_edc_wr_enable_threshold = 40000;
6965
6966 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6967
6968 pi->voltage_control =
6969 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6970 VOLTAGE_OBJ_GPIO_LUT);
6971 if (!pi->voltage_control) {
6972 si_pi->voltage_control_svi2 =
6973 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6974 VOLTAGE_OBJ_SVID2);
6975 if (si_pi->voltage_control_svi2)
6976 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6977 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
6978 }
6979
6980 pi->mvdd_control =
6981 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
6982 VOLTAGE_OBJ_GPIO_LUT);
6983
6984 eg_pi->vddci_control =
6985 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
6986 VOLTAGE_OBJ_GPIO_LUT);
6987 if (!eg_pi->vddci_control)
6988 si_pi->vddci_control_svi2 =
6989 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
6990 VOLTAGE_OBJ_SVID2);
6991
6992 si_pi->vddc_phase_shed_control =
6993 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6994 VOLTAGE_OBJ_PHASE_LUT);
6995
6996 rv770_get_engine_memory_ss(rdev);
6997
6998 pi->asi = RV770_ASI_DFLT;
6999 pi->pasi = CYPRESS_HASI_DFLT;
7000 pi->vrc = SISLANDS_VRC_DFLT;
7001
7002 pi->gfx_clock_gating = true;
7003
7004 eg_pi->sclk_deep_sleep = true;
7005 si_pi->sclk_deep_sleep_above_low = false;
7006
7007 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7008 pi->thermal_protection = true;
7009 else
7010 pi->thermal_protection = false;
7011
7012 eg_pi->dynamic_ac_timing = true;
7013
7014 eg_pi->light_sleep = true;
7015 #if defined(CONFIG_ACPI)
7016 eg_pi->pcie_performance_request =
7017 radeon_acpi_is_pcie_performance_request_supported(rdev);
7018 #else
7019 eg_pi->pcie_performance_request = false;
7020 #endif
7021
7022 si_pi->sram_end = SMC_RAM_END;
7023
7024 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7025 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7026 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7027 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7028 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7029 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7030 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7031
7032 si_initialize_powertune_defaults(rdev);
7033
7034 /* make sure dc limits are valid */
7035 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7036 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7037 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7038 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7039
7040 si_pi->fan_ctrl_is_in_default_mode = true;
7041
7042 return 0;
7043 }
7044
7045 void si_dpm_fini(struct radeon_device *rdev)
7046 {
7047 int i;
7048
7049 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7050 kfree(rdev->pm.dpm.ps[i].ps_priv);
7051 }
7052 kfree(rdev->pm.dpm.ps);
7053 kfree(rdev->pm.dpm.priv);
7054 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7055 r600_free_extended_power_table(rdev);
7056 }
7057
7058 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7059 struct seq_file *m)
7060 {
7061 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7062 struct radeon_ps *rps = &eg_pi->current_rps;
7063 struct ni_ps *ps = ni_get_ps(rps);
7064 struct rv7xx_pl *pl;
7065 u32 current_index =
7066 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7067 CURRENT_STATE_INDEX_SHIFT;
7068
7069 if (current_index >= ps->performance_level_count) {
7070 seq_printf(m, "invalid dpm profile %d\n", current_index);
7071 } else {
7072 pl = &ps->performance_levels[current_index];
7073 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7074 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7075 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7076 }
7077 }
7078
7079 u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7080 {
7081 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7082 struct radeon_ps *rps = &eg_pi->current_rps;
7083 struct ni_ps *ps = ni_get_ps(rps);
7084 struct rv7xx_pl *pl;
7085 u32 current_index =
7086 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7087 CURRENT_STATE_INDEX_SHIFT;
7088
7089 if (current_index >= ps->performance_level_count) {
7090 return 0;
7091 } else {
7092 pl = &ps->performance_levels[current_index];
7093 return pl->sclk;
7094 }
7095 }
7096
7097 u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7098 {
7099 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7100 struct radeon_ps *rps = &eg_pi->current_rps;
7101 struct ni_ps *ps = ni_get_ps(rps);
7102 struct rv7xx_pl *pl;
7103 u32 current_index =
7104 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7105 CURRENT_STATE_INDEX_SHIFT;
7106
7107 if (current_index >= ps->performance_level_count) {
7108 return 0;
7109 } else {
7110 pl = &ps->performance_levels[current_index];
7111 return pl->mclk;
7112 }
7113 }
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