drivers/gpu/drm/rockchip/dw-mipi-dsi.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/regmap.h>
  17 #include <linux/reset.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc.h>
  21 #include <drm/drm_crtc_helper.h>
  22 #include <drm/drm_mipi_dsi.h>
  23 #include <drm/drm_of.h>
  24 #include <drm/drm_panel.h>
  25 #include <drm/drmP.h>
  26 #include <video/mipi_display.h>
  27
  28 #include "rockchip_drm_drv.h"
  29 #include "rockchip_drm_vop.h"
  30
  31 #define DRIVER_NAME    "dw-mipi-dsi"
  32
  33 #define RK3288_GRF_SOC_CON6             0x025c
  34 #define RK3288_DSI0_SEL_VOP_LIT         BIT(6)
  35 #define RK3288_DSI1_SEL_VOP_LIT         BIT(9)
  36
  37 #define RK3399_GRF_SOC_CON19            0x6250
  38 #define RK3399_DSI0_SEL_VOP_LIT         BIT(0)
  39 #define RK3399_DSI1_SEL_VOP_LIT         BIT(4)
  40
  41 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
  42 #define RK3399_GRF_SOC_CON22            0x6258
  43 #define RK3399_GRF_DSI_MODE             0xffff0000
  44
  45 #define DSI_VERSION                     0x00
  46 #define DSI_PWR_UP                      0x04
  47 #define RESET                           0
  48 #define POWERUP                         BIT(0)
  49
  50 #define DSI_CLKMGR_CFG                  0x08
  51 #define TO_CLK_DIVIDSION(div)           (((div) & 0xff) << 8)
  52 #define TX_ESC_CLK_DIVIDSION(div)       (((div) & 0xff) << 0)
  53
  54 #define DSI_DPI_VCID                    0x0c
  55 #define DPI_VID(vid)                    (((vid) & 0x3) << 0)
  56
  57 #define DSI_DPI_COLOR_CODING            0x10
  58 #define EN18_LOOSELY                    BIT(8)
  59 #define DPI_COLOR_CODING_16BIT_1        0x0
  60 #define DPI_COLOR_CODING_16BIT_2        0x1
  61 #define DPI_COLOR_CODING_16BIT_3        0x2
  62 #define DPI_COLOR_CODING_18BIT_1        0x3
  63 #define DPI_COLOR_CODING_18BIT_2        0x4
  64 #define DPI_COLOR_CODING_24BIT          0x5
  65
  66 #define DSI_DPI_CFG_POL                 0x14
  67 #define COLORM_ACTIVE_LOW               BIT(4)
  68 #define SHUTD_ACTIVE_LOW                BIT(3)
  69 #define HSYNC_ACTIVE_LOW                BIT(2)
  70 #define VSYNC_ACTIVE_LOW                BIT(1)
  71 #define DATAEN_ACTIVE_LOW               BIT(0)
  72
  73 #define DSI_DPI_LP_CMD_TIM              0x18
  74 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  75 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  76
  77 #define DSI_DBI_CFG                     0x20
  78 #define DSI_DBI_CMDSIZE                 0x28
  79
  80 #define DSI_PCKHDL_CFG                  0x2c
  81 #define EN_CRC_RX                       BIT(4)
  82 #define EN_ECC_RX                       BIT(3)
  83 #define EN_BTA                          BIT(2)
  84 #define EN_EOTP_RX                      BIT(1)
  85 #define EN_EOTP_TX                      BIT(0)
  86
  87 #define DSI_MODE_CFG                    0x34
  88 #define ENABLE_VIDEO_MODE               0
  89 #define ENABLE_CMD_MODE                 BIT(0)
  90
  91 #define DSI_VID_MODE_CFG                0x38
  92 #define FRAME_BTA_ACK                   BIT(14)
  93 #define ENABLE_LOW_POWER                (0x3f << 8)
  94 #define ENABLE_LOW_POWER_MASK           (0x3f << 8)
  95 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES     0x0
  96 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS     0x1
  97 #define VID_MODE_TYPE_BURST                     0x2
  98 #define VID_MODE_TYPE_MASK                      0x3
  99
 100 #define DSI_VID_PKT_SIZE                0x3c
 101 #define VID_PKT_SIZE(p)                 (((p) & 0x3fff) << 0)
 102 #define VID_PKT_MAX_SIZE                0x3fff
 103
 104 #define DSI_VID_HSA_TIME                0x48
 105 #define DSI_VID_HBP_TIME                0x4c
 106 #define DSI_VID_HLINE_TIME              0x50
 107 #define DSI_VID_VSA_LINES               0x54
 108 #define DSI_VID_VBP_LINES               0x58
 109 #define DSI_VID_VFP_LINES               0x5c
 110 #define DSI_VID_VACTIVE_LINES           0x60
 111 #define DSI_CMD_MODE_CFG                0x68
 112 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 113 #define DCS_LW_TX_LP                    BIT(19)
 114 #define DCS_SR_0P_TX_LP                 BIT(18)
 115 #define DCS_SW_1P_TX_LP                 BIT(17)
 116 #define DCS_SW_0P_TX_LP                 BIT(16)
 117 #define GEN_LW_TX_LP                    BIT(14)
 118 #define GEN_SR_2P_TX_LP                 BIT(13)
 119 #define GEN_SR_1P_TX_LP                 BIT(12)
 120 #define GEN_SR_0P_TX_LP                 BIT(11)
 121 #define GEN_SW_2P_TX_LP                 BIT(10)
 122 #define GEN_SW_1P_TX_LP                 BIT(9)
 123 #define GEN_SW_0P_TX_LP                 BIT(8)
 124 #define EN_ACK_RQST                     BIT(1)
 125 #define EN_TEAR_FX                      BIT(0)
 126
 127 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 128                                          DCS_LW_TX_LP | \
 129                                          DCS_SR_0P_TX_LP | \
 130                                          DCS_SW_1P_TX_LP | \
 131                                          DCS_SW_0P_TX_LP | \
 132                                          GEN_LW_TX_LP | \
 133                                          GEN_SR_2P_TX_LP | \
 134                                          GEN_SR_1P_TX_LP | \
 135                                          GEN_SR_0P_TX_LP | \
 136                                          GEN_SW_2P_TX_LP | \
 137                                          GEN_SW_1P_TX_LP | \
 138                                          GEN_SW_0P_TX_LP)
 139
 140 #define DSI_GEN_HDR                     0x6c
 141 #define GEN_HDATA(data)                 (((data) & 0xffff) << 8)
 142 #define GEN_HDATA_MASK                  (0xffff << 8)
 143 #define GEN_HTYPE(type)                 (((type) & 0xff) << 0)
 144 #define GEN_HTYPE_MASK                  0xff
 145
 146 #define DSI_GEN_PLD_DATA                0x70
 147
 148 #define DSI_CMD_PKT_STATUS              0x74
 149 #define GEN_CMD_EMPTY                   BIT(0)
 150 #define GEN_CMD_FULL                    BIT(1)
 151 #define GEN_PLD_W_EMPTY                 BIT(2)
 152 #define GEN_PLD_W_FULL                  BIT(3)
 153 #define GEN_PLD_R_EMPTY                 BIT(4)
 154 #define GEN_PLD_R_FULL                  BIT(5)
 155 #define GEN_RD_CMD_BUSY                 BIT(6)
 156
 157 #define DSI_TO_CNT_CFG                  0x78
 158 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 159 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 160
 161 #define DSI_BTA_TO_CNT                  0x8c
 162 #define DSI_LPCLK_CTRL                  0x94
 163 #define AUTO_CLKLANE_CTRL               BIT(1)
 164 #define PHY_TXREQUESTCLKHS              BIT(0)
 165
 166 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 167 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 168 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 169
 170 #define DSI_PHY_TMR_CFG                 0x9c
 171 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 172 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 173 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 174
 175 #define DSI_PHY_RSTZ                    0xa0
 176 #define PHY_DISFORCEPLL                 0
 177 #define PHY_ENFORCEPLL                  BIT(3)
 178 #define PHY_DISABLECLK                  0
 179 #define PHY_ENABLECLK                   BIT(2)
 180 #define PHY_RSTZ                        0
 181 #define PHY_UNRSTZ                      BIT(1)
 182 #define PHY_SHUTDOWNZ                   0
 183 #define PHY_UNSHUTDOWNZ                 BIT(0)
 184
 185 #define DSI_PHY_IF_CFG                  0xa4
 186 #define N_LANES(n)                      ((((n) - 1) & 0x3) << 0)
 187 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 188
 189 #define DSI_PHY_STATUS                  0xb0
 190 #define LOCK                            BIT(0)
 191 #define STOP_STATE_CLK_LANE             BIT(2)
 192
 193 #define DSI_PHY_TST_CTRL0               0xb4
 194 #define PHY_TESTCLK                     BIT(1)
 195 #define PHY_UNTESTCLK                   0
 196 #define PHY_TESTCLR                     BIT(0)
 197 #define PHY_UNTESTCLR                   0
 198
 199 #define DSI_PHY_TST_CTRL1               0xb8
 200 #define PHY_TESTEN                      BIT(16)
 201 #define PHY_UNTESTEN                    0
 202 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 203 #define PHY_TESTDIN(n)                  (((n) & 0xff) << 0)
 204
 205 #define DSI_INT_ST0                     0xbc
 206 #define DSI_INT_ST1                     0xc0
 207 #define DSI_INT_MSK0                    0xc4
 208 #define DSI_INT_MSK1                    0xc8
 209
 210 #define PHY_STATUS_TIMEOUT_US           10000
 211 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 212
 213 #define BYPASS_VCO_RANGE        BIT(7)
 214 #define VCO_RANGE_CON_SEL(val)  (((val) & 0x7) << 3)
 215 #define VCO_IN_CAP_CON_DEFAULT  (0x0 << 1)
 216 #define VCO_IN_CAP_CON_LOW      (0x1 << 1)
 217 #define VCO_IN_CAP_CON_HIGH     (0x2 << 1)
 218 #define REF_BIAS_CUR_SEL        BIT(0)
 219
 220 #define CP_CURRENT_3MA          BIT(3)
 221 #define CP_PROGRAM_EN           BIT(7)
 222 #define LPF_PROGRAM_EN          BIT(6)
 223 #define LPF_RESISTORS_20_KOHM   0
 224
 225 #define HSFREQRANGE_SEL(val)    (((val) & 0x3f) << 1)
 226
 227 #define INPUT_DIVIDER(val)      (((val) - 1) & 0x7f)
 228 #define LOW_PROGRAM_EN          0
 229 #define HIGH_PROGRAM_EN         BIT(7)
 230 #define LOOP_DIV_LOW_SEL(val)   (((val) - 1) & 0x1f)
 231 #define LOOP_DIV_HIGH_SEL(val)  ((((val) - 1) >> 5) & 0x1f)
 232 #define PLL_LOOP_DIV_EN         BIT(5)
 233 #define PLL_INPUT_DIV_EN        BIT(4)
 234
 235 #define POWER_CONTROL           BIT(6)
 236 #define INTERNAL_REG_CURRENT    BIT(3)
 237 #define BIAS_BLOCK_ON           BIT(2)
 238 #define BANDGAP_ON              BIT(0)
 239
 240 #define TER_RESISTOR_HIGH       BIT(7)
 241 #define TER_RESISTOR_LOW        0
 242 #define LEVEL_SHIFTERS_ON       BIT(6)
 243 #define TER_CAL_DONE            BIT(5)
 244 #define SETRD_MAX               (0x7 << 2)
 245 #define POWER_MANAGE            BIT(1)
 246 #define TER_RESISTORS_ON        BIT(0)
 247
 248 #define BIASEXTR_SEL(val)       ((val) & 0x7)
 249 #define BANDGAP_SEL(val)        ((val) & 0x7)
 250 #define TLP_PROGRAM_EN          BIT(7)
 251 #define THS_PRE_PROGRAM_EN      BIT(7)
 252 #define THS_ZERO_PROGRAM_EN     BIT(6)
 253
 254 enum {
 255         BANDGAP_97_07,
 256         BANDGAP_98_05,
 257         BANDGAP_99_02,
 258         BANDGAP_100_00,
 259         BANDGAP_93_17,
 260         BANDGAP_94_15,
 261         BANDGAP_95_12,
 262         BANDGAP_96_10,
 263 };
 264
 265 enum {
 266         BIASEXTR_87_1,
 267         BIASEXTR_91_5,
 268         BIASEXTR_95_9,
 269         BIASEXTR_100,
 270         BIASEXTR_105_94,
 271         BIASEXTR_111_88,
 272         BIASEXTR_118_8,
 273         BIASEXTR_127_7,
 274 };
 275
 276 struct dw_mipi_dsi_plat_data {
 277         u32 dsi0_en_bit;
 278         u32 dsi1_en_bit;
 279         u32 grf_switch_reg;
 280         u32 grf_dsi0_mode;
 281         u32 grf_dsi0_mode_reg;
 282         unsigned int max_data_lanes;
 283 };
 284
 285 struct dw_mipi_dsi {
 286         struct drm_encoder encoder;
 287         struct drm_connector connector;
 288         struct mipi_dsi_host dsi_host;
 289         struct drm_panel *panel;
 290         struct device *dev;
 291         struct regmap *grf_regmap;
 292         void __iomem *base;
 293
 294         struct clk *pllref_clk;
 295         struct clk *pclk;
 296         struct clk *phy_cfg_clk;
 297
 298         int dpms_mode;
 299         unsigned int lane_mbps; /* per lane */
 300         u32 channel;
 301         u32 lanes;
 302         u32 format;
 303         u16 input_div;
 304         u16 feedback_div;
 305         unsigned long mode_flags;
 306
 307         const struct dw_mipi_dsi_plat_data *pdata;
 308 };
 309
 310 enum dw_mipi_dsi_mode {
 311         DW_MIPI_DSI_CMD_MODE,
 312         DW_MIPI_DSI_VID_MODE,
 313 };
 314
 315 struct dphy_pll_testdin_map {
 316         unsigned int max_mbps;
 317         u8 testdin;
 318 };
 319
 320 /* The table is based on 27MHz DPHY pll reference clock. */
 321 static const struct dphy_pll_testdin_map dptdin_map[] = {
 322         {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
 323         { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
 324         { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
 325         { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
 326         { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
 327         { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
 328         { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
 329         {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 330         {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 331         {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 332 };
 333
 334 static int max_mbps_to_testdin(unsigned int max_mbps)
 335 {
 336         int i;
 337
 338         for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
 339                 if (dptdin_map[i].max_mbps > max_mbps)
 340                         return dptdin_map[i].testdin;
 341
 342         return -EINVAL;
 343 }
 344
 345 /*
 346  * The controller should generate 2 frames before
 347  * preparing the peripheral.
 348  */
 349 static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode)
 350 {
 351         int refresh, two_frames;
 352
 353         refresh = drm_mode_vrefresh(mode);
 354         two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
 355         msleep(two_frames);
 356 }
 357
 358 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 359 {
 360         return container_of(host, struct dw_mipi_dsi, dsi_host);
 361 }
 362
 363 static inline struct dw_mipi_dsi *con_to_dsi(struct drm_connector *con)
 364 {
 365         return container_of(con, struct dw_mipi_dsi, connector);
 366 }
 367
 368 static inline struct dw_mipi_dsi *encoder_to_dsi(struct drm_encoder *encoder)
 369 {
 370         return container_of(encoder, struct dw_mipi_dsi, encoder);
 371 }
 372
 373 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 374 {
 375         writel(val, dsi->base + reg);
 376 }
 377
 378 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 379 {
 380         return readl(dsi->base + reg);
 381 }
 382
 383 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 384                                   u8 test_data)
 385 {
 386         /*
 387          * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
 388          * is latched internally as the current test code. Test data is
 389          * programmed internally by rising edge on TESTCLK.
 390          */
 391         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 392
 393         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
 394                                           PHY_TESTDIN(test_code));
 395
 396         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
 397
 398         dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
 399                                           PHY_TESTDIN(test_data));
 400
 401         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 402 }
 403
 404 /**
 405  * ns2bc - Nanoseconds to byte clock cycles
 406  */
 407 static inline unsigned int ns2bc(struct dw_mipi_dsi *dsi, int ns)
 408 {
 409         return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
 410 }
 411
 412 /**
 413  * ns2ui - Nanoseconds to UI time periods
 414  */
 415 static inline unsigned int ns2ui(struct dw_mipi_dsi *dsi, int ns)
 416 {
 417         return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
 418 }
 419
 420 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 421 {
 422         int ret, testdin, vco, val;
 423
 424         vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 425
 426         testdin = max_mbps_to_testdin(dsi->lane_mbps);
 427         if (testdin < 0) {
 428                 dev_err(dsi->dev,
 429                         "failed to get testdin for %dmbps lane clock\n",
 430                         dsi->lane_mbps);
 431                 return testdin;
 432         }
 433
 434         /* Start by clearing PHY state */
 435         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
 436         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
 437         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
 438
 439         ret = clk_prepare_enable(dsi->phy_cfg_clk);
 440         if (ret) {
 441                 dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
 442                 return ret;
 443         }
 444
 445         dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 446                                          VCO_RANGE_CON_SEL(vco) |
 447                                          VCO_IN_CAP_CON_LOW |
 448                                          REF_BIAS_CUR_SEL);
 449
 450         dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
 451         dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
 452                                          LPF_RESISTORS_20_KOHM);
 453
 454         dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
 455
 456         dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
 457         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 458                                          LOW_PROGRAM_EN);
 459         dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 460                                          HIGH_PROGRAM_EN);
 461         dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
 462
 463         dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
 464                                          BIASEXTR_SEL(BIASEXTR_127_7));
 465         dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
 466                                          BANDGAP_SEL(BANDGAP_96_10));
 467
 468         dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
 469                                          BIAS_BLOCK_ON | BANDGAP_ON);
 470
 471         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
 472                                          SETRD_MAX | TER_RESISTORS_ON);
 473         dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
 474                                          SETRD_MAX | POWER_MANAGE |
 475                                          TER_RESISTORS_ON);
 476
 477         dw_mipi_dsi_phy_write(dsi, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500));
 478         dw_mipi_dsi_phy_write(dsi, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
 479         dw_mipi_dsi_phy_write(dsi, 0x62, THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
 480         dw_mipi_dsi_phy_write(dsi, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
 481         dw_mipi_dsi_phy_write(dsi, 0x64, BIT(5) | ns2bc(dsi, 100));
 482         dw_mipi_dsi_phy_write(dsi, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7));
 483
 484         dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500));
 485         dw_mipi_dsi_phy_write(dsi, 0x71,
 486                               THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 5));
 487         dw_mipi_dsi_phy_write(dsi, 0x72,
 488                               THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
 489         dw_mipi_dsi_phy_write(dsi, 0x73,
 490                               THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
 491         dw_mipi_dsi_phy_write(dsi, 0x74, BIT(5) | ns2bc(dsi, 100));
 492
 493         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 494                                      PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 495
 496         ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 497                                  val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 498         if (ret < 0) {
 499                 dev_err(dsi->dev, "failed to wait for phy lock state\n");
 500                 goto phy_init_end;
 501         }
 502
 503         ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 504                                  val, val & STOP_STATE_CLK_LANE, 1000,
 505                                  PHY_STATUS_TIMEOUT_US);
 506         if (ret < 0)
 507                 dev_err(dsi->dev,
 508                         "failed to wait for phy clk lane stop state\n");
 509
 510 phy_init_end:
 511         clk_disable_unprepare(dsi->phy_cfg_clk);
 512
 513         return ret;
 514 }
 515
 516 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
 517                                     struct drm_display_mode *mode)
 518 {
 519         unsigned int i, pre;
 520         unsigned long mpclk, pllref, tmp;
 521         unsigned int m = 1, n = 1, target_mbps = 1000;
 522         unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
 523         int bpp;
 524
 525         bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 526         if (bpp < 0) {
 527                 dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
 528                         dsi->format);
 529                 return bpp;
 530         }
 531
 532         mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
 533         if (mpclk) {
 534                 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
 535                 tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
 536                 if (tmp < max_mbps)
 537                         target_mbps = tmp;
 538                 else
 539                         dev_err(dsi->dev, "DPHY clock frequency is out of range\n");
 540         }
 541
 542         pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
 543         tmp = pllref;
 544
 545         /*
 546          * The limits on the PLL divisor are:
 547          *
 548          *      5MHz <= (pllref / n) <= 40MHz
 549          *
 550          * we walk over these values in descreasing order so that if we hit
 551          * an exact match for target_mbps it is more likely that "m" will be
 552          * even.
 553          *
 554          * TODO: ensure that "m" is even after this loop.
 555          */
 556         for (i = pllref / 5; i > (pllref / 40); i--) {
 557                 pre = pllref / i;
 558                 if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
 559                         tmp = target_mbps % pre;
 560                         n = i;
 561                         m = target_mbps / pre;
 562                 }
 563                 if (tmp == 0)
 564                         break;
 565         }
 566
 567         dsi->lane_mbps = pllref / n * m;
 568         dsi->input_div = n;
 569         dsi->feedback_div = m;
 570
 571         return 0;
 572 }
 573
 574 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 575                                    struct mipi_dsi_device *device)
 576 {
 577         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 578
 579         if (device->lanes > dsi->pdata->max_data_lanes) {
 580                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 581                         device->lanes);
 582                 return -EINVAL;
 583         }
 584
 585         dsi->lanes = device->lanes;
 586         dsi->channel = device->channel;
 587         dsi->format = device->format;
 588         dsi->mode_flags = device->mode_flags;
 589         dsi->panel = of_drm_find_panel(device->dev.of_node);
 590         if (dsi->panel)
 591                 return drm_panel_attach(dsi->panel, &dsi->connector);
 592
 593         return -EINVAL;
 594 }
 595
 596 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 597                                    struct mipi_dsi_device *device)
 598 {
 599         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 600
 601         drm_panel_detach(dsi->panel);
 602
 603         return 0;
 604 }
 605
 606 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
 607                                    const struct mipi_dsi_msg *msg)
 608 {
 609         bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
 610         u32 val = 0;
 611
 612         if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
 613                 val |= EN_ACK_RQST;
 614         if (lpm)
 615                 val |= CMD_MODE_ALL_LP;
 616
 617         dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
 618         dsi_write(dsi, DSI_CMD_MODE_CFG, val);
 619 }
 620
 621 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 622 {
 623         int ret;
 624         u32 val, mask;
 625
 626         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 627                                  val, !(val & GEN_CMD_FULL), 1000,
 628                                  CMD_PKT_STATUS_TIMEOUT_US);
 629         if (ret < 0) {
 630                 dev_err(dsi->dev, "failed to get available command FIFO\n");
 631                 return ret;
 632         }
 633
 634         dsi_write(dsi, DSI_GEN_HDR, hdr_val);
 635
 636         mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
 637         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 638                                  val, (val & mask) == mask,
 639                                  1000, CMD_PKT_STATUS_TIMEOUT_US);
 640         if (ret < 0) {
 641                 dev_err(dsi->dev, "failed to write command FIFO\n");
 642                 return ret;
 643         }
 644
 645         return 0;
 646 }
 647
 648 static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
 649                                        const struct mipi_dsi_msg *msg)
 650 {
 651         const u8 *tx_buf = msg->tx_buf;
 652         u16 data = 0;
 653         u32 val;
 654
 655         if (msg->tx_len > 0)
 656                 data |= tx_buf[0];
 657         if (msg->tx_len > 1)
 658                 data |= tx_buf[1] << 8;
 659
 660         if (msg->tx_len > 2) {
 661                 dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
 662                         msg->tx_len);
 663                 return -EINVAL;
 664         }
 665
 666         val = GEN_HDATA(data) | GEN_HTYPE(msg->type);
 667         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
 668 }
 669
 670 static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
 671                                       const struct mipi_dsi_msg *msg)
 672 {
 673         const u8 *tx_buf = msg->tx_buf;
 674         int len = msg->tx_len, pld_data_bytes = sizeof(u32), ret;
 675         u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
 676         u32 remainder;
 677         u32 val;
 678
 679         if (msg->tx_len < 3) {
 680                 dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
 681                         msg->tx_len);
 682                 return -EINVAL;
 683         }
 684
 685         while (DIV_ROUND_UP(len, pld_data_bytes)) {
 686                 if (len < pld_data_bytes) {
 687                         remainder = 0;
 688                         memcpy(&remainder, tx_buf, len);
 689                         dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
 690                         len = 0;
 691                 } else {
 692                         memcpy(&remainder, tx_buf, pld_data_bytes);
 693                         dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
 694                         tx_buf += pld_data_bytes;
 695                         len -= pld_data_bytes;
 696                 }
 697
 698                 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 699                                          val, !(val & GEN_PLD_W_FULL), 1000,
 700                                          CMD_PKT_STATUS_TIMEOUT_US);
 701                 if (ret < 0) {
 702                         dev_err(dsi->dev,
 703                                 "failed to get available write payload FIFO\n");
 704                         return ret;
 705                 }
 706         }
 707
 708         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val);
 709 }
 710
 711 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 712                                          const struct mipi_dsi_msg *msg)
 713 {
 714         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 715         int ret;
 716
 717         dw_mipi_message_config(dsi, msg);
 718
 719         switch (msg->type) {
 720         case MIPI_DSI_DCS_SHORT_WRITE:
 721         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 722         case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
 723                 ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
 724                 break;
 725         case MIPI_DSI_DCS_LONG_WRITE:
 726                 ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
 727                 break;
 728         default:
 729                 dev_err(dsi->dev, "unsupported message type 0x%02x\n",
 730                         msg->type);
 731                 ret = -EINVAL;
 732         }
 733
 734         return ret;
 735 }
 736
 737 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 738         .attach = dw_mipi_dsi_host_attach,
 739         .detach = dw_mipi_dsi_host_detach,
 740         .transfer = dw_mipi_dsi_host_transfer,
 741 };
 742
 743 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 744 {
 745         u32 val;
 746
 747         val = ENABLE_LOW_POWER;
 748
 749         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 750                 val |= VID_MODE_TYPE_BURST;
 751         else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 752                 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
 753         else
 754                 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
 755
 756         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 757 }
 758
 759 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 760                                  enum dw_mipi_dsi_mode mode)
 761 {
 762         if (mode == DW_MIPI_DSI_CMD_MODE) {
 763                 dsi_write(dsi, DSI_PWR_UP, RESET);
 764                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 765                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 766         } else {
 767                 dsi_write(dsi, DSI_PWR_UP, RESET);
 768                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 769                 dw_mipi_dsi_video_mode_config(dsi);
 770                 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 771                 dsi_write(dsi, DSI_PWR_UP, POWERUP);
 772         }
 773 }
 774
 775 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
 776 {
 777         dsi_write(dsi, DSI_PWR_UP, RESET);
 778         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 779 }
 780
 781 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 782 {
 783         /*
 784          * The maximum permitted escape clock is 20MHz and it is derived from
 785          * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:
 786          *
 787          *     (lane_mbps >> 3) / esc_clk_division < 20
 788          * which is:
 789          *     (lane_mbps >> 3) / 20 > esc_clk_division
 790          */
 791         u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
 792
 793         dsi_write(dsi, DSI_PWR_UP, RESET);
 794         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 795                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 796         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
 797                   TX_ESC_CLK_DIVIDSION(esc_clk_division));
 798 }
 799
 800 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 801                                    struct drm_display_mode *mode)
 802 {
 803         u32 val = 0, color = 0;
 804
 805         switch (dsi->format) {
 806         case MIPI_DSI_FMT_RGB888:
 807                 color = DPI_COLOR_CODING_24BIT;
 808                 break;
 809         case MIPI_DSI_FMT_RGB666:
 810                 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
 811                 break;
 812         case MIPI_DSI_FMT_RGB666_PACKED:
 813                 color = DPI_COLOR_CODING_18BIT_1;
 814                 break;
 815         case MIPI_DSI_FMT_RGB565:
 816                 color = DPI_COLOR_CODING_16BIT_1;
 817                 break;
 818         }
 819
 820         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 821                 val |= VSYNC_ACTIVE_LOW;
 822         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 823                 val |= HSYNC_ACTIVE_LOW;
 824
 825         dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
 826         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 827         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 828         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 829                   | INVACT_LPCMD_TIME(4));
 830 }
 831
 832 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 833 {
 834         dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
 835 }
 836
 837 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 838                                             struct drm_display_mode *mode)
 839 {
 840         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
 841 }
 842
 843 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 844 {
 845         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 846         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 847         dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 848 }
 849
 850 /* Get lane byte clock cycles. */
 851 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 852                                            struct drm_display_mode *mode,
 853                                            u32 hcomponent)
 854 {
 855         u32 frac, lbcc;
 856
 857         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 858
 859         frac = lbcc % mode->clock;
 860         lbcc = lbcc / mode->clock;
 861         if (frac)
 862                 lbcc++;
 863
 864         return lbcc;
 865 }
 866
 867 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
 868                                           struct drm_display_mode *mode)
 869 {
 870         u32 htotal, hsa, hbp, lbcc;
 871
 872         htotal = mode->htotal;
 873         hsa = mode->hsync_end - mode->hsync_start;
 874         hbp = mode->htotal - mode->hsync_end;
 875
 876         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
 877         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 878
 879         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
 880         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 881
 882         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
 883         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 884 }
 885
 886 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
 887                                                struct drm_display_mode *mode)
 888 {
 889         u32 vactive, vsa, vfp, vbp;
 890
 891         vactive = mode->vdisplay;
 892         vsa = mode->vsync_end - mode->vsync_start;
 893         vfp = mode->vsync_start - mode->vdisplay;
 894         vbp = mode->vtotal - mode->vsync_end;
 895
 896         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 897         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 898         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 899         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 900 }
 901
 902 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 903 {
 904         dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
 905                   | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
 906
 907         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 908                   | PHY_CLKLP2HS_TIME(0x40));
 909 }
 910
 911 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 912 {
 913         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 914                   N_LANES(dsi->lanes));
 915 }
 916
 917 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 918 {
 919         dsi_read(dsi, DSI_INT_ST0);
 920         dsi_read(dsi, DSI_INT_ST1);
 921         dsi_write(dsi, DSI_INT_MSK0, 0);
 922         dsi_write(dsi, DSI_INT_MSK1, 0);
 923 }
 924
 925 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 926 {
 927         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 928
 929         if (dsi->dpms_mode != DRM_MODE_DPMS_ON)
 930                 return;
 931
 932         if (clk_prepare_enable(dsi->pclk)) {
 933                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 934                 return;
 935         }
 936
 937         drm_panel_disable(dsi->panel);
 938
 939         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 940         drm_panel_unprepare(dsi->panel);
 941
 942         dw_mipi_dsi_disable(dsi);
 943         pm_runtime_put(dsi->dev);
 944         clk_disable_unprepare(dsi->pclk);
 945         dsi->dpms_mode = DRM_MODE_DPMS_OFF;
 946 }
 947
 948 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 949 {
 950         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
 951         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 952         const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 953         int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
 954         u32 val;
 955         int ret;
 956
 957         ret = dw_mipi_dsi_get_lane_bps(dsi, mode);
 958         if (ret < 0)
 959                 return;
 960
 961         if (dsi->dpms_mode == DRM_MODE_DPMS_ON)
 962                 return;
 963
 964         if (clk_prepare_enable(dsi->pclk)) {
 965                 dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
 966                 return;
 967         }
 968
 969         pm_runtime_get_sync(dsi->dev);
 970         dw_mipi_dsi_init(dsi);
 971         dw_mipi_dsi_dpi_config(dsi, mode);
 972         dw_mipi_dsi_packet_handler_config(dsi);
 973         dw_mipi_dsi_video_mode_config(dsi);
 974         dw_mipi_dsi_video_packet_config(dsi, mode);
 975         dw_mipi_dsi_command_mode_config(dsi);
 976         dw_mipi_dsi_line_timer_config(dsi, mode);
 977         dw_mipi_dsi_vertical_timing_config(dsi, mode);
 978         dw_mipi_dsi_dphy_timing_config(dsi);
 979         dw_mipi_dsi_dphy_interface_config(dsi);
 980         dw_mipi_dsi_clear_err(dsi);
 981
 982         if (pdata->grf_dsi0_mode_reg)
 983                 regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
 984                              pdata->grf_dsi0_mode);
 985
 986         dw_mipi_dsi_phy_init(dsi);
 987         dw_mipi_dsi_wait_for_two_frames(mode);
 988
 989         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
 990         if (drm_panel_prepare(dsi->panel))
 991                 dev_err(dsi->dev, "failed to prepare panel\n");
 992
 993         dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
 994         drm_panel_enable(dsi->panel);
 995
 996         clk_disable_unprepare(dsi->pclk);
 997
 998         if (mux)
 999                 val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
1000         else
1001                 val = pdata->dsi0_en_bit << 16;
1002
1003         regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
1004         dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
1005         dsi->dpms_mode = DRM_MODE_DPMS_ON;
1006 }
1007
1008 static int
1009 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
1010                                  struct drm_crtc_state *crtc_state,
1011                                  struct drm_connector_state *conn_state)
1012 {
1013         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1014         struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
1015
1016         switch (dsi->format) {
1017         case MIPI_DSI_FMT_RGB888:
1018                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1019                 break;
1020         case MIPI_DSI_FMT_RGB666:
1021                 s->output_mode = ROCKCHIP_OUT_MODE_P666;
1022                 break;
1023         case MIPI_DSI_FMT_RGB565:
1024                 s->output_mode = ROCKCHIP_OUT_MODE_P565;
1025                 break;
1026         default:
1027                 WARN_ON(1);
1028                 return -EINVAL;
1029         }
1030
1031         s->output_type = DRM_MODE_CONNECTOR_DSI;
1032
1033         return 0;
1034 }
1035
1036 static const struct drm_encoder_helper_funcs
1037 dw_mipi_dsi_encoder_helper_funcs = {
1038         .enable = dw_mipi_dsi_encoder_enable,
1039         .disable = dw_mipi_dsi_encoder_disable,
1040         .atomic_check = dw_mipi_dsi_encoder_atomic_check,
1041 };
1042
1043 static const struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = {
1044         .destroy = drm_encoder_cleanup,
1045 };
1046
1047 static int dw_mipi_dsi_connector_get_modes(struct drm_connector *connector)
1048 {
1049         struct dw_mipi_dsi *dsi = con_to_dsi(connector);
1050
1051         return drm_panel_get_modes(dsi->panel);
1052 }
1053
1054 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
1055         .get_modes = dw_mipi_dsi_connector_get_modes,
1056 };
1057
1058 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector *connector)
1059 {
1060         drm_connector_unregister(connector);
1061         drm_connector_cleanup(connector);
1062 }
1063
1064 static const struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs = {
1065         .dpms = drm_atomic_helper_connector_dpms,
1066         .fill_modes = drm_helper_probe_single_connector_modes,
1067         .destroy = dw_mipi_dsi_drm_connector_destroy,
1068         .reset = drm_atomic_helper_connector_reset,
1069         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1070         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1071 };
1072
1073 static int dw_mipi_dsi_register(struct drm_device *drm,
1074                                 struct dw_mipi_dsi *dsi)
1075 {
1076         struct drm_encoder *encoder = &dsi->encoder;
1077         struct drm_connector *connector = &dsi->connector;
1078         struct device *dev = dsi->dev;
1079         int ret;
1080
1081         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
1082                                                              dev->of_node);
1083         /*
1084          * If we failed to find the CRTC(s) which this encoder is
1085          * supposed to be connected to, it's because the CRTC has
1086          * not been registered yet.  Defer probing, and hope that
1087          * the required CRTC is added later.
1088          */
1089         if (encoder->possible_crtcs == 0)
1090                 return -EPROBE_DEFER;
1091
1092         drm_encoder_helper_add(&dsi->encoder,
1093                                &dw_mipi_dsi_encoder_helper_funcs);
1094         ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs,
1095                                DRM_MODE_ENCODER_DSI, NULL);
1096         if (ret) {
1097                 dev_err(dev, "Failed to initialize encoder with drm\n");
1098                 return ret;
1099         }
1100
1101         drm_connector_helper_add(connector,
1102                                  &dw_mipi_dsi_connector_helper_funcs);
1103
1104         drm_connector_init(drm, &dsi->connector,
1105                            &dw_mipi_dsi_atomic_connector_funcs,
1106                            DRM_MODE_CONNECTOR_DSI);
1107
1108         drm_mode_connector_attach_encoder(connector, encoder);
1109
1110         return 0;
1111 }
1112
1113 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi)
1114 {
1115         struct device_node *np = dsi->dev->of_node;
1116
1117         dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1118         if (IS_ERR(dsi->grf_regmap)) {
1119                 dev_err(dsi->dev, "Unable to get rockchip,grf\n");
1120                 return PTR_ERR(dsi->grf_regmap);
1121         }
1122
1123         return 0;
1124 }
1125
1126 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
1127         .dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
1128         .dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
1129         .grf_switch_reg = RK3288_GRF_SOC_CON6,
1130         .max_data_lanes = 4,
1131 };
1132
1133 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
1134         .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
1135         .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
1136         .grf_switch_reg = RK3399_GRF_SOC_CON19,
1137         .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
1138         .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
1139         .max_data_lanes = 4,
1140 };
1141
1142 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
1143         {
1144          .compatible = "rockchip,rk3288-mipi-dsi",
1145          .data = &rk3288_mipi_dsi_drv_data,
1146         }, {
1147          .compatible = "rockchip,rk3399-mipi-dsi",
1148          .data = &rk3399_mipi_dsi_drv_data,
1149         },
1150         { /* sentinel */ }
1151 };
1152 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids);
1153
1154 static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
1155                             void *data)
1156 {
1157         const struct of_device_id *of_id =
1158                         of_match_device(dw_mipi_dsi_dt_ids, dev);
1159         const struct dw_mipi_dsi_plat_data *pdata = of_id->data;
1160         struct platform_device *pdev = to_platform_device(dev);
1161         struct reset_control *apb_rst;
1162         struct drm_device *drm = data;
1163         struct dw_mipi_dsi *dsi;
1164         struct resource *res;
1165         int ret;
1166
1167         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1168         if (!dsi)
1169                 return -ENOMEM;
1170
1171         dsi->dev = dev;
1172         dsi->pdata = pdata;
1173         dsi->dpms_mode = DRM_MODE_DPMS_OFF;
1174
1175         ret = rockchip_mipi_parse_dt(dsi);
1176         if (ret)
1177                 return ret;
1178
1179         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1180         if (!res)
1181                 return -ENODEV;
1182
1183         dsi->base = devm_ioremap_resource(dev, res);
1184         if (IS_ERR(dsi->base))
1185                 return PTR_ERR(dsi->base);
1186
1187         dsi->pllref_clk = devm_clk_get(dev, "ref");
1188         if (IS_ERR(dsi->pllref_clk)) {
1189                 ret = PTR_ERR(dsi->pllref_clk);
1190                 dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
1191                 return ret;
1192         }
1193
1194         dsi->pclk = devm_clk_get(dev, "pclk");
1195         if (IS_ERR(dsi->pclk)) {
1196                 ret = PTR_ERR(dsi->pclk);
1197                 dev_err(dev, "Unable to get pclk: %d\n", ret);
1198                 return ret;
1199         }
1200
1201         /*
1202          * Note that the reset was not defined in the initial device tree, so
1203          * we have to be prepared for it not being found.
1204          */
1205         apb_rst = devm_reset_control_get(dev, "apb");
1206         if (IS_ERR(apb_rst)) {
1207                 ret = PTR_ERR(apb_rst);
1208                 if (ret == -ENOENT) {
1209                         apb_rst = NULL;
1210                 } else {
1211                         dev_err(dev, "Unable to get reset control: %d\n", ret);
1212                         return ret;
1213                 }
1214         }
1215
1216         if (apb_rst) {
1217                 ret = clk_prepare_enable(dsi->pclk);
1218                 if (ret) {
1219                         dev_err(dev, "%s: Failed to enable pclk\n", __func__);
1220                         return ret;
1221                 }
1222
1223                 reset_control_assert(apb_rst);
1224                 usleep_range(10, 20);
1225                 reset_control_deassert(apb_rst);
1226
1227                 clk_disable_unprepare(dsi->pclk);
1228         }
1229
1230         dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1231         if (IS_ERR(dsi->phy_cfg_clk)) {
1232                 ret = PTR_ERR(dsi->phy_cfg_clk);
1233                 if (ret != -ENOENT) {
1234                         dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret);
1235                         return ret;
1236                 }
1237                 dsi->phy_cfg_clk = NULL;
1238                 dev_dbg(dev, "have not phy_cfg_clk\n");
1239         }
1240
1241         ret = clk_prepare_enable(dsi->pllref_clk);
1242         if (ret) {
1243                 dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
1244                 return ret;
1245         }
1246
1247         ret = dw_mipi_dsi_register(drm, dsi);
1248         if (ret) {
1249                 dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
1250                 goto err_pllref;
1251         }
1252
1253         pm_runtime_enable(dev);
1254
1255         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1256         dsi->dsi_host.dev = dev;
1257         ret = mipi_dsi_host_register(&dsi->dsi_host);
1258         if (ret) {
1259                 dev_err(dev, "Failed to register MIPI host: %d\n", ret);
1260                 goto err_cleanup;
1261         }
1262
1263         if (!dsi->panel) {
1264                 ret = -EPROBE_DEFER;
1265                 goto err_mipi_dsi_host;
1266         }
1267
1268         dev_set_drvdata(dev, dsi);
1269         return 0;
1270
1271 err_mipi_dsi_host:
1272         mipi_dsi_host_unregister(&dsi->dsi_host);
1273 err_cleanup:
1274         drm_encoder_cleanup(&dsi->encoder);
1275         drm_connector_cleanup(&dsi->connector);
1276 err_pllref:
1277         clk_disable_unprepare(dsi->pllref_clk);
1278         return ret;
1279 }
1280
1281 static void dw_mipi_dsi_unbind(struct device *dev, struct device *master,
1282                                void *data)
1283 {
1284         struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
1285
1286         mipi_dsi_host_unregister(&dsi->dsi_host);
1287         pm_runtime_disable(dev);
1288         clk_disable_unprepare(dsi->pllref_clk);
1289 }
1290
1291 static const struct component_ops dw_mipi_dsi_ops = {
1292         .bind   = dw_mipi_dsi_bind,
1293         .unbind = dw_mipi_dsi_unbind,
1294 };
1295
1296 static int dw_mipi_dsi_probe(struct platform_device *pdev)
1297 {
1298         return component_add(&pdev->dev, &dw_mipi_dsi_ops);
1299 }
1300
1301 static int dw_mipi_dsi_remove(struct platform_device *pdev)
1302 {
1303         component_del(&pdev->dev, &dw_mipi_dsi_ops);
1304         return 0;
1305 }
1306
1307 static struct platform_driver dw_mipi_dsi_driver = {
1308         .probe          = dw_mipi_dsi_probe,
1309         .remove         = dw_mipi_dsi_remove,
1310         .driver         = {
1311                 .of_match_table = dw_mipi_dsi_dt_ids,
1312                 .name   = DRIVER_NAME,
1313         },
1314 };
1315 module_platform_driver(dw_mipi_dsi_driver);
1316
1317 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1318 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1319 MODULE_LICENSE("GPL");
1320 MODULE_ALIAS("platform:" DRIVER_NAME);