2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/component.h>
11 #include <linux/iopoll.h>
12 #include <linux/math64.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/regmap.h>
16 #include <linux/mfd/syscon.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_mipi_dsi.h>
21 #include <drm/drm_of.h>
22 #include <drm/drm_panel.h>
24 #include <video/mipi_display.h>
26 #include "rockchip_drm_drv.h"
27 #include "rockchip_drm_vop.h"
29 #define DRIVER_NAME "dw-mipi-dsi"
31 #define GRF_SOC_CON6 0x025c
32 #define DSI0_SEL_VOP_LIT (1 << 6)
33 #define DSI1_SEL_VOP_LIT (1 << 9)
35 #define DSI_VERSION 0x00
36 #define DSI_PWR_UP 0x04
38 #define POWERUP BIT(0)
40 #define DSI_CLKMGR_CFG 0x08
41 #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8)
42 #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0)
44 #define DSI_DPI_VCID 0x0c
45 #define DPI_VID(vid) (((vid) & 0x3) << 0)
47 #define DSI_DPI_COLOR_CODING 0x10
48 #define EN18_LOOSELY BIT(8)
49 #define DPI_COLOR_CODING_16BIT_1 0x0
50 #define DPI_COLOR_CODING_16BIT_2 0x1
51 #define DPI_COLOR_CODING_16BIT_3 0x2
52 #define DPI_COLOR_CODING_18BIT_1 0x3
53 #define DPI_COLOR_CODING_18BIT_2 0x4
54 #define DPI_COLOR_CODING_24BIT 0x5
56 #define DSI_DPI_CFG_POL 0x14
57 #define COLORM_ACTIVE_LOW BIT(4)
58 #define SHUTD_ACTIVE_LOW BIT(3)
59 #define HSYNC_ACTIVE_LOW BIT(2)
60 #define VSYNC_ACTIVE_LOW BIT(1)
61 #define DATAEN_ACTIVE_LOW BIT(0)
63 #define DSI_DPI_LP_CMD_TIM 0x18
64 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
65 #define INVACT_LPCMD_TIME(p) ((p) & 0xff)
67 #define DSI_DBI_CFG 0x20
68 #define DSI_DBI_CMDSIZE 0x28
70 #define DSI_PCKHDL_CFG 0x2c
71 #define EN_CRC_RX BIT(4)
72 #define EN_ECC_RX BIT(3)
74 #define EN_EOTP_RX BIT(1)
75 #define EN_EOTP_TX BIT(0)
77 #define DSI_MODE_CFG 0x34
78 #define ENABLE_VIDEO_MODE 0
79 #define ENABLE_CMD_MODE BIT(0)
81 #define DSI_VID_MODE_CFG 0x38
82 #define FRAME_BTA_ACK BIT(14)
83 #define ENABLE_LOW_POWER (0x3f << 8)
84 #define ENABLE_LOW_POWER_MASK (0x3f << 8)
85 #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x2
86 #define VID_MODE_TYPE_MASK 0x3
88 #define DSI_VID_PKT_SIZE 0x3c
89 #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0)
90 #define VID_PKT_MAX_SIZE 0x3fff
92 #define DSI_VID_HSA_TIME 0x48
93 #define DSI_VID_HBP_TIME 0x4c
94 #define DSI_VID_HLINE_TIME 0x50
95 #define DSI_VID_VSA_LINES 0x54
96 #define DSI_VID_VBP_LINES 0x58
97 #define DSI_VID_VFP_LINES 0x5c
98 #define DSI_VID_VACTIVE_LINES 0x60
99 #define DSI_CMD_MODE_CFG 0x68
100 #define MAX_RD_PKT_SIZE_LP BIT(24)
101 #define DCS_LW_TX_LP BIT(19)
102 #define DCS_SR_0P_TX_LP BIT(18)
103 #define DCS_SW_1P_TX_LP BIT(17)
104 #define DCS_SW_0P_TX_LP BIT(16)
105 #define GEN_LW_TX_LP BIT(14)
106 #define GEN_SR_2P_TX_LP BIT(13)
107 #define GEN_SR_1P_TX_LP BIT(12)
108 #define GEN_SR_0P_TX_LP BIT(11)
109 #define GEN_SW_2P_TX_LP BIT(10)
110 #define GEN_SW_1P_TX_LP BIT(9)
111 #define GEN_SW_0P_TX_LP BIT(8)
112 #define EN_ACK_RQST BIT(1)
113 #define EN_TEAR_FX BIT(0)
115 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
128 #define DSI_GEN_HDR 0x6c
129 #define GEN_HDATA(data) (((data) & 0xffff) << 8)
130 #define GEN_HDATA_MASK (0xffff << 8)
131 #define GEN_HTYPE(type) (((type) & 0xff) << 0)
132 #define GEN_HTYPE_MASK 0xff
134 #define DSI_GEN_PLD_DATA 0x70
136 #define DSI_CMD_PKT_STATUS 0x74
137 #define GEN_CMD_EMPTY BIT(0)
138 #define GEN_CMD_FULL BIT(1)
139 #define GEN_PLD_W_EMPTY BIT(2)
140 #define GEN_PLD_W_FULL BIT(3)
141 #define GEN_PLD_R_EMPTY BIT(4)
142 #define GEN_PLD_R_FULL BIT(5)
143 #define GEN_RD_CMD_BUSY BIT(6)
145 #define DSI_TO_CNT_CFG 0x78
146 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
147 #define LPRX_TO_CNT(p) ((p) & 0xffff)
149 #define DSI_BTA_TO_CNT 0x8c
151 #define DSI_LPCLK_CTRL 0x94
152 #define AUTO_CLKLANE_CTRL BIT(1)
153 #define PHY_TXREQUESTCLKHS BIT(0)
155 #define DSI_PHY_TMR_LPCLK_CFG 0x98
156 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
157 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
159 #define DSI_PHY_TMR_CFG 0x9c
160 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
161 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
162 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
164 #define DSI_PHY_RSTZ 0xa0
165 #define PHY_DISFORCEPLL 0
166 #define PHY_ENFORCEPLL BIT(3)
167 #define PHY_DISABLECLK 0
168 #define PHY_ENABLECLK BIT(2)
170 #define PHY_UNRSTZ BIT(1)
171 #define PHY_SHUTDOWNZ 0
172 #define PHY_UNSHUTDOWNZ BIT(0)
174 #define DSI_PHY_IF_CFG 0xa4
175 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
176 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
178 #define DSI_PHY_STATUS 0xb0
180 #define STOP_STATE_CLK_LANE BIT(2)
182 #define DSI_PHY_TST_CTRL0 0xb4
183 #define PHY_TESTCLK BIT(1)
184 #define PHY_UNTESTCLK 0
185 #define PHY_TESTCLR BIT(0)
186 #define PHY_UNTESTCLR 0
188 #define DSI_PHY_TST_CTRL1 0xb8
189 #define PHY_TESTEN BIT(16)
190 #define PHY_UNTESTEN 0
191 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
192 #define PHY_TESTDIN(n) (((n) & 0xff) << 0)
194 #define DSI_INT_ST0 0xbc
195 #define DSI_INT_ST1 0xc0
196 #define DSI_INT_MSK0 0xc4
197 #define DSI_INT_MSK1 0xc8
199 #define PHY_STATUS_TIMEOUT_US 10000
200 #define CMD_PKT_STATUS_TIMEOUT_US 20000
202 #define BYPASS_VCO_RANGE BIT(7)
203 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
204 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
205 #define VCO_IN_CAP_CON_LOW (0x1 << 1)
206 #define VCO_IN_CAP_CON_HIGH (0x2 << 1)
207 #define REF_BIAS_CUR_SEL BIT(0)
209 #define CP_CURRENT_3MA BIT(3)
210 #define CP_PROGRAM_EN BIT(7)
211 #define LPF_PROGRAM_EN BIT(6)
212 #define LPF_RESISTORS_20_KOHM 0
214 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
216 #define INPUT_DIVIDER(val) ((val - 1) & 0x7f)
217 #define LOW_PROGRAM_EN 0
218 #define HIGH_PROGRAM_EN BIT(7)
219 #define LOOP_DIV_LOW_SEL(val) ((val - 1) & 0x1f)
220 #define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0x1f)
221 #define PLL_LOOP_DIV_EN BIT(5)
222 #define PLL_INPUT_DIV_EN BIT(4)
224 #define POWER_CONTROL BIT(6)
225 #define INTERNAL_REG_CURRENT BIT(3)
226 #define BIAS_BLOCK_ON BIT(2)
227 #define BANDGAP_ON BIT(0)
229 #define TER_RESISTOR_HIGH BIT(7)
230 #define TER_RESISTOR_LOW 0
231 #define LEVEL_SHIFTERS_ON BIT(6)
232 #define TER_CAL_DONE BIT(5)
233 #define SETRD_MAX (0x7 << 2)
234 #define POWER_MANAGE BIT(1)
235 #define TER_RESISTORS_ON BIT(0)
237 #define BIASEXTR_SEL(val) ((val) & 0x7)
238 #define BANDGAP_SEL(val) ((val) & 0x7)
239 #define TLP_PROGRAM_EN BIT(7)
240 #define THS_PRE_PROGRAM_EN BIT(7)
241 #define THS_ZERO_PROGRAM_EN BIT(6)
265 struct dw_mipi_dsi_plat_data
{
266 unsigned int max_data_lanes
;
267 enum drm_mode_status (*mode_valid
)(struct drm_connector
*connector
,
268 struct drm_display_mode
*mode
);
272 struct drm_encoder encoder
;
273 struct drm_connector connector
;
274 struct mipi_dsi_host dsi_host
;
275 struct drm_panel
*panel
;
277 struct regmap
*grf_regmap
;
280 struct clk
*pllref_clk
;
283 unsigned int lane_mbps
; /* per lane */
290 const struct dw_mipi_dsi_plat_data
*pdata
;
293 enum dw_mipi_dsi_mode
{
294 DW_MIPI_DSI_CMD_MODE
,
295 DW_MIPI_DSI_VID_MODE
,
298 struct dphy_pll_testdin_map
{
299 unsigned int max_mbps
;
303 /* The table is based on 27MHz DPHY pll reference clock. */
304 static const struct dphy_pll_testdin_map dptdin_map
[] = {
305 { 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
306 { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
307 { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
308 { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
309 { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
310 { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
311 { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
312 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
313 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
314 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
317 static int max_mbps_to_testdin(unsigned int max_mbps
)
321 for (i
= 0; i
< ARRAY_SIZE(dptdin_map
); i
++)
322 if (dptdin_map
[i
].max_mbps
> max_mbps
)
323 return dptdin_map
[i
].testdin
;
329 * The controller should generate 2 frames before
330 * preparing the peripheral.
332 static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode
*mode
)
334 int refresh
, two_frames
;
336 refresh
= drm_mode_vrefresh(mode
);
337 two_frames
= DIV_ROUND_UP(MSEC_PER_SEC
, refresh
) * 2;
341 static inline struct dw_mipi_dsi
*host_to_dsi(struct mipi_dsi_host
*host
)
343 return container_of(host
, struct dw_mipi_dsi
, dsi_host
);
346 static inline struct dw_mipi_dsi
*con_to_dsi(struct drm_connector
*con
)
348 return container_of(con
, struct dw_mipi_dsi
, connector
);
351 static inline struct dw_mipi_dsi
*encoder_to_dsi(struct drm_encoder
*encoder
)
353 return container_of(encoder
, struct dw_mipi_dsi
, encoder
);
355 static inline void dsi_write(struct dw_mipi_dsi
*dsi
, u32 reg
, u32 val
)
357 writel(val
, dsi
->base
+ reg
);
360 static inline u32
dsi_read(struct dw_mipi_dsi
*dsi
, u32 reg
)
362 return readl(dsi
->base
+ reg
);
365 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi
*dsi
, u8 test_code
,
369 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
370 * is latched internally as the current test code. Test data is
371 * programmed internally by rising edge on TESTCLK.
373 dsi_write(dsi
, DSI_PHY_TST_CTRL0
, PHY_TESTCLK
| PHY_UNTESTCLR
);
375 dsi_write(dsi
, DSI_PHY_TST_CTRL1
, PHY_TESTEN
| PHY_TESTDOUT(0) |
376 PHY_TESTDIN(test_code
));
378 dsi_write(dsi
, DSI_PHY_TST_CTRL0
, PHY_UNTESTCLK
| PHY_UNTESTCLR
);
380 dsi_write(dsi
, DSI_PHY_TST_CTRL1
, PHY_UNTESTEN
| PHY_TESTDOUT(0) |
381 PHY_TESTDIN(test_data
));
383 dsi_write(dsi
, DSI_PHY_TST_CTRL0
, PHY_TESTCLK
| PHY_UNTESTCLR
);
386 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi
*dsi
)
388 int ret
, testdin
, vco
, val
;
390 vco
= (dsi
->lane_mbps
< 200) ? 0 : (dsi
->lane_mbps
+ 100) / 200;
392 testdin
= max_mbps_to_testdin(dsi
->lane_mbps
);
395 "failed to get testdin for %dmbps lane clock\n",
400 dsi_write(dsi
, DSI_PWR_UP
, POWERUP
);
402 dw_mipi_dsi_phy_write(dsi
, 0x10, BYPASS_VCO_RANGE
|
403 VCO_RANGE_CON_SEL(vco
) |
407 dw_mipi_dsi_phy_write(dsi
, 0x11, CP_CURRENT_3MA
);
408 dw_mipi_dsi_phy_write(dsi
, 0x12, CP_PROGRAM_EN
| LPF_PROGRAM_EN
|
409 LPF_RESISTORS_20_KOHM
);
411 dw_mipi_dsi_phy_write(dsi
, 0x44, HSFREQRANGE_SEL(testdin
));
413 dw_mipi_dsi_phy_write(dsi
, 0x19, PLL_LOOP_DIV_EN
| PLL_INPUT_DIV_EN
);
414 dw_mipi_dsi_phy_write(dsi
, 0x17, INPUT_DIVIDER(dsi
->input_div
));
415 dw_mipi_dsi_phy_write(dsi
, 0x18, LOOP_DIV_LOW_SEL(dsi
->feedback_div
) |
417 dw_mipi_dsi_phy_write(dsi
, 0x18, LOOP_DIV_HIGH_SEL(dsi
->feedback_div
) |
420 dw_mipi_dsi_phy_write(dsi
, 0x20, POWER_CONTROL
| INTERNAL_REG_CURRENT
|
421 BIAS_BLOCK_ON
| BANDGAP_ON
);
423 dw_mipi_dsi_phy_write(dsi
, 0x21, TER_RESISTOR_LOW
| TER_CAL_DONE
|
424 SETRD_MAX
| TER_RESISTORS_ON
);
425 dw_mipi_dsi_phy_write(dsi
, 0x21, TER_RESISTOR_HIGH
| LEVEL_SHIFTERS_ON
|
426 SETRD_MAX
| POWER_MANAGE
|
429 dw_mipi_dsi_phy_write(dsi
, 0x22, LOW_PROGRAM_EN
|
430 BIASEXTR_SEL(BIASEXTR_127_7
));
431 dw_mipi_dsi_phy_write(dsi
, 0x22, HIGH_PROGRAM_EN
|
432 BANDGAP_SEL(BANDGAP_96_10
));
434 dw_mipi_dsi_phy_write(dsi
, 0x70, TLP_PROGRAM_EN
| 0xf);
435 dw_mipi_dsi_phy_write(dsi
, 0x71, THS_PRE_PROGRAM_EN
| 0x55);
436 dw_mipi_dsi_phy_write(dsi
, 0x72, THS_ZERO_PROGRAM_EN
| 0xa);
438 dsi_write(dsi
, DSI_PHY_RSTZ
, PHY_ENFORCEPLL
| PHY_ENABLECLK
|
439 PHY_UNRSTZ
| PHY_UNSHUTDOWNZ
);
442 ret
= readx_poll_timeout(readl
, dsi
->base
+ DSI_PHY_STATUS
,
443 val
, val
& LOCK
, 1000, PHY_STATUS_TIMEOUT_US
);
445 dev_err(dsi
->dev
, "failed to wait for phy lock state\n");
449 ret
= readx_poll_timeout(readl
, dsi
->base
+ DSI_PHY_STATUS
,
450 val
, val
& STOP_STATE_CLK_LANE
, 1000,
451 PHY_STATUS_TIMEOUT_US
);
454 "failed to wait for phy clk lane stop state\n");
461 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi
*dsi
,
462 struct drm_display_mode
*mode
)
465 unsigned long mpclk
, pllref
, tmp
;
466 unsigned int m
= 1, n
= 1, target_mbps
= 1000;
467 unsigned int max_mbps
= dptdin_map
[ARRAY_SIZE(dptdin_map
) - 1].max_mbps
;
470 bpp
= mipi_dsi_pixel_format_to_bpp(dsi
->format
);
472 dev_err(dsi
->dev
, "failed to get bpp for pixel format %d\n",
477 mpclk
= DIV_ROUND_UP(mode
->clock
, MSEC_PER_SEC
);
479 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
480 tmp
= mpclk
* (bpp
/ dsi
->lanes
) * 10 / 9;
484 dev_err(dsi
->dev
, "DPHY clock frequency is out of range\n");
487 pllref
= DIV_ROUND_UP(clk_get_rate(dsi
->pllref_clk
), USEC_PER_SEC
);
490 for (i
= 1; i
< 6; i
++) {
492 if ((tmp
> (target_mbps
% pre
)) && (target_mbps
/ pre
< 512)) {
493 tmp
= target_mbps
% pre
;
495 m
= target_mbps
/ pre
;
501 dsi
->lane_mbps
= pllref
/ n
* m
;
503 dsi
->feedback_div
= m
;
508 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host
*host
,
509 struct mipi_dsi_device
*device
)
511 struct dw_mipi_dsi
*dsi
= host_to_dsi(host
);
513 if (device
->lanes
> dsi
->pdata
->max_data_lanes
) {
514 dev_err(dsi
->dev
, "the number of data lanes(%u) is too many\n",
519 if (!(device
->mode_flags
& MIPI_DSI_MODE_VIDEO_BURST
) ||
520 !(device
->mode_flags
& MIPI_DSI_MODE_VIDEO_SYNC_PULSE
)) {
521 dev_err(dsi
->dev
, "device mode is unsupported\n");
525 dsi
->lanes
= device
->lanes
;
526 dsi
->channel
= device
->channel
;
527 dsi
->format
= device
->format
;
528 dsi
->panel
= of_drm_find_panel(device
->dev
.of_node
);
530 return drm_panel_attach(dsi
->panel
, &dsi
->connector
);
535 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host
*host
,
536 struct mipi_dsi_device
*device
)
538 struct dw_mipi_dsi
*dsi
= host_to_dsi(host
);
540 drm_panel_detach(dsi
->panel
);
545 static void dw_mipi_message_config(struct dw_mipi_dsi
*dsi
,
546 const struct mipi_dsi_msg
*msg
)
548 bool lpm
= msg
->flags
& MIPI_DSI_MSG_USE_LPM
;
551 if (msg
->flags
& MIPI_DSI_MSG_REQ_ACK
)
554 val
|= CMD_MODE_ALL_LP
;
556 dsi_write(dsi
, DSI_LPCLK_CTRL
, lpm
? 0 : PHY_TXREQUESTCLKHS
);
557 dsi_write(dsi
, DSI_CMD_MODE_CFG
, val
);
560 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi
*dsi
, u32 hdr_val
)
565 ret
= readx_poll_timeout(readl
, dsi
->base
+ DSI_CMD_PKT_STATUS
,
566 val
, !(val
& GEN_CMD_FULL
), 1000,
567 CMD_PKT_STATUS_TIMEOUT_US
);
569 dev_err(dsi
->dev
, "failed to get available command FIFO\n");
573 dsi_write(dsi
, DSI_GEN_HDR
, hdr_val
);
575 mask
= GEN_CMD_EMPTY
| GEN_PLD_W_EMPTY
;
576 ret
= readx_poll_timeout(readl
, dsi
->base
+ DSI_CMD_PKT_STATUS
,
577 val
, (val
& mask
) == mask
,
578 1000, CMD_PKT_STATUS_TIMEOUT_US
);
580 dev_err(dsi
->dev
, "failed to write command FIFO\n");
587 static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi
*dsi
,
588 const struct mipi_dsi_msg
*msg
)
590 const u8
*tx_buf
= msg
->tx_buf
;
597 data
|= tx_buf
[1] << 8;
599 if (msg
->tx_len
> 2) {
600 dev_err(dsi
->dev
, "too long tx buf length %zu for short write\n",
605 val
= GEN_HDATA(data
) | GEN_HTYPE(msg
->type
);
606 return dw_mipi_dsi_gen_pkt_hdr_write(dsi
, val
);
609 static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi
*dsi
,
610 const struct mipi_dsi_msg
*msg
)
612 const u8
*tx_buf
= msg
->tx_buf
;
613 int len
= msg
->tx_len
, pld_data_bytes
= sizeof(u32
), ret
;
614 u32 hdr_val
= GEN_HDATA(msg
->tx_len
) | GEN_HTYPE(msg
->type
);
618 if (msg
->tx_len
< 3) {
619 dev_err(dsi
->dev
, "wrong tx buf length %zu for long write\n",
624 while (DIV_ROUND_UP(len
, pld_data_bytes
)) {
625 if (len
< pld_data_bytes
) {
627 memcpy(&remainder
, tx_buf
, len
);
628 dsi_write(dsi
, DSI_GEN_PLD_DATA
, remainder
);
631 memcpy(&remainder
, tx_buf
, pld_data_bytes
);
632 dsi_write(dsi
, DSI_GEN_PLD_DATA
, remainder
);
633 tx_buf
+= pld_data_bytes
;
634 len
-= pld_data_bytes
;
637 ret
= readx_poll_timeout(readl
, dsi
->base
+ DSI_CMD_PKT_STATUS
,
638 val
, !(val
& GEN_PLD_W_FULL
), 1000,
639 CMD_PKT_STATUS_TIMEOUT_US
);
642 "failed to get available write payload FIFO\n");
647 return dw_mipi_dsi_gen_pkt_hdr_write(dsi
, hdr_val
);
650 static ssize_t
dw_mipi_dsi_host_transfer(struct mipi_dsi_host
*host
,
651 const struct mipi_dsi_msg
*msg
)
653 struct dw_mipi_dsi
*dsi
= host_to_dsi(host
);
656 dw_mipi_message_config(dsi
, msg
);
659 case MIPI_DSI_DCS_SHORT_WRITE
:
660 case MIPI_DSI_DCS_SHORT_WRITE_PARAM
:
661 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE
:
662 ret
= dw_mipi_dsi_dcs_short_write(dsi
, msg
);
664 case MIPI_DSI_DCS_LONG_WRITE
:
665 ret
= dw_mipi_dsi_dcs_long_write(dsi
, msg
);
668 dev_err(dsi
->dev
, "unsupported message type 0x%02x\n",
676 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops
= {
677 .attach
= dw_mipi_dsi_host_attach
,
678 .detach
= dw_mipi_dsi_host_detach
,
679 .transfer
= dw_mipi_dsi_host_transfer
,
682 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi
*dsi
)
686 val
= VID_MODE_TYPE_BURST_SYNC_PULSES
| ENABLE_LOW_POWER
;
688 dsi_write(dsi
, DSI_VID_MODE_CFG
, val
);
691 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi
*dsi
,
692 enum dw_mipi_dsi_mode mode
)
694 if (mode
== DW_MIPI_DSI_CMD_MODE
) {
695 dsi_write(dsi
, DSI_PWR_UP
, RESET
);
696 dsi_write(dsi
, DSI_MODE_CFG
, ENABLE_CMD_MODE
);
697 dsi_write(dsi
, DSI_PWR_UP
, POWERUP
);
699 dsi_write(dsi
, DSI_PWR_UP
, RESET
);
700 dsi_write(dsi
, DSI_MODE_CFG
, ENABLE_VIDEO_MODE
);
701 dw_mipi_dsi_video_mode_config(dsi
);
702 dsi_write(dsi
, DSI_LPCLK_CTRL
, PHY_TXREQUESTCLKHS
);
703 dsi_write(dsi
, DSI_PWR_UP
, POWERUP
);
707 static void dw_mipi_dsi_disable(struct dw_mipi_dsi
*dsi
)
709 dsi_write(dsi
, DSI_PWR_UP
, RESET
);
710 dsi_write(dsi
, DSI_PHY_RSTZ
, PHY_RSTZ
);
713 static void dw_mipi_dsi_init(struct dw_mipi_dsi
*dsi
)
716 * The maximum permitted escape clock is 20MHz and it is derived from
717 * lanebyteclk, which is running at "lane_mbps / 8". Thus we want:
719 * (lane_mbps >> 3) / esc_clk_division < 20
721 * (lane_mbps >> 3) / 20 > esc_clk_division
723 u32 esc_clk_division
= (dsi
->lane_mbps
>> 3) / 20 + 1;
725 dsi_write(dsi
, DSI_PWR_UP
, RESET
);
726 dsi_write(dsi
, DSI_PHY_RSTZ
, PHY_DISFORCEPLL
| PHY_DISABLECLK
727 | PHY_RSTZ
| PHY_SHUTDOWNZ
);
728 dsi_write(dsi
, DSI_CLKMGR_CFG
, TO_CLK_DIVIDSION(10) |
729 TX_ESC_CLK_DIVIDSION(esc_clk_division
));
732 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi
*dsi
,
733 struct drm_display_mode
*mode
)
735 u32 val
= 0, color
= 0;
737 switch (dsi
->format
) {
738 case MIPI_DSI_FMT_RGB888
:
739 color
= DPI_COLOR_CODING_24BIT
;
741 case MIPI_DSI_FMT_RGB666
:
742 color
= DPI_COLOR_CODING_18BIT_2
| EN18_LOOSELY
;
744 case MIPI_DSI_FMT_RGB666_PACKED
:
745 color
= DPI_COLOR_CODING_18BIT_1
;
747 case MIPI_DSI_FMT_RGB565
:
748 color
= DPI_COLOR_CODING_16BIT_1
;
752 if (!(mode
->flags
& DRM_MODE_FLAG_PVSYNC
))
753 val
|= VSYNC_ACTIVE_LOW
;
754 if (!(mode
->flags
& DRM_MODE_FLAG_PHSYNC
))
755 val
|= HSYNC_ACTIVE_LOW
;
757 dsi_write(dsi
, DSI_DPI_VCID
, DPI_VID(dsi
->channel
));
758 dsi_write(dsi
, DSI_DPI_COLOR_CODING
, color
);
759 dsi_write(dsi
, DSI_DPI_CFG_POL
, val
);
760 dsi_write(dsi
, DSI_DPI_LP_CMD_TIM
, OUTVACT_LPCMD_TIME(4)
761 | INVACT_LPCMD_TIME(4));
764 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi
*dsi
)
766 dsi_write(dsi
, DSI_PCKHDL_CFG
, EN_CRC_RX
| EN_ECC_RX
| EN_BTA
);
769 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi
*dsi
,
770 struct drm_display_mode
*mode
)
772 dsi_write(dsi
, DSI_VID_PKT_SIZE
, VID_PKT_SIZE(mode
->hdisplay
));
775 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi
*dsi
)
777 dsi_write(dsi
, DSI_TO_CNT_CFG
, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
778 dsi_write(dsi
, DSI_BTA_TO_CNT
, 0xd00);
779 dsi_write(dsi
, DSI_MODE_CFG
, ENABLE_CMD_MODE
);
782 /* Get lane byte clock cycles. */
783 static u32
dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi
*dsi
,
784 struct drm_display_mode
*mode
,
789 lbcc
= hcomponent
* dsi
->lane_mbps
* MSEC_PER_SEC
/ 8;
791 frac
= lbcc
% mode
->clock
;
792 lbcc
= lbcc
/ mode
->clock
;
799 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi
*dsi
,
800 struct drm_display_mode
*mode
)
802 u32 htotal
, hsa
, hbp
, lbcc
;
804 htotal
= mode
->htotal
;
805 hsa
= mode
->hsync_end
- mode
->hsync_start
;
806 hbp
= mode
->htotal
- mode
->hsync_end
;
808 lbcc
= dw_mipi_dsi_get_hcomponent_lbcc(dsi
, mode
, htotal
);
809 dsi_write(dsi
, DSI_VID_HLINE_TIME
, lbcc
);
811 lbcc
= dw_mipi_dsi_get_hcomponent_lbcc(dsi
, mode
, hsa
);
812 dsi_write(dsi
, DSI_VID_HSA_TIME
, lbcc
);
814 lbcc
= dw_mipi_dsi_get_hcomponent_lbcc(dsi
, mode
, hbp
);
815 dsi_write(dsi
, DSI_VID_HBP_TIME
, lbcc
);
818 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi
*dsi
,
819 struct drm_display_mode
*mode
)
821 u32 vactive
, vsa
, vfp
, vbp
;
823 vactive
= mode
->vdisplay
;
824 vsa
= mode
->vsync_end
- mode
->vsync_start
;
825 vfp
= mode
->vsync_start
- mode
->vdisplay
;
826 vbp
= mode
->vtotal
- mode
->vsync_end
;
828 dsi_write(dsi
, DSI_VID_VACTIVE_LINES
, vactive
);
829 dsi_write(dsi
, DSI_VID_VSA_LINES
, vsa
);
830 dsi_write(dsi
, DSI_VID_VFP_LINES
, vfp
);
831 dsi_write(dsi
, DSI_VID_VBP_LINES
, vbp
);
834 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi
*dsi
)
836 dsi_write(dsi
, DSI_PHY_TMR_CFG
, PHY_HS2LP_TIME(0x40)
837 | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
839 dsi_write(dsi
, DSI_PHY_TMR_LPCLK_CFG
, PHY_CLKHS2LP_TIME(0x40)
840 | PHY_CLKLP2HS_TIME(0x40));
843 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi
*dsi
)
845 dsi_write(dsi
, DSI_PHY_IF_CFG
, PHY_STOP_WAIT_TIME(0x20) |
846 N_LANES(dsi
->lanes
));
849 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi
*dsi
)
851 dsi_read(dsi
, DSI_INT_ST0
);
852 dsi_read(dsi
, DSI_INT_ST1
);
853 dsi_write(dsi
, DSI_INT_MSK0
, 0);
854 dsi_write(dsi
, DSI_INT_MSK1
, 0);
857 static void dw_mipi_dsi_encoder_disable(struct drm_encoder
*encoder
)
859 struct dw_mipi_dsi
*dsi
= encoder_to_dsi(encoder
);
861 if (clk_prepare_enable(dsi
->pclk
)) {
862 dev_err(dsi
->dev
, "%s: Failed to enable pclk\n", __func__
);
866 drm_panel_disable(dsi
->panel
);
868 dw_mipi_dsi_set_mode(dsi
, DW_MIPI_DSI_CMD_MODE
);
869 drm_panel_unprepare(dsi
->panel
);
871 dw_mipi_dsi_disable(dsi
);
872 clk_disable_unprepare(dsi
->pclk
);
875 static void dw_mipi_dsi_encoder_enable(struct drm_encoder
*encoder
)
877 struct dw_mipi_dsi
*dsi
= encoder_to_dsi(encoder
);
878 struct drm_display_mode
*mode
= &encoder
->crtc
->state
->adjusted_mode
;
879 int mux
= drm_of_encoder_active_endpoint_id(dsi
->dev
->of_node
, encoder
);
883 ret
= dw_mipi_dsi_get_lane_bps(dsi
, mode
);
887 if (clk_prepare_enable(dsi
->pclk
)) {
888 dev_err(dsi
->dev
, "%s: Failed to enable pclk\n", __func__
);
892 dw_mipi_dsi_init(dsi
);
893 dw_mipi_dsi_dpi_config(dsi
, mode
);
894 dw_mipi_dsi_packet_handler_config(dsi
);
895 dw_mipi_dsi_video_mode_config(dsi
);
896 dw_mipi_dsi_video_packet_config(dsi
, mode
);
897 dw_mipi_dsi_command_mode_config(dsi
);
898 dw_mipi_dsi_line_timer_config(dsi
, mode
);
899 dw_mipi_dsi_vertical_timing_config(dsi
, mode
);
900 dw_mipi_dsi_dphy_timing_config(dsi
);
901 dw_mipi_dsi_dphy_interface_config(dsi
);
902 dw_mipi_dsi_clear_err(dsi
);
904 dw_mipi_dsi_phy_init(dsi
);
905 dw_mipi_dsi_wait_for_two_frames(mode
);
907 dw_mipi_dsi_set_mode(dsi
, DW_MIPI_DSI_CMD_MODE
);
908 if (drm_panel_prepare(dsi
->panel
))
909 dev_err(dsi
->dev
, "failed to prepare panel\n");
911 dw_mipi_dsi_set_mode(dsi
, DW_MIPI_DSI_VID_MODE
);
912 drm_panel_enable(dsi
->panel
);
914 clk_disable_unprepare(dsi
->pclk
);
917 val
= DSI0_SEL_VOP_LIT
| (DSI0_SEL_VOP_LIT
<< 16);
919 val
= DSI0_SEL_VOP_LIT
<< 16;
921 regmap_write(dsi
->grf_regmap
, GRF_SOC_CON6
, val
);
922 dev_dbg(dsi
->dev
, "vop %s output to dsi0\n", (mux
) ? "LIT" : "BIG");
926 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder
*encoder
,
927 struct drm_crtc_state
*crtc_state
,
928 struct drm_connector_state
*conn_state
)
930 struct rockchip_crtc_state
*s
= to_rockchip_crtc_state(crtc_state
);
931 struct dw_mipi_dsi
*dsi
= encoder_to_dsi(encoder
);
933 switch (dsi
->format
) {
934 case MIPI_DSI_FMT_RGB888
:
935 s
->output_mode
= ROCKCHIP_OUT_MODE_P888
;
937 case MIPI_DSI_FMT_RGB666
:
938 s
->output_mode
= ROCKCHIP_OUT_MODE_P666
;
940 case MIPI_DSI_FMT_RGB565
:
941 s
->output_mode
= ROCKCHIP_OUT_MODE_P565
;
948 s
->output_type
= DRM_MODE_CONNECTOR_DSI
;
953 static struct drm_encoder_helper_funcs
954 dw_mipi_dsi_encoder_helper_funcs
= {
955 .enable
= dw_mipi_dsi_encoder_enable
,
956 .disable
= dw_mipi_dsi_encoder_disable
,
957 .atomic_check
= dw_mipi_dsi_encoder_atomic_check
,
960 static struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs
= {
961 .destroy
= drm_encoder_cleanup
,
964 static int dw_mipi_dsi_connector_get_modes(struct drm_connector
*connector
)
966 struct dw_mipi_dsi
*dsi
= con_to_dsi(connector
);
968 return drm_panel_get_modes(dsi
->panel
);
971 static enum drm_mode_status
dw_mipi_dsi_mode_valid(
972 struct drm_connector
*connector
,
973 struct drm_display_mode
*mode
)
975 struct dw_mipi_dsi
*dsi
= con_to_dsi(connector
);
977 enum drm_mode_status mode_status
= MODE_OK
;
979 if (dsi
->pdata
->mode_valid
)
980 mode_status
= dsi
->pdata
->mode_valid(connector
, mode
);
985 static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs
= {
986 .get_modes
= dw_mipi_dsi_connector_get_modes
,
987 .mode_valid
= dw_mipi_dsi_mode_valid
,
990 static void dw_mipi_dsi_drm_connector_destroy(struct drm_connector
*connector
)
992 drm_connector_unregister(connector
);
993 drm_connector_cleanup(connector
);
996 static struct drm_connector_funcs dw_mipi_dsi_atomic_connector_funcs
= {
997 .dpms
= drm_atomic_helper_connector_dpms
,
998 .fill_modes
= drm_helper_probe_single_connector_modes
,
999 .destroy
= dw_mipi_dsi_drm_connector_destroy
,
1000 .reset
= drm_atomic_helper_connector_reset
,
1001 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
1002 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
1005 static int dw_mipi_dsi_register(struct drm_device
*drm
,
1006 struct dw_mipi_dsi
*dsi
)
1008 struct drm_encoder
*encoder
= &dsi
->encoder
;
1009 struct drm_connector
*connector
= &dsi
->connector
;
1010 struct device
*dev
= dsi
->dev
;
1013 encoder
->possible_crtcs
= drm_of_find_possible_crtcs(drm
,
1016 * If we failed to find the CRTC(s) which this encoder is
1017 * supposed to be connected to, it's because the CRTC has
1018 * not been registered yet. Defer probing, and hope that
1019 * the required CRTC is added later.
1021 if (encoder
->possible_crtcs
== 0)
1022 return -EPROBE_DEFER
;
1024 drm_encoder_helper_add(&dsi
->encoder
,
1025 &dw_mipi_dsi_encoder_helper_funcs
);
1026 ret
= drm_encoder_init(drm
, &dsi
->encoder
, &dw_mipi_dsi_encoder_funcs
,
1027 DRM_MODE_ENCODER_DSI
, NULL
);
1029 dev_err(dev
, "Failed to initialize encoder with drm\n");
1033 drm_connector_helper_add(connector
,
1034 &dw_mipi_dsi_connector_helper_funcs
);
1036 drm_connector_init(drm
, &dsi
->connector
,
1037 &dw_mipi_dsi_atomic_connector_funcs
,
1038 DRM_MODE_CONNECTOR_DSI
);
1040 drm_mode_connector_attach_encoder(connector
, encoder
);
1045 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi
*dsi
)
1047 struct device_node
*np
= dsi
->dev
->of_node
;
1049 dsi
->grf_regmap
= syscon_regmap_lookup_by_phandle(np
, "rockchip,grf");
1050 if (IS_ERR(dsi
->grf_regmap
)) {
1051 dev_err(dsi
->dev
, "Unable to get rockchip,grf\n");
1052 return PTR_ERR(dsi
->grf_regmap
);
1058 static enum drm_mode_status
rk3288_mipi_dsi_mode_valid(
1059 struct drm_connector
*connector
,
1060 struct drm_display_mode
*mode
)
1063 * The VID_PKT_SIZE field in the DSI_VID_PKT_CFG
1064 * register is 11-bit.
1066 if (mode
->hdisplay
> 0x7ff)
1067 return MODE_BAD_HVALUE
;
1070 * The V_ACTIVE_LINES field in the DSI_VTIMING_CFG
1071 * register is 11-bit.
1073 if (mode
->vdisplay
> 0x7ff)
1074 return MODE_BAD_VVALUE
;
1079 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data
= {
1080 .max_data_lanes
= 4,
1081 .mode_valid
= rk3288_mipi_dsi_mode_valid
,
1084 static const struct of_device_id dw_mipi_dsi_dt_ids
[] = {
1086 .compatible
= "rockchip,rk3288-mipi-dsi",
1087 .data
= &rk3288_mipi_dsi_drv_data
,
1091 MODULE_DEVICE_TABLE(of
, dw_mipi_dsi_dt_ids
);
1093 static int dw_mipi_dsi_bind(struct device
*dev
, struct device
*master
,
1096 const struct of_device_id
*of_id
=
1097 of_match_device(dw_mipi_dsi_dt_ids
, dev
);
1098 const struct dw_mipi_dsi_plat_data
*pdata
= of_id
->data
;
1099 struct platform_device
*pdev
= to_platform_device(dev
);
1100 struct drm_device
*drm
= data
;
1101 struct dw_mipi_dsi
*dsi
;
1102 struct resource
*res
;
1105 dsi
= devm_kzalloc(dev
, sizeof(*dsi
), GFP_KERNEL
);
1112 ret
= rockchip_mipi_parse_dt(dsi
);
1116 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1120 dsi
->base
= devm_ioremap_resource(dev
, res
);
1121 if (IS_ERR(dsi
->base
))
1122 return PTR_ERR(dsi
->base
);
1124 dsi
->pllref_clk
= devm_clk_get(dev
, "ref");
1125 if (IS_ERR(dsi
->pllref_clk
)) {
1126 ret
= PTR_ERR(dsi
->pllref_clk
);
1127 dev_err(dev
, "Unable to get pll reference clock: %d\n", ret
);
1131 dsi
->pclk
= devm_clk_get(dev
, "pclk");
1132 if (IS_ERR(dsi
->pclk
)) {
1133 ret
= PTR_ERR(dsi
->pclk
);
1134 dev_err(dev
, "Unable to get pclk: %d\n", ret
);
1138 ret
= clk_prepare_enable(dsi
->pllref_clk
);
1140 dev_err(dev
, "%s: Failed to enable pllref_clk\n", __func__
);
1144 ret
= dw_mipi_dsi_register(drm
, dsi
);
1146 dev_err(dev
, "Failed to register mipi_dsi: %d\n", ret
);
1150 dev_set_drvdata(dev
, dsi
);
1152 dsi
->dsi_host
.ops
= &dw_mipi_dsi_host_ops
;
1153 dsi
->dsi_host
.dev
= dev
;
1154 return mipi_dsi_host_register(&dsi
->dsi_host
);
1157 clk_disable_unprepare(dsi
->pllref_clk
);
1161 static void dw_mipi_dsi_unbind(struct device
*dev
, struct device
*master
,
1164 struct dw_mipi_dsi
*dsi
= dev_get_drvdata(dev
);
1166 mipi_dsi_host_unregister(&dsi
->dsi_host
);
1167 clk_disable_unprepare(dsi
->pllref_clk
);
1170 static const struct component_ops dw_mipi_dsi_ops
= {
1171 .bind
= dw_mipi_dsi_bind
,
1172 .unbind
= dw_mipi_dsi_unbind
,
1175 static int dw_mipi_dsi_probe(struct platform_device
*pdev
)
1177 return component_add(&pdev
->dev
, &dw_mipi_dsi_ops
);
1180 static int dw_mipi_dsi_remove(struct platform_device
*pdev
)
1182 component_del(&pdev
->dev
, &dw_mipi_dsi_ops
);
1186 static struct platform_driver dw_mipi_dsi_driver
= {
1187 .probe
= dw_mipi_dsi_probe
,
1188 .remove
= dw_mipi_dsi_remove
,
1190 .of_match_table
= dw_mipi_dsi_dt_ids
,
1191 .name
= DRIVER_NAME
,
1194 module_platform_driver(dw_mipi_dsi_driver
);
1196 MODULE_DESCRIPTION("ROCKCHIP MIPI DSI host controller driver");
1197 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1198 MODULE_LICENSE("GPL");
1199 MODULE_ALIAS("platform:" DRIVER_NAME
);