2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_flip_work.h>
21 #include <drm/drm_plane_helper.h>
22 #ifdef CONFIG_DRM_ANALOGIX_DP
23 #include <drm/bridge/analogix_dp.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
30 #include <linux/iopoll.h>
32 #include <linux/of_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/component.h>
36 #include <linux/reset.h>
37 #include <linux/delay.h>
39 #include "rockchip_drm_drv.h"
40 #include "rockchip_drm_gem.h"
41 #include "rockchip_drm_fb.h"
42 #include "rockchip_drm_psr.h"
43 #include "rockchip_drm_vop.h"
45 #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
46 vop_mask_write(x, off, mask, shift, v, write_mask, true)
48 #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
49 vop_mask_write(x, off, mask, shift, v, write_mask, false)
51 #define REG_SET(x, base, reg, v, mode) \
52 __REG_SET_##mode(x, base + reg.offset, \
53 reg.mask, reg.shift, v, reg.write_mask)
54 #define REG_SET_MASK(x, base, reg, mask, v, mode) \
55 __REG_SET_##mode(x, base + reg.offset, \
56 mask, reg.shift, v, reg.write_mask)
58 #define VOP_WIN_SET(x, win, name, v) \
59 REG_SET(x, win->base, win->phy->name, v, RELAXED)
60 #define VOP_SCL_SET(x, win, name, v) \
61 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
62 #define VOP_SCL_SET_EXT(x, win, name, v) \
63 REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
64 #define VOP_CTRL_SET(x, name, v) \
65 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
67 #define VOP_INTR_GET(vop, name) \
68 vop_read_reg(vop, 0, &vop->data->ctrl->name)
70 #define VOP_INTR_SET(vop, name, mask, v) \
71 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
72 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
74 int i, reg = 0, mask = 0; \
75 for (i = 0; i < vop->data->intr->nintrs; i++) { \
76 if (vop->data->intr->intrs[i] & type) { \
81 VOP_INTR_SET(vop, name, mask, reg); \
83 #define VOP_INTR_GET_TYPE(vop, name, type) \
84 vop_get_intr_type(vop, &vop->data->intr->name, type)
86 #define VOP_WIN_GET(x, win, name) \
87 vop_read_reg(x, win->base, &win->phy->name)
89 #define VOP_WIN_GET_YRGBADDR(vop, win) \
90 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
92 #define to_vop(x) container_of(x, struct vop, crtc)
93 #define to_vop_win(x) container_of(x, struct vop_win, base)
100 struct drm_plane base
;
101 const struct vop_win_data
*data
;
106 struct drm_crtc crtc
;
108 struct drm_device
*drm_dev
;
111 /* mutex vsync_ work */
112 struct mutex vsync_mutex
;
113 bool vsync_work_pending
;
114 struct completion dsp_hold_completion
;
116 /* protected by dev->event_lock */
117 struct drm_pending_vblank_event
*event
;
119 struct drm_flip_work fb_unref_work
;
120 unsigned long pending
;
122 struct completion line_flag_completion
;
124 const struct vop_data
*data
;
129 /* physical map length of vop register */
132 /* one time only one process allowed to config the register */
134 /* lock vop irq reg */
143 /* vop share memory frequency */
147 struct reset_control
*dclk_rst
;
149 struct vop_win win
[];
152 static inline void vop_writel(struct vop
*vop
, uint32_t offset
, uint32_t v
)
154 writel(v
, vop
->regs
+ offset
);
155 vop
->regsbak
[offset
>> 2] = v
;
158 static inline uint32_t vop_readl(struct vop
*vop
, uint32_t offset
)
160 return readl(vop
->regs
+ offset
);
163 static inline uint32_t vop_read_reg(struct vop
*vop
, uint32_t base
,
164 const struct vop_reg
*reg
)
166 return (vop_readl(vop
, base
+ reg
->offset
) >> reg
->shift
) & reg
->mask
;
169 static inline void vop_mask_write(struct vop
*vop
, uint32_t offset
,
170 uint32_t mask
, uint32_t shift
, uint32_t v
,
171 bool write_mask
, bool relaxed
)
177 v
= ((v
<< shift
) & 0xffff) | (mask
<< (shift
+ 16));
179 uint32_t cached_val
= vop
->regsbak
[offset
>> 2];
181 v
= (cached_val
& ~(mask
<< shift
)) | ((v
& mask
) << shift
);
182 vop
->regsbak
[offset
>> 2] = v
;
186 writel_relaxed(v
, vop
->regs
+ offset
);
188 writel(v
, vop
->regs
+ offset
);
191 static inline uint32_t vop_get_intr_type(struct vop
*vop
,
192 const struct vop_reg
*reg
, int type
)
195 uint32_t regs
= vop_read_reg(vop
, 0, reg
);
197 for (i
= 0; i
< vop
->data
->intr
->nintrs
; i
++) {
198 if ((type
& vop
->data
->intr
->intrs
[i
]) && (regs
& 1 << i
))
199 ret
|= vop
->data
->intr
->intrs
[i
];
205 static inline void vop_cfg_done(struct vop
*vop
)
207 VOP_CTRL_SET(vop
, cfg_done
, 1);
210 static bool has_rb_swapped(uint32_t format
)
213 case DRM_FORMAT_XBGR8888
:
214 case DRM_FORMAT_ABGR8888
:
215 case DRM_FORMAT_BGR888
:
216 case DRM_FORMAT_BGR565
:
223 static enum vop_data_format
vop_convert_format(uint32_t format
)
226 case DRM_FORMAT_XRGB8888
:
227 case DRM_FORMAT_ARGB8888
:
228 case DRM_FORMAT_XBGR8888
:
229 case DRM_FORMAT_ABGR8888
:
230 return VOP_FMT_ARGB8888
;
231 case DRM_FORMAT_RGB888
:
232 case DRM_FORMAT_BGR888
:
233 return VOP_FMT_RGB888
;
234 case DRM_FORMAT_RGB565
:
235 case DRM_FORMAT_BGR565
:
236 return VOP_FMT_RGB565
;
237 case DRM_FORMAT_NV12
:
238 return VOP_FMT_YUV420SP
;
239 case DRM_FORMAT_NV16
:
240 return VOP_FMT_YUV422SP
;
241 case DRM_FORMAT_NV24
:
242 return VOP_FMT_YUV444SP
;
244 DRM_ERROR("unsupported format[%08x]\n", format
);
249 static bool is_yuv_support(uint32_t format
)
252 case DRM_FORMAT_NV12
:
253 case DRM_FORMAT_NV16
:
254 case DRM_FORMAT_NV24
:
261 static bool is_alpha_support(uint32_t format
)
264 case DRM_FORMAT_ARGB8888
:
265 case DRM_FORMAT_ABGR8888
:
272 static uint16_t scl_vop_cal_scale(enum scale_mode mode
, uint32_t src
,
273 uint32_t dst
, bool is_horizontal
,
274 int vsu_mode
, int *vskiplines
)
276 uint16_t val
= 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT
;
279 if (mode
== SCALE_UP
)
280 val
= GET_SCL_FT_BIC(src
, dst
);
281 else if (mode
== SCALE_DOWN
)
282 val
= GET_SCL_FT_BILI_DN(src
, dst
);
284 if (mode
== SCALE_UP
) {
285 if (vsu_mode
== SCALE_UP_BIL
)
286 val
= GET_SCL_FT_BILI_UP(src
, dst
);
288 val
= GET_SCL_FT_BIC(src
, dst
);
289 } else if (mode
== SCALE_DOWN
) {
291 *vskiplines
= scl_get_vskiplines(src
, dst
);
292 val
= scl_get_bili_dn_vskip(src
, dst
,
295 val
= GET_SCL_FT_BILI_DN(src
, dst
);
303 static void scl_vop_cal_scl_fac(struct vop
*vop
, const struct vop_win_data
*win
,
304 uint32_t src_w
, uint32_t src_h
, uint32_t dst_w
,
305 uint32_t dst_h
, uint32_t pixel_format
)
307 uint16_t yrgb_hor_scl_mode
, yrgb_ver_scl_mode
;
308 uint16_t cbcr_hor_scl_mode
= SCALE_NONE
;
309 uint16_t cbcr_ver_scl_mode
= SCALE_NONE
;
310 int hsub
= drm_format_horz_chroma_subsampling(pixel_format
);
311 int vsub
= drm_format_vert_chroma_subsampling(pixel_format
);
312 bool is_yuv
= is_yuv_support(pixel_format
);
313 uint16_t cbcr_src_w
= src_w
/ hsub
;
314 uint16_t cbcr_src_h
= src_h
/ vsub
;
321 DRM_DEV_ERROR(vop
->dev
, "Maximum dst width (3840) exceeded\n");
325 if (!win
->phy
->scl
->ext
) {
326 VOP_SCL_SET(vop
, win
, scale_yrgb_x
,
327 scl_cal_scale2(src_w
, dst_w
));
328 VOP_SCL_SET(vop
, win
, scale_yrgb_y
,
329 scl_cal_scale2(src_h
, dst_h
));
331 VOP_SCL_SET(vop
, win
, scale_cbcr_x
,
332 scl_cal_scale2(cbcr_src_w
, dst_w
));
333 VOP_SCL_SET(vop
, win
, scale_cbcr_y
,
334 scl_cal_scale2(cbcr_src_h
, dst_h
));
339 yrgb_hor_scl_mode
= scl_get_scl_mode(src_w
, dst_w
);
340 yrgb_ver_scl_mode
= scl_get_scl_mode(src_h
, dst_h
);
343 cbcr_hor_scl_mode
= scl_get_scl_mode(cbcr_src_w
, dst_w
);
344 cbcr_ver_scl_mode
= scl_get_scl_mode(cbcr_src_h
, dst_h
);
345 if (cbcr_hor_scl_mode
== SCALE_DOWN
)
346 lb_mode
= scl_vop_cal_lb_mode(dst_w
, true);
348 lb_mode
= scl_vop_cal_lb_mode(cbcr_src_w
, true);
350 if (yrgb_hor_scl_mode
== SCALE_DOWN
)
351 lb_mode
= scl_vop_cal_lb_mode(dst_w
, false);
353 lb_mode
= scl_vop_cal_lb_mode(src_w
, false);
356 VOP_SCL_SET_EXT(vop
, win
, lb_mode
, lb_mode
);
357 if (lb_mode
== LB_RGB_3840X2
) {
358 if (yrgb_ver_scl_mode
!= SCALE_NONE
) {
359 DRM_DEV_ERROR(vop
->dev
, "not allow yrgb ver scale\n");
362 if (cbcr_ver_scl_mode
!= SCALE_NONE
) {
363 DRM_DEV_ERROR(vop
->dev
, "not allow cbcr ver scale\n");
366 vsu_mode
= SCALE_UP_BIL
;
367 } else if (lb_mode
== LB_RGB_2560X4
) {
368 vsu_mode
= SCALE_UP_BIL
;
370 vsu_mode
= SCALE_UP_BIC
;
373 val
= scl_vop_cal_scale(yrgb_hor_scl_mode
, src_w
, dst_w
,
375 VOP_SCL_SET(vop
, win
, scale_yrgb_x
, val
);
376 val
= scl_vop_cal_scale(yrgb_ver_scl_mode
, src_h
, dst_h
,
377 false, vsu_mode
, &vskiplines
);
378 VOP_SCL_SET(vop
, win
, scale_yrgb_y
, val
);
380 VOP_SCL_SET_EXT(vop
, win
, vsd_yrgb_gt4
, vskiplines
== 4);
381 VOP_SCL_SET_EXT(vop
, win
, vsd_yrgb_gt2
, vskiplines
== 2);
383 VOP_SCL_SET_EXT(vop
, win
, yrgb_hor_scl_mode
, yrgb_hor_scl_mode
);
384 VOP_SCL_SET_EXT(vop
, win
, yrgb_ver_scl_mode
, yrgb_ver_scl_mode
);
385 VOP_SCL_SET_EXT(vop
, win
, yrgb_hsd_mode
, SCALE_DOWN_BIL
);
386 VOP_SCL_SET_EXT(vop
, win
, yrgb_vsd_mode
, SCALE_DOWN_BIL
);
387 VOP_SCL_SET_EXT(vop
, win
, yrgb_vsu_mode
, vsu_mode
);
389 val
= scl_vop_cal_scale(cbcr_hor_scl_mode
, cbcr_src_w
,
390 dst_w
, true, 0, NULL
);
391 VOP_SCL_SET(vop
, win
, scale_cbcr_x
, val
);
392 val
= scl_vop_cal_scale(cbcr_ver_scl_mode
, cbcr_src_h
,
393 dst_h
, false, vsu_mode
, &vskiplines
);
394 VOP_SCL_SET(vop
, win
, scale_cbcr_y
, val
);
396 VOP_SCL_SET_EXT(vop
, win
, vsd_cbcr_gt4
, vskiplines
== 4);
397 VOP_SCL_SET_EXT(vop
, win
, vsd_cbcr_gt2
, vskiplines
== 2);
398 VOP_SCL_SET_EXT(vop
, win
, cbcr_hor_scl_mode
, cbcr_hor_scl_mode
);
399 VOP_SCL_SET_EXT(vop
, win
, cbcr_ver_scl_mode
, cbcr_ver_scl_mode
);
400 VOP_SCL_SET_EXT(vop
, win
, cbcr_hsd_mode
, SCALE_DOWN_BIL
);
401 VOP_SCL_SET_EXT(vop
, win
, cbcr_vsd_mode
, SCALE_DOWN_BIL
);
402 VOP_SCL_SET_EXT(vop
, win
, cbcr_vsu_mode
, vsu_mode
);
406 static void vop_dsp_hold_valid_irq_enable(struct vop
*vop
)
410 if (WARN_ON(!vop
->is_enabled
))
413 spin_lock_irqsave(&vop
->irq_lock
, flags
);
415 VOP_INTR_SET_TYPE(vop
, clear
, DSP_HOLD_VALID_INTR
, 1);
416 VOP_INTR_SET_TYPE(vop
, enable
, DSP_HOLD_VALID_INTR
, 1);
418 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
421 static void vop_dsp_hold_valid_irq_disable(struct vop
*vop
)
425 if (WARN_ON(!vop
->is_enabled
))
428 spin_lock_irqsave(&vop
->irq_lock
, flags
);
430 VOP_INTR_SET_TYPE(vop
, enable
, DSP_HOLD_VALID_INTR
, 0);
432 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
436 * (1) each frame starts at the start of the Vsync pulse which is signaled by
437 * the "FRAME_SYNC" interrupt.
438 * (2) the active data region of each frame ends at dsp_vact_end
439 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
440 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
442 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
444 * LINE_FLAG -------------------------------+
448 * | Vsync | Vbp | Vactive | Vfp |
452 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
453 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
454 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
455 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
457 static bool vop_line_flag_irq_is_enabled(struct vop
*vop
)
459 uint32_t line_flag_irq
;
462 spin_lock_irqsave(&vop
->irq_lock
, flags
);
464 line_flag_irq
= VOP_INTR_GET_TYPE(vop
, enable
, LINE_FLAG_INTR
);
466 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
468 return !!line_flag_irq
;
471 static void vop_line_flag_irq_enable(struct vop
*vop
)
475 if (WARN_ON(!vop
->is_enabled
))
478 spin_lock_irqsave(&vop
->irq_lock
, flags
);
480 VOP_INTR_SET_TYPE(vop
, clear
, LINE_FLAG_INTR
, 1);
481 VOP_INTR_SET_TYPE(vop
, enable
, LINE_FLAG_INTR
, 1);
483 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
486 static void vop_line_flag_irq_disable(struct vop
*vop
)
490 if (WARN_ON(!vop
->is_enabled
))
493 spin_lock_irqsave(&vop
->irq_lock
, flags
);
495 VOP_INTR_SET_TYPE(vop
, enable
, LINE_FLAG_INTR
, 0);
497 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
500 static int vop_enable(struct drm_crtc
*crtc
)
502 struct vop
*vop
= to_vop(crtc
);
505 ret
= pm_runtime_get_sync(vop
->dev
);
507 dev_err(vop
->dev
, "failed to get pm runtime: %d\n", ret
);
511 ret
= clk_enable(vop
->hclk
);
512 if (WARN_ON(ret
< 0))
513 goto err_put_pm_runtime
;
515 ret
= clk_enable(vop
->dclk
);
516 if (WARN_ON(ret
< 0))
517 goto err_disable_hclk
;
519 ret
= clk_enable(vop
->aclk
);
520 if (WARN_ON(ret
< 0))
521 goto err_disable_dclk
;
524 * Slave iommu shares power, irq and clock with vop. It was associated
525 * automatically with this master device via common driver code.
526 * Now that we have enabled the clock we attach it to the shared drm
529 ret
= rockchip_drm_dma_attach_device(vop
->drm_dev
, vop
->dev
);
531 dev_err(vop
->dev
, "failed to attach dma mapping, %d\n", ret
);
532 goto err_disable_aclk
;
535 memcpy(vop
->regs
, vop
->regsbak
, vop
->len
);
537 * We need to make sure that all windows are disabled before we
538 * enable the crtc. Otherwise we might try to scan from a destroyed
541 for (i
= 0; i
< vop
->data
->win_size
; i
++) {
542 struct vop_win
*vop_win
= &vop
->win
[i
];
543 const struct vop_win_data
*win
= vop_win
->data
;
545 spin_lock(&vop
->reg_lock
);
546 VOP_WIN_SET(vop
, win
, enable
, 0);
547 spin_unlock(&vop
->reg_lock
);
553 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
555 vop
->is_enabled
= true;
557 spin_lock(&vop
->reg_lock
);
559 VOP_CTRL_SET(vop
, standby
, 0);
561 spin_unlock(&vop
->reg_lock
);
563 enable_irq(vop
->irq
);
565 drm_crtc_vblank_on(crtc
);
570 clk_disable(vop
->aclk
);
572 clk_disable(vop
->dclk
);
574 clk_disable(vop
->hclk
);
576 pm_runtime_put_sync(vop
->dev
);
580 static void vop_crtc_disable(struct drm_crtc
*crtc
)
582 struct vop
*vop
= to_vop(crtc
);
586 rockchip_drm_psr_deactivate(&vop
->crtc
);
588 drm_crtc_vblank_off(crtc
);
591 * Vop standby will take effect at end of current frame,
592 * if dsp hold valid irq happen, it means standby complete.
594 * we must wait standby complete when we want to disable aclk,
595 * if not, memory bus maybe dead.
597 reinit_completion(&vop
->dsp_hold_completion
);
598 vop_dsp_hold_valid_irq_enable(vop
);
600 spin_lock(&vop
->reg_lock
);
602 VOP_CTRL_SET(vop
, standby
, 1);
604 spin_unlock(&vop
->reg_lock
);
606 wait_for_completion(&vop
->dsp_hold_completion
);
608 vop_dsp_hold_valid_irq_disable(vop
);
610 disable_irq(vop
->irq
);
612 vop
->is_enabled
= false;
615 * vop standby complete, so iommu detach is safe.
617 rockchip_drm_dma_detach_device(vop
->drm_dev
, vop
->dev
);
619 clk_disable(vop
->dclk
);
620 clk_disable(vop
->aclk
);
621 clk_disable(vop
->hclk
);
622 pm_runtime_put(vop
->dev
);
624 if (crtc
->state
->event
&& !crtc
->state
->active
) {
625 spin_lock_irq(&crtc
->dev
->event_lock
);
626 drm_crtc_send_vblank_event(crtc
, crtc
->state
->event
);
627 spin_unlock_irq(&crtc
->dev
->event_lock
);
629 crtc
->state
->event
= NULL
;
633 static void vop_plane_destroy(struct drm_plane
*plane
)
635 drm_plane_cleanup(plane
);
638 static int vop_plane_atomic_check(struct drm_plane
*plane
,
639 struct drm_plane_state
*state
)
641 struct drm_crtc
*crtc
= state
->crtc
;
642 struct drm_crtc_state
*crtc_state
;
643 struct drm_framebuffer
*fb
= state
->fb
;
644 struct vop_win
*vop_win
= to_vop_win(plane
);
645 const struct vop_win_data
*win
= vop_win
->data
;
647 struct drm_rect clip
;
648 int min_scale
= win
->phy
->scl
? FRAC_16_16(1, 8) :
649 DRM_PLANE_HELPER_NO_SCALING
;
650 int max_scale
= win
->phy
->scl
? FRAC_16_16(8, 1) :
651 DRM_PLANE_HELPER_NO_SCALING
;
656 crtc_state
= drm_atomic_get_existing_crtc_state(state
->state
, crtc
);
657 if (WARN_ON(!crtc_state
))
662 clip
.x2
= crtc_state
->adjusted_mode
.hdisplay
;
663 clip
.y2
= crtc_state
->adjusted_mode
.vdisplay
;
665 ret
= drm_plane_helper_check_state(state
, &clip
,
666 min_scale
, max_scale
,
674 ret
= vop_convert_format(fb
->format
->format
);
679 * Src.x1 can be odd when do clip, but yuv plane start point
680 * need align with 2 pixel.
682 if (is_yuv_support(fb
->format
->format
) && ((state
->src
.x1
>> 16) % 2)) {
683 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
690 static void vop_plane_atomic_disable(struct drm_plane
*plane
,
691 struct drm_plane_state
*old_state
)
693 struct vop_win
*vop_win
= to_vop_win(plane
);
694 const struct vop_win_data
*win
= vop_win
->data
;
695 struct vop
*vop
= to_vop(old_state
->crtc
);
697 if (!old_state
->crtc
)
700 spin_lock(&vop
->reg_lock
);
702 VOP_WIN_SET(vop
, win
, enable
, 0);
704 spin_unlock(&vop
->reg_lock
);
707 static void vop_plane_atomic_update(struct drm_plane
*plane
,
708 struct drm_plane_state
*old_state
)
710 struct drm_plane_state
*state
= plane
->state
;
711 struct drm_crtc
*crtc
= state
->crtc
;
712 struct vop_win
*vop_win
= to_vop_win(plane
);
713 const struct vop_win_data
*win
= vop_win
->data
;
714 struct vop
*vop
= to_vop(state
->crtc
);
715 struct drm_framebuffer
*fb
= state
->fb
;
716 unsigned int actual_w
, actual_h
;
717 unsigned int dsp_stx
, dsp_sty
;
718 uint32_t act_info
, dsp_info
, dsp_st
;
719 struct drm_rect
*src
= &state
->src
;
720 struct drm_rect
*dest
= &state
->dst
;
721 struct drm_gem_object
*obj
, *uv_obj
;
722 struct rockchip_gem_object
*rk_obj
, *rk_uv_obj
;
723 unsigned long offset
;
730 * can't update plane when vop is disabled.
735 if (WARN_ON(!vop
->is_enabled
))
738 if (!state
->visible
) {
739 vop_plane_atomic_disable(plane
, old_state
);
743 obj
= rockchip_fb_get_gem_obj(fb
, 0);
744 rk_obj
= to_rockchip_obj(obj
);
746 actual_w
= drm_rect_width(src
) >> 16;
747 actual_h
= drm_rect_height(src
) >> 16;
748 act_info
= (actual_h
- 1) << 16 | ((actual_w
- 1) & 0xffff);
750 dsp_info
= (drm_rect_height(dest
) - 1) << 16;
751 dsp_info
|= (drm_rect_width(dest
) - 1) & 0xffff;
753 dsp_stx
= dest
->x1
+ crtc
->mode
.htotal
- crtc
->mode
.hsync_start
;
754 dsp_sty
= dest
->y1
+ crtc
->mode
.vtotal
- crtc
->mode
.vsync_start
;
755 dsp_st
= dsp_sty
<< 16 | (dsp_stx
& 0xffff);
757 offset
= (src
->x1
>> 16) * fb
->format
->cpp
[0];
758 offset
+= (src
->y1
>> 16) * fb
->pitches
[0];
759 dma_addr
= rk_obj
->dma_addr
+ offset
+ fb
->offsets
[0];
761 format
= vop_convert_format(fb
->format
->format
);
763 spin_lock(&vop
->reg_lock
);
765 VOP_WIN_SET(vop
, win
, format
, format
);
766 VOP_WIN_SET(vop
, win
, yrgb_vir
, DIV_ROUND_UP(fb
->pitches
[0], 4));
767 VOP_WIN_SET(vop
, win
, yrgb_mst
, dma_addr
);
768 if (is_yuv_support(fb
->format
->format
)) {
769 int hsub
= drm_format_horz_chroma_subsampling(fb
->format
->format
);
770 int vsub
= drm_format_vert_chroma_subsampling(fb
->format
->format
);
771 int bpp
= fb
->format
->cpp
[1];
773 uv_obj
= rockchip_fb_get_gem_obj(fb
, 1);
774 rk_uv_obj
= to_rockchip_obj(uv_obj
);
776 offset
= (src
->x1
>> 16) * bpp
/ hsub
;
777 offset
+= (src
->y1
>> 16) * fb
->pitches
[1] / vsub
;
779 dma_addr
= rk_uv_obj
->dma_addr
+ offset
+ fb
->offsets
[1];
780 VOP_WIN_SET(vop
, win
, uv_vir
, DIV_ROUND_UP(fb
->pitches
[1], 4));
781 VOP_WIN_SET(vop
, win
, uv_mst
, dma_addr
);
785 scl_vop_cal_scl_fac(vop
, win
, actual_w
, actual_h
,
786 drm_rect_width(dest
), drm_rect_height(dest
),
789 VOP_WIN_SET(vop
, win
, act_info
, act_info
);
790 VOP_WIN_SET(vop
, win
, dsp_info
, dsp_info
);
791 VOP_WIN_SET(vop
, win
, dsp_st
, dsp_st
);
793 rb_swap
= has_rb_swapped(fb
->format
->format
);
794 VOP_WIN_SET(vop
, win
, rb_swap
, rb_swap
);
796 if (is_alpha_support(fb
->format
->format
)) {
797 VOP_WIN_SET(vop
, win
, dst_alpha_ctl
,
798 DST_FACTOR_M0(ALPHA_SRC_INVERSE
));
799 val
= SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL
) |
800 SRC_ALPHA_M0(ALPHA_STRAIGHT
) |
801 SRC_BLEND_M0(ALPHA_PER_PIX
) |
802 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION
) |
803 SRC_FACTOR_M0(ALPHA_ONE
);
804 VOP_WIN_SET(vop
, win
, src_alpha_ctl
, val
);
806 VOP_WIN_SET(vop
, win
, src_alpha_ctl
, SRC_ALPHA_EN(0));
809 VOP_WIN_SET(vop
, win
, enable
, 1);
810 spin_unlock(&vop
->reg_lock
);
813 static const struct drm_plane_helper_funcs plane_helper_funcs
= {
814 .atomic_check
= vop_plane_atomic_check
,
815 .atomic_update
= vop_plane_atomic_update
,
816 .atomic_disable
= vop_plane_atomic_disable
,
819 static const struct drm_plane_funcs vop_plane_funcs
= {
820 .update_plane
= drm_atomic_helper_update_plane
,
821 .disable_plane
= drm_atomic_helper_disable_plane
,
822 .destroy
= vop_plane_destroy
,
823 .reset
= drm_atomic_helper_plane_reset
,
824 .atomic_duplicate_state
= drm_atomic_helper_plane_duplicate_state
,
825 .atomic_destroy_state
= drm_atomic_helper_plane_destroy_state
,
828 static int vop_crtc_enable_vblank(struct drm_crtc
*crtc
)
830 struct vop
*vop
= to_vop(crtc
);
833 if (WARN_ON(!vop
->is_enabled
))
836 spin_lock_irqsave(&vop
->irq_lock
, flags
);
838 VOP_INTR_SET_TYPE(vop
, clear
, FS_INTR
, 1);
839 VOP_INTR_SET_TYPE(vop
, enable
, FS_INTR
, 1);
841 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
846 static void vop_crtc_disable_vblank(struct drm_crtc
*crtc
)
848 struct vop
*vop
= to_vop(crtc
);
851 if (WARN_ON(!vop
->is_enabled
))
854 spin_lock_irqsave(&vop
->irq_lock
, flags
);
856 VOP_INTR_SET_TYPE(vop
, enable
, FS_INTR
, 0);
858 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
861 static bool vop_crtc_mode_fixup(struct drm_crtc
*crtc
,
862 const struct drm_display_mode
*mode
,
863 struct drm_display_mode
*adjusted_mode
)
865 struct vop
*vop
= to_vop(crtc
);
867 adjusted_mode
->clock
=
868 clk_round_rate(vop
->dclk
, mode
->clock
* 1000) / 1000;
873 static void vop_crtc_enable(struct drm_crtc
*crtc
)
875 struct vop
*vop
= to_vop(crtc
);
876 const struct vop_data
*vop_data
= vop
->data
;
877 struct rockchip_crtc_state
*s
= to_rockchip_crtc_state(crtc
->state
);
878 struct drm_display_mode
*adjusted_mode
= &crtc
->state
->adjusted_mode
;
879 u16 hsync_len
= adjusted_mode
->hsync_end
- adjusted_mode
->hsync_start
;
880 u16 hdisplay
= adjusted_mode
->hdisplay
;
881 u16 htotal
= adjusted_mode
->htotal
;
882 u16 hact_st
= adjusted_mode
->htotal
- adjusted_mode
->hsync_start
;
883 u16 hact_end
= hact_st
+ hdisplay
;
884 u16 vdisplay
= adjusted_mode
->vdisplay
;
885 u16 vtotal
= adjusted_mode
->vtotal
;
886 u16 vsync_len
= adjusted_mode
->vsync_end
- adjusted_mode
->vsync_start
;
887 u16 vact_st
= adjusted_mode
->vtotal
- adjusted_mode
->vsync_start
;
888 u16 vact_end
= vact_st
+ vdisplay
;
889 uint32_t pin_pol
, val
;
894 ret
= vop_enable(crtc
);
896 DRM_DEV_ERROR(vop
->dev
, "Failed to enable vop (%d)\n", ret
);
901 * If dclk rate is zero, mean that scanout is stop,
902 * we don't need wait any more.
904 if (clk_get_rate(vop
->dclk
)) {
906 * Rk3288 vop timing register is immediately, when configure
907 * display timing on display time, may cause tearing.
909 * Vop standby will take effect at end of current frame,
910 * if dsp hold valid irq happen, it means standby complete.
913 * standby and wait complete --> |----
917 * configure display timing --> |
922 reinit_completion(&vop
->dsp_hold_completion
);
923 vop_dsp_hold_valid_irq_enable(vop
);
925 spin_lock(&vop
->reg_lock
);
927 VOP_CTRL_SET(vop
, standby
, 1);
929 spin_unlock(&vop
->reg_lock
);
931 wait_for_completion(&vop
->dsp_hold_completion
);
933 vop_dsp_hold_valid_irq_disable(vop
);
936 pin_pol
= BIT(DCLK_INVERT
);
937 pin_pol
|= (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
) ?
938 BIT(HSYNC_POSITIVE
) : 0;
939 pin_pol
|= (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
) ?
940 BIT(VSYNC_POSITIVE
) : 0;
941 VOP_CTRL_SET(vop
, pin_pol
, pin_pol
);
943 switch (s
->output_type
) {
944 case DRM_MODE_CONNECTOR_LVDS
:
945 VOP_CTRL_SET(vop
, rgb_en
, 1);
946 VOP_CTRL_SET(vop
, rgb_pin_pol
, pin_pol
);
948 case DRM_MODE_CONNECTOR_eDP
:
949 VOP_CTRL_SET(vop
, edp_pin_pol
, pin_pol
);
950 VOP_CTRL_SET(vop
, edp_en
, 1);
952 case DRM_MODE_CONNECTOR_HDMIA
:
953 VOP_CTRL_SET(vop
, hdmi_pin_pol
, pin_pol
);
954 VOP_CTRL_SET(vop
, hdmi_en
, 1);
956 case DRM_MODE_CONNECTOR_DSI
:
957 VOP_CTRL_SET(vop
, mipi_pin_pol
, pin_pol
);
958 VOP_CTRL_SET(vop
, mipi_en
, 1);
960 case DRM_MODE_CONNECTOR_DisplayPort
:
961 pin_pol
&= ~BIT(DCLK_INVERT
);
962 VOP_CTRL_SET(vop
, dp_pin_pol
, pin_pol
);
963 VOP_CTRL_SET(vop
, dp_en
, 1);
966 DRM_DEV_ERROR(vop
->dev
, "unsupported connector_type [%d]\n",
971 * if vop is not support RGB10 output, need force RGB10 to RGB888.
973 if (s
->output_mode
== ROCKCHIP_OUT_MODE_AAAA
&&
974 !(vop_data
->feature
& VOP_FEATURE_OUTPUT_RGB10
))
975 s
->output_mode
= ROCKCHIP_OUT_MODE_P888
;
976 VOP_CTRL_SET(vop
, out_mode
, s
->output_mode
);
978 VOP_CTRL_SET(vop
, htotal_pw
, (htotal
<< 16) | hsync_len
);
981 VOP_CTRL_SET(vop
, hact_st_end
, val
);
982 VOP_CTRL_SET(vop
, hpost_st_end
, val
);
984 VOP_CTRL_SET(vop
, vtotal_pw
, (vtotal
<< 16) | vsync_len
);
987 VOP_CTRL_SET(vop
, vact_st_end
, val
);
988 VOP_CTRL_SET(vop
, vpost_st_end
, val
);
990 VOP_CTRL_SET(vop
, line_flag_num
[0], vact_end
);
992 clk_set_rate(vop
->dclk
, adjusted_mode
->clock
* 1000);
994 VOP_CTRL_SET(vop
, standby
, 0);
996 rockchip_drm_psr_activate(&vop
->crtc
);
999 static bool vop_fs_irq_is_pending(struct vop
*vop
)
1001 return VOP_INTR_GET_TYPE(vop
, status
, FS_INTR
);
1004 static void vop_wait_for_irq_handler(struct vop
*vop
)
1010 * Spin until frame start interrupt status bit goes low, which means
1011 * that interrupt handler was invoked and cleared it. The timeout of
1012 * 10 msecs is really too long, but it is just a safety measure if
1013 * something goes really wrong. The wait will only happen in the very
1014 * unlikely case of a vblank happening exactly at the same time and
1015 * shouldn't exceed microseconds range.
1017 ret
= readx_poll_timeout_atomic(vop_fs_irq_is_pending
, vop
, pending
,
1018 !pending
, 0, 10 * 1000);
1020 DRM_DEV_ERROR(vop
->dev
, "VOP vblank IRQ stuck for 10 ms\n");
1022 synchronize_irq(vop
->irq
);
1025 static void vop_crtc_atomic_flush(struct drm_crtc
*crtc
,
1026 struct drm_crtc_state
*old_crtc_state
)
1028 struct drm_atomic_state
*old_state
= old_crtc_state
->state
;
1029 struct drm_plane_state
*old_plane_state
;
1030 struct vop
*vop
= to_vop(crtc
);
1031 struct drm_plane
*plane
;
1034 if (WARN_ON(!vop
->is_enabled
))
1037 spin_lock(&vop
->reg_lock
);
1041 spin_unlock(&vop
->reg_lock
);
1044 * There is a (rather unlikely) possiblity that a vblank interrupt
1045 * fired before we set the cfg_done bit. To avoid spuriously
1046 * signalling flip completion we need to wait for it to finish.
1048 vop_wait_for_irq_handler(vop
);
1050 spin_lock_irq(&crtc
->dev
->event_lock
);
1051 if (crtc
->state
->event
) {
1052 WARN_ON(drm_crtc_vblank_get(crtc
) != 0);
1053 WARN_ON(vop
->event
);
1055 vop
->event
= crtc
->state
->event
;
1056 crtc
->state
->event
= NULL
;
1058 spin_unlock_irq(&crtc
->dev
->event_lock
);
1060 for_each_plane_in_state(old_state
, plane
, old_plane_state
, i
) {
1061 if (!old_plane_state
->fb
)
1064 if (old_plane_state
->fb
== plane
->state
->fb
)
1067 drm_framebuffer_reference(old_plane_state
->fb
);
1068 drm_flip_work_queue(&vop
->fb_unref_work
, old_plane_state
->fb
);
1069 set_bit(VOP_PENDING_FB_UNREF
, &vop
->pending
);
1070 WARN_ON(drm_crtc_vblank_get(crtc
) != 0);
1074 static void vop_crtc_atomic_begin(struct drm_crtc
*crtc
,
1075 struct drm_crtc_state
*old_crtc_state
)
1077 rockchip_drm_psr_flush(crtc
);
1080 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs
= {
1081 .enable
= vop_crtc_enable
,
1082 .disable
= vop_crtc_disable
,
1083 .mode_fixup
= vop_crtc_mode_fixup
,
1084 .atomic_flush
= vop_crtc_atomic_flush
,
1085 .atomic_begin
= vop_crtc_atomic_begin
,
1088 static void vop_crtc_destroy(struct drm_crtc
*crtc
)
1090 drm_crtc_cleanup(crtc
);
1093 static void vop_crtc_reset(struct drm_crtc
*crtc
)
1096 __drm_atomic_helper_crtc_destroy_state(crtc
->state
);
1099 crtc
->state
= kzalloc(sizeof(struct rockchip_crtc_state
), GFP_KERNEL
);
1101 crtc
->state
->crtc
= crtc
;
1104 static struct drm_crtc_state
*vop_crtc_duplicate_state(struct drm_crtc
*crtc
)
1106 struct rockchip_crtc_state
*rockchip_state
;
1108 rockchip_state
= kzalloc(sizeof(*rockchip_state
), GFP_KERNEL
);
1109 if (!rockchip_state
)
1112 __drm_atomic_helper_crtc_duplicate_state(crtc
, &rockchip_state
->base
);
1113 return &rockchip_state
->base
;
1116 static void vop_crtc_destroy_state(struct drm_crtc
*crtc
,
1117 struct drm_crtc_state
*state
)
1119 struct rockchip_crtc_state
*s
= to_rockchip_crtc_state(state
);
1121 __drm_atomic_helper_crtc_destroy_state(&s
->base
);
1125 #ifdef CONFIG_DRM_ANALOGIX_DP
1126 static struct drm_connector
*vop_get_edp_connector(struct vop
*vop
)
1128 struct drm_connector
*connector
;
1129 struct drm_connector_list_iter conn_iter
;
1131 drm_connector_list_iter_begin(vop
->drm_dev
, &conn_iter
);
1132 drm_for_each_connector_iter(connector
, &conn_iter
) {
1133 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
) {
1134 drm_connector_list_iter_end(&conn_iter
);
1138 drm_connector_list_iter_end(&conn_iter
);
1143 static int vop_crtc_set_crc_source(struct drm_crtc
*crtc
,
1144 const char *source_name
, size_t *values_cnt
)
1146 struct vop
*vop
= to_vop(crtc
);
1147 struct drm_connector
*connector
;
1150 connector
= vop_get_edp_connector(vop
);
1156 if (source_name
&& strcmp(source_name
, "auto") == 0)
1157 ret
= analogix_dp_start_crc(connector
);
1158 else if (!source_name
)
1159 ret
= analogix_dp_stop_crc(connector
);
1166 static int vop_crtc_set_crc_source(struct drm_crtc
*crtc
,
1167 const char *source_name
, size_t *values_cnt
)
1173 static const struct drm_crtc_funcs vop_crtc_funcs
= {
1174 .set_config
= drm_atomic_helper_set_config
,
1175 .page_flip
= drm_atomic_helper_page_flip
,
1176 .destroy
= vop_crtc_destroy
,
1177 .reset
= vop_crtc_reset
,
1178 .atomic_duplicate_state
= vop_crtc_duplicate_state
,
1179 .atomic_destroy_state
= vop_crtc_destroy_state
,
1180 .enable_vblank
= vop_crtc_enable_vblank
,
1181 .disable_vblank
= vop_crtc_disable_vblank
,
1182 .set_crc_source
= vop_crtc_set_crc_source
,
1185 static void vop_fb_unref_worker(struct drm_flip_work
*work
, void *val
)
1187 struct vop
*vop
= container_of(work
, struct vop
, fb_unref_work
);
1188 struct drm_framebuffer
*fb
= val
;
1190 drm_crtc_vblank_put(&vop
->crtc
);
1191 drm_framebuffer_unreference(fb
);
1194 static void vop_handle_vblank(struct vop
*vop
)
1196 struct drm_device
*drm
= vop
->drm_dev
;
1197 struct drm_crtc
*crtc
= &vop
->crtc
;
1198 unsigned long flags
;
1200 spin_lock_irqsave(&drm
->event_lock
, flags
);
1202 drm_crtc_send_vblank_event(crtc
, vop
->event
);
1203 drm_crtc_vblank_put(crtc
);
1206 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
1208 if (test_and_clear_bit(VOP_PENDING_FB_UNREF
, &vop
->pending
))
1209 drm_flip_work_commit(&vop
->fb_unref_work
, system_unbound_wq
);
1212 static irqreturn_t
vop_isr(int irq
, void *data
)
1214 struct vop
*vop
= data
;
1215 struct drm_crtc
*crtc
= &vop
->crtc
;
1216 uint32_t active_irqs
;
1217 unsigned long flags
;
1221 * interrupt register has interrupt status, enable and clear bits, we
1222 * must hold irq_lock to avoid a race with enable/disable_vblank().
1224 spin_lock_irqsave(&vop
->irq_lock
, flags
);
1226 active_irqs
= VOP_INTR_GET_TYPE(vop
, status
, INTR_MASK
);
1227 /* Clear all active interrupt sources */
1229 VOP_INTR_SET_TYPE(vop
, clear
, active_irqs
, 1);
1231 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
1233 /* This is expected for vop iommu irqs, since the irq is shared */
1237 if (active_irqs
& DSP_HOLD_VALID_INTR
) {
1238 complete(&vop
->dsp_hold_completion
);
1239 active_irqs
&= ~DSP_HOLD_VALID_INTR
;
1243 if (active_irqs
& LINE_FLAG_INTR
) {
1244 complete(&vop
->line_flag_completion
);
1245 active_irqs
&= ~LINE_FLAG_INTR
;
1249 if (active_irqs
& FS_INTR
) {
1250 drm_crtc_handle_vblank(crtc
);
1251 vop_handle_vblank(vop
);
1252 active_irqs
&= ~FS_INTR
;
1256 /* Unhandled irqs are spurious. */
1258 DRM_DEV_ERROR(vop
->dev
, "Unknown VOP IRQs: %#02x\n",
1264 static int vop_create_crtc(struct vop
*vop
)
1266 const struct vop_data
*vop_data
= vop
->data
;
1267 struct device
*dev
= vop
->dev
;
1268 struct drm_device
*drm_dev
= vop
->drm_dev
;
1269 struct drm_plane
*primary
= NULL
, *cursor
= NULL
, *plane
, *tmp
;
1270 struct drm_crtc
*crtc
= &vop
->crtc
;
1271 struct device_node
*port
;
1276 * Create drm_plane for primary and cursor planes first, since we need
1277 * to pass them to drm_crtc_init_with_planes, which sets the
1278 * "possible_crtcs" to the newly initialized crtc.
1280 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1281 struct vop_win
*vop_win
= &vop
->win
[i
];
1282 const struct vop_win_data
*win_data
= vop_win
->data
;
1284 if (win_data
->type
!= DRM_PLANE_TYPE_PRIMARY
&&
1285 win_data
->type
!= DRM_PLANE_TYPE_CURSOR
)
1288 ret
= drm_universal_plane_init(vop
->drm_dev
, &vop_win
->base
,
1289 0, &vop_plane_funcs
,
1290 win_data
->phy
->data_formats
,
1291 win_data
->phy
->nformats
,
1292 win_data
->type
, NULL
);
1294 DRM_DEV_ERROR(vop
->dev
, "failed to init plane %d\n",
1296 goto err_cleanup_planes
;
1299 plane
= &vop_win
->base
;
1300 drm_plane_helper_add(plane
, &plane_helper_funcs
);
1301 if (plane
->type
== DRM_PLANE_TYPE_PRIMARY
)
1303 else if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
1307 ret
= drm_crtc_init_with_planes(drm_dev
, crtc
, primary
, cursor
,
1308 &vop_crtc_funcs
, NULL
);
1310 goto err_cleanup_planes
;
1312 drm_crtc_helper_add(crtc
, &vop_crtc_helper_funcs
);
1315 * Create drm_planes for overlay windows with possible_crtcs restricted
1316 * to the newly created crtc.
1318 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1319 struct vop_win
*vop_win
= &vop
->win
[i
];
1320 const struct vop_win_data
*win_data
= vop_win
->data
;
1321 unsigned long possible_crtcs
= 1 << drm_crtc_index(crtc
);
1323 if (win_data
->type
!= DRM_PLANE_TYPE_OVERLAY
)
1326 ret
= drm_universal_plane_init(vop
->drm_dev
, &vop_win
->base
,
1329 win_data
->phy
->data_formats
,
1330 win_data
->phy
->nformats
,
1331 win_data
->type
, NULL
);
1333 DRM_DEV_ERROR(vop
->dev
, "failed to init overlay %d\n",
1335 goto err_cleanup_crtc
;
1337 drm_plane_helper_add(&vop_win
->base
, &plane_helper_funcs
);
1340 port
= of_get_child_by_name(dev
->of_node
, "port");
1342 DRM_DEV_ERROR(vop
->dev
, "no port node found in %s\n",
1343 dev
->of_node
->full_name
);
1345 goto err_cleanup_crtc
;
1348 drm_flip_work_init(&vop
->fb_unref_work
, "fb_unref",
1349 vop_fb_unref_worker
);
1351 init_completion(&vop
->dsp_hold_completion
);
1352 init_completion(&vop
->line_flag_completion
);
1358 drm_crtc_cleanup(crtc
);
1360 list_for_each_entry_safe(plane
, tmp
, &drm_dev
->mode_config
.plane_list
,
1362 drm_plane_cleanup(plane
);
1366 static void vop_destroy_crtc(struct vop
*vop
)
1368 struct drm_crtc
*crtc
= &vop
->crtc
;
1369 struct drm_device
*drm_dev
= vop
->drm_dev
;
1370 struct drm_plane
*plane
, *tmp
;
1372 of_node_put(crtc
->port
);
1375 * We need to cleanup the planes now. Why?
1377 * The planes are "&vop->win[i].base". That means the memory is
1378 * all part of the big "struct vop" chunk of memory. That memory
1379 * was devm allocated and associated with this component. We need to
1380 * free it ourselves before vop_unbind() finishes.
1382 list_for_each_entry_safe(plane
, tmp
, &drm_dev
->mode_config
.plane_list
,
1384 vop_plane_destroy(plane
);
1387 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1388 * references the CRTC.
1390 drm_crtc_cleanup(crtc
);
1391 drm_flip_work_cleanup(&vop
->fb_unref_work
);
1394 static int vop_initial(struct vop
*vop
)
1396 const struct vop_data
*vop_data
= vop
->data
;
1397 const struct vop_reg_data
*init_table
= vop_data
->init_table
;
1398 struct reset_control
*ahb_rst
;
1401 vop
->hclk
= devm_clk_get(vop
->dev
, "hclk_vop");
1402 if (IS_ERR(vop
->hclk
)) {
1403 dev_err(vop
->dev
, "failed to get hclk source\n");
1404 return PTR_ERR(vop
->hclk
);
1406 vop
->aclk
= devm_clk_get(vop
->dev
, "aclk_vop");
1407 if (IS_ERR(vop
->aclk
)) {
1408 dev_err(vop
->dev
, "failed to get aclk source\n");
1409 return PTR_ERR(vop
->aclk
);
1411 vop
->dclk
= devm_clk_get(vop
->dev
, "dclk_vop");
1412 if (IS_ERR(vop
->dclk
)) {
1413 dev_err(vop
->dev
, "failed to get dclk source\n");
1414 return PTR_ERR(vop
->dclk
);
1417 ret
= pm_runtime_get_sync(vop
->dev
);
1419 dev_err(vop
->dev
, "failed to get pm runtime: %d\n", ret
);
1423 ret
= clk_prepare(vop
->dclk
);
1425 dev_err(vop
->dev
, "failed to prepare dclk\n");
1426 goto err_put_pm_runtime
;
1429 /* Enable both the hclk and aclk to setup the vop */
1430 ret
= clk_prepare_enable(vop
->hclk
);
1432 dev_err(vop
->dev
, "failed to prepare/enable hclk\n");
1433 goto err_unprepare_dclk
;
1436 ret
= clk_prepare_enable(vop
->aclk
);
1438 dev_err(vop
->dev
, "failed to prepare/enable aclk\n");
1439 goto err_disable_hclk
;
1443 * do hclk_reset, reset all vop registers.
1445 ahb_rst
= devm_reset_control_get(vop
->dev
, "ahb");
1446 if (IS_ERR(ahb_rst
)) {
1447 dev_err(vop
->dev
, "failed to get ahb reset\n");
1448 ret
= PTR_ERR(ahb_rst
);
1449 goto err_disable_aclk
;
1451 reset_control_assert(ahb_rst
);
1452 usleep_range(10, 20);
1453 reset_control_deassert(ahb_rst
);
1455 memcpy(vop
->regsbak
, vop
->regs
, vop
->len
);
1457 for (i
= 0; i
< vop_data
->table_size
; i
++)
1458 vop_writel(vop
, init_table
[i
].offset
, init_table
[i
].value
);
1460 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1461 const struct vop_win_data
*win
= &vop_data
->win
[i
];
1463 VOP_WIN_SET(vop
, win
, enable
, 0);
1469 * do dclk_reset, let all config take affect.
1471 vop
->dclk_rst
= devm_reset_control_get(vop
->dev
, "dclk");
1472 if (IS_ERR(vop
->dclk_rst
)) {
1473 dev_err(vop
->dev
, "failed to get dclk reset\n");
1474 ret
= PTR_ERR(vop
->dclk_rst
);
1475 goto err_disable_aclk
;
1477 reset_control_assert(vop
->dclk_rst
);
1478 usleep_range(10, 20);
1479 reset_control_deassert(vop
->dclk_rst
);
1481 clk_disable(vop
->hclk
);
1482 clk_disable(vop
->aclk
);
1484 vop
->is_enabled
= false;
1486 pm_runtime_put_sync(vop
->dev
);
1491 clk_disable_unprepare(vop
->aclk
);
1493 clk_disable_unprepare(vop
->hclk
);
1495 clk_unprepare(vop
->dclk
);
1497 pm_runtime_put_sync(vop
->dev
);
1502 * Initialize the vop->win array elements.
1504 static void vop_win_init(struct vop
*vop
)
1506 const struct vop_data
*vop_data
= vop
->data
;
1509 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1510 struct vop_win
*vop_win
= &vop
->win
[i
];
1511 const struct vop_win_data
*win_data
= &vop_data
->win
[i
];
1513 vop_win
->data
= win_data
;
1519 * rockchip_drm_wait_vact_end
1520 * @crtc: CRTC to enable line flag
1521 * @mstimeout: millisecond for timeout
1523 * Wait for vact_end line flag irq or timeout.
1526 * Zero on success, negative errno on failure.
1528 int rockchip_drm_wait_vact_end(struct drm_crtc
*crtc
, unsigned int mstimeout
)
1530 struct vop
*vop
= to_vop(crtc
);
1531 unsigned long jiffies_left
;
1533 if (!crtc
|| !vop
->is_enabled
)
1539 if (vop_line_flag_irq_is_enabled(vop
))
1542 reinit_completion(&vop
->line_flag_completion
);
1543 vop_line_flag_irq_enable(vop
);
1545 jiffies_left
= wait_for_completion_timeout(&vop
->line_flag_completion
,
1546 msecs_to_jiffies(mstimeout
));
1547 vop_line_flag_irq_disable(vop
);
1549 if (jiffies_left
== 0) {
1550 dev_err(vop
->dev
, "Timeout waiting for IRQ\n");
1556 EXPORT_SYMBOL(rockchip_drm_wait_vact_end
);
1558 static int vop_bind(struct device
*dev
, struct device
*master
, void *data
)
1560 struct platform_device
*pdev
= to_platform_device(dev
);
1561 const struct vop_data
*vop_data
;
1562 struct drm_device
*drm_dev
= data
;
1564 struct resource
*res
;
1568 vop_data
= of_device_get_match_data(dev
);
1572 /* Allocate vop struct and its vop_win array */
1573 alloc_size
= sizeof(*vop
) + sizeof(*vop
->win
) * vop_data
->win_size
;
1574 vop
= devm_kzalloc(dev
, alloc_size
, GFP_KERNEL
);
1579 vop
->data
= vop_data
;
1580 vop
->drm_dev
= drm_dev
;
1581 dev_set_drvdata(dev
, vop
);
1585 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1586 vop
->len
= resource_size(res
);
1587 vop
->regs
= devm_ioremap_resource(dev
, res
);
1588 if (IS_ERR(vop
->regs
))
1589 return PTR_ERR(vop
->regs
);
1591 vop
->regsbak
= devm_kzalloc(dev
, vop
->len
, GFP_KERNEL
);
1595 irq
= platform_get_irq(pdev
, 0);
1597 dev_err(dev
, "cannot find irq for vop\n");
1600 vop
->irq
= (unsigned int)irq
;
1602 spin_lock_init(&vop
->reg_lock
);
1603 spin_lock_init(&vop
->irq_lock
);
1605 mutex_init(&vop
->vsync_mutex
);
1607 ret
= devm_request_irq(dev
, vop
->irq
, vop_isr
,
1608 IRQF_SHARED
, dev_name(dev
), vop
);
1612 /* IRQ is initially disabled; it gets enabled in power_on */
1613 disable_irq(vop
->irq
);
1615 ret
= vop_create_crtc(vop
);
1617 goto err_enable_irq
;
1619 pm_runtime_enable(&pdev
->dev
);
1621 ret
= vop_initial(vop
);
1623 dev_err(&pdev
->dev
, "cannot initial vop dev - err %d\n", ret
);
1624 goto err_disable_pm_runtime
;
1629 err_disable_pm_runtime
:
1630 pm_runtime_disable(&pdev
->dev
);
1631 vop_destroy_crtc(vop
);
1633 enable_irq(vop
->irq
); /* To balance out the disable_irq above */
1637 static void vop_unbind(struct device
*dev
, struct device
*master
, void *data
)
1639 struct vop
*vop
= dev_get_drvdata(dev
);
1641 pm_runtime_disable(dev
);
1642 vop_destroy_crtc(vop
);
1644 clk_unprepare(vop
->aclk
);
1645 clk_unprepare(vop
->hclk
);
1646 clk_unprepare(vop
->dclk
);
1649 const struct component_ops vop_component_ops
= {
1651 .unbind
= vop_unbind
,
1653 EXPORT_SYMBOL_GPL(vop_component_ops
);