2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/component.h>
20 #include "rockchip_drm_vop.h"
21 #include "rockchip_vop_reg.h"
23 #define VOP_REG(off, _mask, s) \
28 static const uint32_t formats_win_full
[] = {
42 static const uint32_t formats_win_lite
[] = {
53 static const struct vop_scl_extension rk3288_win_full_scl_ext
= {
54 .cbcr_vsd_mode
= VOP_REG(RK3288_WIN0_CTRL1
, 0x1, 31),
55 .cbcr_vsu_mode
= VOP_REG(RK3288_WIN0_CTRL1
, 0x1, 30),
56 .cbcr_hsd_mode
= VOP_REG(RK3288_WIN0_CTRL1
, 0x3, 28),
57 .cbcr_ver_scl_mode
= VOP_REG(RK3288_WIN0_CTRL1
, 0x3, 26),
58 .cbcr_hor_scl_mode
= VOP_REG(RK3288_WIN0_CTRL1
, 0x3, 24),
59 .yrgb_vsd_mode
= VOP_REG(RK3288_WIN0_CTRL1
, 0x1, 23),
60 .yrgb_vsu_mode
= VOP_REG(RK3288_WIN0_CTRL1
, 0x1, 22),
61 .yrgb_hsd_mode
= VOP_REG(RK3288_WIN0_CTRL1
, 0x3, 20),
62 .yrgb_ver_scl_mode
= VOP_REG(RK3288_WIN0_CTRL1
, 0x3, 18),
63 .yrgb_hor_scl_mode
= VOP_REG(RK3288_WIN0_CTRL1
, 0x3, 16),
64 .line_load_mode
= VOP_REG(RK3288_WIN0_CTRL1
, 0x1, 15),
65 .cbcr_axi_gather_num
= VOP_REG(RK3288_WIN0_CTRL1
, 0x7, 12),
66 .yrgb_axi_gather_num
= VOP_REG(RK3288_WIN0_CTRL1
, 0xf, 8),
67 .vsd_cbcr_gt2
= VOP_REG(RK3288_WIN0_CTRL1
, 0x1, 7),
68 .vsd_cbcr_gt4
= VOP_REG(RK3288_WIN0_CTRL1
, 0x1, 6),
69 .vsd_yrgb_gt2
= VOP_REG(RK3288_WIN0_CTRL1
, 0x1, 5),
70 .vsd_yrgb_gt4
= VOP_REG(RK3288_WIN0_CTRL1
, 0x1, 4),
71 .bic_coe_sel
= VOP_REG(RK3288_WIN0_CTRL1
, 0x3, 2),
72 .cbcr_axi_gather_en
= VOP_REG(RK3288_WIN0_CTRL1
, 0x1, 1),
73 .yrgb_axi_gather_en
= VOP_REG(RK3288_WIN0_CTRL1
, 0x1, 0),
74 .lb_mode
= VOP_REG(RK3288_WIN0_CTRL0
, 0x7, 5),
77 static const struct vop_scl_regs rk3288_win_full_scl
= {
78 .ext
= &rk3288_win_full_scl_ext
,
79 .scale_yrgb_x
= VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB
, 0xffff, 0x0),
80 .scale_yrgb_y
= VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB
, 0xffff, 16),
81 .scale_cbcr_x
= VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR
, 0xffff, 0x0),
82 .scale_cbcr_y
= VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR
, 0xffff, 16),
85 static const struct vop_win_phy rk3288_win01_data
= {
86 .scl
= &rk3288_win_full_scl
,
87 .data_formats
= formats_win_full
,
88 .nformats
= ARRAY_SIZE(formats_win_full
),
89 .enable
= VOP_REG(RK3288_WIN0_CTRL0
, 0x1, 0),
90 .format
= VOP_REG(RK3288_WIN0_CTRL0
, 0x7, 1),
91 .rb_swap
= VOP_REG(RK3288_WIN0_CTRL0
, 0x1, 12),
92 .act_info
= VOP_REG(RK3288_WIN0_ACT_INFO
, 0x1fff1fff, 0),
93 .dsp_info
= VOP_REG(RK3288_WIN0_DSP_INFO
, 0x0fff0fff, 0),
94 .dsp_st
= VOP_REG(RK3288_WIN0_DSP_ST
, 0x1fff1fff, 0),
95 .yrgb_mst
= VOP_REG(RK3288_WIN0_YRGB_MST
, 0xffffffff, 0),
96 .uv_mst
= VOP_REG(RK3288_WIN0_CBR_MST
, 0xffffffff, 0),
97 .yrgb_vir
= VOP_REG(RK3288_WIN0_VIR
, 0x3fff, 0),
98 .uv_vir
= VOP_REG(RK3288_WIN0_VIR
, 0x3fff, 16),
99 .src_alpha_ctl
= VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL
, 0xff, 0),
100 .dst_alpha_ctl
= VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL
, 0xff, 0),
103 static const struct vop_win_phy rk3288_win23_data
= {
104 .data_formats
= formats_win_lite
,
105 .nformats
= ARRAY_SIZE(formats_win_lite
),
106 .enable
= VOP_REG(RK3288_WIN2_CTRL0
, 0x1, 0),
107 .format
= VOP_REG(RK3288_WIN2_CTRL0
, 0x7, 1),
108 .rb_swap
= VOP_REG(RK3288_WIN2_CTRL0
, 0x1, 12),
109 .dsp_info
= VOP_REG(RK3288_WIN2_DSP_INFO0
, 0x0fff0fff, 0),
110 .dsp_st
= VOP_REG(RK3288_WIN2_DSP_ST0
, 0x1fff1fff, 0),
111 .yrgb_mst
= VOP_REG(RK3288_WIN2_MST0
, 0xffffffff, 0),
112 .yrgb_vir
= VOP_REG(RK3288_WIN2_VIR0_1
, 0x1fff, 0),
113 .src_alpha_ctl
= VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL
, 0xff, 0),
114 .dst_alpha_ctl
= VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL
, 0xff, 0),
117 static const struct vop_ctrl rk3288_ctrl_data
= {
118 .standby
= VOP_REG(RK3288_SYS_CTRL
, 0x1, 22),
119 .gate_en
= VOP_REG(RK3288_SYS_CTRL
, 0x1, 23),
120 .mmu_en
= VOP_REG(RK3288_SYS_CTRL
, 0x1, 20),
121 .rgb_en
= VOP_REG(RK3288_SYS_CTRL
, 0x1, 12),
122 .hdmi_en
= VOP_REG(RK3288_SYS_CTRL
, 0x1, 13),
123 .edp_en
= VOP_REG(RK3288_SYS_CTRL
, 0x1, 14),
124 .mipi_en
= VOP_REG(RK3288_SYS_CTRL
, 0x1, 15),
125 .dither_down
= VOP_REG(RK3288_DSP_CTRL1
, 0xf, 1),
126 .dither_up
= VOP_REG(RK3288_DSP_CTRL1
, 0x1, 6),
127 .data_blank
= VOP_REG(RK3288_DSP_CTRL0
, 0x1, 19),
128 .out_mode
= VOP_REG(RK3288_DSP_CTRL0
, 0xf, 0),
129 .pin_pol
= VOP_REG(RK3288_DSP_CTRL0
, 0xf, 4),
130 .htotal_pw
= VOP_REG(RK3288_DSP_HTOTAL_HS_END
, 0x1fff1fff, 0),
131 .hact_st_end
= VOP_REG(RK3288_DSP_HACT_ST_END
, 0x1fff1fff, 0),
132 .vtotal_pw
= VOP_REG(RK3288_DSP_VTOTAL_VS_END
, 0x1fff1fff, 0),
133 .vact_st_end
= VOP_REG(RK3288_DSP_VACT_ST_END
, 0x1fff1fff, 0),
134 .hpost_st_end
= VOP_REG(RK3288_POST_DSP_HACT_INFO
, 0x1fff1fff, 0),
135 .vpost_st_end
= VOP_REG(RK3288_POST_DSP_VACT_INFO
, 0x1fff1fff, 0),
136 .cfg_done
= VOP_REG(RK3288_REG_CFG_DONE
, 0x1, 0),
139 static const struct vop_reg_data rk3288_init_reg_table
[] = {
140 {RK3288_SYS_CTRL
, 0x00c00000},
141 {RK3288_DSP_CTRL0
, 0x00000000},
142 {RK3288_WIN0_CTRL0
, 0x00000080},
143 {RK3288_WIN1_CTRL0
, 0x00000080},
144 /* TODO: Win2/3 support multiple area function, but we haven't found
145 * a suitable way to use it yet, so let's just use them as other windows
146 * with only area 0 enabled.
148 {RK3288_WIN2_CTRL0
, 0x00000010},
149 {RK3288_WIN3_CTRL0
, 0x00000010},
153 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
154 * special support to get alpha blending working. For now, just use overlay
155 * window 3 for the drm cursor.
158 static const struct vop_win_data rk3288_vop_win_data
[] = {
159 { .base
= 0x00, .phy
= &rk3288_win01_data
,
160 .type
= DRM_PLANE_TYPE_PRIMARY
},
161 { .base
= 0x40, .phy
= &rk3288_win01_data
,
162 .type
= DRM_PLANE_TYPE_OVERLAY
},
163 { .base
= 0x00, .phy
= &rk3288_win23_data
,
164 .type
= DRM_PLANE_TYPE_OVERLAY
},
165 { .base
= 0x50, .phy
= &rk3288_win23_data
,
166 .type
= DRM_PLANE_TYPE_CURSOR
},
169 static const int rk3288_vop_intrs
[] = {
176 static const struct vop_intr rk3288_vop_intr
= {
177 .intrs
= rk3288_vop_intrs
,
178 .nintrs
= ARRAY_SIZE(rk3288_vop_intrs
),
179 .status
= VOP_REG(RK3288_INTR_CTRL0
, 0xf, 0),
180 .enable
= VOP_REG(RK3288_INTR_CTRL0
, 0xf, 4),
181 .clear
= VOP_REG(RK3288_INTR_CTRL0
, 0xf, 8),
184 static const struct vop_data rk3288_vop
= {
185 .init_table
= rk3288_init_reg_table
,
186 .table_size
= ARRAY_SIZE(rk3288_init_reg_table
),
187 .intr
= &rk3288_vop_intr
,
188 .ctrl
= &rk3288_ctrl_data
,
189 .win
= rk3288_vop_win_data
,
190 .win_size
= ARRAY_SIZE(rk3288_vop_win_data
),
193 static const struct vop_scl_regs rk3036_win_scl
= {
194 .scale_yrgb_x
= VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB
, 0xffff, 0x0),
195 .scale_yrgb_y
= VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB
, 0xffff, 16),
196 .scale_cbcr_x
= VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR
, 0xffff, 0x0),
197 .scale_cbcr_y
= VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR
, 0xffff, 16),
200 static const struct vop_win_phy rk3036_win0_data
= {
201 .scl
= &rk3036_win_scl
,
202 .data_formats
= formats_win_full
,
203 .nformats
= ARRAY_SIZE(formats_win_full
),
204 .enable
= VOP_REG(RK3036_SYS_CTRL
, 0x1, 0),
205 .format
= VOP_REG(RK3036_SYS_CTRL
, 0x7, 3),
206 .rb_swap
= VOP_REG(RK3036_SYS_CTRL
, 0x1, 15),
207 .act_info
= VOP_REG(RK3036_WIN0_ACT_INFO
, 0x1fff1fff, 0),
208 .dsp_info
= VOP_REG(RK3036_WIN0_DSP_INFO
, 0x0fff0fff, 0),
209 .dsp_st
= VOP_REG(RK3036_WIN0_DSP_ST
, 0x1fff1fff, 0),
210 .yrgb_mst
= VOP_REG(RK3036_WIN0_YRGB_MST
, 0xffffffff, 0),
211 .uv_mst
= VOP_REG(RK3036_WIN0_CBR_MST
, 0xffffffff, 0),
212 .yrgb_vir
= VOP_REG(RK3036_WIN0_VIR
, 0xffff, 0),
213 .uv_vir
= VOP_REG(RK3036_WIN0_VIR
, 0x1fff, 16),
216 static const struct vop_win_phy rk3036_win1_data
= {
217 .data_formats
= formats_win_lite
,
218 .nformats
= ARRAY_SIZE(formats_win_lite
),
219 .enable
= VOP_REG(RK3036_SYS_CTRL
, 0x1, 1),
220 .format
= VOP_REG(RK3036_SYS_CTRL
, 0x7, 6),
221 .rb_swap
= VOP_REG(RK3036_SYS_CTRL
, 0x1, 19),
222 .act_info
= VOP_REG(RK3036_WIN1_ACT_INFO
, 0x1fff1fff, 0),
223 .dsp_info
= VOP_REG(RK3036_WIN1_DSP_INFO
, 0x0fff0fff, 0),
224 .dsp_st
= VOP_REG(RK3036_WIN1_DSP_ST
, 0x1fff1fff, 0),
225 .yrgb_mst
= VOP_REG(RK3036_WIN1_MST
, 0xffffffff, 0),
226 .yrgb_vir
= VOP_REG(RK3036_WIN1_VIR
, 0xffff, 0),
229 static const struct vop_win_data rk3036_vop_win_data
[] = {
230 { .base
= 0x00, .phy
= &rk3036_win0_data
,
231 .type
= DRM_PLANE_TYPE_PRIMARY
},
232 { .base
= 0x00, .phy
= &rk3036_win1_data
,
233 .type
= DRM_PLANE_TYPE_CURSOR
},
236 static const int rk3036_vop_intrs
[] = {
243 static const struct vop_intr rk3036_intr
= {
244 .intrs
= rk3036_vop_intrs
,
245 .nintrs
= ARRAY_SIZE(rk3036_vop_intrs
),
246 .status
= VOP_REG(RK3036_INT_STATUS
, 0xf, 0),
247 .enable
= VOP_REG(RK3036_INT_STATUS
, 0xf, 4),
248 .clear
= VOP_REG(RK3036_INT_STATUS
, 0xf, 8),
251 static const struct vop_ctrl rk3036_ctrl_data
= {
252 .standby
= VOP_REG(RK3036_SYS_CTRL
, 0x1, 30),
253 .out_mode
= VOP_REG(RK3036_DSP_CTRL0
, 0xf, 0),
254 .pin_pol
= VOP_REG(RK3036_DSP_CTRL0
, 0xf, 4),
255 .htotal_pw
= VOP_REG(RK3036_DSP_HTOTAL_HS_END
, 0x1fff1fff, 0),
256 .hact_st_end
= VOP_REG(RK3036_DSP_HACT_ST_END
, 0x1fff1fff, 0),
257 .vtotal_pw
= VOP_REG(RK3036_DSP_VTOTAL_VS_END
, 0x1fff1fff, 0),
258 .vact_st_end
= VOP_REG(RK3036_DSP_VACT_ST_END
, 0x1fff1fff, 0),
259 .cfg_done
= VOP_REG(RK3036_REG_CFG_DONE
, 0x1, 0),
262 static const struct vop_reg_data rk3036_vop_init_reg_table
[] = {
263 {RK3036_DSP_CTRL1
, 0x00000000},
266 static const struct vop_data rk3036_vop
= {
267 .init_table
= rk3036_vop_init_reg_table
,
268 .table_size
= ARRAY_SIZE(rk3036_vop_init_reg_table
),
269 .ctrl
= &rk3036_ctrl_data
,
270 .intr
= &rk3036_intr
,
271 .win
= rk3036_vop_win_data
,
272 .win_size
= ARRAY_SIZE(rk3036_vop_win_data
),
275 static const struct of_device_id vop_driver_dt_match
[] = {
276 { .compatible
= "rockchip,rk3288-vop",
277 .data
= &rk3288_vop
},
278 { .compatible
= "rockchip,rk3036-vop",
279 .data
= &rk3036_vop
},
282 MODULE_DEVICE_TABLE(of
, vop_driver_dt_match
);
284 static int vop_probe(struct platform_device
*pdev
)
286 struct device
*dev
= &pdev
->dev
;
289 dev_err(dev
, "can't find vop devices\n");
293 return component_add(dev
, &vop_component_ops
);
296 static int vop_remove(struct platform_device
*pdev
)
298 component_del(&pdev
->dev
, &vop_component_ops
);
303 static struct platform_driver vop_platform_driver
= {
305 .remove
= vop_remove
,
307 .name
= "rockchip-vop",
308 .owner
= THIS_MODULE
,
309 .of_match_table
= of_match_ptr(vop_driver_dt_match
),
313 module_platform_driver(vop_platform_driver
);
315 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
316 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
317 MODULE_LICENSE("GPL v2");