drivers/gpu/drm/sti/sti_gdp.c

   1 /*
   2  * Copyright (C) STMicroelectronics SA 2014
   3  * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
   4  *          Fabien Dessenne <fabien.dessenne@st.com>
   5  *          for STMicroelectronics.
   6  * License terms:  GNU General Public License (GPL), version 2
   7  */
   8 #include <linux/seq_file.h>
   9
  10 #include <drm/drm_atomic.h>
  11 #include <drm/drm_fb_cma_helper.h>
  12 #include <drm/drm_gem_cma_helper.h>
  13
  14 #include "sti_compositor.h"
  15 #include "sti_gdp.h"
  16 #include "sti_plane.h"
  17 #include "sti_vtg.h"
  18
  19 #define ALPHASWITCH     BIT(6)
  20 #define ENA_COLOR_FILL  BIT(8)
  21 #define BIGNOTLITTLE    BIT(23)
  22 #define WAIT_NEXT_VSYNC BIT(31)
  23
  24 /* GDP color formats */
  25 #define GDP_RGB565      0x00
  26 #define GDP_RGB888      0x01
  27 #define GDP_RGB888_32   0x02
  28 #define GDP_XBGR8888    (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH)
  29 #define GDP_ARGB8565    0x04
  30 #define GDP_ARGB8888    0x05
  31 #define GDP_ABGR8888    (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH)
  32 #define GDP_ARGB1555    0x06
  33 #define GDP_ARGB4444    0x07
  34
  35 #define GDP2STR(fmt) { GDP_ ## fmt, #fmt }
  36
  37 static struct gdp_format_to_str {
  38         int format;
  39         char name[20];
  40 } gdp_format_to_str[] = {
  41                 GDP2STR(RGB565),
  42                 GDP2STR(RGB888),
  43                 GDP2STR(RGB888_32),
  44                 GDP2STR(XBGR8888),
  45                 GDP2STR(ARGB8565),
  46                 GDP2STR(ARGB8888),
  47                 GDP2STR(ABGR8888),
  48                 GDP2STR(ARGB1555),
  49                 GDP2STR(ARGB4444)
  50                 };
  51
  52 #define GAM_GDP_CTL_OFFSET      0x00
  53 #define GAM_GDP_AGC_OFFSET      0x04
  54 #define GAM_GDP_VPO_OFFSET      0x0C
  55 #define GAM_GDP_VPS_OFFSET      0x10
  56 #define GAM_GDP_PML_OFFSET      0x14
  57 #define GAM_GDP_PMP_OFFSET      0x18
  58 #define GAM_GDP_SIZE_OFFSET     0x1C
  59 #define GAM_GDP_NVN_OFFSET      0x24
  60 #define GAM_GDP_KEY1_OFFSET     0x28
  61 #define GAM_GDP_KEY2_OFFSET     0x2C
  62 #define GAM_GDP_PPT_OFFSET      0x34
  63 #define GAM_GDP_CML_OFFSET      0x3C
  64 #define GAM_GDP_MST_OFFSET      0x68
  65
  66 #define GAM_GDP_ALPHARANGE_255  BIT(5)
  67 #define GAM_GDP_AGC_FULL_RANGE  0x00808080
  68 #define GAM_GDP_PPT_IGNORE      (BIT(1) | BIT(0))
  69
  70 #define GAM_GDP_SIZE_MAX_WIDTH  3840
  71 #define GAM_GDP_SIZE_MAX_HEIGHT 2160
  72
  73 #define GDP_NODE_NB_BANK        2
  74 #define GDP_NODE_PER_FIELD      2
  75
  76 struct sti_gdp_node {
  77         u32 gam_gdp_ctl;
  78         u32 gam_gdp_agc;
  79         u32 reserved1;
  80         u32 gam_gdp_vpo;
  81         u32 gam_gdp_vps;
  82         u32 gam_gdp_pml;
  83         u32 gam_gdp_pmp;
  84         u32 gam_gdp_size;
  85         u32 reserved2;
  86         u32 gam_gdp_nvn;
  87         u32 gam_gdp_key1;
  88         u32 gam_gdp_key2;
  89         u32 reserved3;
  90         u32 gam_gdp_ppt;
  91         u32 reserved4;
  92         u32 gam_gdp_cml;
  93 };
  94
  95 struct sti_gdp_node_list {
  96         struct sti_gdp_node *top_field;
  97         dma_addr_t top_field_paddr;
  98         struct sti_gdp_node *btm_field;
  99         dma_addr_t btm_field_paddr;
 100 };
 101
 102 /**
 103  * STI GDP structure
 104  *
 105  * @sti_plane:          sti_plane structure
 106  * @dev:                driver device
 107  * @regs:               gdp registers
 108  * @clk_pix:            pixel clock for the current gdp
 109  * @clk_main_parent:    gdp parent clock if main path used
 110  * @clk_aux_parent:     gdp parent clock if aux path used
 111  * @vtg_field_nb:       callback for VTG FIELD (top or bottom) notification
 112  * @is_curr_top:        true if the current node processed is the top field
 113  * @node_list:          array of node list
 114  * @vtg:                registered vtg
 115  */
 116 struct sti_gdp {
 117         struct sti_plane plane;
 118         struct device *dev;
 119         void __iomem *regs;
 120         struct clk *clk_pix;
 121         struct clk *clk_main_parent;
 122         struct clk *clk_aux_parent;
 123         struct notifier_block vtg_field_nb;
 124         bool is_curr_top;
 125         struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK];
 126         struct sti_vtg *vtg;
 127 };
 128
 129 #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane)
 130
 131 static const uint32_t gdp_supported_formats[] = {
 132         DRM_FORMAT_XRGB8888,
 133         DRM_FORMAT_XBGR8888,
 134         DRM_FORMAT_ARGB8888,
 135         DRM_FORMAT_ABGR8888,
 136         DRM_FORMAT_ARGB4444,
 137         DRM_FORMAT_ARGB1555,
 138         DRM_FORMAT_RGB565,
 139         DRM_FORMAT_RGB888,
 140 };
 141
 142 #define DBGFS_DUMP(reg) seq_printf(s, "\n  %-25s 0x%08X", #reg, \
 143                                    readl(gdp->regs + reg ## _OFFSET))
 144
 145 static void gdp_dbg_ctl(struct seq_file *s, int val)
 146 {
 147         int i;
 148
 149         seq_puts(s, "\tColor:");
 150         for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) {
 151                 if (gdp_format_to_str[i].format == (val & 0x1F)) {
 152                         seq_puts(s, gdp_format_to_str[i].name);
 153                         break;
 154                 }
 155         }
 156         if (i == ARRAY_SIZE(gdp_format_to_str))
 157                 seq_puts(s, "<UNKNOWN>");
 158
 159         seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0);
 160 }
 161
 162 static void gdp_dbg_vpo(struct seq_file *s, int val)
 163 {
 164         seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF);
 165 }
 166
 167 static void gdp_dbg_vps(struct seq_file *s, int val)
 168 {
 169         seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF);
 170 }
 171
 172 static void gdp_dbg_size(struct seq_file *s, int val)
 173 {
 174         seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF);
 175 }
 176
 177 static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val)
 178 {
 179         void *base = NULL;
 180         unsigned int i;
 181
 182         for (i = 0; i < GDP_NODE_NB_BANK; i++) {
 183                 if (gdp->node_list[i].top_field_paddr == val) {
 184                         base = gdp->node_list[i].top_field;
 185                         break;
 186                 }
 187                 if (gdp->node_list[i].btm_field_paddr == val) {
 188                         base = gdp->node_list[i].btm_field;
 189                         break;
 190                 }
 191         }
 192
 193         if (base)
 194                 seq_printf(s, "\tVirt @: %p", base);
 195 }
 196
 197 static void gdp_dbg_ppt(struct seq_file *s, int val)
 198 {
 199         if (val & GAM_GDP_PPT_IGNORE)
 200                 seq_puts(s, "\tNot displayed on mixer!");
 201 }
 202
 203 static void gdp_dbg_mst(struct seq_file *s, int val)
 204 {
 205         if (val & 1)
 206                 seq_puts(s, "\tBUFFER UNDERFLOW!");
 207 }
 208
 209 static int gdp_dbg_show(struct seq_file *s, void *data)
 210 {
 211         struct drm_info_node *node = s->private;
 212         struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data;
 213         struct drm_plane *drm_plane = &gdp->plane.drm_plane;
 214         struct drm_crtc *crtc = drm_plane->crtc;
 215
 216         seq_printf(s, "%s: (vaddr = 0x%p)",
 217                    sti_plane_to_str(&gdp->plane), gdp->regs);
 218
 219         DBGFS_DUMP(GAM_GDP_CTL);
 220         gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET));
 221         DBGFS_DUMP(GAM_GDP_AGC);
 222         DBGFS_DUMP(GAM_GDP_VPO);
 223         gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET));
 224         DBGFS_DUMP(GAM_GDP_VPS);
 225         gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET));
 226         DBGFS_DUMP(GAM_GDP_PML);
 227         DBGFS_DUMP(GAM_GDP_PMP);
 228         DBGFS_DUMP(GAM_GDP_SIZE);
 229         gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET));
 230         DBGFS_DUMP(GAM_GDP_NVN);
 231         gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET));
 232         DBGFS_DUMP(GAM_GDP_KEY1);
 233         DBGFS_DUMP(GAM_GDP_KEY2);
 234         DBGFS_DUMP(GAM_GDP_PPT);
 235         gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET));
 236         DBGFS_DUMP(GAM_GDP_CML);
 237         DBGFS_DUMP(GAM_GDP_MST);
 238         gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET));
 239
 240         seq_puts(s, "\n\n");
 241         if (!crtc)
 242                 seq_puts(s, "  Not connected to any DRM CRTC\n");
 243         else
 244                 seq_printf(s, "  Connected to DRM CRTC #%d (%s)\n",
 245                            crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc)));
 246
 247         return 0;
 248 }
 249
 250 static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node)
 251 {
 252         seq_printf(s, "\t@:0x%p", node);
 253         seq_printf(s, "\n\tCTL  0x%08X", node->gam_gdp_ctl);
 254         gdp_dbg_ctl(s, node->gam_gdp_ctl);
 255         seq_printf(s, "\n\tAGC  0x%08X", node->gam_gdp_agc);
 256         seq_printf(s, "\n\tVPO  0x%08X", node->gam_gdp_vpo);
 257         gdp_dbg_vpo(s, node->gam_gdp_vpo);
 258         seq_printf(s, "\n\tVPS  0x%08X", node->gam_gdp_vps);
 259         gdp_dbg_vps(s, node->gam_gdp_vps);
 260         seq_printf(s, "\n\tPML  0x%08X", node->gam_gdp_pml);
 261         seq_printf(s, "\n\tPMP  0x%08X", node->gam_gdp_pmp);
 262         seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size);
 263         gdp_dbg_size(s, node->gam_gdp_size);
 264         seq_printf(s, "\n\tNVN  0x%08X", node->gam_gdp_nvn);
 265         seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1);
 266         seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2);
 267         seq_printf(s, "\n\tPPT  0x%08X", node->gam_gdp_ppt);
 268         gdp_dbg_ppt(s, node->gam_gdp_ppt);
 269         seq_printf(s, "\n\tCML  0x%08X\n", node->gam_gdp_cml);
 270 }
 271
 272 static int gdp_node_dbg_show(struct seq_file *s, void *arg)
 273 {
 274         struct drm_info_node *node = s->private;
 275         struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data;
 276         unsigned int b;
 277
 278         for (b = 0; b < GDP_NODE_NB_BANK; b++) {
 279                 seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b);
 280                 gdp_node_dump_node(s, gdp->node_list[b].top_field);
 281                 seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b);
 282                 gdp_node_dump_node(s, gdp->node_list[b].btm_field);
 283         }
 284
 285         return 0;
 286 }
 287
 288 static struct drm_info_list gdp0_debugfs_files[] = {
 289         { "gdp0", gdp_dbg_show, 0, NULL },
 290         { "gdp0_node", gdp_node_dbg_show, 0, NULL },
 291 };
 292
 293 static struct drm_info_list gdp1_debugfs_files[] = {
 294         { "gdp1", gdp_dbg_show, 0, NULL },
 295         { "gdp1_node", gdp_node_dbg_show, 0, NULL },
 296 };
 297
 298 static struct drm_info_list gdp2_debugfs_files[] = {
 299         { "gdp2", gdp_dbg_show, 0, NULL },
 300         { "gdp2_node", gdp_node_dbg_show, 0, NULL },
 301 };
 302
 303 static struct drm_info_list gdp3_debugfs_files[] = {
 304         { "gdp3", gdp_dbg_show, 0, NULL },
 305         { "gdp3_node", gdp_node_dbg_show, 0, NULL },
 306 };
 307
 308 static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor)
 309 {
 310         unsigned int i;
 311         struct drm_info_list *gdp_debugfs_files;
 312         int nb_files;
 313
 314         switch (gdp->plane.desc) {
 315         case STI_GDP_0:
 316                 gdp_debugfs_files = gdp0_debugfs_files;
 317                 nb_files = ARRAY_SIZE(gdp0_debugfs_files);
 318                 break;
 319         case STI_GDP_1:
 320                 gdp_debugfs_files = gdp1_debugfs_files;
 321                 nb_files = ARRAY_SIZE(gdp1_debugfs_files);
 322                 break;
 323         case STI_GDP_2:
 324                 gdp_debugfs_files = gdp2_debugfs_files;
 325                 nb_files = ARRAY_SIZE(gdp2_debugfs_files);
 326                 break;
 327         case STI_GDP_3:
 328                 gdp_debugfs_files = gdp3_debugfs_files;
 329                 nb_files = ARRAY_SIZE(gdp3_debugfs_files);
 330                 break;
 331         default:
 332                 return -EINVAL;
 333         }
 334
 335         for (i = 0; i < nb_files; i++)
 336                 gdp_debugfs_files[i].data = gdp;
 337
 338         return drm_debugfs_create_files(gdp_debugfs_files,
 339                                         nb_files,
 340                                         minor->debugfs_root, minor);
 341 }
 342
 343 static int sti_gdp_fourcc2format(int fourcc)
 344 {
 345         switch (fourcc) {
 346         case DRM_FORMAT_XRGB8888:
 347                 return GDP_RGB888_32;
 348         case DRM_FORMAT_XBGR8888:
 349                 return GDP_XBGR8888;
 350         case DRM_FORMAT_ARGB8888:
 351                 return GDP_ARGB8888;
 352         case DRM_FORMAT_ABGR8888:
 353                 return GDP_ABGR8888;
 354         case DRM_FORMAT_ARGB4444:
 355                 return GDP_ARGB4444;
 356         case DRM_FORMAT_ARGB1555:
 357                 return GDP_ARGB1555;
 358         case DRM_FORMAT_RGB565:
 359                 return GDP_RGB565;
 360         case DRM_FORMAT_RGB888:
 361                 return GDP_RGB888;
 362         }
 363         return -1;
 364 }
 365
 366 static int sti_gdp_get_alpharange(int format)
 367 {
 368         switch (format) {
 369         case GDP_ARGB8565:
 370         case GDP_ARGB8888:
 371         case GDP_ABGR8888:
 372                 return GAM_GDP_ALPHARANGE_255;
 373         }
 374         return 0;
 375 }
 376
 377 /**
 378  * sti_gdp_get_free_nodes
 379  * @gdp: gdp pointer
 380  *
 381  * Look for a GDP node list that is not currently read by the HW.
 382  *
 383  * RETURNS:
 384  * Pointer to the free GDP node list
 385  */
 386 static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp)
 387 {
 388         int hw_nvn;
 389         unsigned int i;
 390
 391         hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
 392         if (!hw_nvn)
 393                 goto end;
 394
 395         for (i = 0; i < GDP_NODE_NB_BANK; i++)
 396                 if ((hw_nvn != gdp->node_list[i].btm_field_paddr) &&
 397                     (hw_nvn != gdp->node_list[i].top_field_paddr))
 398                         return &gdp->node_list[i];
 399
 400         /* in hazardious cases restart with the first node */
 401         DRM_ERROR("inconsistent NVN for %s: 0x%08X\n",
 402                         sti_plane_to_str(&gdp->plane), hw_nvn);
 403
 404 end:
 405         return &gdp->node_list[0];
 406 }
 407
 408 /**
 409  * sti_gdp_get_current_nodes
 410  * @gdp: gdp pointer
 411  *
 412  * Look for GDP nodes that are currently read by the HW.
 413  *
 414  * RETURNS:
 415  * Pointer to the current GDP node list
 416  */
 417 static
 418 struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp)
 419 {
 420         int hw_nvn;
 421         unsigned int i;
 422
 423         hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
 424         if (!hw_nvn)
 425                 goto end;
 426
 427         for (i = 0; i < GDP_NODE_NB_BANK; i++)
 428                 if ((hw_nvn == gdp->node_list[i].btm_field_paddr) ||
 429                                 (hw_nvn == gdp->node_list[i].top_field_paddr))
 430                         return &gdp->node_list[i];
 431
 432 end:
 433         DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n",
 434                                 hw_nvn, sti_plane_to_str(&gdp->plane));
 435
 436         return NULL;
 437 }
 438
 439 /**
 440  * sti_gdp_disable
 441  * @gdp: gdp pointer
 442  *
 443  * Disable a GDP.
 444  */
 445 static void sti_gdp_disable(struct sti_gdp *gdp)
 446 {
 447         unsigned int i;
 448
 449         DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane));
 450
 451         /* Set the nodes as 'to be ignored on mixer' */
 452         for (i = 0; i < GDP_NODE_NB_BANK; i++) {
 453                 gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
 454                 gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
 455         }
 456
 457         if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb))
 458                 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
 459
 460         if (gdp->clk_pix)
 461                 clk_disable_unprepare(gdp->clk_pix);
 462
 463         gdp->plane.status = STI_PLANE_DISABLED;
 464         gdp->vtg = NULL;
 465 }
 466
 467 /**
 468  * sti_gdp_field_cb
 469  * @nb: notifier block
 470  * @event: event message
 471  * @data: private data
 472  *
 473  * Handle VTG top field and bottom field event.
 474  *
 475  * RETURNS:
 476  * 0 on success.
 477  */
 478 static int sti_gdp_field_cb(struct notifier_block *nb,
 479                             unsigned long event, void *data)
 480 {
 481         struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb);
 482
 483         if (gdp->plane.status == STI_PLANE_FLUSHING) {
 484                 /* disable need to be synchronize on vsync event */
 485                 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
 486                                  sti_plane_to_str(&gdp->plane));
 487
 488                 sti_gdp_disable(gdp);
 489         }
 490
 491         switch (event) {
 492         case VTG_TOP_FIELD_EVENT:
 493                 gdp->is_curr_top = true;
 494                 break;
 495         case VTG_BOTTOM_FIELD_EVENT:
 496                 gdp->is_curr_top = false;
 497                 break;
 498         default:
 499                 DRM_ERROR("unsupported event: %lu\n", event);
 500                 break;
 501         }
 502
 503         return 0;
 504 }
 505
 506 static void sti_gdp_init(struct sti_gdp *gdp)
 507 {
 508         struct device_node *np = gdp->dev->of_node;
 509         dma_addr_t dma_addr;
 510         void *base;
 511         unsigned int i, size;
 512
 513         /* Allocate all the nodes within a single memory page */
 514         size = sizeof(struct sti_gdp_node) *
 515             GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK;
 516         base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL | GFP_DMA);
 517
 518         if (!base) {
 519                 DRM_ERROR("Failed to allocate memory for GDP node\n");
 520                 return;
 521         }
 522         memset(base, 0, size);
 523
 524         for (i = 0; i < GDP_NODE_NB_BANK; i++) {
 525                 if (dma_addr & 0xF) {
 526                         DRM_ERROR("Mem alignment failed\n");
 527                         return;
 528                 }
 529                 gdp->node_list[i].top_field = base;
 530                 gdp->node_list[i].top_field_paddr = dma_addr;
 531
 532                 DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base);
 533                 base += sizeof(struct sti_gdp_node);
 534                 dma_addr += sizeof(struct sti_gdp_node);
 535
 536                 if (dma_addr & 0xF) {
 537                         DRM_ERROR("Mem alignment failed\n");
 538                         return;
 539                 }
 540                 gdp->node_list[i].btm_field = base;
 541                 gdp->node_list[i].btm_field_paddr = dma_addr;
 542                 DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base);
 543                 base += sizeof(struct sti_gdp_node);
 544                 dma_addr += sizeof(struct sti_gdp_node);
 545         }
 546
 547         if (of_device_is_compatible(np, "st,stih407-compositor")) {
 548                 /* GDP of STiH407 chip have its own pixel clock */
 549                 char *clk_name;
 550
 551                 switch (gdp->plane.desc) {
 552                 case STI_GDP_0:
 553                         clk_name = "pix_gdp1";
 554                         break;
 555                 case STI_GDP_1:
 556                         clk_name = "pix_gdp2";
 557                         break;
 558                 case STI_GDP_2:
 559                         clk_name = "pix_gdp3";
 560                         break;
 561                 case STI_GDP_3:
 562                         clk_name = "pix_gdp4";
 563                         break;
 564                 default:
 565                         DRM_ERROR("GDP id not recognized\n");
 566                         return;
 567                 }
 568
 569                 gdp->clk_pix = devm_clk_get(gdp->dev, clk_name);
 570                 if (IS_ERR(gdp->clk_pix))
 571                         DRM_ERROR("Cannot get %s clock\n", clk_name);
 572
 573                 gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent");
 574                 if (IS_ERR(gdp->clk_main_parent))
 575                         DRM_ERROR("Cannot get main_parent clock\n");
 576
 577                 gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent");
 578                 if (IS_ERR(gdp->clk_aux_parent))
 579                         DRM_ERROR("Cannot get aux_parent clock\n");
 580         }
 581 }
 582
 583 /**
 584  * sti_gdp_get_dst
 585  * @dev: device
 586  * @dst: requested destination size
 587  * @src: source size
 588  *
 589  * Return the cropped / clamped destination size
 590  *
 591  * RETURNS:
 592  * cropped / clamped destination size
 593  */
 594 static int sti_gdp_get_dst(struct device *dev, int dst, int src)
 595 {
 596         if (dst == src)
 597                 return dst;
 598
 599         if (dst < src) {
 600                 dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n");
 601                 return dst;
 602         }
 603
 604         dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n");
 605         return src;
 606 }
 607
 608 static int sti_gdp_atomic_check(struct drm_plane *drm_plane,
 609                                 struct drm_plane_state *state)
 610 {
 611         struct sti_plane *plane = to_sti_plane(drm_plane);
 612         struct sti_gdp *gdp = to_sti_gdp(plane);
 613         struct drm_crtc *crtc = state->crtc;
 614         struct drm_framebuffer *fb =  state->fb;
 615         struct drm_crtc_state *crtc_state;
 616         struct sti_mixer *mixer;
 617         struct drm_display_mode *mode;
 618         int dst_x, dst_y, dst_w, dst_h;
 619         int src_x, src_y, src_w, src_h;
 620         int format;
 621
 622         /* no need for further checks if the plane is being disabled */
 623         if (!crtc || !fb)
 624                 return 0;
 625
 626         mixer = to_sti_mixer(crtc);
 627         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 628         mode = &crtc_state->mode;
 629         dst_x = state->crtc_x;
 630         dst_y = state->crtc_y;
 631         dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x);
 632         dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y);
 633         /* src_x are in 16.16 format */
 634         src_x = state->src_x >> 16;
 635         src_y = state->src_y >> 16;
 636         src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH);
 637         src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT);
 638
 639         format = sti_gdp_fourcc2format(fb->format->format);
 640         if (format == -1) {
 641                 DRM_ERROR("Format not supported by GDP %.4s\n",
 642                           (char *)&fb->format->format);
 643                 return -EINVAL;
 644         }
 645
 646         if (!drm_fb_cma_get_gem_obj(fb, 0)) {
 647                 DRM_ERROR("Can't get CMA GEM object for fb\n");
 648                 return -EINVAL;
 649         }
 650
 651         /* Set gdp clock */
 652         if (mode->clock && gdp->clk_pix) {
 653                 struct clk *clkp;
 654                 int rate = mode->clock * 1000;
 655                 int res;
 656
 657                 /*
 658                  * According to the mixer used, the gdp pixel clock
 659                  * should have a different parent clock.
 660                  */
 661                 if (mixer->id == STI_MIXER_MAIN)
 662                         clkp = gdp->clk_main_parent;
 663                 else
 664                         clkp = gdp->clk_aux_parent;
 665
 666                 if (clkp)
 667                         clk_set_parent(gdp->clk_pix, clkp);
 668
 669                 res = clk_set_rate(gdp->clk_pix, rate);
 670                 if (res < 0) {
 671                         DRM_ERROR("Cannot set rate (%dHz) for gdp\n",
 672                                   rate);
 673                         return -EINVAL;
 674                 }
 675         }
 676
 677         DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
 678                       crtc->base.id, sti_mixer_to_str(mixer),
 679                       drm_plane->base.id, sti_plane_to_str(plane));
 680         DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
 681                       sti_plane_to_str(plane),
 682                       dst_w, dst_h, dst_x, dst_y,
 683                       src_w, src_h, src_x, src_y);
 684
 685         return 0;
 686 }
 687
 688 static void sti_gdp_atomic_update(struct drm_plane *drm_plane,
 689                                   struct drm_plane_state *oldstate)
 690 {
 691         struct drm_plane_state *state = drm_plane->state;
 692         struct sti_plane *plane = to_sti_plane(drm_plane);
 693         struct sti_gdp *gdp = to_sti_gdp(plane);
 694         struct drm_crtc *crtc = state->crtc;
 695         struct drm_framebuffer *fb =  state->fb;
 696         struct drm_display_mode *mode;
 697         int dst_x, dst_y, dst_w, dst_h;
 698         int src_x, src_y, src_w, src_h;
 699         struct drm_gem_cma_object *cma_obj;
 700         struct sti_gdp_node_list *list;
 701         struct sti_gdp_node_list *curr_list;
 702         struct sti_gdp_node *top_field, *btm_field;
 703         u32 dma_updated_top;
 704         u32 dma_updated_btm;
 705         int format;
 706         unsigned int bpp;
 707         u32 ydo, xdo, yds, xds;
 708
 709         if (!crtc || !fb)
 710                 return;
 711
 712         if ((oldstate->fb == state->fb) &&
 713             (oldstate->crtc_x == state->crtc_x) &&
 714             (oldstate->crtc_y == state->crtc_y) &&
 715             (oldstate->crtc_w == state->crtc_w) &&
 716             (oldstate->crtc_h == state->crtc_h) &&
 717             (oldstate->src_x == state->src_x) &&
 718             (oldstate->src_y == state->src_y) &&
 719             (oldstate->src_w == state->src_w) &&
 720             (oldstate->src_h == state->src_h)) {
 721                 /* No change since last update, do not post cmd */
 722                 DRM_DEBUG_DRIVER("No change, not posting cmd\n");
 723                 plane->status = STI_PLANE_UPDATED;
 724                 return;
 725         }
 726
 727         if (!gdp->vtg) {
 728                 struct sti_compositor *compo = dev_get_drvdata(gdp->dev);
 729                 struct sti_mixer *mixer = to_sti_mixer(crtc);
 730
 731                 /* Register gdp callback */
 732                 gdp->vtg = compo->vtg[mixer->id];
 733                 sti_vtg_register_client(gdp->vtg, &gdp->vtg_field_nb, crtc);
 734                 clk_prepare_enable(gdp->clk_pix);
 735         }
 736
 737         mode = &crtc->mode;
 738         dst_x = state->crtc_x;
 739         dst_y = state->crtc_y;
 740         dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x);
 741         dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y);
 742         /* src_x are in 16.16 format */
 743         src_x = state->src_x >> 16;
 744         src_y = state->src_y >> 16;
 745         src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH);
 746         src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT);
 747
 748         list = sti_gdp_get_free_nodes(gdp);
 749         top_field = list->top_field;
 750         btm_field = list->btm_field;
 751
 752         dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__,
 753                 sti_plane_to_str(plane), top_field, btm_field);
 754
 755         /* build the top field */
 756         top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE;
 757         top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC;
 758         format = sti_gdp_fourcc2format(fb->format->format);
 759         top_field->gam_gdp_ctl |= format;
 760         top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format);
 761         top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE;
 762
 763         cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
 764
 765         DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id,
 766                          (char *)&fb->format->format,
 767                          (unsigned long)cma_obj->paddr);
 768
 769         /* pixel memory location */
 770         bpp = fb->format->cpp[0];
 771         top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0];
 772         top_field->gam_gdp_pml += src_x * bpp;
 773         top_field->gam_gdp_pml += src_y * fb->pitches[0];
 774
 775         /* output parameters (clamped / cropped) */
 776         dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w);
 777         dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h);
 778         ydo = sti_vtg_get_line_number(*mode, dst_y);
 779         yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1);
 780         xdo = sti_vtg_get_pixel_number(*mode, dst_x);
 781         xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1);
 782         top_field->gam_gdp_vpo = (ydo << 16) | xdo;
 783         top_field->gam_gdp_vps = (yds << 16) | xds;
 784
 785         /* input parameters */
 786         src_w = dst_w;
 787         top_field->gam_gdp_pmp = fb->pitches[0];
 788         top_field->gam_gdp_size = src_h << 16 | src_w;
 789
 790         /* Same content and chained together */
 791         memcpy(btm_field, top_field, sizeof(*btm_field));
 792         top_field->gam_gdp_nvn = list->btm_field_paddr;
 793         btm_field->gam_gdp_nvn = list->top_field_paddr;
 794
 795         /* Interlaced mode */
 796         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 797                 btm_field->gam_gdp_pml = top_field->gam_gdp_pml +
 798                                          fb->pitches[0];
 799
 800         /* Update the NVN field of the 'right' field of the current GDP node
 801          * (being used by the HW) with the address of the updated ('free') top
 802          * field GDP node.
 803          * - In interlaced mode the 'right' field is the bottom field as we
 804          *   update frames starting from their top field
 805          * - In progressive mode, we update both bottom and top fields which
 806          *   are equal nodes.
 807          * At the next VSYNC, the updated node list will be used by the HW.
 808          */
 809         curr_list = sti_gdp_get_current_nodes(gdp);
 810         dma_updated_top = list->top_field_paddr;
 811         dma_updated_btm = list->btm_field_paddr;
 812
 813         dev_dbg(gdp->dev, "Current NVN:0x%X\n",
 814                 readl(gdp->regs + GAM_GDP_NVN_OFFSET));
 815         dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n",
 816                 (unsigned long)cma_obj->paddr,
 817                 readl(gdp->regs + GAM_GDP_PML_OFFSET));
 818
 819         if (!curr_list) {
 820                 /* First update or invalid node should directly write in the
 821                  * hw register */
 822                 DRM_DEBUG_DRIVER("%s first update (or invalid node)\n",
 823                                  sti_plane_to_str(plane));
 824
 825                 writel(gdp->is_curr_top ?
 826                                 dma_updated_btm : dma_updated_top,
 827                                 gdp->regs + GAM_GDP_NVN_OFFSET);
 828                 goto end;
 829         }
 830
 831         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 832                 if (gdp->is_curr_top) {
 833                         /* Do not update in the middle of the frame, but
 834                          * postpone the update after the bottom field has
 835                          * been displayed */
 836                         curr_list->btm_field->gam_gdp_nvn = dma_updated_top;
 837                 } else {
 838                         /* Direct update to avoid one frame delay */
 839                         writel(dma_updated_top,
 840                                gdp->regs + GAM_GDP_NVN_OFFSET);
 841                 }
 842         } else {
 843                 /* Direct update for progressive to avoid one frame delay */
 844                 writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET);
 845         }
 846
 847 end:
 848         sti_plane_update_fps(plane, true, false);
 849
 850         plane->status = STI_PLANE_UPDATED;
 851 }
 852
 853 static void sti_gdp_atomic_disable(struct drm_plane *drm_plane,
 854                                    struct drm_plane_state *oldstate)
 855 {
 856         struct sti_plane *plane = to_sti_plane(drm_plane);
 857
 858         if (!oldstate->crtc) {
 859                 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
 860                                  drm_plane->base.id);
 861                 return;
 862         }
 863
 864         DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
 865                          oldstate->crtc->base.id,
 866                          sti_mixer_to_str(to_sti_mixer(oldstate->crtc)),
 867                          drm_plane->base.id, sti_plane_to_str(plane));
 868
 869         plane->status = STI_PLANE_DISABLING;
 870 }
 871
 872 static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = {
 873         .atomic_check = sti_gdp_atomic_check,
 874         .atomic_update = sti_gdp_atomic_update,
 875         .atomic_disable = sti_gdp_atomic_disable,
 876 };
 877
 878 static void sti_gdp_destroy(struct drm_plane *drm_plane)
 879 {
 880         DRM_DEBUG_DRIVER("\n");
 881
 882         drm_plane_helper_disable(drm_plane);
 883         drm_plane_cleanup(drm_plane);
 884 }
 885
 886 static int sti_gdp_late_register(struct drm_plane *drm_plane)
 887 {
 888         struct sti_plane *plane = to_sti_plane(drm_plane);
 889         struct sti_gdp *gdp = to_sti_gdp(plane);
 890
 891         return gdp_debugfs_init(gdp, drm_plane->dev->primary);
 892 }
 893
 894 static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs = {
 895         .update_plane = drm_atomic_helper_update_plane,
 896         .disable_plane = drm_atomic_helper_disable_plane,
 897         .destroy = sti_gdp_destroy,
 898         .reset = sti_plane_reset,
 899         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 900         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 901         .late_register = sti_gdp_late_register,
 902 };
 903
 904 struct drm_plane *sti_gdp_create(struct drm_device *drm_dev,
 905                                  struct device *dev, int desc,
 906                                  void __iomem *baseaddr,
 907                                  unsigned int possible_crtcs,
 908                                  enum drm_plane_type type)
 909 {
 910         struct sti_gdp *gdp;
 911         int res;
 912
 913         gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL);
 914         if (!gdp) {
 915                 DRM_ERROR("Failed to allocate memory for GDP\n");
 916                 return NULL;
 917         }
 918
 919         gdp->dev = dev;
 920         gdp->regs = baseaddr;
 921         gdp->plane.desc = desc;
 922         gdp->plane.status = STI_PLANE_DISABLED;
 923
 924         gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb;
 925
 926         sti_gdp_init(gdp);
 927
 928         res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane,
 929                                        possible_crtcs,
 930                                        &sti_gdp_plane_helpers_funcs,
 931                                        gdp_supported_formats,
 932                                        ARRAY_SIZE(gdp_supported_formats),
 933                                        NULL, type, NULL);
 934         if (res) {
 935                 DRM_ERROR("Failed to initialize universal plane\n");
 936                 goto err;
 937         }
 938
 939         drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs);
 940
 941         sti_plane_init_property(&gdp->plane, type);
 942
 943         return &gdp->plane.drm_plane;
 944
 945 err:
 946         devm_kfree(dev, gdp);
 947         return NULL;
 948 }