1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics SA 2014
4 * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
8 #include <linux/component.h>
9 #include <linux/debugfs.h>
10 #include <linux/hdmi.h>
11 #include <linux/module.h>
12 #include <linux/of_gpio.h>
13 #include <linux/platform_device.h>
14 #include <linux/reset.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_crtc_helper.h>
19 #include <drm/drm_edid.h>
21 #include <sound/hdmi-codec.h>
24 #include "sti_hdmi_tx3g4c28phy.h"
27 #define HDMI_CFG 0x0000
28 #define HDMI_INT_EN 0x0004
29 #define HDMI_INT_STA 0x0008
30 #define HDMI_INT_CLR 0x000C
31 #define HDMI_STA 0x0010
32 #define HDMI_ACTIVE_VID_XMIN 0x0100
33 #define HDMI_ACTIVE_VID_XMAX 0x0104
34 #define HDMI_ACTIVE_VID_YMIN 0x0108
35 #define HDMI_ACTIVE_VID_YMAX 0x010C
36 #define HDMI_DFLT_CHL0_DAT 0x0110
37 #define HDMI_DFLT_CHL1_DAT 0x0114
38 #define HDMI_DFLT_CHL2_DAT 0x0118
39 #define HDMI_AUDIO_CFG 0x0200
40 #define HDMI_SPDIF_FIFO_STATUS 0x0204
41 #define HDMI_SW_DI_1_HEAD_WORD 0x0210
42 #define HDMI_SW_DI_1_PKT_WORD0 0x0214
43 #define HDMI_SW_DI_1_PKT_WORD1 0x0218
44 #define HDMI_SW_DI_1_PKT_WORD2 0x021C
45 #define HDMI_SW_DI_1_PKT_WORD3 0x0220
46 #define HDMI_SW_DI_1_PKT_WORD4 0x0224
47 #define HDMI_SW_DI_1_PKT_WORD5 0x0228
48 #define HDMI_SW_DI_1_PKT_WORD6 0x022C
49 #define HDMI_SW_DI_CFG 0x0230
50 #define HDMI_SAMPLE_FLAT_MASK 0x0244
51 #define HDMI_AUDN 0x0400
52 #define HDMI_AUD_CTS 0x0404
53 #define HDMI_SW_DI_2_HEAD_WORD 0x0600
54 #define HDMI_SW_DI_2_PKT_WORD0 0x0604
55 #define HDMI_SW_DI_2_PKT_WORD1 0x0608
56 #define HDMI_SW_DI_2_PKT_WORD2 0x060C
57 #define HDMI_SW_DI_2_PKT_WORD3 0x0610
58 #define HDMI_SW_DI_2_PKT_WORD4 0x0614
59 #define HDMI_SW_DI_2_PKT_WORD5 0x0618
60 #define HDMI_SW_DI_2_PKT_WORD6 0x061C
61 #define HDMI_SW_DI_3_HEAD_WORD 0x0620
62 #define HDMI_SW_DI_3_PKT_WORD0 0x0624
63 #define HDMI_SW_DI_3_PKT_WORD1 0x0628
64 #define HDMI_SW_DI_3_PKT_WORD2 0x062C
65 #define HDMI_SW_DI_3_PKT_WORD3 0x0630
66 #define HDMI_SW_DI_3_PKT_WORD4 0x0634
67 #define HDMI_SW_DI_3_PKT_WORD5 0x0638
68 #define HDMI_SW_DI_3_PKT_WORD6 0x063C
70 #define HDMI_IFRAME_SLOT_AVI 1
71 #define HDMI_IFRAME_SLOT_AUDIO 2
72 #define HDMI_IFRAME_SLOT_VENDOR 3
74 #define XCAT(prefix, x, suffix) prefix ## x ## suffix
75 #define HDMI_SW_DI_N_HEAD_WORD(x) XCAT(HDMI_SW_DI_, x, _HEAD_WORD)
76 #define HDMI_SW_DI_N_PKT_WORD0(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD0)
77 #define HDMI_SW_DI_N_PKT_WORD1(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD1)
78 #define HDMI_SW_DI_N_PKT_WORD2(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD2)
79 #define HDMI_SW_DI_N_PKT_WORD3(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD3)
80 #define HDMI_SW_DI_N_PKT_WORD4(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD4)
81 #define HDMI_SW_DI_N_PKT_WORD5(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD5)
82 #define HDMI_SW_DI_N_PKT_WORD6(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD6)
84 #define HDMI_SW_DI_MAX_WORD 7
86 #define HDMI_IFRAME_DISABLED 0x0
87 #define HDMI_IFRAME_SINGLE_SHOT 0x1
88 #define HDMI_IFRAME_FIELD 0x2
89 #define HDMI_IFRAME_FRAME 0x3
90 #define HDMI_IFRAME_MASK 0x3
91 #define HDMI_IFRAME_CFG_DI_N(x, n) ((x) << ((n-1)*4)) /* n from 1 to 6 */
93 #define HDMI_CFG_DEVICE_EN BIT(0)
94 #define HDMI_CFG_HDMI_NOT_DVI BIT(1)
95 #define HDMI_CFG_HDCP_EN BIT(2)
96 #define HDMI_CFG_ESS_NOT_OESS BIT(3)
97 #define HDMI_CFG_H_SYNC_POL_NEG BIT(4)
98 #define HDMI_CFG_V_SYNC_POL_NEG BIT(6)
99 #define HDMI_CFG_422_EN BIT(8)
100 #define HDMI_CFG_FIFO_OVERRUN_CLR BIT(12)
101 #define HDMI_CFG_FIFO_UNDERRUN_CLR BIT(13)
102 #define HDMI_CFG_SW_RST_EN BIT(31)
104 #define HDMI_INT_GLOBAL BIT(0)
105 #define HDMI_INT_SW_RST BIT(1)
106 #define HDMI_INT_PIX_CAP BIT(3)
107 #define HDMI_INT_HOT_PLUG BIT(4)
108 #define HDMI_INT_DLL_LCK BIT(5)
109 #define HDMI_INT_NEW_FRAME BIT(6)
110 #define HDMI_INT_GENCTRL_PKT BIT(7)
111 #define HDMI_INT_AUDIO_FIFO_XRUN BIT(8)
112 #define HDMI_INT_SINK_TERM_PRESENT BIT(11)
114 #define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \
116 | HDMI_INT_HOT_PLUG \
119 #define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \
120 | HDMI_INT_AUDIO_FIFO_XRUN \
121 | HDMI_INT_GENCTRL_PKT \
122 | HDMI_INT_NEW_FRAME \
124 | HDMI_INT_HOT_PLUG \
129 #define HDMI_STA_SW_RST BIT(1)
131 #define HDMI_AUD_CFG_8CH BIT(0)
132 #define HDMI_AUD_CFG_SPDIF_DIV_2 BIT(1)
133 #define HDMI_AUD_CFG_SPDIF_DIV_3 BIT(2)
134 #define HDMI_AUD_CFG_SPDIF_CLK_DIV_4 (BIT(1) | BIT(2))
135 #define HDMI_AUD_CFG_CTS_CLK_256FS BIT(12)
136 #define HDMI_AUD_CFG_DTS_INVALID BIT(16)
137 #define HDMI_AUD_CFG_ONE_BIT_INVALID (BIT(18) | BIT(19) | BIT(20) | BIT(21))
138 #define HDMI_AUD_CFG_CH12_VALID BIT(28)
139 #define HDMI_AUD_CFG_CH34_VALID BIT(29)
140 #define HDMI_AUD_CFG_CH56_VALID BIT(30)
141 #define HDMI_AUD_CFG_CH78_VALID BIT(31)
143 /* sample flat mask */
144 #define HDMI_SAMPLE_FLAT_NO 0
145 #define HDMI_SAMPLE_FLAT_SP0 BIT(0)
146 #define HDMI_SAMPLE_FLAT_SP1 BIT(1)
147 #define HDMI_SAMPLE_FLAT_SP2 BIT(2)
148 #define HDMI_SAMPLE_FLAT_SP3 BIT(3)
149 #define HDMI_SAMPLE_FLAT_ALL (HDMI_SAMPLE_FLAT_SP0 | HDMI_SAMPLE_FLAT_SP1 |\
150 HDMI_SAMPLE_FLAT_SP2 | HDMI_SAMPLE_FLAT_SP3)
152 #define HDMI_INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
153 #define HDMI_INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
154 #define HDMI_INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)
156 struct sti_hdmi_connector
{
157 struct drm_connector drm_connector
;
158 struct drm_encoder
*encoder
;
159 struct sti_hdmi
*hdmi
;
160 struct drm_property
*colorspace_property
;
163 #define to_sti_hdmi_connector(x) \
164 container_of(x, struct sti_hdmi_connector, drm_connector)
166 u32
hdmi_read(struct sti_hdmi
*hdmi
, int offset
)
168 return readl(hdmi
->regs
+ offset
);
171 void hdmi_write(struct sti_hdmi
*hdmi
, u32 val
, int offset
)
173 writel(val
, hdmi
->regs
+ offset
);
177 * HDMI interrupt handler threaded
180 * @arg: connector structure
182 static irqreturn_t
hdmi_irq_thread(int irq
, void *arg
)
184 struct sti_hdmi
*hdmi
= arg
;
186 /* Hot plug/unplug IRQ */
187 if (hdmi
->irq_status
& HDMI_INT_HOT_PLUG
) {
188 hdmi
->hpd
= readl(hdmi
->regs
+ HDMI_STA
) & HDMI_STA_HOT_PLUG
;
190 drm_helper_hpd_irq_event(hdmi
->drm_dev
);
193 /* Sw reset and PLL lock are exclusive so we can use the same
194 * event to signal them
196 if (hdmi
->irq_status
& (HDMI_INT_SW_RST
| HDMI_INT_DLL_LCK
)) {
197 hdmi
->event_received
= true;
198 wake_up_interruptible(&hdmi
->wait_event
);
201 /* Audio FIFO underrun IRQ */
202 if (hdmi
->irq_status
& HDMI_INT_AUDIO_FIFO_XRUN
)
203 DRM_INFO("Warning: audio FIFO underrun occurs!\n");
209 * HDMI interrupt handler
212 * @arg: connector structure
214 static irqreturn_t
hdmi_irq(int irq
, void *arg
)
216 struct sti_hdmi
*hdmi
= arg
;
218 /* read interrupt status */
219 hdmi
->irq_status
= hdmi_read(hdmi
, HDMI_INT_STA
);
221 /* clear interrupt status */
222 hdmi_write(hdmi
, hdmi
->irq_status
, HDMI_INT_CLR
);
224 /* force sync bus write */
225 hdmi_read(hdmi
, HDMI_INT_STA
);
227 return IRQ_WAKE_THREAD
;
231 * Set hdmi active area depending on the drm display mode selected
233 * @hdmi: pointer on the hdmi internal structure
235 static void hdmi_active_area(struct sti_hdmi
*hdmi
)
240 xmin
= sti_vtg_get_pixel_number(hdmi
->mode
, 1);
241 xmax
= sti_vtg_get_pixel_number(hdmi
->mode
, hdmi
->mode
.hdisplay
);
242 ymin
= sti_vtg_get_line_number(hdmi
->mode
, 0);
243 ymax
= sti_vtg_get_line_number(hdmi
->mode
, hdmi
->mode
.vdisplay
- 1);
245 hdmi_write(hdmi
, xmin
, HDMI_ACTIVE_VID_XMIN
);
246 hdmi_write(hdmi
, xmax
, HDMI_ACTIVE_VID_XMAX
);
247 hdmi_write(hdmi
, ymin
, HDMI_ACTIVE_VID_YMIN
);
248 hdmi_write(hdmi
, ymax
, HDMI_ACTIVE_VID_YMAX
);
252 * Overall hdmi configuration
254 * @hdmi: pointer on the hdmi internal structure
256 static void hdmi_config(struct sti_hdmi
*hdmi
)
260 DRM_DEBUG_DRIVER("\n");
262 /* Clear overrun and underrun fifo */
263 conf
= HDMI_CFG_FIFO_OVERRUN_CLR
| HDMI_CFG_FIFO_UNDERRUN_CLR
;
265 /* Select encryption type and the framing mode */
266 conf
|= HDMI_CFG_ESS_NOT_OESS
;
267 if (hdmi
->hdmi_monitor
)
268 conf
|= HDMI_CFG_HDMI_NOT_DVI
;
270 /* Set Hsync polarity */
271 if (hdmi
->mode
.flags
& DRM_MODE_FLAG_NHSYNC
) {
272 DRM_DEBUG_DRIVER("H Sync Negative\n");
273 conf
|= HDMI_CFG_H_SYNC_POL_NEG
;
276 /* Set Vsync polarity */
277 if (hdmi
->mode
.flags
& DRM_MODE_FLAG_NVSYNC
) {
278 DRM_DEBUG_DRIVER("V Sync Negative\n");
279 conf
|= HDMI_CFG_V_SYNC_POL_NEG
;
283 conf
|= HDMI_CFG_DEVICE_EN
;
285 hdmi_write(hdmi
, conf
, HDMI_CFG
);
289 * Helper to reset info frame
291 * @hdmi: pointer on the hdmi internal structure
292 * @slot: infoframe to reset
294 static void hdmi_infoframe_reset(struct sti_hdmi
*hdmi
,
298 u32 head_offset
, pack_offset
;
301 case HDMI_IFRAME_SLOT_AVI
:
302 head_offset
= HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI
);
303 pack_offset
= HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI
);
305 case HDMI_IFRAME_SLOT_AUDIO
:
306 head_offset
= HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO
);
307 pack_offset
= HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO
);
309 case HDMI_IFRAME_SLOT_VENDOR
:
310 head_offset
= HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR
);
311 pack_offset
= HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR
);
314 DRM_ERROR("unsupported infoframe slot: %#x\n", slot
);
318 /* Disable transmission for the selected slot */
319 val
= hdmi_read(hdmi
, HDMI_SW_DI_CFG
);
320 val
&= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK
, slot
);
321 hdmi_write(hdmi
, val
, HDMI_SW_DI_CFG
);
323 /* Reset info frame registers */
324 hdmi_write(hdmi
, 0x0, head_offset
);
325 for (i
= 0; i
< HDMI_SW_DI_MAX_WORD
; i
+= sizeof(u32
))
326 hdmi_write(hdmi
, 0x0, pack_offset
+ i
);
330 * Helper to concatenate infoframe in 32 bits word
332 * @ptr: pointer on the hdmi internal structure
333 * @data: infoframe to write
334 * @size: size to write
336 static inline unsigned int hdmi_infoframe_subpack(const u8
*ptr
, size_t size
)
338 unsigned long value
= 0;
341 for (i
= size
; i
> 0; i
--)
342 value
= (value
<< 8) | ptr
[i
- 1];
348 * Helper to write info frame
350 * @hdmi: pointer on the hdmi internal structure
351 * @data: infoframe to write
352 * @size: size to write
354 static void hdmi_infoframe_write_infopack(struct sti_hdmi
*hdmi
,
358 const u8
*ptr
= data
;
359 u32 val
, slot
, mode
, i
;
360 u32 head_offset
, pack_offset
;
363 case HDMI_INFOFRAME_TYPE_AVI
:
364 slot
= HDMI_IFRAME_SLOT_AVI
;
365 mode
= HDMI_IFRAME_FIELD
;
366 head_offset
= HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI
);
367 pack_offset
= HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI
);
369 case HDMI_INFOFRAME_TYPE_AUDIO
:
370 slot
= HDMI_IFRAME_SLOT_AUDIO
;
371 mode
= HDMI_IFRAME_FRAME
;
372 head_offset
= HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO
);
373 pack_offset
= HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO
);
375 case HDMI_INFOFRAME_TYPE_VENDOR
:
376 slot
= HDMI_IFRAME_SLOT_VENDOR
;
377 mode
= HDMI_IFRAME_FRAME
;
378 head_offset
= HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR
);
379 pack_offset
= HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR
);
382 DRM_ERROR("unsupported infoframe type: %#x\n", *ptr
);
386 /* Disable transmission slot for updated infoframe */
387 val
= hdmi_read(hdmi
, HDMI_SW_DI_CFG
);
388 val
&= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK
, slot
);
389 hdmi_write(hdmi
, val
, HDMI_SW_DI_CFG
);
391 val
= HDMI_INFOFRAME_HEADER_TYPE(*ptr
++);
392 val
|= HDMI_INFOFRAME_HEADER_VERSION(*ptr
++);
393 val
|= HDMI_INFOFRAME_HEADER_LEN(*ptr
++);
394 writel(val
, hdmi
->regs
+ head_offset
);
397 * Each subpack contains 4 bytes
398 * The First Bytes of the first subpacket must contain the checksum
399 * Packet size is increase by one.
401 size
= size
- HDMI_INFOFRAME_HEADER_SIZE
+ 1;
402 for (i
= 0; i
< size
; i
+= sizeof(u32
)) {
405 num
= min_t(size_t, size
- i
, sizeof(u32
));
406 val
= hdmi_infoframe_subpack(ptr
, num
);
408 writel(val
, hdmi
->regs
+ pack_offset
+ i
);
411 /* Enable transmission slot for updated infoframe */
412 val
= hdmi_read(hdmi
, HDMI_SW_DI_CFG
);
413 val
|= HDMI_IFRAME_CFG_DI_N(mode
, slot
);
414 hdmi_write(hdmi
, val
, HDMI_SW_DI_CFG
);
418 * Prepare and configure the AVI infoframe
420 * AVI infoframe are transmitted at least once per two video field and
421 * contains information about HDMI transmission mode such as color space,
424 * @hdmi: pointer on the hdmi internal structure
426 * Return negative value if error occurs
428 static int hdmi_avi_infoframe_config(struct sti_hdmi
*hdmi
)
430 struct drm_display_mode
*mode
= &hdmi
->mode
;
431 struct hdmi_avi_infoframe infoframe
;
432 u8 buffer
[HDMI_INFOFRAME_SIZE(AVI
)];
435 DRM_DEBUG_DRIVER("\n");
437 ret
= drm_hdmi_avi_infoframe_from_display_mode(&infoframe
, mode
, false);
439 DRM_ERROR("failed to setup AVI infoframe: %d\n", ret
);
443 /* fixed infoframe configuration not linked to the mode */
444 infoframe
.colorspace
= hdmi
->colorspace
;
445 infoframe
.quantization_range
= HDMI_QUANTIZATION_RANGE_DEFAULT
;
446 infoframe
.colorimetry
= HDMI_COLORIMETRY_NONE
;
448 ret
= hdmi_avi_infoframe_pack(&infoframe
, buffer
, sizeof(buffer
));
450 DRM_ERROR("failed to pack AVI infoframe: %d\n", ret
);
454 hdmi_infoframe_write_infopack(hdmi
, buffer
, ret
);
460 * Prepare and configure the AUDIO infoframe
462 * AUDIO infoframe are transmitted once per frame and
463 * contains information about HDMI transmission mode such as audio codec,
466 * @hdmi: pointer on the hdmi internal structure
468 * Return negative value if error occurs
470 static int hdmi_audio_infoframe_config(struct sti_hdmi
*hdmi
)
472 struct hdmi_audio_params
*audio
= &hdmi
->audio
;
473 u8 buffer
[HDMI_INFOFRAME_SIZE(AUDIO
)];
476 DRM_DEBUG_DRIVER("enter %s, AIF %s\n", __func__
,
477 audio
->enabled
? "enable" : "disable");
478 if (audio
->enabled
) {
479 /* set audio parameters stored*/
480 ret
= hdmi_audio_infoframe_pack(&audio
->cea
, buffer
,
483 DRM_ERROR("failed to pack audio infoframe: %d\n", ret
);
486 hdmi_infoframe_write_infopack(hdmi
, buffer
, ret
);
488 /*disable audio info frame transmission */
489 val
= hdmi_read(hdmi
, HDMI_SW_DI_CFG
);
490 val
&= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK
,
491 HDMI_IFRAME_SLOT_AUDIO
);
492 hdmi_write(hdmi
, val
, HDMI_SW_DI_CFG
);
499 * Prepare and configure the VS infoframe
501 * Vendor Specific infoframe are transmitted once per frame and
502 * contains vendor specific information.
504 * @hdmi: pointer on the hdmi internal structure
506 * Return negative value if error occurs
508 #define HDMI_VENDOR_INFOFRAME_MAX_SIZE 6
509 static int hdmi_vendor_infoframe_config(struct sti_hdmi
*hdmi
)
511 struct drm_display_mode
*mode
= &hdmi
->mode
;
512 struct hdmi_vendor_infoframe infoframe
;
513 u8 buffer
[HDMI_INFOFRAME_HEADER_SIZE
+ HDMI_VENDOR_INFOFRAME_MAX_SIZE
];
516 DRM_DEBUG_DRIVER("\n");
518 ret
= drm_hdmi_vendor_infoframe_from_display_mode(&infoframe
,
523 * Going into that statement does not means vendor infoframe
524 * fails. It just informed us that vendor infoframe is not
525 * needed for the selected mode. Only 4k or stereoscopic 3D
526 * mode requires vendor infoframe. So just simply return 0.
531 ret
= hdmi_vendor_infoframe_pack(&infoframe
, buffer
, sizeof(buffer
));
533 DRM_ERROR("failed to pack VS infoframe: %d\n", ret
);
537 hdmi_infoframe_write_infopack(hdmi
, buffer
, ret
);
543 * Software reset of the hdmi subsystem
545 * @hdmi: pointer on the hdmi internal structure
548 #define HDMI_TIMEOUT_SWRESET 100 /*milliseconds */
549 static void hdmi_swreset(struct sti_hdmi
*hdmi
)
553 DRM_DEBUG_DRIVER("\n");
555 /* Enable hdmi_audio clock only during hdmi reset */
556 if (clk_prepare_enable(hdmi
->clk_audio
))
557 DRM_INFO("Failed to prepare/enable hdmi_audio clk\n");
560 hdmi
->event_received
= false;
562 val
= hdmi_read(hdmi
, HDMI_CFG
);
563 val
|= HDMI_CFG_SW_RST_EN
;
564 hdmi_write(hdmi
, val
, HDMI_CFG
);
566 /* Wait reset completed */
567 wait_event_interruptible_timeout(hdmi
->wait_event
,
568 hdmi
->event_received
,
570 (HDMI_TIMEOUT_SWRESET
));
573 * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is
574 * set to '1' and clk_audio is running.
576 if ((hdmi_read(hdmi
, HDMI_STA
) & HDMI_STA_SW_RST
) == 0)
577 DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n");
579 val
= hdmi_read(hdmi
, HDMI_CFG
);
580 val
&= ~HDMI_CFG_SW_RST_EN
;
581 hdmi_write(hdmi
, val
, HDMI_CFG
);
583 /* Disable hdmi_audio clock. Not used anymore for drm purpose */
584 clk_disable_unprepare(hdmi
->clk_audio
);
587 #define DBGFS_PRINT_STR(str1, str2) seq_printf(s, "%-24s %s\n", str1, str2)
588 #define DBGFS_PRINT_INT(str1, int2) seq_printf(s, "%-24s %d\n", str1, int2)
589 #define DBGFS_DUMP(str, reg) seq_printf(s, "%s %-25s 0x%08X", str, #reg, \
590 hdmi_read(hdmi, reg))
591 #define DBGFS_DUMP_DI(reg, slot) DBGFS_DUMP("\n", reg(slot))
593 static void hdmi_dbg_cfg(struct seq_file
*s
, int val
)
598 tmp
= val
& HDMI_CFG_HDMI_NOT_DVI
;
599 DBGFS_PRINT_STR("mode:", tmp
? "HDMI" : "DVI");
600 seq_puts(s
, "\t\t\t\t\t");
601 tmp
= val
& HDMI_CFG_HDCP_EN
;
602 DBGFS_PRINT_STR("HDCP:", tmp
? "enable" : "disable");
603 seq_puts(s
, "\t\t\t\t\t");
604 tmp
= val
& HDMI_CFG_ESS_NOT_OESS
;
605 DBGFS_PRINT_STR("HDCP mode:", tmp
? "ESS enable" : "OESS enable");
606 seq_puts(s
, "\t\t\t\t\t");
607 tmp
= val
& HDMI_CFG_H_SYNC_POL_NEG
;
608 DBGFS_PRINT_STR("Hsync polarity:", tmp
? "inverted" : "normal");
609 seq_puts(s
, "\t\t\t\t\t");
610 tmp
= val
& HDMI_CFG_V_SYNC_POL_NEG
;
611 DBGFS_PRINT_STR("Vsync polarity:", tmp
? "inverted" : "normal");
612 seq_puts(s
, "\t\t\t\t\t");
613 tmp
= val
& HDMI_CFG_422_EN
;
614 DBGFS_PRINT_STR("YUV422 format:", tmp
? "enable" : "disable");
617 static void hdmi_dbg_sta(struct seq_file
*s
, int val
)
622 tmp
= (val
& HDMI_STA_DLL_LCK
);
623 DBGFS_PRINT_STR("pll:", tmp
? "locked" : "not locked");
624 seq_puts(s
, "\t\t\t\t\t");
625 tmp
= (val
& HDMI_STA_HOT_PLUG
);
626 DBGFS_PRINT_STR("hdmi cable:", tmp
? "connected" : "not connected");
629 static void hdmi_dbg_sw_di_cfg(struct seq_file
*s
, int val
)
632 char *const en_di
[] = {"no transmission",
633 "single transmission",
638 tmp
= (val
& HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK
, 1));
639 DBGFS_PRINT_STR("Data island 1:", en_di
[tmp
]);
640 seq_puts(s
, "\t\t\t\t\t");
641 tmp
= (val
& HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK
, 2)) >> 4;
642 DBGFS_PRINT_STR("Data island 2:", en_di
[tmp
]);
643 seq_puts(s
, "\t\t\t\t\t");
644 tmp
= (val
& HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK
, 3)) >> 8;
645 DBGFS_PRINT_STR("Data island 3:", en_di
[tmp
]);
646 seq_puts(s
, "\t\t\t\t\t");
647 tmp
= (val
& HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK
, 4)) >> 12;
648 DBGFS_PRINT_STR("Data island 4:", en_di
[tmp
]);
649 seq_puts(s
, "\t\t\t\t\t");
650 tmp
= (val
& HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK
, 5)) >> 16;
651 DBGFS_PRINT_STR("Data island 5:", en_di
[tmp
]);
652 seq_puts(s
, "\t\t\t\t\t");
653 tmp
= (val
& HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK
, 6)) >> 20;
654 DBGFS_PRINT_STR("Data island 6:", en_di
[tmp
]);
657 static int hdmi_dbg_show(struct seq_file
*s
, void *data
)
659 struct drm_info_node
*node
= s
->private;
660 struct sti_hdmi
*hdmi
= (struct sti_hdmi
*)node
->info_ent
->data
;
662 seq_printf(s
, "HDMI: (vaddr = 0x%p)", hdmi
->regs
);
663 DBGFS_DUMP("\n", HDMI_CFG
);
664 hdmi_dbg_cfg(s
, hdmi_read(hdmi
, HDMI_CFG
));
665 DBGFS_DUMP("", HDMI_INT_EN
);
666 DBGFS_DUMP("\n", HDMI_STA
);
667 hdmi_dbg_sta(s
, hdmi_read(hdmi
, HDMI_STA
));
668 DBGFS_DUMP("", HDMI_ACTIVE_VID_XMIN
);
670 DBGFS_PRINT_INT("Xmin:", hdmi_read(hdmi
, HDMI_ACTIVE_VID_XMIN
));
671 DBGFS_DUMP("", HDMI_ACTIVE_VID_XMAX
);
673 DBGFS_PRINT_INT("Xmax:", hdmi_read(hdmi
, HDMI_ACTIVE_VID_XMAX
));
674 DBGFS_DUMP("", HDMI_ACTIVE_VID_YMIN
);
676 DBGFS_PRINT_INT("Ymin:", hdmi_read(hdmi
, HDMI_ACTIVE_VID_YMIN
));
677 DBGFS_DUMP("", HDMI_ACTIVE_VID_YMAX
);
679 DBGFS_PRINT_INT("Ymax:", hdmi_read(hdmi
, HDMI_ACTIVE_VID_YMAX
));
680 DBGFS_DUMP("", HDMI_SW_DI_CFG
);
681 hdmi_dbg_sw_di_cfg(s
, hdmi_read(hdmi
, HDMI_SW_DI_CFG
));
683 DBGFS_DUMP("\n", HDMI_AUDIO_CFG
);
684 DBGFS_DUMP("\n", HDMI_SPDIF_FIFO_STATUS
);
685 DBGFS_DUMP("\n", HDMI_AUDN
);
687 seq_printf(s
, "\n AVI Infoframe (Data Island slot N=%d):",
688 HDMI_IFRAME_SLOT_AVI
);
689 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD
, HDMI_IFRAME_SLOT_AVI
);
690 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0
, HDMI_IFRAME_SLOT_AVI
);
691 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1
, HDMI_IFRAME_SLOT_AVI
);
692 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2
, HDMI_IFRAME_SLOT_AVI
);
693 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3
, HDMI_IFRAME_SLOT_AVI
);
694 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4
, HDMI_IFRAME_SLOT_AVI
);
695 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5
, HDMI_IFRAME_SLOT_AVI
);
696 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6
, HDMI_IFRAME_SLOT_AVI
);
697 seq_printf(s
, "\n\n AUDIO Infoframe (Data Island slot N=%d):",
698 HDMI_IFRAME_SLOT_AUDIO
);
699 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD
, HDMI_IFRAME_SLOT_AUDIO
);
700 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0
, HDMI_IFRAME_SLOT_AUDIO
);
701 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1
, HDMI_IFRAME_SLOT_AUDIO
);
702 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2
, HDMI_IFRAME_SLOT_AUDIO
);
703 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3
, HDMI_IFRAME_SLOT_AUDIO
);
704 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4
, HDMI_IFRAME_SLOT_AUDIO
);
705 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5
, HDMI_IFRAME_SLOT_AUDIO
);
706 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6
, HDMI_IFRAME_SLOT_AUDIO
);
707 seq_printf(s
, "\n\n VENDOR SPECIFIC Infoframe (Data Island slot N=%d):",
708 HDMI_IFRAME_SLOT_VENDOR
);
709 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD
, HDMI_IFRAME_SLOT_VENDOR
);
710 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0
, HDMI_IFRAME_SLOT_VENDOR
);
711 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1
, HDMI_IFRAME_SLOT_VENDOR
);
712 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2
, HDMI_IFRAME_SLOT_VENDOR
);
713 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3
, HDMI_IFRAME_SLOT_VENDOR
);
714 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4
, HDMI_IFRAME_SLOT_VENDOR
);
715 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5
, HDMI_IFRAME_SLOT_VENDOR
);
716 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6
, HDMI_IFRAME_SLOT_VENDOR
);
721 static struct drm_info_list hdmi_debugfs_files
[] = {
722 { "hdmi", hdmi_dbg_show
, 0, NULL
},
725 static int hdmi_debugfs_init(struct sti_hdmi
*hdmi
, struct drm_minor
*minor
)
729 for (i
= 0; i
< ARRAY_SIZE(hdmi_debugfs_files
); i
++)
730 hdmi_debugfs_files
[i
].data
= hdmi
;
732 return drm_debugfs_create_files(hdmi_debugfs_files
,
733 ARRAY_SIZE(hdmi_debugfs_files
),
734 minor
->debugfs_root
, minor
);
737 static void sti_hdmi_disable(struct drm_bridge
*bridge
)
739 struct sti_hdmi
*hdmi
= bridge
->driver_private
;
741 u32 val
= hdmi_read(hdmi
, HDMI_CFG
);
746 DRM_DEBUG_DRIVER("\n");
749 val
&= ~HDMI_CFG_DEVICE_EN
;
750 hdmi_write(hdmi
, val
, HDMI_CFG
);
752 hdmi_write(hdmi
, 0xffffffff, HDMI_INT_CLR
);
755 hdmi
->phy_ops
->stop(hdmi
);
757 /* Reset info frame transmission */
758 hdmi_infoframe_reset(hdmi
, HDMI_IFRAME_SLOT_AVI
);
759 hdmi_infoframe_reset(hdmi
, HDMI_IFRAME_SLOT_AUDIO
);
760 hdmi_infoframe_reset(hdmi
, HDMI_IFRAME_SLOT_VENDOR
);
762 /* Set the default channel data to be a dark red */
763 hdmi_write(hdmi
, 0x0000, HDMI_DFLT_CHL0_DAT
);
764 hdmi_write(hdmi
, 0x0000, HDMI_DFLT_CHL1_DAT
);
765 hdmi_write(hdmi
, 0x0060, HDMI_DFLT_CHL2_DAT
);
767 /* Disable/unprepare hdmi clock */
768 clk_disable_unprepare(hdmi
->clk_phy
);
769 clk_disable_unprepare(hdmi
->clk_tmds
);
770 clk_disable_unprepare(hdmi
->clk_pix
);
772 hdmi
->enabled
= false;
774 cec_notifier_set_phys_addr(hdmi
->notifier
, CEC_PHYS_ADDR_INVALID
);
778 * sti_hdmi_audio_get_non_coherent_n() - get N parameter for non-coherent
779 * clocks. None-coherent clocks means that audio and TMDS clocks have not the
780 * same source (drifts between clocks). In this case assumption is that CTS is
781 * automatically calculated by hardware.
783 * @audio_fs: audio frame clock frequency in Hz
785 * Values computed are based on table described in HDMI specification 1.4b
789 static int sti_hdmi_audio_get_non_coherent_n(unsigned int audio_fs
)
816 /* Not pre-defined, recommended value: 128 * fs / 1000 */
817 n
= (audio_fs
* 128) / 1000;
823 static int hdmi_audio_configure(struct sti_hdmi
*hdmi
)
826 struct hdmi_audio_params
*params
= &hdmi
->audio
;
827 struct hdmi_audio_infoframe
*info
= ¶ms
->cea
;
829 DRM_DEBUG_DRIVER("\n");
834 /* update N parameter */
835 n
= sti_hdmi_audio_get_non_coherent_n(params
->sample_rate
);
837 DRM_DEBUG_DRIVER("Audio rate = %d Hz, TMDS clock = %d Hz, n = %d\n",
838 params
->sample_rate
, hdmi
->mode
.clock
* 1000, n
);
839 hdmi_write(hdmi
, n
, HDMI_AUDN
);
841 /* update HDMI registers according to configuration */
842 audio_cfg
= HDMI_AUD_CFG_SPDIF_DIV_2
| HDMI_AUD_CFG_DTS_INVALID
|
843 HDMI_AUD_CFG_ONE_BIT_INVALID
;
845 switch (info
->channels
) {
847 audio_cfg
|= HDMI_AUD_CFG_CH78_VALID
;
849 audio_cfg
|= HDMI_AUD_CFG_CH56_VALID
;
851 audio_cfg
|= HDMI_AUD_CFG_CH34_VALID
| HDMI_AUD_CFG_8CH
;
853 audio_cfg
|= HDMI_AUD_CFG_CH12_VALID
;
856 DRM_ERROR("ERROR: Unsupported number of channels (%d)!\n",
861 hdmi_write(hdmi
, audio_cfg
, HDMI_AUDIO_CFG
);
863 return hdmi_audio_infoframe_config(hdmi
);
866 static void sti_hdmi_pre_enable(struct drm_bridge
*bridge
)
868 struct sti_hdmi
*hdmi
= bridge
->driver_private
;
870 DRM_DEBUG_DRIVER("\n");
875 /* Prepare/enable clocks */
876 if (clk_prepare_enable(hdmi
->clk_pix
))
877 DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n");
878 if (clk_prepare_enable(hdmi
->clk_tmds
))
879 DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n");
880 if (clk_prepare_enable(hdmi
->clk_phy
))
881 DRM_ERROR("Failed to prepare/enable hdmi_rejec_pll clk\n");
883 hdmi
->enabled
= true;
885 /* Program hdmi serializer and start phy */
886 if (!hdmi
->phy_ops
->start(hdmi
)) {
887 DRM_ERROR("Unable to start hdmi phy\n");
891 /* Program hdmi active area */
892 hdmi_active_area(hdmi
);
894 /* Enable working interrupts */
895 hdmi_write(hdmi
, HDMI_WORKING_INT
, HDMI_INT_EN
);
897 /* Program hdmi config */
900 /* Program AVI infoframe */
901 if (hdmi_avi_infoframe_config(hdmi
))
902 DRM_ERROR("Unable to configure AVI infoframe\n");
904 if (hdmi
->audio
.enabled
) {
905 if (hdmi_audio_configure(hdmi
))
906 DRM_ERROR("Unable to configure audio\n");
908 hdmi_audio_infoframe_config(hdmi
);
911 /* Program VS infoframe */
912 if (hdmi_vendor_infoframe_config(hdmi
))
913 DRM_ERROR("Unable to configure VS infoframe\n");
919 static void sti_hdmi_set_mode(struct drm_bridge
*bridge
,
920 struct drm_display_mode
*mode
,
921 struct drm_display_mode
*adjusted_mode
)
923 struct sti_hdmi
*hdmi
= bridge
->driver_private
;
926 DRM_DEBUG_DRIVER("\n");
928 /* Copy the drm display mode in the connector local structure */
929 memcpy(&hdmi
->mode
, mode
, sizeof(struct drm_display_mode
));
931 /* Update clock framerate according to the selected mode */
932 ret
= clk_set_rate(hdmi
->clk_pix
, mode
->clock
* 1000);
934 DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n",
938 ret
= clk_set_rate(hdmi
->clk_phy
, mode
->clock
* 1000);
940 DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n",
946 static void sti_hdmi_bridge_nope(struct drm_bridge
*bridge
)
951 static const struct drm_bridge_funcs sti_hdmi_bridge_funcs
= {
952 .pre_enable
= sti_hdmi_pre_enable
,
953 .enable
= sti_hdmi_bridge_nope
,
954 .disable
= sti_hdmi_disable
,
955 .post_disable
= sti_hdmi_bridge_nope
,
956 .mode_set
= sti_hdmi_set_mode
,
959 static int sti_hdmi_connector_get_modes(struct drm_connector
*connector
)
961 struct sti_hdmi_connector
*hdmi_connector
962 = to_sti_hdmi_connector(connector
);
963 struct sti_hdmi
*hdmi
= hdmi_connector
->hdmi
;
967 DRM_DEBUG_DRIVER("\n");
969 edid
= drm_get_edid(connector
, hdmi
->ddc_adapt
);
973 hdmi
->hdmi_monitor
= drm_detect_hdmi_monitor(edid
);
974 DRM_DEBUG_KMS("%s : %dx%d cm\n",
975 (hdmi
->hdmi_monitor
? "hdmi monitor" : "dvi monitor"),
976 edid
->width_cm
, edid
->height_cm
);
977 cec_notifier_set_phys_addr_from_edid(hdmi
->notifier
, edid
);
979 count
= drm_add_edid_modes(connector
, edid
);
980 drm_connector_update_edid_property(connector
, edid
);
986 DRM_ERROR("Can't read HDMI EDID\n");
990 #define CLK_TOLERANCE_HZ 50
992 static int sti_hdmi_connector_mode_valid(struct drm_connector
*connector
,
993 struct drm_display_mode
*mode
)
995 int target
= mode
->clock
* 1000;
996 int target_min
= target
- CLK_TOLERANCE_HZ
;
997 int target_max
= target
+ CLK_TOLERANCE_HZ
;
999 struct sti_hdmi_connector
*hdmi_connector
1000 = to_sti_hdmi_connector(connector
);
1001 struct sti_hdmi
*hdmi
= hdmi_connector
->hdmi
;
1004 result
= clk_round_rate(hdmi
->clk_pix
, target
);
1006 DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
1009 if ((result
< target_min
) || (result
> target_max
)) {
1010 DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target
);
1018 struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs
= {
1019 .get_modes
= sti_hdmi_connector_get_modes
,
1020 .mode_valid
= sti_hdmi_connector_mode_valid
,
1023 /* get detection status of display device */
1024 static enum drm_connector_status
1025 sti_hdmi_connector_detect(struct drm_connector
*connector
, bool force
)
1027 struct sti_hdmi_connector
*hdmi_connector
1028 = to_sti_hdmi_connector(connector
);
1029 struct sti_hdmi
*hdmi
= hdmi_connector
->hdmi
;
1031 DRM_DEBUG_DRIVER("\n");
1034 DRM_DEBUG_DRIVER("hdmi cable connected\n");
1035 return connector_status_connected
;
1038 DRM_DEBUG_DRIVER("hdmi cable disconnected\n");
1039 cec_notifier_set_phys_addr(hdmi
->notifier
, CEC_PHYS_ADDR_INVALID
);
1040 return connector_status_disconnected
;
1043 static void sti_hdmi_connector_init_property(struct drm_device
*drm_dev
,
1044 struct drm_connector
*connector
)
1046 struct sti_hdmi_connector
*hdmi_connector
1047 = to_sti_hdmi_connector(connector
);
1048 struct sti_hdmi
*hdmi
= hdmi_connector
->hdmi
;
1049 struct drm_property
*prop
;
1051 /* colorspace property */
1052 hdmi
->colorspace
= DEFAULT_COLORSPACE_MODE
;
1053 prop
= drm_property_create_enum(drm_dev
, 0, "colorspace",
1054 colorspace_mode_names
,
1055 ARRAY_SIZE(colorspace_mode_names
));
1057 DRM_ERROR("fails to create colorspace property\n");
1060 hdmi_connector
->colorspace_property
= prop
;
1061 drm_object_attach_property(&connector
->base
, prop
, hdmi
->colorspace
);
1065 sti_hdmi_connector_set_property(struct drm_connector
*connector
,
1066 struct drm_connector_state
*state
,
1067 struct drm_property
*property
,
1070 struct sti_hdmi_connector
*hdmi_connector
1071 = to_sti_hdmi_connector(connector
);
1072 struct sti_hdmi
*hdmi
= hdmi_connector
->hdmi
;
1074 if (property
== hdmi_connector
->colorspace_property
) {
1075 hdmi
->colorspace
= val
;
1079 DRM_ERROR("failed to set hdmi connector property\n");
1084 sti_hdmi_connector_get_property(struct drm_connector
*connector
,
1085 const struct drm_connector_state
*state
,
1086 struct drm_property
*property
,
1089 struct sti_hdmi_connector
*hdmi_connector
1090 = to_sti_hdmi_connector(connector
);
1091 struct sti_hdmi
*hdmi
= hdmi_connector
->hdmi
;
1093 if (property
== hdmi_connector
->colorspace_property
) {
1094 *val
= hdmi
->colorspace
;
1098 DRM_ERROR("failed to get hdmi connector property\n");
1102 static int sti_hdmi_late_register(struct drm_connector
*connector
)
1104 struct sti_hdmi_connector
*hdmi_connector
1105 = to_sti_hdmi_connector(connector
);
1106 struct sti_hdmi
*hdmi
= hdmi_connector
->hdmi
;
1108 if (hdmi_debugfs_init(hdmi
, hdmi
->drm_dev
->primary
)) {
1109 DRM_ERROR("HDMI debugfs setup failed\n");
1116 static const struct drm_connector_funcs sti_hdmi_connector_funcs
= {
1117 .fill_modes
= drm_helper_probe_single_connector_modes
,
1118 .detect
= sti_hdmi_connector_detect
,
1119 .destroy
= drm_connector_cleanup
,
1120 .reset
= drm_atomic_helper_connector_reset
,
1121 .atomic_set_property
= sti_hdmi_connector_set_property
,
1122 .atomic_get_property
= sti_hdmi_connector_get_property
,
1123 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
1124 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
1125 .late_register
= sti_hdmi_late_register
,
1128 static struct drm_encoder
*sti_hdmi_find_encoder(struct drm_device
*dev
)
1130 struct drm_encoder
*encoder
;
1132 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
1133 if (encoder
->encoder_type
== DRM_MODE_ENCODER_TMDS
)
1140 static void hdmi_audio_shutdown(struct device
*dev
, void *data
)
1142 struct sti_hdmi
*hdmi
= dev_get_drvdata(dev
);
1145 DRM_DEBUG_DRIVER("\n");
1148 audio_cfg
= HDMI_AUD_CFG_SPDIF_DIV_2
| HDMI_AUD_CFG_DTS_INVALID
|
1149 HDMI_AUD_CFG_ONE_BIT_INVALID
;
1150 hdmi_write(hdmi
, audio_cfg
, HDMI_AUDIO_CFG
);
1152 hdmi
->audio
.enabled
= false;
1153 hdmi_audio_infoframe_config(hdmi
);
1156 static int hdmi_audio_hw_params(struct device
*dev
,
1158 struct hdmi_codec_daifmt
*daifmt
,
1159 struct hdmi_codec_params
*params
)
1161 struct sti_hdmi
*hdmi
= dev_get_drvdata(dev
);
1164 DRM_DEBUG_DRIVER("\n");
1166 if ((daifmt
->fmt
!= HDMI_I2S
) || daifmt
->bit_clk_inv
||
1167 daifmt
->frame_clk_inv
|| daifmt
->bit_clk_master
||
1168 daifmt
->frame_clk_master
) {
1169 dev_err(dev
, "%s: Bad flags %d %d %d %d\n", __func__
,
1170 daifmt
->bit_clk_inv
, daifmt
->frame_clk_inv
,
1171 daifmt
->bit_clk_master
,
1172 daifmt
->frame_clk_master
);
1176 hdmi
->audio
.sample_width
= params
->sample_width
;
1177 hdmi
->audio
.sample_rate
= params
->sample_rate
;
1178 hdmi
->audio
.cea
= params
->cea
;
1180 hdmi
->audio
.enabled
= true;
1182 ret
= hdmi_audio_configure(hdmi
);
1189 static int hdmi_audio_digital_mute(struct device
*dev
, void *data
, bool enable
)
1191 struct sti_hdmi
*hdmi
= dev_get_drvdata(dev
);
1193 DRM_DEBUG_DRIVER("%s\n", enable
? "enable" : "disable");
1196 hdmi_write(hdmi
, HDMI_SAMPLE_FLAT_ALL
, HDMI_SAMPLE_FLAT_MASK
);
1198 hdmi_write(hdmi
, HDMI_SAMPLE_FLAT_NO
, HDMI_SAMPLE_FLAT_MASK
);
1203 static int hdmi_audio_get_eld(struct device
*dev
, void *data
, uint8_t *buf
, size_t len
)
1205 struct sti_hdmi
*hdmi
= dev_get_drvdata(dev
);
1206 struct drm_connector
*connector
= hdmi
->drm_connector
;
1208 DRM_DEBUG_DRIVER("\n");
1209 memcpy(buf
, connector
->eld
, min(sizeof(connector
->eld
), len
));
1214 static const struct hdmi_codec_ops audio_codec_ops
= {
1215 .hw_params
= hdmi_audio_hw_params
,
1216 .audio_shutdown
= hdmi_audio_shutdown
,
1217 .digital_mute
= hdmi_audio_digital_mute
,
1218 .get_eld
= hdmi_audio_get_eld
,
1221 static int sti_hdmi_register_audio_driver(struct device
*dev
,
1222 struct sti_hdmi
*hdmi
)
1224 struct hdmi_codec_pdata codec_data
= {
1225 .ops
= &audio_codec_ops
,
1226 .max_i2s_channels
= 8,
1230 DRM_DEBUG_DRIVER("\n");
1232 hdmi
->audio
.enabled
= false;
1234 hdmi
->audio_pdev
= platform_device_register_data(
1235 dev
, HDMI_CODEC_DRV_NAME
, PLATFORM_DEVID_AUTO
,
1236 &codec_data
, sizeof(codec_data
));
1238 if (IS_ERR(hdmi
->audio_pdev
))
1239 return PTR_ERR(hdmi
->audio_pdev
);
1241 DRM_INFO("%s Driver bound %s\n", HDMI_CODEC_DRV_NAME
, dev_name(dev
));
1246 static int sti_hdmi_bind(struct device
*dev
, struct device
*master
, void *data
)
1248 struct sti_hdmi
*hdmi
= dev_get_drvdata(dev
);
1249 struct drm_device
*drm_dev
= data
;
1250 struct drm_encoder
*encoder
;
1251 struct sti_hdmi_connector
*connector
;
1252 struct drm_connector
*drm_connector
;
1253 struct drm_bridge
*bridge
;
1256 /* Set the drm device handle */
1257 hdmi
->drm_dev
= drm_dev
;
1259 encoder
= sti_hdmi_find_encoder(drm_dev
);
1263 connector
= devm_kzalloc(dev
, sizeof(*connector
), GFP_KERNEL
);
1267 connector
->hdmi
= hdmi
;
1269 bridge
= devm_kzalloc(dev
, sizeof(*bridge
), GFP_KERNEL
);
1273 bridge
->driver_private
= hdmi
;
1274 bridge
->funcs
= &sti_hdmi_bridge_funcs
;
1275 drm_bridge_attach(encoder
, bridge
, NULL
);
1277 connector
->encoder
= encoder
;
1279 drm_connector
= (struct drm_connector
*)connector
;
1281 drm_connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
1283 drm_connector_init(drm_dev
, drm_connector
,
1284 &sti_hdmi_connector_funcs
, DRM_MODE_CONNECTOR_HDMIA
);
1285 drm_connector_helper_add(drm_connector
,
1286 &sti_hdmi_connector_helper_funcs
);
1288 /* initialise property */
1289 sti_hdmi_connector_init_property(drm_dev
, drm_connector
);
1291 hdmi
->drm_connector
= drm_connector
;
1293 err
= drm_mode_connector_attach_encoder(drm_connector
, encoder
);
1295 DRM_ERROR("Failed to attach a connector to a encoder\n");
1299 err
= sti_hdmi_register_audio_driver(dev
, hdmi
);
1301 DRM_ERROR("Failed to attach an audio codec\n");
1305 /* Initialize audio infoframe */
1306 err
= hdmi_audio_infoframe_init(&hdmi
->audio
.cea
);
1308 DRM_ERROR("Failed to init audio infoframe\n");
1312 /* Enable default interrupts */
1313 hdmi_write(hdmi
, HDMI_DEFAULT_INT
, HDMI_INT_EN
);
1318 drm_bridge_remove(bridge
);
1319 hdmi
->drm_connector
= NULL
;
1323 static void sti_hdmi_unbind(struct device
*dev
,
1324 struct device
*master
, void *data
)
1328 static const struct component_ops sti_hdmi_ops
= {
1329 .bind
= sti_hdmi_bind
,
1330 .unbind
= sti_hdmi_unbind
,
1333 static const struct of_device_id hdmi_of_match
[] = {
1335 .compatible
= "st,stih407-hdmi",
1336 .data
= &tx3g4c28phy_ops
,
1341 MODULE_DEVICE_TABLE(of
, hdmi_of_match
);
1343 static int sti_hdmi_probe(struct platform_device
*pdev
)
1345 struct device
*dev
= &pdev
->dev
;
1346 struct sti_hdmi
*hdmi
;
1347 struct device_node
*np
= dev
->of_node
;
1348 struct resource
*res
;
1349 struct device_node
*ddc
;
1352 DRM_INFO("%s\n", __func__
);
1354 hdmi
= devm_kzalloc(dev
, sizeof(*hdmi
), GFP_KERNEL
);
1358 ddc
= of_parse_phandle(pdev
->dev
.of_node
, "ddc", 0);
1360 hdmi
->ddc_adapt
= of_get_i2c_adapter_by_node(ddc
);
1362 if (!hdmi
->ddc_adapt
)
1363 return -EPROBE_DEFER
;
1366 hdmi
->dev
= pdev
->dev
;
1369 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "hdmi-reg");
1371 DRM_ERROR("Invalid hdmi resource\n");
1373 goto release_adapter
;
1375 hdmi
->regs
= devm_ioremap_nocache(dev
, res
->start
, resource_size(res
));
1378 goto release_adapter
;
1381 hdmi
->phy_ops
= (struct hdmi_phy_ops
*)
1382 of_match_node(hdmi_of_match
, np
)->data
;
1384 /* Get clock resources */
1385 hdmi
->clk_pix
= devm_clk_get(dev
, "pix");
1386 if (IS_ERR(hdmi
->clk_pix
)) {
1387 DRM_ERROR("Cannot get hdmi_pix clock\n");
1388 ret
= PTR_ERR(hdmi
->clk_pix
);
1389 goto release_adapter
;
1392 hdmi
->clk_tmds
= devm_clk_get(dev
, "tmds");
1393 if (IS_ERR(hdmi
->clk_tmds
)) {
1394 DRM_ERROR("Cannot get hdmi_tmds clock\n");
1395 ret
= PTR_ERR(hdmi
->clk_tmds
);
1396 goto release_adapter
;
1399 hdmi
->clk_phy
= devm_clk_get(dev
, "phy");
1400 if (IS_ERR(hdmi
->clk_phy
)) {
1401 DRM_ERROR("Cannot get hdmi_phy clock\n");
1402 ret
= PTR_ERR(hdmi
->clk_phy
);
1403 goto release_adapter
;
1406 hdmi
->clk_audio
= devm_clk_get(dev
, "audio");
1407 if (IS_ERR(hdmi
->clk_audio
)) {
1408 DRM_ERROR("Cannot get hdmi_audio clock\n");
1409 ret
= PTR_ERR(hdmi
->clk_audio
);
1410 goto release_adapter
;
1413 hdmi
->hpd
= readl(hdmi
->regs
+ HDMI_STA
) & HDMI_STA_HOT_PLUG
;
1415 init_waitqueue_head(&hdmi
->wait_event
);
1417 hdmi
->irq
= platform_get_irq_byname(pdev
, "irq");
1418 if (hdmi
->irq
< 0) {
1419 DRM_ERROR("Cannot get HDMI irq\n");
1421 goto release_adapter
;
1424 ret
= devm_request_threaded_irq(dev
, hdmi
->irq
, hdmi_irq
,
1425 hdmi_irq_thread
, IRQF_ONESHOT
, dev_name(dev
), hdmi
);
1427 DRM_ERROR("Failed to register HDMI interrupt\n");
1428 goto release_adapter
;
1431 hdmi
->notifier
= cec_notifier_get(&pdev
->dev
);
1432 if (!hdmi
->notifier
)
1433 goto release_adapter
;
1435 hdmi
->reset
= devm_reset_control_get(dev
, "hdmi");
1436 /* Take hdmi out of reset */
1437 if (!IS_ERR(hdmi
->reset
))
1438 reset_control_deassert(hdmi
->reset
);
1440 platform_set_drvdata(pdev
, hdmi
);
1442 return component_add(&pdev
->dev
, &sti_hdmi_ops
);
1445 i2c_put_adapter(hdmi
->ddc_adapt
);
1450 static int sti_hdmi_remove(struct platform_device
*pdev
)
1452 struct sti_hdmi
*hdmi
= dev_get_drvdata(&pdev
->dev
);
1454 cec_notifier_set_phys_addr(hdmi
->notifier
, CEC_PHYS_ADDR_INVALID
);
1456 i2c_put_adapter(hdmi
->ddc_adapt
);
1457 if (hdmi
->audio_pdev
)
1458 platform_device_unregister(hdmi
->audio_pdev
);
1459 component_del(&pdev
->dev
, &sti_hdmi_ops
);
1461 cec_notifier_put(hdmi
->notifier
);
1465 struct platform_driver sti_hdmi_driver
= {
1468 .owner
= THIS_MODULE
,
1469 .of_match_table
= hdmi_of_match
,
1471 .probe
= sti_hdmi_probe
,
1472 .remove
= sti_hdmi_remove
,
1475 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
1476 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
1477 MODULE_LICENSE("GPL");