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[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / stm / ltdc.c
1 /*
2 * Copyright (C) STMicroelectronics SA 2017
3 *
4 * Authors: Philippe Cornu <philippe.cornu@st.com>
5 * Yannick Fertre <yannick.fertre@st.com>
6 * Fabien Dessenne <fabien.dessenne@st.com>
7 * Mickael Reulier <mickael.reulier@st.com>
8 *
9 * License terms: GNU General Public License (GPL), version 2
10 */
11
12 #include <linux/clk.h>
13 #include <linux/component.h>
14 #include <linux/of_address.h>
15 #include <linux/of_graph.h>
16 #include <linux/reset.h>
17
18 #include <drm/drm_atomic.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_crtc_helper.h>
21 #include <drm/drm_fb_cma_helper.h>
22 #include <drm/drm_gem_cma_helper.h>
23 #include <drm/drm_of.h>
24 #include <drm/drm_panel.h>
25 #include <drm/drm_plane_helper.h>
26
27 #include <video/videomode.h>
28
29 #include "ltdc.h"
30
31 #define NB_CRTC 1
32 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
33
34 #define MAX_IRQ 4
35
36 #define HWVER_10200 0x010200
37 #define HWVER_10300 0x010300
38 #define HWVER_20101 0x020101
39
40 /*
41 * The address of some registers depends on the HW version: such registers have
42 * an extra offset specified with reg_ofs.
43 */
44 #define REG_OFS_NONE 0
45 #define REG_OFS_4 4 /* Insertion of "Layer Configuration 2" reg */
46 #define REG_OFS (ldev->caps.reg_ofs)
47 #define LAY_OFS 0x80 /* Register Offset between 2 layers */
48
49 /* Global register offsets */
50 #define LTDC_IDR 0x0000 /* IDentification */
51 #define LTDC_LCR 0x0004 /* Layer Count */
52 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */
53 #define LTDC_BPCR 0x000C /* Back Porch Configuration */
54 #define LTDC_AWCR 0x0010 /* Active Width Configuration */
55 #define LTDC_TWCR 0x0014 /* Total Width Configuration */
56 #define LTDC_GCR 0x0018 /* Global Control */
57 #define LTDC_GC1R 0x001C /* Global Configuration 1 */
58 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */
59 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */
60 #define LTDC_GACR 0x0028 /* GAmma Correction */
61 #define LTDC_BCCR 0x002C /* Background Color Configuration */
62 #define LTDC_IER 0x0034 /* Interrupt Enable */
63 #define LTDC_ISR 0x0038 /* Interrupt Status */
64 #define LTDC_ICR 0x003C /* Interrupt Clear */
65 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Configuration */
66 #define LTDC_CPSR 0x0044 /* Current Position Status */
67 #define LTDC_CDSR 0x0048 /* Current Display Status */
68
69 /* Layer register offsets */
70 #define LTDC_L1LC1R (0x0080) /* L1 Layer Configuration 1 */
71 #define LTDC_L1LC2R (0x0084) /* L1 Layer Configuration 2 */
72 #define LTDC_L1CR (0x0084 + REG_OFS) /* L1 Control */
73 #define LTDC_L1WHPCR (0x0088 + REG_OFS) /* L1 Window Hor Position Config */
74 #define LTDC_L1WVPCR (0x008C + REG_OFS) /* L1 Window Vert Position Config */
75 #define LTDC_L1CKCR (0x0090 + REG_OFS) /* L1 Color Keying Configuration */
76 #define LTDC_L1PFCR (0x0094 + REG_OFS) /* L1 Pixel Format Configuration */
77 #define LTDC_L1CACR (0x0098 + REG_OFS) /* L1 Constant Alpha Config */
78 #define LTDC_L1DCCR (0x009C + REG_OFS) /* L1 Default Color Configuration */
79 #define LTDC_L1BFCR (0x00A0 + REG_OFS) /* L1 Blend Factors Configuration */
80 #define LTDC_L1FBBCR (0x00A4 + REG_OFS) /* L1 FrameBuffer Bus Control */
81 #define LTDC_L1AFBCR (0x00A8 + REG_OFS) /* L1 AuxFB Control */
82 #define LTDC_L1CFBAR (0x00AC + REG_OFS) /* L1 Color FrameBuffer Address */
83 #define LTDC_L1CFBLR (0x00B0 + REG_OFS) /* L1 Color FrameBuffer Length */
84 #define LTDC_L1CFBLNR (0x00B4 + REG_OFS) /* L1 Color FrameBuffer Line Nb */
85 #define LTDC_L1AFBAR (0x00B8 + REG_OFS) /* L1 AuxFB Address */
86 #define LTDC_L1AFBLR (0x00BC + REG_OFS) /* L1 AuxFB Length */
87 #define LTDC_L1AFBLNR (0x00C0 + REG_OFS) /* L1 AuxFB Line Number */
88 #define LTDC_L1CLUTWR (0x00C4 + REG_OFS) /* L1 CLUT Write */
89 #define LTDC_L1YS1R (0x00E0 + REG_OFS) /* L1 YCbCr Scale 1 */
90 #define LTDC_L1YS2R (0x00E4 + REG_OFS) /* L1 YCbCr Scale 2 */
91
92 /* Bit definitions */
93 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
94 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
95
96 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
97 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
98
99 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
100 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
101
102 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
103 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
104
105 #define GCR_LTDCEN BIT(0) /* LTDC ENable */
106 #define GCR_DEN BIT(16) /* Dither ENable */
107 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity */
108 #define GCR_DEPOL BIT(29) /* Data Enable POLarity */
109 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity */
110 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity */
111
112 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
113 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
114 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
115 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */
116 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
117 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
118 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
119 #define GC1R_BCP BIT(22) /* Background Colour Programmable */
120 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */
121 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
122 #define GC1R_TP BIT(25) /* Timing Programmable */
123 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
124 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
125 #define GC1R_DWP BIT(28) /* Dither Width Programmable */
126 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */
127 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
128
129 #define GC2R_EDCA BIT(0) /* External Display Control Ability */
130 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
131 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
132 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
133 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
134 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
135
136 #define SRCR_IMR BIT(0) /* IMmediate Reload */
137 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
138
139 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */
140 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */
141 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */
142 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */
143 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */
144
145 #define IER_LIE BIT(0) /* Line Interrupt Enable */
146 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */
147 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */
148 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */
149
150 #define ISR_LIF BIT(0) /* Line Interrupt Flag */
151 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */
152 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */
153 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */
154
155 #define LXCR_LEN BIT(0) /* Layer ENable */
156 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */
157 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
158
159 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
160 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
161
162 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
163 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
164
165 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
166
167 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
168
169 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
170 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
171
172 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
173 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
174
175 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
176
177 #define HSPOL_AL 0 /* Horizontal Sync POLarity Active Low */
178 #define VSPOL_AL 0 /* Vertical Sync POLarity Active Low */
179 #define DEPOL_AL 0 /* Data Enable POLarity Active Low */
180 #define PCPOL_IPC 0 /* Input Pixel Clock */
181 #define HSPOL_AH GCR_HSPOL /* Horizontal Sync POLarity Active High */
182 #define VSPOL_AH GCR_VSPOL /* Vertical Sync POLarity Active High */
183 #define DEPOL_AH GCR_DEPOL /* Data Enable POLarity Active High */
184 #define PCPOL_IIPC GCR_PCPOL /* Inverted Input Pixel Clock */
185 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */
186 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
187 #define BF1_CA 0x400 /* Constant Alpha */
188 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
189 #define BF2_1CA 0x005 /* 1 - Constant Alpha */
190
191 #define NB_PF 8 /* Max nb of HW pixel format */
192
193 enum ltdc_pix_fmt {
194 PF_NONE,
195 /* RGB formats */
196 PF_ARGB8888, /* ARGB [32 bits] */
197 PF_RGBA8888, /* RGBA [32 bits] */
198 PF_RGB888, /* RGB [24 bits] */
199 PF_RGB565, /* RGB [16 bits] */
200 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
201 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
202 /* Indexed formats */
203 PF_L8, /* Indexed 8 bits [8 bits] */
204 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */
205 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */
206 };
207
208 /* The index gives the encoding of the pixel format for an HW version */
209 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
210 PF_ARGB8888, /* 0x00 */
211 PF_RGB888, /* 0x01 */
212 PF_RGB565, /* 0x02 */
213 PF_ARGB1555, /* 0x03 */
214 PF_ARGB4444, /* 0x04 */
215 PF_L8, /* 0x05 */
216 PF_AL44, /* 0x06 */
217 PF_AL88 /* 0x07 */
218 };
219
220 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
221 PF_ARGB8888, /* 0x00 */
222 PF_RGB888, /* 0x01 */
223 PF_RGB565, /* 0x02 */
224 PF_RGBA8888, /* 0x03 */
225 PF_AL44, /* 0x04 */
226 PF_L8, /* 0x05 */
227 PF_ARGB1555, /* 0x06 */
228 PF_ARGB4444 /* 0x07 */
229 };
230
231 static inline u32 reg_read(void __iomem *base, u32 reg)
232 {
233 return readl_relaxed(base + reg);
234 }
235
236 static inline void reg_write(void __iomem *base, u32 reg, u32 val)
237 {
238 writel_relaxed(val, base + reg);
239 }
240
241 static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
242 {
243 reg_write(base, reg, reg_read(base, reg) | mask);
244 }
245
246 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
247 {
248 reg_write(base, reg, reg_read(base, reg) & ~mask);
249 }
250
251 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask,
252 u32 val)
253 {
254 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val);
255 }
256
257 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc)
258 {
259 return (struct ltdc_device *)crtc->dev->dev_private;
260 }
261
262 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane)
263 {
264 return (struct ltdc_device *)plane->dev->dev_private;
265 }
266
267 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc)
268 {
269 return (struct ltdc_device *)enc->dev->dev_private;
270 }
271
272 static inline struct ltdc_device *connector_to_ltdc(struct drm_connector *con)
273 {
274 return (struct ltdc_device *)con->dev->dev_private;
275 }
276
277 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
278 {
279 enum ltdc_pix_fmt pf;
280
281 switch (drm_fmt) {
282 case DRM_FORMAT_ARGB8888:
283 case DRM_FORMAT_XRGB8888:
284 pf = PF_ARGB8888;
285 break;
286 case DRM_FORMAT_RGBA8888:
287 case DRM_FORMAT_RGBX8888:
288 pf = PF_RGBA8888;
289 break;
290 case DRM_FORMAT_RGB888:
291 pf = PF_RGB888;
292 break;
293 case DRM_FORMAT_RGB565:
294 pf = PF_RGB565;
295 break;
296 case DRM_FORMAT_ARGB1555:
297 case DRM_FORMAT_XRGB1555:
298 pf = PF_ARGB1555;
299 break;
300 case DRM_FORMAT_ARGB4444:
301 case DRM_FORMAT_XRGB4444:
302 pf = PF_ARGB4444;
303 break;
304 case DRM_FORMAT_C8:
305 pf = PF_L8;
306 break;
307 default:
308 pf = PF_NONE;
309 break;
310 /* Note: There are no DRM_FORMAT for AL44 and AL88 */
311 }
312
313 return pf;
314 }
315
316 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf)
317 {
318 switch (pf) {
319 case PF_ARGB8888:
320 return DRM_FORMAT_ARGB8888;
321 case PF_RGBA8888:
322 return DRM_FORMAT_RGBA8888;
323 case PF_RGB888:
324 return DRM_FORMAT_RGB888;
325 case PF_RGB565:
326 return DRM_FORMAT_RGB565;
327 case PF_ARGB1555:
328 return DRM_FORMAT_ARGB1555;
329 case PF_ARGB4444:
330 return DRM_FORMAT_ARGB4444;
331 case PF_L8:
332 return DRM_FORMAT_C8;
333 case PF_AL44: /* No DRM support */
334 case PF_AL88: /* No DRM support */
335 case PF_NONE:
336 default:
337 return 0;
338 }
339 }
340
341 static irqreturn_t ltdc_irq_thread(int irq, void *arg)
342 {
343 struct drm_device *ddev = arg;
344 struct ltdc_device *ldev = ddev->dev_private;
345 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0);
346
347 /* Line IRQ : trigger the vblank event */
348 if (ldev->irq_status & ISR_LIF)
349 drm_crtc_handle_vblank(crtc);
350
351 /* Save FIFO Underrun & Transfer Error status */
352 mutex_lock(&ldev->err_lock);
353 if (ldev->irq_status & ISR_FUIF)
354 ldev->error_status |= ISR_FUIF;
355 if (ldev->irq_status & ISR_TERRIF)
356 ldev->error_status |= ISR_TERRIF;
357 mutex_unlock(&ldev->err_lock);
358
359 return IRQ_HANDLED;
360 }
361
362 static irqreturn_t ltdc_irq(int irq, void *arg)
363 {
364 struct drm_device *ddev = arg;
365 struct ltdc_device *ldev = ddev->dev_private;
366
367 /* Read & Clear the interrupt status */
368 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR);
369 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status);
370
371 return IRQ_WAKE_THREAD;
372 }
373
374 /*
375 * DRM_CRTC
376 */
377
378 static void ltdc_crtc_load_lut(struct drm_crtc *crtc)
379 {
380 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
381 unsigned int i, lay;
382
383 for (lay = 0; lay < ldev->caps.nb_layers; lay++)
384 for (i = 0; i < 256; i++)
385 reg_write(ldev->regs, LTDC_L1CLUTWR + lay * LAY_OFS,
386 ldev->clut[i]);
387 }
388
389 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
390 struct drm_crtc_state *old_state)
391 {
392 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
393
394 DRM_DEBUG_DRIVER("\n");
395
396 /* Sets the background color value */
397 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK);
398
399 /* Enable IRQ */
400 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
401
402 /* Immediately commit the planes */
403 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
404
405 /* Enable LTDC */
406 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN);
407
408 drm_crtc_vblank_on(crtc);
409 }
410
411 static void ltdc_crtc_disable(struct drm_crtc *crtc)
412 {
413 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
414
415 DRM_DEBUG_DRIVER("\n");
416
417 drm_crtc_vblank_off(crtc);
418
419 /* disable LTDC */
420 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN);
421
422 /* disable IRQ */
423 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
424
425 /* immediately commit disable of layers before switching off LTDC */
426 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
427 }
428
429 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
430 {
431 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
432 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
433 struct videomode vm;
434 int rate = mode->clock * 1000;
435 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
436 u32 total_width, total_height;
437 u32 val;
438
439 drm_display_mode_to_videomode(mode, &vm);
440
441 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name);
442 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive);
443 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
444 vm.hfront_porch, vm.hback_porch, vm.hsync_len,
445 vm.vfront_porch, vm.vback_porch, vm.vsync_len);
446
447 /* Convert video timings to ltdc timings */
448 hsync = vm.hsync_len - 1;
449 vsync = vm.vsync_len - 1;
450 accum_hbp = hsync + vm.hback_porch;
451 accum_vbp = vsync + vm.vback_porch;
452 accum_act_w = accum_hbp + vm.hactive;
453 accum_act_h = accum_vbp + vm.vactive;
454 total_width = accum_act_w + vm.hfront_porch;
455 total_height = accum_act_h + vm.vfront_porch;
456
457 clk_disable(ldev->pixel_clk);
458
459 if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
460 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
461 return;
462 }
463
464 clk_enable(ldev->pixel_clk);
465
466 /* Configures the HS, VS, DE and PC polarities. */
467 val = HSPOL_AL | VSPOL_AL | DEPOL_AL | PCPOL_IPC;
468
469 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
470 val |= HSPOL_AH;
471
472 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
473 val |= VSPOL_AH;
474
475 if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
476 val |= DEPOL_AH;
477
478 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
479 val |= PCPOL_IIPC;
480
481 reg_update_bits(ldev->regs, LTDC_GCR,
482 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
483
484 /* Set Synchronization size */
485 val = (hsync << 16) | vsync;
486 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
487
488 /* Set Accumulated Back porch */
489 val = (accum_hbp << 16) | accum_vbp;
490 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
491
492 /* Set Accumulated Active Width */
493 val = (accum_act_w << 16) | accum_act_h;
494 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
495
496 /* Set total width & height */
497 val = (total_width << 16) | total_height;
498 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
499
500 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1));
501 }
502
503 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
504 struct drm_crtc_state *old_crtc_state)
505 {
506 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
507 struct drm_pending_vblank_event *event = crtc->state->event;
508
509 DRM_DEBUG_ATOMIC("\n");
510
511 /* Commit shadow registers = update planes at next vblank */
512 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
513
514 if (event) {
515 crtc->state->event = NULL;
516
517 spin_lock_irq(&crtc->dev->event_lock);
518 if (drm_crtc_vblank_get(crtc) == 0)
519 drm_crtc_arm_vblank_event(crtc, event);
520 else
521 drm_crtc_send_vblank_event(crtc, event);
522 spin_unlock_irq(&crtc->dev->event_lock);
523 }
524 }
525
526 static struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
527 .load_lut = ltdc_crtc_load_lut,
528 .disable = ltdc_crtc_disable,
529 .mode_set_nofb = ltdc_crtc_mode_set_nofb,
530 .atomic_flush = ltdc_crtc_atomic_flush,
531 .atomic_enable = ltdc_crtc_atomic_enable,
532 };
533
534 int ltdc_crtc_enable_vblank(struct drm_device *ddev, unsigned int pipe)
535 {
536 struct ltdc_device *ldev = ddev->dev_private;
537
538 DRM_DEBUG_DRIVER("\n");
539 reg_set(ldev->regs, LTDC_IER, IER_LIE);
540
541 return 0;
542 }
543
544 void ltdc_crtc_disable_vblank(struct drm_device *ddev, unsigned int pipe)
545 {
546 struct ltdc_device *ldev = ddev->dev_private;
547
548 DRM_DEBUG_DRIVER("\n");
549 reg_clear(ldev->regs, LTDC_IER, IER_LIE);
550 }
551
552 static struct drm_crtc_funcs ltdc_crtc_funcs = {
553 .destroy = drm_crtc_cleanup,
554 .set_config = drm_atomic_helper_set_config,
555 .page_flip = drm_atomic_helper_page_flip,
556 .reset = drm_atomic_helper_crtc_reset,
557 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
558 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
559 };
560
561 /*
562 * DRM_PLANE
563 */
564
565 static int ltdc_plane_atomic_check(struct drm_plane *plane,
566 struct drm_plane_state *state)
567 {
568 struct drm_framebuffer *fb = state->fb;
569 u32 src_x, src_y, src_w, src_h;
570
571 DRM_DEBUG_DRIVER("\n");
572
573 if (!fb)
574 return 0;
575
576 /* convert src_ from 16:16 format */
577 src_x = state->src_x >> 16;
578 src_y = state->src_y >> 16;
579 src_w = state->src_w >> 16;
580 src_h = state->src_h >> 16;
581
582 /* Reject scaling */
583 if ((src_w != state->crtc_w) || (src_h != state->crtc_h)) {
584 DRM_ERROR("Scaling is not supported");
585 return -EINVAL;
586 }
587
588 return 0;
589 }
590
591 static void ltdc_plane_atomic_update(struct drm_plane *plane,
592 struct drm_plane_state *oldstate)
593 {
594 struct ltdc_device *ldev = plane_to_ltdc(plane);
595 struct drm_plane_state *state = plane->state;
596 struct drm_framebuffer *fb = state->fb;
597 u32 lofs = plane->index * LAY_OFS;
598 u32 x0 = state->crtc_x;
599 u32 x1 = state->crtc_x + state->crtc_w - 1;
600 u32 y0 = state->crtc_y;
601 u32 y1 = state->crtc_y + state->crtc_h - 1;
602 u32 src_x, src_y, src_w, src_h;
603 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr;
604 enum ltdc_pix_fmt pf;
605
606 if (!state->crtc || !fb) {
607 DRM_DEBUG_DRIVER("fb or crtc NULL");
608 return;
609 }
610
611 /* convert src_ from 16:16 format */
612 src_x = state->src_x >> 16;
613 src_y = state->src_y >> 16;
614 src_w = state->src_w >> 16;
615 src_h = state->src_h >> 16;
616
617 DRM_DEBUG_DRIVER(
618 "plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
619 plane->base.id, fb->base.id,
620 src_w, src_h, src_x, src_y,
621 state->crtc_w, state->crtc_h, state->crtc_x, state->crtc_y);
622
623 bpcr = reg_read(ldev->regs, LTDC_BPCR);
624 ahbp = (bpcr & BPCR_AHBP) >> 16;
625 avbp = bpcr & BPCR_AVBP;
626
627 /* Configures the horizontal start and stop position */
628 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
629 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs,
630 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
631
632 /* Configures the vertical start and stop position */
633 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
634 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs,
635 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
636
637 /* Specifies the pixel format */
638 pf = to_ltdc_pixelformat(fb->format->format);
639 for (val = 0; val < NB_PF; val++)
640 if (ldev->caps.pix_fmt_hw[val] == pf)
641 break;
642
643 if (val == NB_PF) {
644 DRM_ERROR("Pixel format %.4s not supported\n",
645 (char *)&fb->format->format);
646 val = 0; /* set by default ARGB 32 bits */
647 }
648 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
649
650 /* Configures the color frame buffer pitch in bytes & line length */
651 pitch_in_bytes = fb->pitches[0];
652 line_length = drm_format_plane_cpp(fb->format->format, 0) *
653 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
654 val = ((pitch_in_bytes << 16) | line_length);
655 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs,
656 LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
657
658 /* Specifies the constant alpha value */
659 val = CONSTA_MAX;
660 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs,
661 LXCACR_CONSTA, val);
662
663 /* Specifies the blending factors */
664 val = BF1_PAXCA | BF2_1PAXCA;
665 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs,
666 LXBFCR_BF2 | LXBFCR_BF1, val);
667
668 /* Configures the frame buffer line number */
669 val = y1 - y0 + 1;
670 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs,
671 LXCFBLNR_CFBLN, val);
672
673 /* Sets the FB address */
674 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0);
675
676 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
677 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr);
678
679 /* Enable layer and CLUT if needed */
680 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
681 val |= LXCR_LEN;
682 reg_update_bits(ldev->regs, LTDC_L1CR + lofs,
683 LXCR_LEN | LXCR_CLUTEN, val);
684
685 mutex_lock(&ldev->err_lock);
686 if (ldev->error_status & ISR_FUIF) {
687 DRM_DEBUG_DRIVER("Fifo underrun\n");
688 ldev->error_status &= ~ISR_FUIF;
689 }
690 if (ldev->error_status & ISR_TERRIF) {
691 DRM_DEBUG_DRIVER("Transfer error\n");
692 ldev->error_status &= ~ISR_TERRIF;
693 }
694 mutex_unlock(&ldev->err_lock);
695 }
696
697 static void ltdc_plane_atomic_disable(struct drm_plane *plane,
698 struct drm_plane_state *oldstate)
699 {
700 struct ltdc_device *ldev = plane_to_ltdc(plane);
701 u32 lofs = plane->index * LAY_OFS;
702
703 /* disable layer */
704 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN);
705
706 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
707 oldstate->crtc->base.id, plane->base.id);
708 }
709
710 static struct drm_plane_funcs ltdc_plane_funcs = {
711 .update_plane = drm_atomic_helper_update_plane,
712 .disable_plane = drm_atomic_helper_disable_plane,
713 .destroy = drm_plane_cleanup,
714 .set_property = drm_atomic_helper_plane_set_property,
715 .reset = drm_atomic_helper_plane_reset,
716 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
717 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
718 };
719
720 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
721 .atomic_check = ltdc_plane_atomic_check,
722 .atomic_update = ltdc_plane_atomic_update,
723 .atomic_disable = ltdc_plane_atomic_disable,
724 };
725
726 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
727 enum drm_plane_type type)
728 {
729 unsigned long possible_crtcs = CRTC_MASK;
730 struct ltdc_device *ldev = ddev->dev_private;
731 struct device *dev = ddev->dev;
732 struct drm_plane *plane;
733 unsigned int i, nb_fmt = 0;
734 u32 formats[NB_PF];
735 u32 drm_fmt;
736 int ret;
737
738 /* Get supported pixel formats */
739 for (i = 0; i < NB_PF; i++) {
740 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]);
741 if (!drm_fmt)
742 continue;
743 formats[nb_fmt++] = drm_fmt;
744 }
745
746 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
747 if (!plane)
748 return 0;
749
750 ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
751 &ltdc_plane_funcs, formats, nb_fmt,
752 type, NULL);
753 if (ret < 0)
754 return 0;
755
756 drm_plane_helper_add(plane, &ltdc_plane_helper_funcs);
757
758 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
759
760 return plane;
761 }
762
763 static void ltdc_plane_destroy_all(struct drm_device *ddev)
764 {
765 struct drm_plane *plane, *plane_temp;
766
767 list_for_each_entry_safe(plane, plane_temp,
768 &ddev->mode_config.plane_list, head)
769 drm_plane_cleanup(plane);
770 }
771
772 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
773 {
774 struct ltdc_device *ldev = ddev->dev_private;
775 struct drm_plane *primary, *overlay;
776 unsigned int i;
777 int res;
778
779 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY);
780 if (!primary) {
781 DRM_ERROR("Can not create primary plane\n");
782 return -EINVAL;
783 }
784
785 res = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
786 &ltdc_crtc_funcs, NULL);
787 if (res) {
788 DRM_ERROR("Can not initialize CRTC\n");
789 goto cleanup;
790 }
791
792 drm_crtc_helper_add(crtc, &ltdc_crtc_helper_funcs);
793
794 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
795
796 /* Add planes. Note : the first layer is used by primary plane */
797 for (i = 1; i < ldev->caps.nb_layers; i++) {
798 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY);
799 if (!overlay) {
800 res = -ENOMEM;
801 DRM_ERROR("Can not create overlay plane %d\n", i);
802 goto cleanup;
803 }
804 }
805
806 return 0;
807
808 cleanup:
809 ltdc_plane_destroy_all(ddev);
810 return res;
811 }
812
813 /*
814 * DRM_ENCODER
815 */
816
817 static void ltdc_rgb_encoder_enable(struct drm_encoder *encoder)
818 {
819 struct ltdc_device *ldev = encoder_to_ltdc(encoder);
820
821 DRM_DEBUG_DRIVER("\n");
822
823 drm_panel_prepare(ldev->panel);
824 drm_panel_enable(ldev->panel);
825 }
826
827 static void ltdc_rgb_encoder_disable(struct drm_encoder *encoder)
828 {
829 struct ltdc_device *ldev = encoder_to_ltdc(encoder);
830
831 DRM_DEBUG_DRIVER("\n");
832
833 drm_panel_disable(ldev->panel);
834 drm_panel_unprepare(ldev->panel);
835 }
836
837 static const struct drm_encoder_helper_funcs ltdc_rgb_encoder_helper_funcs = {
838 .enable = ltdc_rgb_encoder_enable,
839 .disable = ltdc_rgb_encoder_disable,
840 };
841
842 static const struct drm_encoder_funcs ltdc_rgb_encoder_funcs = {
843 .destroy = drm_encoder_cleanup,
844 };
845
846 static struct drm_encoder *ltdc_rgb_encoder_create(struct drm_device *ddev)
847 {
848 struct drm_encoder *encoder;
849
850 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
851 if (!encoder)
852 return NULL;
853
854 encoder->possible_crtcs = CRTC_MASK;
855 encoder->possible_clones = 0; /* No cloning support */
856
857 drm_encoder_init(ddev, encoder, &ltdc_rgb_encoder_funcs,
858 DRM_MODE_ENCODER_DPI, NULL);
859
860 drm_encoder_helper_add(encoder, &ltdc_rgb_encoder_helper_funcs);
861
862 DRM_DEBUG_DRIVER("RGB encoder:%d created\n", encoder->base.id);
863
864 return encoder;
865 }
866
867 /*
868 * DRM_CONNECTOR
869 */
870
871 static int ltdc_rgb_connector_get_modes(struct drm_connector *connector)
872 {
873 struct drm_device *ddev = connector->dev;
874 struct ltdc_device *ldev = ddev->dev_private;
875 int ret = 0;
876
877 DRM_DEBUG_DRIVER("\n");
878
879 if (ldev->panel)
880 ret = drm_panel_get_modes(ldev->panel);
881
882 return ret < 0 ? 0 : ret;
883 }
884
885 static struct drm_connector_helper_funcs ltdc_rgb_connector_helper_funcs = {
886 .get_modes = ltdc_rgb_connector_get_modes,
887 };
888
889 static enum drm_connector_status
890 ltdc_rgb_connector_detect(struct drm_connector *connector, bool force)
891 {
892 struct ltdc_device *ldev = connector_to_ltdc(connector);
893
894 return ldev->panel ? connector_status_connected :
895 connector_status_disconnected;
896 }
897
898 static void ltdc_rgb_connector_destroy(struct drm_connector *connector)
899 {
900 DRM_DEBUG_DRIVER("\n");
901
902 drm_connector_unregister(connector);
903 drm_connector_cleanup(connector);
904 }
905
906 static const struct drm_connector_funcs ltdc_rgb_connector_funcs = {
907 .dpms = drm_atomic_helper_connector_dpms,
908 .fill_modes = drm_helper_probe_single_connector_modes,
909 .detect = ltdc_rgb_connector_detect,
910 .destroy = ltdc_rgb_connector_destroy,
911 .reset = drm_atomic_helper_connector_reset,
912 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
913 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
914 };
915
916 struct drm_connector *ltdc_rgb_connector_create(struct drm_device *ddev)
917 {
918 struct drm_connector *connector;
919 int err;
920
921 connector = devm_kzalloc(ddev->dev, sizeof(*connector), GFP_KERNEL);
922 if (!connector) {
923 DRM_ERROR("Failed to allocate connector\n");
924 return NULL;
925 }
926
927 connector->polled = DRM_CONNECTOR_POLL_HPD;
928
929 err = drm_connector_init(ddev, connector, &ltdc_rgb_connector_funcs,
930 DRM_MODE_CONNECTOR_DPI);
931 if (err) {
932 DRM_ERROR("Failed to initialize connector\n");
933 return NULL;
934 }
935
936 drm_connector_helper_add(connector, &ltdc_rgb_connector_helper_funcs);
937
938 DRM_DEBUG_DRIVER("RGB connector:%d created\n", connector->base.id);
939
940 return connector;
941 }
942
943 static int ltdc_get_caps(struct drm_device *ddev)
944 {
945 struct ltdc_device *ldev = ddev->dev_private;
946 u32 bus_width_log2, lcr, gc2r;
947
948 /* at least 1 layer must be managed */
949 lcr = reg_read(ldev->regs, LTDC_LCR);
950
951 ldev->caps.nb_layers = max_t(int, lcr, 1);
952
953 /* set data bus width */
954 gc2r = reg_read(ldev->regs, LTDC_GC2R);
955 bus_width_log2 = (gc2r & GC2R_BW) >> 4;
956 ldev->caps.bus_width = 8 << bus_width_log2;
957 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR);
958
959 switch (ldev->caps.hw_version) {
960 case HWVER_10200:
961 case HWVER_10300:
962 ldev->caps.reg_ofs = REG_OFS_NONE;
963 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
964 break;
965 case HWVER_20101:
966 ldev->caps.reg_ofs = REG_OFS_4;
967 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
968 break;
969 default:
970 return -ENODEV;
971 }
972
973 return 0;
974 }
975
976 static struct drm_panel *ltdc_get_panel(struct drm_device *ddev)
977 {
978 struct device *dev = ddev->dev;
979 struct device_node *np = dev->of_node;
980 struct device_node *entity, *port = NULL;
981 struct drm_panel *panel = NULL;
982
983 DRM_DEBUG_DRIVER("\n");
984
985 /*
986 * Parse ltdc node to get remote port and find RGB panel / HDMI slave
987 * If a dsi or a bridge (hdmi, lvds...) is connected to ltdc,
988 * a remote port & RGB panel will not be found.
989 */
990 for_each_endpoint_of_node(np, entity) {
991 if (!of_device_is_available(entity))
992 continue;
993
994 port = of_graph_get_remote_port_parent(entity);
995 if (port) {
996 panel = of_drm_find_panel(port);
997 of_node_put(port);
998 if (panel) {
999 DRM_DEBUG_DRIVER("remote panel %s\n",
1000 port->full_name);
1001 } else {
1002 DRM_DEBUG_DRIVER("panel missing\n");
1003 of_node_put(entity);
1004 }
1005 }
1006 }
1007
1008 return panel;
1009 }
1010
1011 int ltdc_load(struct drm_device *ddev)
1012 {
1013 struct platform_device *pdev = to_platform_device(ddev->dev);
1014 struct ltdc_device *ldev = ddev->dev_private;
1015 struct device *dev = ddev->dev;
1016 struct device_node *np = dev->of_node;
1017 struct drm_encoder *encoder;
1018 struct drm_connector *connector = NULL;
1019 struct drm_crtc *crtc;
1020 struct reset_control *rstc;
1021 struct resource res;
1022 int irq, ret, i;
1023
1024 DRM_DEBUG_DRIVER("\n");
1025
1026 ldev->panel = ltdc_get_panel(ddev);
1027 if (!ldev->panel)
1028 return -EPROBE_DEFER;
1029
1030 rstc = of_reset_control_get(np, NULL);
1031
1032 mutex_init(&ldev->err_lock);
1033
1034 ldev->pixel_clk = devm_clk_get(dev, "lcd");
1035 if (IS_ERR(ldev->pixel_clk)) {
1036 DRM_ERROR("Unable to get lcd clock\n");
1037 return -ENODEV;
1038 }
1039
1040 if (clk_prepare_enable(ldev->pixel_clk)) {
1041 DRM_ERROR("Unable to prepare pixel clock\n");
1042 return -ENODEV;
1043 }
1044
1045 if (of_address_to_resource(np, 0, &res)) {
1046 DRM_ERROR("Unable to get resource\n");
1047 return -ENODEV;
1048 }
1049
1050 ldev->regs = devm_ioremap_resource(dev, &res);
1051 if (IS_ERR(ldev->regs)) {
1052 DRM_ERROR("Unable to get ltdc registers\n");
1053 return PTR_ERR(ldev->regs);
1054 }
1055
1056 for (i = 0; i < MAX_IRQ; i++) {
1057 irq = platform_get_irq(pdev, i);
1058 if (irq < 0)
1059 continue;
1060
1061 ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
1062 ltdc_irq_thread, IRQF_ONESHOT,
1063 dev_name(dev), ddev);
1064 if (ret) {
1065 DRM_ERROR("Failed to register LTDC interrupt\n");
1066 return ret;
1067 }
1068 }
1069
1070 if (!IS_ERR(rstc))
1071 reset_control_deassert(rstc);
1072
1073 /* Disable interrupts */
1074 reg_clear(ldev->regs, LTDC_IER,
1075 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE);
1076
1077 ret = ltdc_get_caps(ddev);
1078 if (ret) {
1079 DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
1080 ldev->caps.hw_version);
1081 return ret;
1082 }
1083
1084 DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version);
1085
1086 if (ldev->panel) {
1087 encoder = ltdc_rgb_encoder_create(ddev);
1088 if (!encoder) {
1089 DRM_ERROR("Failed to create RGB encoder\n");
1090 ret = -EINVAL;
1091 goto err;
1092 }
1093
1094 connector = ltdc_rgb_connector_create(ddev);
1095 if (!connector) {
1096 DRM_ERROR("Failed to create RGB connector\n");
1097 ret = -EINVAL;
1098 goto err;
1099 }
1100
1101 ret = drm_mode_connector_attach_encoder(connector, encoder);
1102 if (ret) {
1103 DRM_ERROR("Failed to attach connector to encoder\n");
1104 goto err;
1105 }
1106
1107 drm_panel_attach(ldev->panel, connector);
1108 }
1109
1110 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
1111 if (!crtc) {
1112 DRM_ERROR("Failed to allocate crtc\n");
1113 ret = -ENOMEM;
1114 goto err;
1115 }
1116
1117 ret = ltdc_crtc_init(ddev, crtc);
1118 if (ret) {
1119 DRM_ERROR("Failed to init crtc\n");
1120 goto err;
1121 }
1122
1123 ret = drm_vblank_init(ddev, NB_CRTC);
1124 if (ret) {
1125 DRM_ERROR("Failed calling drm_vblank_init()\n");
1126 goto err;
1127 }
1128
1129 /* Allow usage of vblank without having to call drm_irq_install */
1130 ddev->irq_enabled = 1;
1131
1132 return 0;
1133 err:
1134 if (ldev->panel)
1135 drm_panel_detach(ldev->panel);
1136
1137 clk_disable_unprepare(ldev->pixel_clk);
1138
1139 return ret;
1140 }
1141
1142 void ltdc_unload(struct drm_device *ddev)
1143 {
1144 struct ltdc_device *ldev = ddev->dev_private;
1145
1146 DRM_DEBUG_DRIVER("\n");
1147
1148 if (ldev->panel)
1149 drm_panel_detach(ldev->panel);
1150
1151 clk_disable_unprepare(ldev->pixel_clk);
1152 }
1153
1154 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
1155 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
1156 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
1157 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
1158 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
1159 MODULE_LICENSE("GPL v2");
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