drivers/gpu/drm/stm/ltdc.c

   1 /*
   2  * Copyright (C) STMicroelectronics SA 2017
   3  *
   4  * Authors: Philippe Cornu <philippe.cornu@st.com>
   5  *          Yannick Fertre <yannick.fertre@st.com>
   6  *          Fabien Dessenne <fabien.dessenne@st.com>
   7  *          Mickael Reulier <mickael.reulier@st.com>
   8  *
   9  * License terms:  GNU General Public License (GPL), version 2
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/component.h>
  14 #include <linux/of_address.h>
  15 #include <linux/of_graph.h>
  16 #include <linux/reset.h>
  17
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc_helper.h>
  21 #include <drm/drm_fb_cma_helper.h>
  22 #include <drm/drm_gem_cma_helper.h>
  23 #include <drm/drm_of.h>
  24 #include <drm/drm_bridge.h>
  25 #include <drm/drm_plane_helper.h>
  26
  27 #include <video/videomode.h>
  28
  29 #include "ltdc.h"
  30
  31 #define NB_CRTC 1
  32 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
  33
  34 #define MAX_IRQ 4
  35
  36 #define HWVER_10200 0x010200
  37 #define HWVER_10300 0x010300
  38 #define HWVER_20101 0x020101
  39
  40 /*
  41  * The address of some registers depends on the HW version: such registers have
  42  * an extra offset specified with reg_ofs.
  43  */
  44 #define REG_OFS_NONE    0
  45 #define REG_OFS_4       4 /* Insertion of "Layer Configuration 2" reg */
  46 #define REG_OFS         (ldev->caps.reg_ofs)
  47 #define LAY_OFS         0x80    /* Register Offset between 2 layers */
  48
  49 /* Global register offsets */
  50 #define LTDC_IDR        0x0000 /* IDentification */
  51 #define LTDC_LCR        0x0004 /* Layer Count */
  52 #define LTDC_SSCR       0x0008 /* Synchronization Size Configuration */
  53 #define LTDC_BPCR       0x000C /* Back Porch Configuration */
  54 #define LTDC_AWCR       0x0010 /* Active Width Configuration */
  55 #define LTDC_TWCR       0x0014 /* Total Width Configuration */
  56 #define LTDC_GCR        0x0018 /* Global Control */
  57 #define LTDC_GC1R       0x001C /* Global Configuration 1 */
  58 #define LTDC_GC2R       0x0020 /* Global Configuration 2 */
  59 #define LTDC_SRCR       0x0024 /* Shadow Reload Configuration */
  60 #define LTDC_GACR       0x0028 /* GAmma Correction */
  61 #define LTDC_BCCR       0x002C /* Background Color Configuration */
  62 #define LTDC_IER        0x0034 /* Interrupt Enable */
  63 #define LTDC_ISR        0x0038 /* Interrupt Status */
  64 #define LTDC_ICR        0x003C /* Interrupt Clear */
  65 #define LTDC_LIPCR      0x0040 /* Line Interrupt Position Configuration */
  66 #define LTDC_CPSR       0x0044 /* Current Position Status */
  67 #define LTDC_CDSR       0x0048 /* Current Display Status */
  68
  69 /* Layer register offsets */
  70 #define LTDC_L1LC1R     (0x0080)           /* L1 Layer Configuration 1 */
  71 #define LTDC_L1LC2R     (0x0084)           /* L1 Layer Configuration 2 */
  72 #define LTDC_L1CR       (0x0084 + REG_OFS) /* L1 Control */
  73 #define LTDC_L1WHPCR    (0x0088 + REG_OFS) /* L1 Window Hor Position Config */
  74 #define LTDC_L1WVPCR    (0x008C + REG_OFS) /* L1 Window Vert Position Config */
  75 #define LTDC_L1CKCR     (0x0090 + REG_OFS) /* L1 Color Keying Configuration */
  76 #define LTDC_L1PFCR     (0x0094 + REG_OFS) /* L1 Pixel Format Configuration */
  77 #define LTDC_L1CACR     (0x0098 + REG_OFS) /* L1 Constant Alpha Config */
  78 #define LTDC_L1DCCR     (0x009C + REG_OFS) /* L1 Default Color Configuration */
  79 #define LTDC_L1BFCR     (0x00A0 + REG_OFS) /* L1 Blend Factors Configuration */
  80 #define LTDC_L1FBBCR    (0x00A4 + REG_OFS) /* L1 FrameBuffer Bus Control */
  81 #define LTDC_L1AFBCR    (0x00A8 + REG_OFS) /* L1 AuxFB Control */
  82 #define LTDC_L1CFBAR    (0x00AC + REG_OFS) /* L1 Color FrameBuffer Address */
  83 #define LTDC_L1CFBLR    (0x00B0 + REG_OFS) /* L1 Color FrameBuffer Length */
  84 #define LTDC_L1CFBLNR   (0x00B4 + REG_OFS) /* L1 Color FrameBuffer Line Nb */
  85 #define LTDC_L1AFBAR    (0x00B8 + REG_OFS) /* L1 AuxFB Address */
  86 #define LTDC_L1AFBLR    (0x00BC + REG_OFS) /* L1 AuxFB Length */
  87 #define LTDC_L1AFBLNR   (0x00C0 + REG_OFS) /* L1 AuxFB Line Number */
  88 #define LTDC_L1CLUTWR   (0x00C4 + REG_OFS) /* L1 CLUT Write */
  89 #define LTDC_L1YS1R     (0x00E0 + REG_OFS) /* L1 YCbCr Scale 1 */
  90 #define LTDC_L1YS2R     (0x00E4 + REG_OFS) /* L1 YCbCr Scale 2 */
  91
  92 /* Bit definitions */
  93 #define SSCR_VSH        GENMASK(10, 0)  /* Vertical Synchronization Height */
  94 #define SSCR_HSW        GENMASK(27, 16) /* Horizontal Synchronization Width */
  95
  96 #define BPCR_AVBP       GENMASK(10, 0)  /* Accumulated Vertical Back Porch */
  97 #define BPCR_AHBP       GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
  98
  99 #define AWCR_AAH        GENMASK(10, 0)  /* Accumulated Active Height */
 100 #define AWCR_AAW        GENMASK(27, 16) /* Accumulated Active Width */
 101
 102 #define TWCR_TOTALH     GENMASK(10, 0)  /* TOTAL Height */
 103 #define TWCR_TOTALW     GENMASK(27, 16) /* TOTAL Width */
 104
 105 #define GCR_LTDCEN      BIT(0)          /* LTDC ENable */
 106 #define GCR_DEN         BIT(16)         /* Dither ENable */
 107 #define GCR_PCPOL       BIT(28)         /* Pixel Clock POLarity-Inverted */
 108 #define GCR_DEPOL       BIT(29)         /* Data Enable POLarity-High */
 109 #define GCR_VSPOL       BIT(30)         /* Vertical Synchro POLarity-High */
 110 #define GCR_HSPOL       BIT(31)         /* Horizontal Synchro POLarity-High */
 111
 112 #define GC1R_WBCH       GENMASK(3, 0)   /* Width of Blue CHannel output */
 113 #define GC1R_WGCH       GENMASK(7, 4)   /* Width of Green Channel output */
 114 #define GC1R_WRCH       GENMASK(11, 8)  /* Width of Red Channel output */
 115 #define GC1R_PBEN       BIT(12)         /* Precise Blending ENable */
 116 #define GC1R_DT         GENMASK(15, 14) /* Dithering Technique */
 117 #define GC1R_GCT        GENMASK(19, 17) /* Gamma Correction Technique */
 118 #define GC1R_SHREN      BIT(21)         /* SHadow Registers ENabled */
 119 #define GC1R_BCP        BIT(22)         /* Background Colour Programmable */
 120 #define GC1R_BBEN       BIT(23)         /* Background Blending ENabled */
 121 #define GC1R_LNIP       BIT(24)         /* Line Number IRQ Position */
 122 #define GC1R_TP         BIT(25)         /* Timing Programmable */
 123 #define GC1R_IPP        BIT(26)         /* IRQ Polarity Programmable */
 124 #define GC1R_SPP        BIT(27)         /* Sync Polarity Programmable */
 125 #define GC1R_DWP        BIT(28)         /* Dither Width Programmable */
 126 #define GC1R_STREN      BIT(29)         /* STatus Registers ENabled */
 127 #define GC1R_BMEN       BIT(31)         /* Blind Mode ENabled */
 128
 129 #define GC2R_EDCA       BIT(0)          /* External Display Control Ability  */
 130 #define GC2R_STSAEN     BIT(1)          /* Slave Timing Sync Ability ENabled */
 131 #define GC2R_DVAEN      BIT(2)          /* Dual-View Ability ENabled */
 132 #define GC2R_DPAEN      BIT(3)          /* Dual-Port Ability ENabled */
 133 #define GC2R_BW         GENMASK(6, 4)   /* Bus Width (log2 of nb of bytes) */
 134 #define GC2R_EDCEN      BIT(7)          /* External Display Control ENabled */
 135
 136 #define SRCR_IMR        BIT(0)          /* IMmediate Reload */
 137 #define SRCR_VBR        BIT(1)          /* Vertical Blanking Reload */
 138
 139 #define BCCR_BCBLACK    0x00            /* Background Color BLACK */
 140 #define BCCR_BCBLUE     GENMASK(7, 0)   /* Background Color BLUE */
 141 #define BCCR_BCGREEN    GENMASK(15, 8)  /* Background Color GREEN */
 142 #define BCCR_BCRED      GENMASK(23, 16) /* Background Color RED */
 143 #define BCCR_BCWHITE    GENMASK(23, 0)  /* Background Color WHITE */
 144
 145 #define IER_LIE         BIT(0)          /* Line Interrupt Enable */
 146 #define IER_FUIE        BIT(1)          /* Fifo Underrun Interrupt Enable */
 147 #define IER_TERRIE      BIT(2)          /* Transfer ERRor Interrupt Enable */
 148 #define IER_RRIE        BIT(3)          /* Register Reload Interrupt enable */
 149
 150 #define ISR_LIF         BIT(0)          /* Line Interrupt Flag */
 151 #define ISR_FUIF        BIT(1)          /* Fifo Underrun Interrupt Flag */
 152 #define ISR_TERRIF      BIT(2)          /* Transfer ERRor Interrupt Flag */
 153 #define ISR_RRIF        BIT(3)          /* Register Reload Interrupt Flag */
 154
 155 #define LXCR_LEN        BIT(0)          /* Layer ENable */
 156 #define LXCR_COLKEN     BIT(1)          /* Color Keying Enable */
 157 #define LXCR_CLUTEN     BIT(4)          /* Color Look-Up Table ENable */
 158
 159 #define LXWHPCR_WHSTPOS GENMASK(11, 0)  /* Window Horizontal StarT POSition */
 160 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
 161
 162 #define LXWVPCR_WVSTPOS GENMASK(10, 0)  /* Window Vertical StarT POSition */
 163 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
 164
 165 #define LXPFCR_PF       GENMASK(2, 0)   /* Pixel Format */
 166
 167 #define LXCACR_CONSTA   GENMASK(7, 0)   /* CONSTant Alpha */
 168
 169 #define LXBFCR_BF2      GENMASK(2, 0)   /* Blending Factor 2 */
 170 #define LXBFCR_BF1      GENMASK(10, 8)  /* Blending Factor 1 */
 171
 172 #define LXCFBLR_CFBLL   GENMASK(12, 0)  /* Color Frame Buffer Line Length */
 173 #define LXCFBLR_CFBP    GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
 174
 175 #define LXCFBLNR_CFBLN  GENMASK(10, 0)   /* Color Frame Buffer Line Number */
 176
 177 #define CONSTA_MAX 0xFF         /* CONSTant Alpha MAX= 1.0 */
 178 #define BF1_PAXCA  0x600        /* Pixel Alpha x Constant Alpha */
 179 #define BF1_CA     0x400        /* Constant Alpha */
 180 #define BF2_1PAXCA 0x007        /* 1 - (Pixel Alpha x Constant Alpha) */
 181 #define BF2_1CA    0x005        /* 1 - Constant Alpha */
 182
 183 #define NB_PF           8       /* Max nb of HW pixel format */
 184
 185 enum ltdc_pix_fmt {
 186         PF_NONE,
 187         /* RGB formats */
 188         PF_ARGB8888,    /* ARGB [32 bits] */
 189         PF_RGBA8888,    /* RGBA [32 bits] */
 190         PF_RGB888,      /* RGB [24 bits] */
 191         PF_RGB565,      /* RGB [16 bits] */
 192         PF_ARGB1555,    /* ARGB A:1 bit RGB:15 bits [16 bits] */
 193         PF_ARGB4444,    /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
 194         /* Indexed formats */
 195         PF_L8,          /* Indexed 8 bits [8 bits] */
 196         PF_AL44,        /* Alpha:4 bits + indexed 4 bits [8 bits] */
 197         PF_AL88         /* Alpha:8 bits + indexed 8 bits [16 bits] */
 198 };
 199
 200 /* The index gives the encoding of the pixel format for an HW version */
 201 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
 202         PF_ARGB8888,    /* 0x00 */
 203         PF_RGB888,      /* 0x01 */
 204         PF_RGB565,      /* 0x02 */
 205         PF_ARGB1555,    /* 0x03 */
 206         PF_ARGB4444,    /* 0x04 */
 207         PF_L8,          /* 0x05 */
 208         PF_AL44,        /* 0x06 */
 209         PF_AL88         /* 0x07 */
 210 };
 211
 212 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
 213         PF_ARGB8888,    /* 0x00 */
 214         PF_RGB888,      /* 0x01 */
 215         PF_RGB565,      /* 0x02 */
 216         PF_RGBA8888,    /* 0x03 */
 217         PF_AL44,        /* 0x04 */
 218         PF_L8,          /* 0x05 */
 219         PF_ARGB1555,    /* 0x06 */
 220         PF_ARGB4444     /* 0x07 */
 221 };
 222
 223 static inline u32 reg_read(void __iomem *base, u32 reg)
 224 {
 225         return readl_relaxed(base + reg);
 226 }
 227
 228 static inline void reg_write(void __iomem *base, u32 reg, u32 val)
 229 {
 230         writel_relaxed(val, base + reg);
 231 }
 232
 233 static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
 234 {
 235         reg_write(base, reg, reg_read(base, reg) | mask);
 236 }
 237
 238 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
 239 {
 240         reg_write(base, reg, reg_read(base, reg) & ~mask);
 241 }
 242
 243 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask,
 244                                    u32 val)
 245 {
 246         reg_write(base, reg, (reg_read(base, reg) & ~mask) | val);
 247 }
 248
 249 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc)
 250 {
 251         return (struct ltdc_device *)crtc->dev->dev_private;
 252 }
 253
 254 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane)
 255 {
 256         return (struct ltdc_device *)plane->dev->dev_private;
 257 }
 258
 259 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc)
 260 {
 261         return (struct ltdc_device *)enc->dev->dev_private;
 262 }
 263
 264 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
 265 {
 266         enum ltdc_pix_fmt pf;
 267
 268         switch (drm_fmt) {
 269         case DRM_FORMAT_ARGB8888:
 270         case DRM_FORMAT_XRGB8888:
 271                 pf = PF_ARGB8888;
 272                 break;
 273         case DRM_FORMAT_RGBA8888:
 274         case DRM_FORMAT_RGBX8888:
 275                 pf = PF_RGBA8888;
 276                 break;
 277         case DRM_FORMAT_RGB888:
 278                 pf = PF_RGB888;
 279                 break;
 280         case DRM_FORMAT_RGB565:
 281                 pf = PF_RGB565;
 282                 break;
 283         case DRM_FORMAT_ARGB1555:
 284         case DRM_FORMAT_XRGB1555:
 285                 pf = PF_ARGB1555;
 286                 break;
 287         case DRM_FORMAT_ARGB4444:
 288         case DRM_FORMAT_XRGB4444:
 289                 pf = PF_ARGB4444;
 290                 break;
 291         case DRM_FORMAT_C8:
 292                 pf = PF_L8;
 293                 break;
 294         default:
 295                 pf = PF_NONE;
 296                 break;
 297         /* Note: There are no DRM_FORMAT for AL44 and AL88 */
 298         }
 299
 300         return pf;
 301 }
 302
 303 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf)
 304 {
 305         switch (pf) {
 306         case PF_ARGB8888:
 307                 return DRM_FORMAT_ARGB8888;
 308         case PF_RGBA8888:
 309                 return DRM_FORMAT_RGBA8888;
 310         case PF_RGB888:
 311                 return DRM_FORMAT_RGB888;
 312         case PF_RGB565:
 313                 return DRM_FORMAT_RGB565;
 314         case PF_ARGB1555:
 315                 return DRM_FORMAT_ARGB1555;
 316         case PF_ARGB4444:
 317                 return DRM_FORMAT_ARGB4444;
 318         case PF_L8:
 319                 return DRM_FORMAT_C8;
 320         case PF_AL44: /* No DRM support */
 321         case PF_AL88: /* No DRM support */
 322         case PF_NONE:
 323         default:
 324                 return 0;
 325         }
 326 }
 327
 328 static irqreturn_t ltdc_irq_thread(int irq, void *arg)
 329 {
 330         struct drm_device *ddev = arg;
 331         struct ltdc_device *ldev = ddev->dev_private;
 332         struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0);
 333
 334         /* Line IRQ : trigger the vblank event */
 335         if (ldev->irq_status & ISR_LIF)
 336                 drm_crtc_handle_vblank(crtc);
 337
 338         /* Save FIFO Underrun & Transfer Error status */
 339         mutex_lock(&ldev->err_lock);
 340         if (ldev->irq_status & ISR_FUIF)
 341                 ldev->error_status |= ISR_FUIF;
 342         if (ldev->irq_status & ISR_TERRIF)
 343                 ldev->error_status |= ISR_TERRIF;
 344         mutex_unlock(&ldev->err_lock);
 345
 346         return IRQ_HANDLED;
 347 }
 348
 349 static irqreturn_t ltdc_irq(int irq, void *arg)
 350 {
 351         struct drm_device *ddev = arg;
 352         struct ltdc_device *ldev = ddev->dev_private;
 353
 354         /* Read & Clear the interrupt status */
 355         ldev->irq_status = reg_read(ldev->regs, LTDC_ISR);
 356         reg_write(ldev->regs, LTDC_ICR, ldev->irq_status);
 357
 358         return IRQ_WAKE_THREAD;
 359 }
 360
 361 /*
 362  * DRM_CRTC
 363  */
 364
 365 static void ltdc_crtc_load_lut(struct drm_crtc *crtc)
 366 {
 367         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 368         unsigned int i, lay;
 369
 370         for (lay = 0; lay < ldev->caps.nb_layers; lay++)
 371                 for (i = 0; i < 256; i++)
 372                         reg_write(ldev->regs, LTDC_L1CLUTWR + lay * LAY_OFS,
 373                                   ldev->clut[i]);
 374 }
 375
 376 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
 377                                     struct drm_crtc_state *old_state)
 378 {
 379         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 380
 381         DRM_DEBUG_DRIVER("\n");
 382
 383         /* Sets the background color value */
 384         reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK);
 385
 386         /* Enable IRQ */
 387         reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
 388
 389         /* Immediately commit the planes */
 390         reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
 391
 392         /* Enable LTDC */
 393         reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN);
 394
 395         drm_crtc_vblank_on(crtc);
 396 }
 397
 398 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc,
 399                                      struct drm_crtc_state *old_state)
 400 {
 401         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 402
 403         DRM_DEBUG_DRIVER("\n");
 404
 405         drm_crtc_vblank_off(crtc);
 406
 407         /* disable LTDC */
 408         reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN);
 409
 410         /* disable IRQ */
 411         reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
 412
 413         /* immediately commit disable of layers before switching off LTDC */
 414         reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
 415 }
 416
 417 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
 418 {
 419         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 420         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 421         struct videomode vm;
 422         int rate = mode->clock * 1000;
 423         u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
 424         u32 total_width, total_height;
 425         u32 val;
 426
 427         drm_display_mode_to_videomode(mode, &vm);
 428
 429         DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name);
 430         DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive);
 431         DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
 432                          vm.hfront_porch, vm.hback_porch, vm.hsync_len,
 433                          vm.vfront_porch, vm.vback_porch, vm.vsync_len);
 434
 435         /* Convert video timings to ltdc timings */
 436         hsync = vm.hsync_len - 1;
 437         vsync = vm.vsync_len - 1;
 438         accum_hbp = hsync + vm.hback_porch;
 439         accum_vbp = vsync + vm.vback_porch;
 440         accum_act_w = accum_hbp + vm.hactive;
 441         accum_act_h = accum_vbp + vm.vactive;
 442         total_width = accum_act_w + vm.hfront_porch;
 443         total_height = accum_act_h + vm.vfront_porch;
 444
 445         clk_disable(ldev->pixel_clk);
 446
 447         if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
 448                 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
 449                 return;
 450         }
 451
 452         clk_enable(ldev->pixel_clk);
 453
 454         /* Configures the HS, VS, DE and PC polarities. Default Active Low */
 455         val = 0;
 456
 457         if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
 458                 val |= GCR_HSPOL;
 459
 460         if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
 461                 val |= GCR_VSPOL;
 462
 463         if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
 464                 val |= GCR_DEPOL;
 465
 466         if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
 467                 val |= GCR_PCPOL;
 468
 469         reg_update_bits(ldev->regs, LTDC_GCR,
 470                         GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
 471
 472         /* Set Synchronization size */
 473         val = (hsync << 16) | vsync;
 474         reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
 475
 476         /* Set Accumulated Back porch */
 477         val = (accum_hbp << 16) | accum_vbp;
 478         reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
 479
 480         /* Set Accumulated Active Width */
 481         val = (accum_act_w << 16) | accum_act_h;
 482         reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
 483
 484         /* Set total width & height */
 485         val = (total_width << 16) | total_height;
 486         reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
 487
 488         reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1));
 489 }
 490
 491 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
 492                                    struct drm_crtc_state *old_crtc_state)
 493 {
 494         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 495         struct drm_pending_vblank_event *event = crtc->state->event;
 496
 497         DRM_DEBUG_ATOMIC("\n");
 498
 499         /* Commit shadow registers = update planes at next vblank */
 500         reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
 501
 502         if (event) {
 503                 crtc->state->event = NULL;
 504
 505                 spin_lock_irq(&crtc->dev->event_lock);
 506                 if (drm_crtc_vblank_get(crtc) == 0)
 507                         drm_crtc_arm_vblank_event(crtc, event);
 508                 else
 509                         drm_crtc_send_vblank_event(crtc, event);
 510                 spin_unlock_irq(&crtc->dev->event_lock);
 511         }
 512 }
 513
 514 static struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
 515         .load_lut = ltdc_crtc_load_lut,
 516         .mode_set_nofb = ltdc_crtc_mode_set_nofb,
 517         .atomic_flush = ltdc_crtc_atomic_flush,
 518         .atomic_enable = ltdc_crtc_atomic_enable,
 519         .atomic_disable = ltdc_crtc_atomic_disable,
 520 };
 521
 522 int ltdc_crtc_enable_vblank(struct drm_device *ddev, unsigned int pipe)
 523 {
 524         struct ltdc_device *ldev = ddev->dev_private;
 525
 526         DRM_DEBUG_DRIVER("\n");
 527         reg_set(ldev->regs, LTDC_IER, IER_LIE);
 528
 529         return 0;
 530 }
 531
 532 void ltdc_crtc_disable_vblank(struct drm_device *ddev, unsigned int pipe)
 533 {
 534         struct ltdc_device *ldev = ddev->dev_private;
 535
 536         DRM_DEBUG_DRIVER("\n");
 537         reg_clear(ldev->regs, LTDC_IER, IER_LIE);
 538 }
 539
 540 static struct drm_crtc_funcs ltdc_crtc_funcs = {
 541         .destroy = drm_crtc_cleanup,
 542         .set_config = drm_atomic_helper_set_config,
 543         .page_flip = drm_atomic_helper_page_flip,
 544         .reset = drm_atomic_helper_crtc_reset,
 545         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 546         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 547 };
 548
 549 /*
 550  * DRM_PLANE
 551  */
 552
 553 static int ltdc_plane_atomic_check(struct drm_plane *plane,
 554                                    struct drm_plane_state *state)
 555 {
 556         struct drm_framebuffer *fb = state->fb;
 557         u32 src_x, src_y, src_w, src_h;
 558
 559         DRM_DEBUG_DRIVER("\n");
 560
 561         if (!fb)
 562                 return 0;
 563
 564         /* convert src_ from 16:16 format */
 565         src_x = state->src_x >> 16;
 566         src_y = state->src_y >> 16;
 567         src_w = state->src_w >> 16;
 568         src_h = state->src_h >> 16;
 569
 570         /* Reject scaling */
 571         if ((src_w != state->crtc_w) || (src_h != state->crtc_h)) {
 572                 DRM_ERROR("Scaling is not supported");
 573                 return -EINVAL;
 574         }
 575
 576         return 0;
 577 }
 578
 579 static void ltdc_plane_atomic_update(struct drm_plane *plane,
 580                                      struct drm_plane_state *oldstate)
 581 {
 582         struct ltdc_device *ldev = plane_to_ltdc(plane);
 583         struct drm_plane_state *state = plane->state;
 584         struct drm_framebuffer *fb = state->fb;
 585         u32 lofs = plane->index * LAY_OFS;
 586         u32 x0 = state->crtc_x;
 587         u32 x1 = state->crtc_x + state->crtc_w - 1;
 588         u32 y0 = state->crtc_y;
 589         u32 y1 = state->crtc_y + state->crtc_h - 1;
 590         u32 src_x, src_y, src_w, src_h;
 591         u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr;
 592         enum ltdc_pix_fmt pf;
 593
 594         if (!state->crtc || !fb) {
 595                 DRM_DEBUG_DRIVER("fb or crtc NULL");
 596                 return;
 597         }
 598
 599         /* convert src_ from 16:16 format */
 600         src_x = state->src_x >> 16;
 601         src_y = state->src_y >> 16;
 602         src_w = state->src_w >> 16;
 603         src_h = state->src_h >> 16;
 604
 605         DRM_DEBUG_DRIVER(
 606                 "plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
 607                 plane->base.id, fb->base.id,
 608                 src_w, src_h, src_x, src_y,
 609                 state->crtc_w, state->crtc_h, state->crtc_x, state->crtc_y);
 610
 611         bpcr = reg_read(ldev->regs, LTDC_BPCR);
 612         ahbp = (bpcr & BPCR_AHBP) >> 16;
 613         avbp = bpcr & BPCR_AVBP;
 614
 615         /* Configures the horizontal start and stop position */
 616         val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
 617         reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs,
 618                         LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
 619
 620         /* Configures the vertical start and stop position */
 621         val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
 622         reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs,
 623                         LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
 624
 625         /* Specifies the pixel format */
 626         pf = to_ltdc_pixelformat(fb->format->format);
 627         for (val = 0; val < NB_PF; val++)
 628                 if (ldev->caps.pix_fmt_hw[val] == pf)
 629                         break;
 630
 631         if (val == NB_PF) {
 632                 DRM_ERROR("Pixel format %.4s not supported\n",
 633                           (char *)&fb->format->format);
 634                 val = 0; /* set by default ARGB 32 bits */
 635         }
 636         reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
 637
 638         /* Configures the color frame buffer pitch in bytes & line length */
 639         pitch_in_bytes = fb->pitches[0];
 640         line_length = drm_format_plane_cpp(fb->format->format, 0) *
 641                       (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
 642         val = ((pitch_in_bytes << 16) | line_length);
 643         reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs,
 644                         LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
 645
 646         /* Specifies the constant alpha value */
 647         val = CONSTA_MAX;
 648         reg_update_bits(ldev->regs, LTDC_L1CACR + lofs,
 649                         LXCACR_CONSTA, val);
 650
 651         /* Specifies the blending factors */
 652         val = BF1_PAXCA | BF2_1PAXCA;
 653         reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs,
 654                         LXBFCR_BF2 | LXBFCR_BF1, val);
 655
 656         /* Configures the frame buffer line number */
 657         val = y1 - y0 + 1;
 658         reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs,
 659                         LXCFBLNR_CFBLN, val);
 660
 661         /* Sets the FB address */
 662         paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0);
 663
 664         DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
 665         reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr);
 666
 667         /* Enable layer and CLUT if needed */
 668         val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
 669         val |= LXCR_LEN;
 670         reg_update_bits(ldev->regs, LTDC_L1CR + lofs,
 671                         LXCR_LEN | LXCR_CLUTEN, val);
 672
 673         mutex_lock(&ldev->err_lock);
 674         if (ldev->error_status & ISR_FUIF) {
 675                 DRM_DEBUG_DRIVER("Fifo underrun\n");
 676                 ldev->error_status &= ~ISR_FUIF;
 677         }
 678         if (ldev->error_status & ISR_TERRIF) {
 679                 DRM_DEBUG_DRIVER("Transfer error\n");
 680                 ldev->error_status &= ~ISR_TERRIF;
 681         }
 682         mutex_unlock(&ldev->err_lock);
 683 }
 684
 685 static void ltdc_plane_atomic_disable(struct drm_plane *plane,
 686                                       struct drm_plane_state *oldstate)
 687 {
 688         struct ltdc_device *ldev = plane_to_ltdc(plane);
 689         u32 lofs = plane->index * LAY_OFS;
 690
 691         /* disable layer */
 692         reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN);
 693
 694         DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
 695                          oldstate->crtc->base.id, plane->base.id);
 696 }
 697
 698 static struct drm_plane_funcs ltdc_plane_funcs = {
 699         .update_plane = drm_atomic_helper_update_plane,
 700         .disable_plane = drm_atomic_helper_disable_plane,
 701         .destroy = drm_plane_cleanup,
 702         .set_property = drm_atomic_helper_plane_set_property,
 703         .reset = drm_atomic_helper_plane_reset,
 704         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 705         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 706 };
 707
 708 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
 709         .atomic_check = ltdc_plane_atomic_check,
 710         .atomic_update = ltdc_plane_atomic_update,
 711         .atomic_disable = ltdc_plane_atomic_disable,
 712 };
 713
 714 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
 715                                            enum drm_plane_type type)
 716 {
 717         unsigned long possible_crtcs = CRTC_MASK;
 718         struct ltdc_device *ldev = ddev->dev_private;
 719         struct device *dev = ddev->dev;
 720         struct drm_plane *plane;
 721         unsigned int i, nb_fmt = 0;
 722         u32 formats[NB_PF];
 723         u32 drm_fmt;
 724         int ret;
 725
 726         /* Get supported pixel formats */
 727         for (i = 0; i < NB_PF; i++) {
 728                 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]);
 729                 if (!drm_fmt)
 730                         continue;
 731                 formats[nb_fmt++] = drm_fmt;
 732         }
 733
 734         plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
 735         if (!plane)
 736                 return 0;
 737
 738         ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
 739                                        &ltdc_plane_funcs, formats, nb_fmt,
 740                                        type, NULL);
 741         if (ret < 0)
 742                 return 0;
 743
 744         drm_plane_helper_add(plane, &ltdc_plane_helper_funcs);
 745
 746         DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
 747
 748         return plane;
 749 }
 750
 751 static void ltdc_plane_destroy_all(struct drm_device *ddev)
 752 {
 753         struct drm_plane *plane, *plane_temp;
 754
 755         list_for_each_entry_safe(plane, plane_temp,
 756                                  &ddev->mode_config.plane_list, head)
 757                 drm_plane_cleanup(plane);
 758 }
 759
 760 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
 761 {
 762         struct ltdc_device *ldev = ddev->dev_private;
 763         struct drm_plane *primary, *overlay;
 764         unsigned int i;
 765         int res;
 766
 767         primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY);
 768         if (!primary) {
 769                 DRM_ERROR("Can not create primary plane\n");
 770                 return -EINVAL;
 771         }
 772
 773         res = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
 774                                         &ltdc_crtc_funcs, NULL);
 775         if (res) {
 776                 DRM_ERROR("Can not initialize CRTC\n");
 777                 goto cleanup;
 778         }
 779
 780         drm_crtc_helper_add(crtc, &ltdc_crtc_helper_funcs);
 781
 782         DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
 783
 784         /* Add planes. Note : the first layer is used by primary plane */
 785         for (i = 1; i < ldev->caps.nb_layers; i++) {
 786                 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY);
 787                 if (!overlay) {
 788                         res = -ENOMEM;
 789                         DRM_ERROR("Can not create overlay plane %d\n", i);
 790                         goto cleanup;
 791                 }
 792         }
 793
 794         return 0;
 795
 796 cleanup:
 797         ltdc_plane_destroy_all(ddev);
 798         return res;
 799 }
 800
 801 /*
 802  * DRM_ENCODER
 803  */
 804
 805 static const struct drm_encoder_funcs ltdc_encoder_funcs = {
 806         .destroy = drm_encoder_cleanup,
 807 };
 808
 809 static int ltdc_encoder_init(struct drm_device *ddev)
 810 {
 811         struct ltdc_device *ldev = ddev->dev_private;
 812         struct drm_encoder *encoder;
 813         int ret;
 814
 815         encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
 816         if (!encoder)
 817                 return -ENOMEM;
 818
 819         encoder->possible_crtcs = CRTC_MASK;
 820         encoder->possible_clones = 0; /* No cloning support */
 821
 822         drm_encoder_init(ddev, encoder, &ltdc_encoder_funcs,
 823                          DRM_MODE_ENCODER_DPI, NULL);
 824
 825         ret = drm_bridge_attach(encoder, ldev->bridge, NULL);
 826         if (ret) {
 827                 drm_encoder_cleanup(encoder);
 828                 return -EINVAL;
 829         }
 830
 831         DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id);
 832
 833         return 0;
 834 }
 835
 836 static int ltdc_get_caps(struct drm_device *ddev)
 837 {
 838         struct ltdc_device *ldev = ddev->dev_private;
 839         u32 bus_width_log2, lcr, gc2r;
 840
 841         /* at least 1 layer must be managed */
 842         lcr = reg_read(ldev->regs, LTDC_LCR);
 843
 844         ldev->caps.nb_layers = max_t(int, lcr, 1);
 845
 846         /* set data bus width */
 847         gc2r = reg_read(ldev->regs, LTDC_GC2R);
 848         bus_width_log2 = (gc2r & GC2R_BW) >> 4;
 849         ldev->caps.bus_width = 8 << bus_width_log2;
 850         ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR);
 851
 852         switch (ldev->caps.hw_version) {
 853         case HWVER_10200:
 854         case HWVER_10300:
 855                 ldev->caps.reg_ofs = REG_OFS_NONE;
 856                 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
 857                 break;
 858         case HWVER_20101:
 859                 ldev->caps.reg_ofs = REG_OFS_4;
 860                 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
 861                 break;
 862         default:
 863                 return -ENODEV;
 864         }
 865
 866         return 0;
 867 }
 868
 869 int ltdc_load(struct drm_device *ddev)
 870 {
 871         struct platform_device *pdev = to_platform_device(ddev->dev);
 872         struct ltdc_device *ldev = ddev->dev_private;
 873         struct device *dev = ddev->dev;
 874         struct device_node *np = dev->of_node;
 875         struct drm_bridge *bridge;
 876         struct drm_panel *panel;
 877         struct drm_crtc *crtc;
 878         struct reset_control *rstc;
 879         struct resource res;
 880         int irq, ret, i;
 881
 882         DRM_DEBUG_DRIVER("\n");
 883
 884         ret = drm_of_find_panel_or_bridge(np, 0, 0, &panel, &bridge);
 885         if (ret)
 886                 return ret;
 887
 888         rstc = of_reset_control_get(np, NULL);
 889
 890         mutex_init(&ldev->err_lock);
 891
 892         ldev->pixel_clk = devm_clk_get(dev, "lcd");
 893         if (IS_ERR(ldev->pixel_clk)) {
 894                 DRM_ERROR("Unable to get lcd clock\n");
 895                 return -ENODEV;
 896         }
 897
 898         if (clk_prepare_enable(ldev->pixel_clk)) {
 899                 DRM_ERROR("Unable to prepare pixel clock\n");
 900                 return -ENODEV;
 901         }
 902
 903         if (of_address_to_resource(np, 0, &res)) {
 904                 DRM_ERROR("Unable to get resource\n");
 905                 ret = -ENODEV;
 906                 goto err;
 907         }
 908
 909         ldev->regs = devm_ioremap_resource(dev, &res);
 910         if (IS_ERR(ldev->regs)) {
 911                 DRM_ERROR("Unable to get ltdc registers\n");
 912                 ret = PTR_ERR(ldev->regs);
 913                 goto err;
 914         }
 915
 916         for (i = 0; i < MAX_IRQ; i++) {
 917                 irq = platform_get_irq(pdev, i);
 918                 if (irq < 0)
 919                         continue;
 920
 921                 ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
 922                                                 ltdc_irq_thread, IRQF_ONESHOT,
 923                                                 dev_name(dev), ddev);
 924                 if (ret) {
 925                         DRM_ERROR("Failed to register LTDC interrupt\n");
 926                         goto err;
 927                 }
 928         }
 929
 930         if (!IS_ERR(rstc))
 931                 reset_control_deassert(rstc);
 932
 933         /* Disable interrupts */
 934         reg_clear(ldev->regs, LTDC_IER,
 935                   IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE);
 936
 937         ret = ltdc_get_caps(ddev);
 938         if (ret) {
 939                 DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
 940                           ldev->caps.hw_version);
 941                 goto err;
 942         }
 943
 944         DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version);
 945
 946         if (panel) {
 947                 bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DPI);
 948                 if (IS_ERR(bridge)) {
 949                         DRM_ERROR("Failed to create panel-bridge\n");
 950                         ret = PTR_ERR(bridge);
 951                         goto err;
 952                 }
 953                 ldev->is_panel_bridge = true;
 954         }
 955
 956         ldev->bridge = bridge;
 957
 958         ret = ltdc_encoder_init(ddev);
 959         if (ret) {
 960                 DRM_ERROR("Failed to init encoder\n");
 961                 goto err;
 962         }
 963
 964         crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
 965         if (!crtc) {
 966                 DRM_ERROR("Failed to allocate crtc\n");
 967                 ret = -ENOMEM;
 968                 goto err;
 969         }
 970
 971         ret = ltdc_crtc_init(ddev, crtc);
 972         if (ret) {
 973                 DRM_ERROR("Failed to init crtc\n");
 974                 goto err;
 975         }
 976
 977         ret = drm_vblank_init(ddev, NB_CRTC);
 978         if (ret) {
 979                 DRM_ERROR("Failed calling drm_vblank_init()\n");
 980                 goto err;
 981         }
 982
 983         /* Allow usage of vblank without having to call drm_irq_install */
 984         ddev->irq_enabled = 1;
 985
 986         return 0;
 987
 988 err:
 989         if (ldev->is_panel_bridge)
 990                 drm_panel_bridge_remove(bridge);
 991
 992         clk_disable_unprepare(ldev->pixel_clk);
 993
 994         return ret;
 995 }
 996
 997 void ltdc_unload(struct drm_device *ddev)
 998 {
 999         struct ltdc_device *ldev = ddev->dev_private;
1000
1001         DRM_DEBUG_DRIVER("\n");
1002
1003         if (ldev->is_panel_bridge)
1004                 drm_panel_bridge_remove(ldev->bridge);
1005
1006         clk_disable_unprepare(ldev->pixel_clk);
1007 }
1008
1009 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
1010 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
1011 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
1012 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
1013 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
1014 MODULE_LICENSE("GPL v2");