drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c

   1 /*
   2  * Copyright (C) 2016 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  */
  11
  12 #include <drm/drmP.h>
  13 #include <drm/drm_atomic_helper.h>
  14 #include <drm/drm_crtc_helper.h>
  15 #include <drm/drm_edid.h>
  16 #include <drm/drm_encoder.h>
  17 #include <drm/drm_of.h>
  18 #include <drm/drm_panel.h>
  19
  20 #include <linux/clk.h>
  21 #include <linux/component.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/of_device.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/regmap.h>
  27 #include <linux/reset.h>
  28
  29 #include "sun4i_backend.h"
  30 #include "sun4i_crtc.h"
  31 #include "sun4i_drv.h"
  32 #include "sun4i_hdmi.h"
  33 #include "sun4i_tcon.h"
  34
  35 static inline struct sun4i_hdmi *
  36 drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder)
  37 {
  38         return container_of(encoder, struct sun4i_hdmi,
  39                             encoder);
  40 }
  41
  42 static inline struct sun4i_hdmi *
  43 drm_connector_to_sun4i_hdmi(struct drm_connector *connector)
  44 {
  45         return container_of(connector, struct sun4i_hdmi,
  46                             connector);
  47 }
  48
  49 static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi,
  50                                            struct drm_display_mode *mode)
  51 {
  52         struct hdmi_avi_infoframe frame;
  53         u8 buffer[17];
  54         int i, ret;
  55
  56         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
  57         if (ret < 0) {
  58                 DRM_ERROR("Failed to get infoframes from mode\n");
  59                 return ret;
  60         }
  61
  62         ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
  63         if (ret < 0) {
  64                 DRM_ERROR("Failed to pack infoframes\n");
  65                 return ret;
  66         }
  67
  68         for (i = 0; i < sizeof(buffer); i++)
  69                 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i));
  70
  71         return 0;
  72 }
  73
  74 static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder,
  75                                    struct drm_crtc_state *crtc_state,
  76                                    struct drm_connector_state *conn_state)
  77 {
  78         struct drm_display_mode *mode = &crtc_state->mode;
  79
  80         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
  81                 return -EINVAL;
  82
  83         return 0;
  84 }
  85
  86 static void sun4i_hdmi_disable(struct drm_encoder *encoder)
  87 {
  88         struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
  89         struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
  90         struct sun4i_tcon *tcon = crtc->tcon;
  91         u32 val;
  92
  93         DRM_DEBUG_DRIVER("Disabling the HDMI Output\n");
  94
  95         val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
  96         val &= ~SUN4I_HDMI_VID_CTRL_ENABLE;
  97         writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
  98
  99         sun4i_tcon_channel_disable(tcon, 1);
 100 }
 101
 102 static void sun4i_hdmi_enable(struct drm_encoder *encoder)
 103 {
 104         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 105         struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
 106         struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
 107         struct sun4i_tcon *tcon = crtc->tcon;
 108         u32 val = 0;
 109
 110         DRM_DEBUG_DRIVER("Enabling the HDMI Output\n");
 111
 112         sun4i_tcon_channel_enable(tcon, 1);
 113
 114         sun4i_hdmi_setup_avi_infoframes(hdmi, mode);
 115         val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI);
 116         val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END);
 117         writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0));
 118
 119         val = SUN4I_HDMI_VID_CTRL_ENABLE;
 120         if (hdmi->hdmi_monitor)
 121                 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE;
 122
 123         writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
 124 }
 125
 126 static void sun4i_hdmi_mode_set(struct drm_encoder *encoder,
 127                                 struct drm_display_mode *mode,
 128                                 struct drm_display_mode *adjusted_mode)
 129 {
 130         struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
 131         struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
 132         struct sun4i_tcon *tcon = crtc->tcon;
 133         unsigned int x, y;
 134         u32 val;
 135
 136         sun4i_tcon1_mode_set(tcon, mode);
 137         sun4i_tcon_set_mux(tcon, 1, encoder);
 138
 139         clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
 140         clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000);
 141         clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000);
 142
 143         /* Set input sync enable */
 144         writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC,
 145                hdmi->base + SUN4I_HDMI_UNKNOWN_REG);
 146
 147         /* Setup timing registers */
 148         writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) |
 149                SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay),
 150                hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG);
 151
 152         x = mode->htotal - mode->hsync_start;
 153         y = mode->vtotal - mode->vsync_start;
 154         writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
 155                hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG);
 156
 157         x = mode->hsync_start - mode->hdisplay;
 158         y = mode->vsync_start - mode->vdisplay;
 159         writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
 160                hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG);
 161
 162         x = mode->hsync_end - mode->hsync_start;
 163         y = mode->vsync_end - mode->vsync_start;
 164         writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
 165                hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG);
 166
 167         val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK;
 168         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 169                 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC;
 170
 171         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 172                 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC;
 173
 174         writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG);
 175 }
 176
 177 static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = {
 178         .atomic_check   = sun4i_hdmi_atomic_check,
 179         .disable        = sun4i_hdmi_disable,
 180         .enable         = sun4i_hdmi_enable,
 181         .mode_set       = sun4i_hdmi_mode_set,
 182 };
 183
 184 static const struct drm_encoder_funcs sun4i_hdmi_funcs = {
 185         .destroy        = drm_encoder_cleanup,
 186 };
 187
 188 static int sun4i_hdmi_get_modes(struct drm_connector *connector)
 189 {
 190         struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
 191         struct edid *edid;
 192         int ret;
 193
 194         edid = drm_get_edid(connector, hdmi->i2c);
 195         if (!edid)
 196                 return 0;
 197
 198         hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 199         DRM_DEBUG_DRIVER("Monitor is %s monitor\n",
 200                          hdmi->hdmi_monitor ? "an HDMI" : "a DVI");
 201
 202         drm_mode_connector_update_edid_property(connector, edid);
 203         cec_s_phys_addr_from_edid(hdmi->cec_adap, edid);
 204         ret = drm_add_edid_modes(connector, edid);
 205         kfree(edid);
 206
 207         return ret;
 208 }
 209
 210 static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = {
 211         .get_modes      = sun4i_hdmi_get_modes,
 212 };
 213
 214 static enum drm_connector_status
 215 sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force)
 216 {
 217         struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
 218         unsigned long reg;
 219
 220         if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_HPD_REG, reg,
 221                                reg & SUN4I_HDMI_HPD_HIGH,
 222                                0, 500000)) {
 223                 cec_phys_addr_invalidate(hdmi->cec_adap);
 224                 return connector_status_disconnected;
 225         }
 226
 227         return connector_status_connected;
 228 }
 229
 230 static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = {
 231         .detect                 = sun4i_hdmi_connector_detect,
 232         .fill_modes             = drm_helper_probe_single_connector_modes,
 233         .destroy                = drm_connector_cleanup,
 234         .reset                  = drm_atomic_helper_connector_reset,
 235         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 236         .atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
 237 };
 238
 239 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC
 240 static bool sun4i_hdmi_cec_pin_read(struct cec_adapter *adap)
 241 {
 242         struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
 243
 244         return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX;
 245 }
 246
 247 static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap)
 248 {
 249         struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
 250
 251         /* Start driving the CEC pin low */
 252         writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC);
 253 }
 254
 255 static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap)
 256 {
 257         struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
 258
 259         /*
 260          * Stop driving the CEC pin, the pull up will take over
 261          * unless another CEC device is driving the pin low.
 262          */
 263         writel(0, hdmi->base + SUN4I_HDMI_CEC);
 264 }
 265
 266 static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = {
 267         .read = sun4i_hdmi_cec_pin_read,
 268         .low = sun4i_hdmi_cec_pin_low,
 269         .high = sun4i_hdmi_cec_pin_high,
 270 };
 271 #endif
 272
 273 #define SUN4I_HDMI_PAD_CTRL1_MASK       (GENMASK(24, 7) | GENMASK(5, 0))
 274 #define SUN4I_HDMI_PLL_CTRL_MASK        (GENMASK(31, 8) | GENMASK(3, 0))
 275
 276 static const struct sun4i_hdmi_variant sun5i_variant = {
 277         .pad_ctrl0_init_val     = SUN4I_HDMI_PAD_CTRL0_TXEN |
 278                                   SUN4I_HDMI_PAD_CTRL0_CKEN |
 279                                   SUN4I_HDMI_PAD_CTRL0_PWENG |
 280                                   SUN4I_HDMI_PAD_CTRL0_PWEND |
 281                                   SUN4I_HDMI_PAD_CTRL0_PWENC |
 282                                   SUN4I_HDMI_PAD_CTRL0_LDODEN |
 283                                   SUN4I_HDMI_PAD_CTRL0_LDOCEN |
 284                                   SUN4I_HDMI_PAD_CTRL0_BIASEN,
 285         .pad_ctrl1_init_val     = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
 286                                   SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
 287                                   SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
 288                                   SUN4I_HDMI_PAD_CTRL1_REG_DEN |
 289                                   SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
 290                                   SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
 291                                   SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
 292                                   SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
 293         .pll_ctrl_init_val      = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
 294                                   SUN4I_HDMI_PLL_CTRL_CS(7) |
 295                                   SUN4I_HDMI_PLL_CTRL_CP_S(15) |
 296                                   SUN4I_HDMI_PLL_CTRL_S(7) |
 297                                   SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
 298                                   SUN4I_HDMI_PLL_CTRL_SDIV2 |
 299                                   SUN4I_HDMI_PLL_CTRL_LDO2_EN |
 300                                   SUN4I_HDMI_PLL_CTRL_LDO1_EN |
 301                                   SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
 302                                   SUN4I_HDMI_PLL_CTRL_BWS |
 303                                   SUN4I_HDMI_PLL_CTRL_PLL_EN,
 304
 305         .ddc_clk_reg            = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
 306         .ddc_clk_pre_divider    = 2,
 307         .ddc_clk_m_offset       = 1,
 308
 309         .field_ddc_en           = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
 310         .field_ddc_start        = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
 311         .field_ddc_reset        = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
 312         .field_ddc_addr_reg     = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
 313         .field_ddc_slave_addr   = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
 314         .field_ddc_int_status   = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
 315         .field_ddc_fifo_clear   = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
 316         .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
 317         .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
 318         .field_ddc_byte_count   = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
 319         .field_ddc_cmd          = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
 320         .field_ddc_sda_en       = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
 321         .field_ddc_sck_en       = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
 322
 323         .ddc_fifo_reg           = SUN4I_HDMI_DDC_FIFO_DATA_REG,
 324         .ddc_fifo_has_dir       = true,
 325 };
 326
 327 static const struct regmap_config sun4i_hdmi_regmap_config = {
 328         .reg_bits       = 32,
 329         .val_bits       = 32,
 330         .reg_stride     = 4,
 331         .max_register   = 0x580,
 332 };
 333
 334 static int sun4i_hdmi_bind(struct device *dev, struct device *master,
 335                            void *data)
 336 {
 337         struct platform_device *pdev = to_platform_device(dev);
 338         struct drm_device *drm = data;
 339         struct sun4i_drv *drv = drm->dev_private;
 340         struct sun4i_hdmi *hdmi;
 341         struct resource *res;
 342         u32 reg;
 343         int ret;
 344
 345         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
 346         if (!hdmi)
 347                 return -ENOMEM;
 348         dev_set_drvdata(dev, hdmi);
 349         hdmi->dev = dev;
 350         hdmi->drv = drv;
 351
 352         hdmi->variant = of_device_get_match_data(dev);
 353         if (!hdmi->variant)
 354                 return -EINVAL;
 355
 356         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 357         hdmi->base = devm_ioremap_resource(dev, res);
 358         if (IS_ERR(hdmi->base)) {
 359                 dev_err(dev, "Couldn't map the HDMI encoder registers\n");
 360                 return PTR_ERR(hdmi->base);
 361         }
 362
 363         if (hdmi->variant->has_reset_control) {
 364                 hdmi->reset = devm_reset_control_get(dev, NULL);
 365                 if (IS_ERR(hdmi->reset)) {
 366                         dev_err(dev, "Couldn't get the HDMI reset control\n");
 367                         return PTR_ERR(hdmi->reset);
 368                 }
 369
 370                 ret = reset_control_deassert(hdmi->reset);
 371                 if (ret) {
 372                         dev_err(dev, "Couldn't deassert HDMI reset\n");
 373                         return ret;
 374                 }
 375         }
 376
 377         hdmi->bus_clk = devm_clk_get(dev, "ahb");
 378         if (IS_ERR(hdmi->bus_clk)) {
 379                 dev_err(dev, "Couldn't get the HDMI bus clock\n");
 380                 ret = PTR_ERR(hdmi->bus_clk);
 381                 goto err_assert_reset;
 382         }
 383         clk_prepare_enable(hdmi->bus_clk);
 384
 385         hdmi->mod_clk = devm_clk_get(dev, "mod");
 386         if (IS_ERR(hdmi->mod_clk)) {
 387                 dev_err(dev, "Couldn't get the HDMI mod clock\n");
 388                 ret = PTR_ERR(hdmi->mod_clk);
 389                 goto err_disable_bus_clk;
 390         }
 391         clk_prepare_enable(hdmi->mod_clk);
 392
 393         hdmi->pll0_clk = devm_clk_get(dev, "pll-0");
 394         if (IS_ERR(hdmi->pll0_clk)) {
 395                 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n");
 396                 ret = PTR_ERR(hdmi->pll0_clk);
 397                 goto err_disable_mod_clk;
 398         }
 399
 400         hdmi->pll1_clk = devm_clk_get(dev, "pll-1");
 401         if (IS_ERR(hdmi->pll1_clk)) {
 402                 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n");
 403                 ret = PTR_ERR(hdmi->pll1_clk);
 404                 goto err_disable_mod_clk;
 405         }
 406
 407         hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base,
 408                                              &sun4i_hdmi_regmap_config);
 409         if (IS_ERR(hdmi->regmap)) {
 410                 dev_err(dev, "Couldn't create HDMI encoder regmap\n");
 411                 return PTR_ERR(hdmi->regmap);
 412         }
 413
 414         ret = sun4i_tmds_create(hdmi);
 415         if (ret) {
 416                 dev_err(dev, "Couldn't create the TMDS clock\n");
 417                 goto err_disable_mod_clk;
 418         }
 419
 420         if (hdmi->variant->has_ddc_parent_clk) {
 421                 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc");
 422                 if (IS_ERR(hdmi->ddc_parent_clk)) {
 423                         dev_err(dev, "Couldn't get the HDMI DDC clock\n");
 424                         return PTR_ERR(hdmi->ddc_parent_clk);
 425                 }
 426         } else {
 427                 hdmi->ddc_parent_clk = hdmi->tmds_clk;
 428         }
 429
 430         writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
 431
 432         writel(hdmi->variant->pad_ctrl0_init_val,
 433                hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG);
 434
 435         /*
 436          * We can't just initialize the register there, we need to
 437          * protect the clock bits that have already been read out and
 438          * cached by the clock framework.
 439          */
 440         reg = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
 441         reg &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
 442         reg |= hdmi->variant->pad_ctrl1_init_val;
 443         writel(reg, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
 444
 445         reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
 446         reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK;
 447         reg |= hdmi->variant->pll_ctrl_init_val;
 448         writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
 449
 450         ret = sun4i_hdmi_i2c_create(dev, hdmi);
 451         if (ret) {
 452                 dev_err(dev, "Couldn't create the HDMI I2C adapter\n");
 453                 goto err_disable_mod_clk;
 454         }
 455
 456         drm_encoder_helper_add(&hdmi->encoder,
 457                                &sun4i_hdmi_helper_funcs);
 458         ret = drm_encoder_init(drm,
 459                                &hdmi->encoder,
 460                                &sun4i_hdmi_funcs,
 461                                DRM_MODE_ENCODER_TMDS,
 462                                NULL);
 463         if (ret) {
 464                 dev_err(dev, "Couldn't initialise the HDMI encoder\n");
 465                 goto err_del_i2c_adapter;
 466         }
 467
 468         hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
 469                                                                   dev->of_node);
 470         if (!hdmi->encoder.possible_crtcs) {
 471                 ret = -EPROBE_DEFER;
 472                 goto err_del_i2c_adapter;
 473         }
 474
 475 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC
 476         hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops,
 477                 hdmi, "sun4i", CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
 478                 CEC_CAP_PASSTHROUGH | CEC_CAP_RC);
 479         ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
 480         if (ret < 0)
 481                 goto err_cleanup_connector;
 482         writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX,
 483                hdmi->base + SUN4I_HDMI_CEC);
 484 #endif
 485
 486         drm_connector_helper_add(&hdmi->connector,
 487                                  &sun4i_hdmi_connector_helper_funcs);
 488         ret = drm_connector_init(drm, &hdmi->connector,
 489                                  &sun4i_hdmi_connector_funcs,
 490                                  DRM_MODE_CONNECTOR_HDMIA);
 491         if (ret) {
 492                 dev_err(dev,
 493                         "Couldn't initialise the HDMI connector\n");
 494                 goto err_cleanup_connector;
 495         }
 496
 497         /* There is no HPD interrupt, so we need to poll the controller */
 498         hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
 499                 DRM_CONNECTOR_POLL_DISCONNECT;
 500
 501         ret = cec_register_adapter(hdmi->cec_adap, dev);
 502         if (ret < 0)
 503                 goto err_cleanup_connector;
 504         drm_mode_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
 505
 506         return 0;
 507
 508 err_cleanup_connector:
 509         cec_delete_adapter(hdmi->cec_adap);
 510         drm_encoder_cleanup(&hdmi->encoder);
 511 err_del_i2c_adapter:
 512         i2c_del_adapter(hdmi->i2c);
 513 err_disable_mod_clk:
 514         clk_disable_unprepare(hdmi->mod_clk);
 515 err_disable_bus_clk:
 516         clk_disable_unprepare(hdmi->bus_clk);
 517 err_assert_reset:
 518         reset_control_assert(hdmi->reset);
 519         return ret;
 520 }
 521
 522 static void sun4i_hdmi_unbind(struct device *dev, struct device *master,
 523                             void *data)
 524 {
 525         struct sun4i_hdmi *hdmi = dev_get_drvdata(dev);
 526
 527         cec_unregister_adapter(hdmi->cec_adap);
 528         drm_connector_cleanup(&hdmi->connector);
 529         drm_encoder_cleanup(&hdmi->encoder);
 530         i2c_del_adapter(hdmi->i2c);
 531         clk_disable_unprepare(hdmi->mod_clk);
 532         clk_disable_unprepare(hdmi->bus_clk);
 533 }
 534
 535 static const struct component_ops sun4i_hdmi_ops = {
 536         .bind   = sun4i_hdmi_bind,
 537         .unbind = sun4i_hdmi_unbind,
 538 };
 539
 540 static int sun4i_hdmi_probe(struct platform_device *pdev)
 541 {
 542         return component_add(&pdev->dev, &sun4i_hdmi_ops);
 543 }
 544
 545 static int sun4i_hdmi_remove(struct platform_device *pdev)
 546 {
 547         component_del(&pdev->dev, &sun4i_hdmi_ops);
 548
 549         return 0;
 550 }
 551
 552 static const struct of_device_id sun4i_hdmi_of_table[] = {
 553         { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, },
 554         { }
 555 };
 556 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table);
 557
 558 static struct platform_driver sun4i_hdmi_driver = {
 559         .probe          = sun4i_hdmi_probe,
 560         .remove         = sun4i_hdmi_remove,
 561         .driver         = {
 562                 .name           = "sun4i-hdmi",
 563                 .of_match_table = sun4i_hdmi_of_table,
 564         },
 565 };
 566 module_platform_driver(sun4i_hdmi_driver);
 567
 568 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
 569 MODULE_DESCRIPTION("Allwinner A10 HDMI Driver");
 570 MODULE_LICENSE("GPL");