2 * Copyright (C) Jernej Skrabec <jernej.skrabec@siol.net>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
10 #include <drm/drm_atomic.h>
11 #include <drm/drm_atomic_helper.h>
12 #include <drm/drm_crtc.h>
13 #include <drm/drm_fb_cma_helper.h>
14 #include <drm/drm_gem_cma_helper.h>
15 #include <drm/drm_gem_framebuffer_helper.h>
16 #include <drm/drm_plane_helper.h>
17 #include <drm/drm_probe_helper.h>
20 #include "sun8i_vi_layer.h"
21 #include "sun8i_mixer.h"
22 #include "sun8i_vi_scaler.h"
24 static void sun8i_vi_layer_enable(struct sun8i_mixer
*mixer
, int channel
,
25 int overlay
, bool enable
, unsigned int zpos
,
26 unsigned int old_zpos
)
28 u32 val
, bld_base
, ch_base
;
30 bld_base
= sun8i_blender_base(mixer
);
31 ch_base
= sun8i_channel_base(mixer
, channel
);
33 DRM_DEBUG_DRIVER("%sabling VI channel %d overlay %d\n",
34 enable
? "En" : "Dis", channel
, overlay
);
37 val
= SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN
;
41 regmap_update_bits(mixer
->engine
.regs
,
42 SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base
, overlay
),
43 SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN
, val
);
45 if (!enable
|| zpos
!= old_zpos
) {
46 regmap_update_bits(mixer
->engine
.regs
,
47 SUN8I_MIXER_BLEND_PIPE_CTL(bld_base
),
48 SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos
),
51 regmap_update_bits(mixer
->engine
.regs
,
52 SUN8I_MIXER_BLEND_ROUTE(bld_base
),
53 SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos
),
58 val
= SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos
);
60 regmap_update_bits(mixer
->engine
.regs
,
61 SUN8I_MIXER_BLEND_PIPE_CTL(bld_base
),
64 val
= channel
<< SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos
);
66 regmap_update_bits(mixer
->engine
.regs
,
67 SUN8I_MIXER_BLEND_ROUTE(bld_base
),
68 SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos
),
73 static int sun8i_vi_layer_update_coord(struct sun8i_mixer
*mixer
, int channel
,
74 int overlay
, struct drm_plane
*plane
,
77 struct drm_plane_state
*state
= plane
->state
;
78 const struct drm_format_info
*format
= state
->fb
->format
;
79 u32 src_w
, src_h
, dst_w
, dst_h
;
80 u32 bld_base
, ch_base
;
87 DRM_DEBUG_DRIVER("Updating VI channel %d overlay %d\n",
90 bld_base
= sun8i_blender_base(mixer
);
91 ch_base
= sun8i_channel_base(mixer
, channel
);
93 src_w
= drm_rect_width(&state
->src
) >> 16;
94 src_h
= drm_rect_height(&state
->src
) >> 16;
95 dst_w
= drm_rect_width(&state
->dst
);
96 dst_h
= drm_rect_height(&state
->dst
);
98 hphase
= state
->src
.x1
& 0xffff;
99 vphase
= state
->src
.y1
& 0xffff;
101 /* make coordinates dividable by subsampling factor */
102 if (format
->hsub
> 1) {
105 mask
= format
->hsub
- 1;
106 remainder
= (state
->src
.x1
>> 16) & mask
;
107 src_w
= (src_w
+ remainder
) & ~mask
;
108 hphase
+= remainder
<< 16;
111 if (format
->vsub
> 1) {
114 mask
= format
->vsub
- 1;
115 remainder
= (state
->src
.y1
>> 16) & mask
;
116 src_h
= (src_h
+ remainder
) & ~mask
;
117 vphase
+= remainder
<< 16;
120 insize
= SUN8I_MIXER_SIZE(src_w
, src_h
);
121 outsize
= SUN8I_MIXER_SIZE(dst_w
, dst_h
);
123 /* Set height and width */
124 DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n",
125 (state
->src
.x1
>> 16) & ~(format
->hsub
- 1),
126 (state
->src
.y1
>> 16) & ~(format
->vsub
- 1));
127 DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w
, src_h
);
128 regmap_write(mixer
->engine
.regs
,
129 SUN8I_MIXER_CHAN_VI_LAYER_SIZE(ch_base
, overlay
),
131 regmap_write(mixer
->engine
.regs
,
132 SUN8I_MIXER_CHAN_VI_OVL_SIZE(ch_base
),
136 * Scaler must be enabled for subsampled formats, so it scales
137 * chroma to same size as luma.
139 subsampled
= format
->hsub
> 1 || format
->vsub
> 1;
141 if (insize
!= outsize
|| subsampled
|| hphase
|| vphase
) {
142 unsigned int scanline
, required
;
143 struct drm_display_mode
*mode
;
144 u32 hscale
, vscale
, fps
;
147 DRM_DEBUG_DRIVER("HW scaling is enabled\n");
149 mode
= &plane
->state
->crtc
->state
->mode
;
150 fps
= (mode
->clock
* 1000) / (mode
->vtotal
* mode
->htotal
);
151 ability
= clk_get_rate(mixer
->mod_clk
);
152 /* BSP algorithm assumes 80% efficiency of VI scaler unit */
154 do_div(ability
, mode
->vdisplay
* fps
* max(src_w
, dst_w
));
156 required
= src_h
* 100 / dst_h
;
158 if (ability
< required
) {
159 DRM_DEBUG_DRIVER("Using vertical coarse scaling\n");
161 vn
= (u32
)ability
* dst_h
/ 100;
165 /* it seems that every RGB scaler has buffer for 2048 pixels */
166 scanline
= subsampled
? mixer
->cfg
->scanline_yuv
: 2048;
168 if (src_w
> scanline
) {
169 DRM_DEBUG_DRIVER("Using horizontal coarse scaling\n");
175 hscale
= (src_w
<< 16) / dst_w
;
176 vscale
= (src_h
<< 16) / dst_h
;
178 sun8i_vi_scaler_setup(mixer
, channel
, src_w
, src_h
, dst_w
,
179 dst_h
, hscale
, vscale
, hphase
, vphase
,
181 sun8i_vi_scaler_enable(mixer
, channel
, true);
183 DRM_DEBUG_DRIVER("HW scaling is not needed\n");
184 sun8i_vi_scaler_enable(mixer
, channel
, false);
187 regmap_write(mixer
->engine
.regs
,
188 SUN8I_MIXER_CHAN_VI_HDS_Y(ch_base
),
189 SUN8I_MIXER_CHAN_VI_DS_N(hn
) |
190 SUN8I_MIXER_CHAN_VI_DS_M(hm
));
191 regmap_write(mixer
->engine
.regs
,
192 SUN8I_MIXER_CHAN_VI_HDS_UV(ch_base
),
193 SUN8I_MIXER_CHAN_VI_DS_N(hn
) |
194 SUN8I_MIXER_CHAN_VI_DS_M(hm
));
195 regmap_write(mixer
->engine
.regs
,
196 SUN8I_MIXER_CHAN_VI_VDS_Y(ch_base
),
197 SUN8I_MIXER_CHAN_VI_DS_N(vn
) |
198 SUN8I_MIXER_CHAN_VI_DS_M(vm
));
199 regmap_write(mixer
->engine
.regs
,
200 SUN8I_MIXER_CHAN_VI_VDS_UV(ch_base
),
201 SUN8I_MIXER_CHAN_VI_DS_N(vn
) |
202 SUN8I_MIXER_CHAN_VI_DS_M(vm
));
204 /* Set base coordinates */
205 DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
206 state
->dst
.x1
, state
->dst
.y1
);
207 DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w
, dst_h
);
208 regmap_write(mixer
->engine
.regs
,
209 SUN8I_MIXER_BLEND_ATTR_COORD(bld_base
, zpos
),
210 SUN8I_MIXER_COORD(state
->dst
.x1
, state
->dst
.y1
));
211 regmap_write(mixer
->engine
.regs
,
212 SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base
, zpos
),
218 static int sun8i_vi_layer_update_formats(struct sun8i_mixer
*mixer
, int channel
,
219 int overlay
, struct drm_plane
*plane
)
221 struct drm_plane_state
*state
= plane
->state
;
222 const struct de2_fmt_info
*fmt_info
;
225 ch_base
= sun8i_channel_base(mixer
, channel
);
227 fmt_info
= sun8i_mixer_format_info(state
->fb
->format
->format
);
229 DRM_DEBUG_DRIVER("Invalid format\n");
233 val
= fmt_info
->de2_fmt
<< SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET
;
234 regmap_update_bits(mixer
->engine
.regs
,
235 SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base
, overlay
),
236 SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK
, val
);
238 if (fmt_info
->csc
!= SUN8I_CSC_MODE_OFF
) {
239 sun8i_csc_set_ccsc_coefficients(mixer
, channel
, fmt_info
->csc
);
240 sun8i_csc_enable_ccsc(mixer
, channel
, true);
242 sun8i_csc_enable_ccsc(mixer
, channel
, false);
246 val
= SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE
;
250 regmap_update_bits(mixer
->engine
.regs
,
251 SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base
, overlay
),
252 SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE
, val
);
254 /* It seems that YUV formats use global alpha setting. */
255 if (mixer
->cfg
->is_de3
)
256 regmap_update_bits(mixer
->engine
.regs
,
257 SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base
,
259 SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK
,
260 SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA(0xff));
265 static int sun8i_vi_layer_update_buffer(struct sun8i_mixer
*mixer
, int channel
,
266 int overlay
, struct drm_plane
*plane
)
268 struct drm_plane_state
*state
= plane
->state
;
269 struct drm_framebuffer
*fb
= state
->fb
;
270 const struct drm_format_info
*format
= fb
->format
;
271 struct drm_gem_cma_object
*gem
;
272 u32 dx
, dy
, src_x
, src_y
;
277 ch_base
= sun8i_channel_base(mixer
, channel
);
279 /* Adjust x and y to be dividable by subsampling factor */
280 src_x
= (state
->src
.x1
>> 16) & ~(format
->hsub
- 1);
281 src_y
= (state
->src
.y1
>> 16) & ~(format
->vsub
- 1);
283 for (i
= 0; i
< format
->num_planes
; i
++) {
284 /* Get the physical address of the buffer in memory */
285 gem
= drm_fb_cma_get_gem_obj(fb
, i
);
287 DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem
->paddr
);
289 /* Compute the start of the displayed memory */
290 paddr
= gem
->paddr
+ fb
->offsets
[i
];
300 /* Fixup framebuffer address for src coordinates */
301 paddr
+= dx
* format
->cpp
[i
];
302 paddr
+= dy
* fb
->pitches
[i
];
304 /* Set the line width */
305 DRM_DEBUG_DRIVER("Layer %d. line width: %d bytes\n",
306 i
+ 1, fb
->pitches
[i
]);
307 regmap_write(mixer
->engine
.regs
,
308 SUN8I_MIXER_CHAN_VI_LAYER_PITCH(ch_base
,
312 DRM_DEBUG_DRIVER("Setting %d. buffer address to %pad\n",
315 regmap_write(mixer
->engine
.regs
,
316 SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(ch_base
,
318 lower_32_bits(paddr
));
324 static int sun8i_vi_layer_atomic_check(struct drm_plane
*plane
,
325 struct drm_plane_state
*state
)
327 struct sun8i_vi_layer
*layer
= plane_to_sun8i_vi_layer(plane
);
328 struct drm_crtc
*crtc
= state
->crtc
;
329 struct drm_crtc_state
*crtc_state
;
330 int min_scale
, max_scale
;
335 crtc_state
= drm_atomic_get_existing_crtc_state(state
->state
, crtc
);
336 if (WARN_ON(!crtc_state
))
339 min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
340 max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
342 if (layer
->mixer
->cfg
->scaler_mask
& BIT(layer
->channel
)) {
343 min_scale
= SUN8I_VI_SCALER_SCALE_MIN
;
344 max_scale
= SUN8I_VI_SCALER_SCALE_MAX
;
347 return drm_atomic_helper_check_plane_state(state
, crtc_state
,
348 min_scale
, max_scale
,
352 static void sun8i_vi_layer_atomic_disable(struct drm_plane
*plane
,
353 struct drm_plane_state
*old_state
)
355 struct sun8i_vi_layer
*layer
= plane_to_sun8i_vi_layer(plane
);
356 unsigned int old_zpos
= old_state
->normalized_zpos
;
357 struct sun8i_mixer
*mixer
= layer
->mixer
;
359 sun8i_vi_layer_enable(mixer
, layer
->channel
, layer
->overlay
, false, 0,
363 static void sun8i_vi_layer_atomic_update(struct drm_plane
*plane
,
364 struct drm_plane_state
*old_state
)
366 struct sun8i_vi_layer
*layer
= plane_to_sun8i_vi_layer(plane
);
367 unsigned int zpos
= plane
->state
->normalized_zpos
;
368 unsigned int old_zpos
= old_state
->normalized_zpos
;
369 struct sun8i_mixer
*mixer
= layer
->mixer
;
371 if (!plane
->state
->visible
) {
372 sun8i_vi_layer_enable(mixer
, layer
->channel
,
373 layer
->overlay
, false, 0, old_zpos
);
377 sun8i_vi_layer_update_coord(mixer
, layer
->channel
,
378 layer
->overlay
, plane
, zpos
);
379 sun8i_vi_layer_update_formats(mixer
, layer
->channel
,
380 layer
->overlay
, plane
);
381 sun8i_vi_layer_update_buffer(mixer
, layer
->channel
,
382 layer
->overlay
, plane
);
383 sun8i_vi_layer_enable(mixer
, layer
->channel
, layer
->overlay
,
384 true, zpos
, old_zpos
);
387 static struct drm_plane_helper_funcs sun8i_vi_layer_helper_funcs
= {
388 .prepare_fb
= drm_gem_fb_prepare_fb
,
389 .atomic_check
= sun8i_vi_layer_atomic_check
,
390 .atomic_disable
= sun8i_vi_layer_atomic_disable
,
391 .atomic_update
= sun8i_vi_layer_atomic_update
,
394 static const struct drm_plane_funcs sun8i_vi_layer_funcs
= {
395 .atomic_destroy_state
= drm_atomic_helper_plane_destroy_state
,
396 .atomic_duplicate_state
= drm_atomic_helper_plane_duplicate_state
,
397 .destroy
= drm_plane_cleanup
,
398 .disable_plane
= drm_atomic_helper_disable_plane
,
399 .reset
= drm_atomic_helper_plane_reset
,
400 .update_plane
= drm_atomic_helper_update_plane
,
404 * While all RGB formats are supported, VI planes don't support
405 * alpha blending, so there is no point having formats with alpha
406 * channel if their opaque analog exist.
408 static const u32 sun8i_vi_layer_formats
[] = {
444 struct sun8i_vi_layer
*sun8i_vi_layer_init_one(struct drm_device
*drm
,
445 struct sun8i_mixer
*mixer
,
448 struct sun8i_vi_layer
*layer
;
449 unsigned int plane_cnt
;
452 layer
= devm_kzalloc(drm
->dev
, sizeof(*layer
), GFP_KERNEL
);
454 return ERR_PTR(-ENOMEM
);
456 /* possible crtcs are set later */
457 ret
= drm_universal_plane_init(drm
, &layer
->plane
, 0,
458 &sun8i_vi_layer_funcs
,
459 sun8i_vi_layer_formats
,
460 ARRAY_SIZE(sun8i_vi_layer_formats
),
461 NULL
, DRM_PLANE_TYPE_OVERLAY
, NULL
);
463 dev_err(drm
->dev
, "Couldn't initialize layer\n");
467 plane_cnt
= mixer
->cfg
->ui_num
+ mixer
->cfg
->vi_num
;
469 ret
= drm_plane_create_zpos_property(&layer
->plane
, index
,
472 dev_err(drm
->dev
, "Couldn't add zpos property\n");
476 drm_plane_helper_add(&layer
->plane
, &sun8i_vi_layer_helper_funcs
);
477 layer
->mixer
= mixer
;
478 layer
->channel
= index
;