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[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / tegra / dc.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/debugfs.h>
9 #include <linux/delay.h>
10 #include <linux/iommu.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
15
16 #include <soc/tegra/pmc.h>
17
18 #include <drm/drm_atomic.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_debugfs.h>
21 #include <drm/drm_fourcc.h>
22 #include <drm/drm_plane_helper.h>
23 #include <drm/drm_vblank.h>
24
25 #include "dc.h"
26 #include "drm.h"
27 #include "gem.h"
28 #include "hub.h"
29 #include "plane.h"
30
31 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
32 struct drm_crtc_state *state);
33
34 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
35 {
36 stats->frames = 0;
37 stats->vblank = 0;
38 stats->underflow = 0;
39 stats->overflow = 0;
40 }
41
42 /* Reads the active copy of a register. */
43 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
44 {
45 u32 value;
46
47 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
48 value = tegra_dc_readl(dc, offset);
49 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
50
51 return value;
52 }
53
54 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
55 unsigned int offset)
56 {
57 if (offset >= 0x500 && offset <= 0x638) {
58 offset = 0x000 + (offset - 0x500);
59 return plane->offset + offset;
60 }
61
62 if (offset >= 0x700 && offset <= 0x719) {
63 offset = 0x180 + (offset - 0x700);
64 return plane->offset + offset;
65 }
66
67 if (offset >= 0x800 && offset <= 0x839) {
68 offset = 0x1c0 + (offset - 0x800);
69 return plane->offset + offset;
70 }
71
72 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
73
74 return plane->offset + offset;
75 }
76
77 static inline u32 tegra_plane_readl(struct tegra_plane *plane,
78 unsigned int offset)
79 {
80 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
81 }
82
83 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
84 unsigned int offset)
85 {
86 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
87 }
88
89 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
90 {
91 struct device_node *np = dc->dev->of_node;
92 struct of_phandle_iterator it;
93 int err;
94
95 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
96 if (it.node == dev->of_node)
97 return true;
98
99 return false;
100 }
101
102 /*
103 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
104 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
105 * Latching happens mmediately if the display controller is in STOP mode or
106 * on the next frame boundary otherwise.
107 *
108 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
109 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
110 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
111 * into the ACTIVE copy, either immediately if the display controller is in
112 * STOP mode, or at the next frame boundary otherwise.
113 */
114 void tegra_dc_commit(struct tegra_dc *dc)
115 {
116 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
117 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
118 }
119
120 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
121 unsigned int bpp)
122 {
123 fixed20_12 outf = dfixed_init(out);
124 fixed20_12 inf = dfixed_init(in);
125 u32 dda_inc;
126 int max;
127
128 if (v)
129 max = 15;
130 else {
131 switch (bpp) {
132 case 2:
133 max = 8;
134 break;
135
136 default:
137 WARN_ON_ONCE(1);
138 fallthrough;
139 case 4:
140 max = 4;
141 break;
142 }
143 }
144
145 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
146 inf.full -= dfixed_const(1);
147
148 dda_inc = dfixed_div(inf, outf);
149 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
150
151 return dda_inc;
152 }
153
154 static inline u32 compute_initial_dda(unsigned int in)
155 {
156 fixed20_12 inf = dfixed_init(in);
157 return dfixed_frac(inf);
158 }
159
160 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
161 {
162 u32 background[3] = {
163 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
164 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
165 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
166 };
167 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
168 BLEND_COLOR_KEY_NONE;
169 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
170 struct tegra_plane_state *state;
171 u32 blending[2];
172 unsigned int i;
173
174 /* disable blending for non-overlapping case */
175 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
176 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
177
178 state = to_tegra_plane_state(plane->base.state);
179
180 if (state->opaque) {
181 /*
182 * Since custom fix-weight blending isn't utilized and weight
183 * of top window is set to max, we can enforce dependent
184 * blending which in this case results in transparent bottom
185 * window if top window is opaque and if top window enables
186 * alpha blending, then bottom window is getting alpha value
187 * of 1 minus the sum of alpha components of the overlapping
188 * plane.
189 */
190 background[0] |= BLEND_CONTROL_DEPENDENT;
191 background[1] |= BLEND_CONTROL_DEPENDENT;
192
193 /*
194 * The region where three windows overlap is the intersection
195 * of the two regions where two windows overlap. It contributes
196 * to the area if all of the windows on top of it have an alpha
197 * component.
198 */
199 switch (state->base.normalized_zpos) {
200 case 0:
201 if (state->blending[0].alpha &&
202 state->blending[1].alpha)
203 background[2] |= BLEND_CONTROL_DEPENDENT;
204 break;
205
206 case 1:
207 background[2] |= BLEND_CONTROL_DEPENDENT;
208 break;
209 }
210 } else {
211 /*
212 * Enable alpha blending if pixel format has an alpha
213 * component.
214 */
215 foreground |= BLEND_CONTROL_ALPHA;
216
217 /*
218 * If any of the windows on top of this window is opaque, it
219 * will completely conceal this window within that area. If
220 * top window has an alpha component, it is blended over the
221 * bottom window.
222 */
223 for (i = 0; i < 2; i++) {
224 if (state->blending[i].alpha &&
225 state->blending[i].top)
226 background[i] |= BLEND_CONTROL_DEPENDENT;
227 }
228
229 switch (state->base.normalized_zpos) {
230 case 0:
231 if (state->blending[0].alpha &&
232 state->blending[1].alpha)
233 background[2] |= BLEND_CONTROL_DEPENDENT;
234 break;
235
236 case 1:
237 /*
238 * When both middle and topmost windows have an alpha,
239 * these windows a mixed together and then the result
240 * is blended over the bottom window.
241 */
242 if (state->blending[0].alpha &&
243 state->blending[0].top)
244 background[2] |= BLEND_CONTROL_ALPHA;
245
246 if (state->blending[1].alpha &&
247 state->blending[1].top)
248 background[2] |= BLEND_CONTROL_ALPHA;
249 break;
250 }
251 }
252
253 switch (state->base.normalized_zpos) {
254 case 0:
255 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
256 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
257 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
258 break;
259
260 case 1:
261 /*
262 * If window B / C is topmost, then X / Y registers are
263 * matching the order of blending[...] state indices,
264 * otherwise a swap is required.
265 */
266 if (!state->blending[0].top && state->blending[1].top) {
267 blending[0] = foreground;
268 blending[1] = background[1];
269 } else {
270 blending[0] = background[0];
271 blending[1] = foreground;
272 }
273
274 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
275 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
276 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
277 break;
278
279 case 2:
280 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
281 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
282 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
283 break;
284 }
285 }
286
287 static void tegra_plane_setup_blending(struct tegra_plane *plane,
288 const struct tegra_dc_window *window)
289 {
290 u32 value;
291
292 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
293 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
294 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
295 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
296
297 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
298 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
299 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
300 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
301
302 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
303 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
304 }
305
306 static bool
307 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
308 const struct tegra_dc_window *window)
309 {
310 struct tegra_dc *dc = plane->dc;
311
312 if (window->src.w == window->dst.w)
313 return false;
314
315 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
316 return false;
317
318 return true;
319 }
320
321 static bool
322 tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
323 const struct tegra_dc_window *window)
324 {
325 struct tegra_dc *dc = plane->dc;
326
327 if (window->src.h == window->dst.h)
328 return false;
329
330 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
331 return false;
332
333 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
334 return false;
335
336 return true;
337 }
338
339 static void tegra_dc_setup_window(struct tegra_plane *plane,
340 const struct tegra_dc_window *window)
341 {
342 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
343 struct tegra_dc *dc = plane->dc;
344 bool yuv, planar;
345 u32 value;
346
347 /*
348 * For YUV planar modes, the number of bytes per pixel takes into
349 * account only the luma component and therefore is 1.
350 */
351 yuv = tegra_plane_format_is_yuv(window->format, &planar);
352 if (!yuv)
353 bpp = window->bits_per_pixel / 8;
354 else
355 bpp = planar ? 1 : 2;
356
357 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
358 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
359
360 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
361 tegra_plane_writel(plane, value, DC_WIN_POSITION);
362
363 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
364 tegra_plane_writel(plane, value, DC_WIN_SIZE);
365
366 h_offset = window->src.x * bpp;
367 v_offset = window->src.y;
368 h_size = window->src.w * bpp;
369 v_size = window->src.h;
370
371 if (window->reflect_x)
372 h_offset += (window->src.w - 1) * bpp;
373
374 if (window->reflect_y)
375 v_offset += window->src.h - 1;
376
377 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
378 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
379
380 /*
381 * For DDA computations the number of bytes per pixel for YUV planar
382 * modes needs to take into account all Y, U and V components.
383 */
384 if (yuv && planar)
385 bpp = 2;
386
387 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
388 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
389
390 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
391 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
392
393 h_dda = compute_initial_dda(window->src.x);
394 v_dda = compute_initial_dda(window->src.y);
395
396 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
397 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
398
399 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
400 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
401
402 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
403
404 if (yuv && planar) {
405 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
406 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
407 value = window->stride[1] << 16 | window->stride[0];
408 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
409 } else {
410 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
411 }
412
413 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
414 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
415
416 if (dc->soc->supports_block_linear) {
417 unsigned long height = window->tiling.value;
418
419 switch (window->tiling.mode) {
420 case TEGRA_BO_TILING_MODE_PITCH:
421 value = DC_WINBUF_SURFACE_KIND_PITCH;
422 break;
423
424 case TEGRA_BO_TILING_MODE_TILED:
425 value = DC_WINBUF_SURFACE_KIND_TILED;
426 break;
427
428 case TEGRA_BO_TILING_MODE_BLOCK:
429 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
430 DC_WINBUF_SURFACE_KIND_BLOCK;
431 break;
432 }
433
434 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
435 } else {
436 switch (window->tiling.mode) {
437 case TEGRA_BO_TILING_MODE_PITCH:
438 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
439 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
440 break;
441
442 case TEGRA_BO_TILING_MODE_TILED:
443 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
444 DC_WIN_BUFFER_ADDR_MODE_TILE;
445 break;
446
447 case TEGRA_BO_TILING_MODE_BLOCK:
448 /*
449 * No need to handle this here because ->atomic_check
450 * will already have filtered it out.
451 */
452 break;
453 }
454
455 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
456 }
457
458 value = WIN_ENABLE;
459
460 if (yuv) {
461 /* setup default colorspace conversion coefficients */
462 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
463 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
464 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
465 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
466 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
467 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
468 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
469 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
470
471 value |= CSC_ENABLE;
472 } else if (window->bits_per_pixel < 24) {
473 value |= COLOR_EXPAND;
474 }
475
476 if (window->reflect_x)
477 value |= H_DIRECTION;
478
479 if (window->reflect_y)
480 value |= V_DIRECTION;
481
482 if (tegra_plane_use_horizontal_filtering(plane, window)) {
483 /*
484 * Enable horizontal 6-tap filter and set filtering
485 * coefficients to the default values defined in TRM.
486 */
487 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
488 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
489 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
490 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
491 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
492 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
493 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
494 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
495 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
496 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
497 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
498 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
499 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
500 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
501 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
502 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
503
504 value |= H_FILTER;
505 }
506
507 if (tegra_plane_use_vertical_filtering(plane, window)) {
508 unsigned int i, k;
509
510 /*
511 * Enable vertical 2-tap filter and set filtering
512 * coefficients to the default values defined in TRM.
513 */
514 for (i = 0, k = 128; i < 16; i++, k -= 8)
515 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
516
517 value |= V_FILTER;
518 }
519
520 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
521
522 if (dc->soc->has_legacy_blending)
523 tegra_plane_setup_blending_legacy(plane);
524 else
525 tegra_plane_setup_blending(plane, window);
526 }
527
528 static const u32 tegra20_primary_formats[] = {
529 DRM_FORMAT_ARGB4444,
530 DRM_FORMAT_ARGB1555,
531 DRM_FORMAT_RGB565,
532 DRM_FORMAT_RGBA5551,
533 DRM_FORMAT_ABGR8888,
534 DRM_FORMAT_ARGB8888,
535 /* non-native formats */
536 DRM_FORMAT_XRGB1555,
537 DRM_FORMAT_RGBX5551,
538 DRM_FORMAT_XBGR8888,
539 DRM_FORMAT_XRGB8888,
540 };
541
542 static const u64 tegra20_modifiers[] = {
543 DRM_FORMAT_MOD_LINEAR,
544 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
545 DRM_FORMAT_MOD_INVALID
546 };
547
548 static const u32 tegra114_primary_formats[] = {
549 DRM_FORMAT_ARGB4444,
550 DRM_FORMAT_ARGB1555,
551 DRM_FORMAT_RGB565,
552 DRM_FORMAT_RGBA5551,
553 DRM_FORMAT_ABGR8888,
554 DRM_FORMAT_ARGB8888,
555 /* new on Tegra114 */
556 DRM_FORMAT_ABGR4444,
557 DRM_FORMAT_ABGR1555,
558 DRM_FORMAT_BGRA5551,
559 DRM_FORMAT_XRGB1555,
560 DRM_FORMAT_RGBX5551,
561 DRM_FORMAT_XBGR1555,
562 DRM_FORMAT_BGRX5551,
563 DRM_FORMAT_BGR565,
564 DRM_FORMAT_BGRA8888,
565 DRM_FORMAT_RGBA8888,
566 DRM_FORMAT_XRGB8888,
567 DRM_FORMAT_XBGR8888,
568 };
569
570 static const u32 tegra124_primary_formats[] = {
571 DRM_FORMAT_ARGB4444,
572 DRM_FORMAT_ARGB1555,
573 DRM_FORMAT_RGB565,
574 DRM_FORMAT_RGBA5551,
575 DRM_FORMAT_ABGR8888,
576 DRM_FORMAT_ARGB8888,
577 /* new on Tegra114 */
578 DRM_FORMAT_ABGR4444,
579 DRM_FORMAT_ABGR1555,
580 DRM_FORMAT_BGRA5551,
581 DRM_FORMAT_XRGB1555,
582 DRM_FORMAT_RGBX5551,
583 DRM_FORMAT_XBGR1555,
584 DRM_FORMAT_BGRX5551,
585 DRM_FORMAT_BGR565,
586 DRM_FORMAT_BGRA8888,
587 DRM_FORMAT_RGBA8888,
588 DRM_FORMAT_XRGB8888,
589 DRM_FORMAT_XBGR8888,
590 /* new on Tegra124 */
591 DRM_FORMAT_RGBX8888,
592 DRM_FORMAT_BGRX8888,
593 };
594
595 static const u64 tegra124_modifiers[] = {
596 DRM_FORMAT_MOD_LINEAR,
597 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
598 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
599 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
600 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
601 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
602 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
603 DRM_FORMAT_MOD_INVALID
604 };
605
606 static int tegra_plane_atomic_check(struct drm_plane *plane,
607 struct drm_plane_state *state)
608 {
609 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
610 unsigned int supported_rotation = DRM_MODE_ROTATE_0 |
611 DRM_MODE_REFLECT_X |
612 DRM_MODE_REFLECT_Y;
613 unsigned int rotation = state->rotation;
614 struct tegra_bo_tiling *tiling = &plane_state->tiling;
615 struct tegra_plane *tegra = to_tegra_plane(plane);
616 struct tegra_dc *dc = to_tegra_dc(state->crtc);
617 int err;
618
619 /* no need for further checks if the plane is being disabled */
620 if (!state->crtc)
621 return 0;
622
623 err = tegra_plane_format(state->fb->format->format,
624 &plane_state->format,
625 &plane_state->swap);
626 if (err < 0)
627 return err;
628
629 /*
630 * Tegra20 and Tegra30 are special cases here because they support
631 * only variants of specific formats with an alpha component, but not
632 * the corresponding opaque formats. However, the opaque formats can
633 * be emulated by disabling alpha blending for the plane.
634 */
635 if (dc->soc->has_legacy_blending) {
636 err = tegra_plane_setup_legacy_state(tegra, plane_state);
637 if (err < 0)
638 return err;
639 }
640
641 err = tegra_fb_get_tiling(state->fb, tiling);
642 if (err < 0)
643 return err;
644
645 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
646 !dc->soc->supports_block_linear) {
647 DRM_ERROR("hardware doesn't support block linear mode\n");
648 return -EINVAL;
649 }
650
651 /*
652 * Older userspace used custom BO flag in order to specify the Y
653 * reflection, while modern userspace uses the generic DRM rotation
654 * property in order to achieve the same result. The legacy BO flag
655 * duplicates the DRM rotation property when both are set.
656 */
657 if (tegra_fb_is_bottom_up(state->fb))
658 rotation |= DRM_MODE_REFLECT_Y;
659
660 rotation = drm_rotation_simplify(rotation, supported_rotation);
661
662 if (rotation & DRM_MODE_REFLECT_X)
663 plane_state->reflect_x = true;
664 else
665 plane_state->reflect_x = false;
666
667 if (rotation & DRM_MODE_REFLECT_Y)
668 plane_state->reflect_y = true;
669 else
670 plane_state->reflect_y = false;
671
672 /*
673 * Tegra doesn't support different strides for U and V planes so we
674 * error out if the user tries to display a framebuffer with such a
675 * configuration.
676 */
677 if (state->fb->format->num_planes > 2) {
678 if (state->fb->pitches[2] != state->fb->pitches[1]) {
679 DRM_ERROR("unsupported UV-plane configuration\n");
680 return -EINVAL;
681 }
682 }
683
684 err = tegra_plane_state_add(tegra, state);
685 if (err < 0)
686 return err;
687
688 return 0;
689 }
690
691 static void tegra_plane_atomic_disable(struct drm_plane *plane,
692 struct drm_plane_state *old_state)
693 {
694 struct tegra_plane *p = to_tegra_plane(plane);
695 u32 value;
696
697 /* rien ne va plus */
698 if (!old_state || !old_state->crtc)
699 return;
700
701 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
702 value &= ~WIN_ENABLE;
703 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
704 }
705
706 static void tegra_plane_atomic_update(struct drm_plane *plane,
707 struct drm_plane_state *old_state)
708 {
709 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
710 struct drm_framebuffer *fb = plane->state->fb;
711 struct tegra_plane *p = to_tegra_plane(plane);
712 struct tegra_dc_window window;
713 unsigned int i;
714
715 /* rien ne va plus */
716 if (!plane->state->crtc || !plane->state->fb)
717 return;
718
719 if (!plane->state->visible)
720 return tegra_plane_atomic_disable(plane, old_state);
721
722 memset(&window, 0, sizeof(window));
723 window.src.x = plane->state->src.x1 >> 16;
724 window.src.y = plane->state->src.y1 >> 16;
725 window.src.w = drm_rect_width(&plane->state->src) >> 16;
726 window.src.h = drm_rect_height(&plane->state->src) >> 16;
727 window.dst.x = plane->state->dst.x1;
728 window.dst.y = plane->state->dst.y1;
729 window.dst.w = drm_rect_width(&plane->state->dst);
730 window.dst.h = drm_rect_height(&plane->state->dst);
731 window.bits_per_pixel = fb->format->cpp[0] * 8;
732 window.reflect_x = state->reflect_x;
733 window.reflect_y = state->reflect_y;
734
735 /* copy from state */
736 window.zpos = plane->state->normalized_zpos;
737 window.tiling = state->tiling;
738 window.format = state->format;
739 window.swap = state->swap;
740
741 for (i = 0; i < fb->format->num_planes; i++) {
742 window.base[i] = state->iova[i] + fb->offsets[i];
743
744 /*
745 * Tegra uses a shared stride for UV planes. Framebuffers are
746 * already checked for this in the tegra_plane_atomic_check()
747 * function, so it's safe to ignore the V-plane pitch here.
748 */
749 if (i < 2)
750 window.stride[i] = fb->pitches[i];
751 }
752
753 tegra_dc_setup_window(p, &window);
754 }
755
756 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
757 .prepare_fb = tegra_plane_prepare_fb,
758 .cleanup_fb = tegra_plane_cleanup_fb,
759 .atomic_check = tegra_plane_atomic_check,
760 .atomic_disable = tegra_plane_atomic_disable,
761 .atomic_update = tegra_plane_atomic_update,
762 };
763
764 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
765 {
766 /*
767 * Ideally this would use drm_crtc_mask(), but that would require the
768 * CRTC to already be in the mode_config's list of CRTCs. However, it
769 * will only be added to that list in the drm_crtc_init_with_planes()
770 * (in tegra_dc_init()), which in turn requires registration of these
771 * planes. So we have ourselves a nice little chicken and egg problem
772 * here.
773 *
774 * We work around this by manually creating the mask from the number
775 * of CRTCs that have been registered, and should therefore always be
776 * the same as drm_crtc_index() after registration.
777 */
778 return 1 << drm->mode_config.num_crtc;
779 }
780
781 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
782 struct tegra_dc *dc)
783 {
784 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
785 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
786 struct tegra_plane *plane;
787 unsigned int num_formats;
788 const u64 *modifiers;
789 const u32 *formats;
790 int err;
791
792 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
793 if (!plane)
794 return ERR_PTR(-ENOMEM);
795
796 /* Always use window A as primary window */
797 plane->offset = 0xa00;
798 plane->index = 0;
799 plane->dc = dc;
800
801 num_formats = dc->soc->num_primary_formats;
802 formats = dc->soc->primary_formats;
803 modifiers = dc->soc->modifiers;
804
805 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
806 &tegra_plane_funcs, formats,
807 num_formats, modifiers, type, NULL);
808 if (err < 0) {
809 kfree(plane);
810 return ERR_PTR(err);
811 }
812
813 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
814 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
815
816 err = drm_plane_create_rotation_property(&plane->base,
817 DRM_MODE_ROTATE_0,
818 DRM_MODE_ROTATE_0 |
819 DRM_MODE_ROTATE_180 |
820 DRM_MODE_REFLECT_X |
821 DRM_MODE_REFLECT_Y);
822 if (err < 0)
823 dev_err(dc->dev, "failed to create rotation property: %d\n",
824 err);
825
826 return &plane->base;
827 }
828
829 static const u32 tegra_cursor_plane_formats[] = {
830 DRM_FORMAT_RGBA8888,
831 };
832
833 static int tegra_cursor_atomic_check(struct drm_plane *plane,
834 struct drm_plane_state *state)
835 {
836 struct tegra_plane *tegra = to_tegra_plane(plane);
837 int err;
838
839 /* no need for further checks if the plane is being disabled */
840 if (!state->crtc)
841 return 0;
842
843 /* scaling not supported for cursor */
844 if ((state->src_w >> 16 != state->crtc_w) ||
845 (state->src_h >> 16 != state->crtc_h))
846 return -EINVAL;
847
848 /* only square cursors supported */
849 if (state->src_w != state->src_h)
850 return -EINVAL;
851
852 if (state->crtc_w != 32 && state->crtc_w != 64 &&
853 state->crtc_w != 128 && state->crtc_w != 256)
854 return -EINVAL;
855
856 err = tegra_plane_state_add(tegra, state);
857 if (err < 0)
858 return err;
859
860 return 0;
861 }
862
863 static void tegra_cursor_atomic_update(struct drm_plane *plane,
864 struct drm_plane_state *old_state)
865 {
866 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
867 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
868 u32 value = CURSOR_CLIP_DISPLAY;
869
870 /* rien ne va plus */
871 if (!plane->state->crtc || !plane->state->fb)
872 return;
873
874 switch (plane->state->crtc_w) {
875 case 32:
876 value |= CURSOR_SIZE_32x32;
877 break;
878
879 case 64:
880 value |= CURSOR_SIZE_64x64;
881 break;
882
883 case 128:
884 value |= CURSOR_SIZE_128x128;
885 break;
886
887 case 256:
888 value |= CURSOR_SIZE_256x256;
889 break;
890
891 default:
892 WARN(1, "cursor size %ux%u not supported\n",
893 plane->state->crtc_w, plane->state->crtc_h);
894 return;
895 }
896
897 value |= (state->iova[0] >> 10) & 0x3fffff;
898 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
899
900 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
901 value = (state->iova[0] >> 32) & 0x3;
902 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
903 #endif
904
905 /* enable cursor and set blend mode */
906 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
907 value |= CURSOR_ENABLE;
908 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
909
910 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
911 value &= ~CURSOR_DST_BLEND_MASK;
912 value &= ~CURSOR_SRC_BLEND_MASK;
913 value |= CURSOR_MODE_NORMAL;
914 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
915 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
916 value |= CURSOR_ALPHA;
917 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
918
919 /* position the cursor */
920 value = (plane->state->crtc_y & 0x3fff) << 16 |
921 (plane->state->crtc_x & 0x3fff);
922 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
923 }
924
925 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
926 struct drm_plane_state *old_state)
927 {
928 struct tegra_dc *dc;
929 u32 value;
930
931 /* rien ne va plus */
932 if (!old_state || !old_state->crtc)
933 return;
934
935 dc = to_tegra_dc(old_state->crtc);
936
937 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
938 value &= ~CURSOR_ENABLE;
939 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
940 }
941
942 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
943 .prepare_fb = tegra_plane_prepare_fb,
944 .cleanup_fb = tegra_plane_cleanup_fb,
945 .atomic_check = tegra_cursor_atomic_check,
946 .atomic_update = tegra_cursor_atomic_update,
947 .atomic_disable = tegra_cursor_atomic_disable,
948 };
949
950 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
951 struct tegra_dc *dc)
952 {
953 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
954 struct tegra_plane *plane;
955 unsigned int num_formats;
956 const u32 *formats;
957 int err;
958
959 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
960 if (!plane)
961 return ERR_PTR(-ENOMEM);
962
963 /*
964 * This index is kind of fake. The cursor isn't a regular plane, but
965 * its update and activation request bits in DC_CMD_STATE_CONTROL do
966 * use the same programming. Setting this fake index here allows the
967 * code in tegra_add_plane_state() to do the right thing without the
968 * need to special-casing the cursor plane.
969 */
970 plane->index = 6;
971 plane->dc = dc;
972
973 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
974 formats = tegra_cursor_plane_formats;
975
976 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
977 &tegra_plane_funcs, formats,
978 num_formats, NULL,
979 DRM_PLANE_TYPE_CURSOR, NULL);
980 if (err < 0) {
981 kfree(plane);
982 return ERR_PTR(err);
983 }
984
985 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
986 drm_plane_create_zpos_immutable_property(&plane->base, 255);
987
988 return &plane->base;
989 }
990
991 static const u32 tegra20_overlay_formats[] = {
992 DRM_FORMAT_ARGB4444,
993 DRM_FORMAT_ARGB1555,
994 DRM_FORMAT_RGB565,
995 DRM_FORMAT_RGBA5551,
996 DRM_FORMAT_ABGR8888,
997 DRM_FORMAT_ARGB8888,
998 /* non-native formats */
999 DRM_FORMAT_XRGB1555,
1000 DRM_FORMAT_RGBX5551,
1001 DRM_FORMAT_XBGR8888,
1002 DRM_FORMAT_XRGB8888,
1003 /* planar formats */
1004 DRM_FORMAT_UYVY,
1005 DRM_FORMAT_YUYV,
1006 DRM_FORMAT_YUV420,
1007 DRM_FORMAT_YUV422,
1008 };
1009
1010 static const u32 tegra114_overlay_formats[] = {
1011 DRM_FORMAT_ARGB4444,
1012 DRM_FORMAT_ARGB1555,
1013 DRM_FORMAT_RGB565,
1014 DRM_FORMAT_RGBA5551,
1015 DRM_FORMAT_ABGR8888,
1016 DRM_FORMAT_ARGB8888,
1017 /* new on Tegra114 */
1018 DRM_FORMAT_ABGR4444,
1019 DRM_FORMAT_ABGR1555,
1020 DRM_FORMAT_BGRA5551,
1021 DRM_FORMAT_XRGB1555,
1022 DRM_FORMAT_RGBX5551,
1023 DRM_FORMAT_XBGR1555,
1024 DRM_FORMAT_BGRX5551,
1025 DRM_FORMAT_BGR565,
1026 DRM_FORMAT_BGRA8888,
1027 DRM_FORMAT_RGBA8888,
1028 DRM_FORMAT_XRGB8888,
1029 DRM_FORMAT_XBGR8888,
1030 /* planar formats */
1031 DRM_FORMAT_UYVY,
1032 DRM_FORMAT_YUYV,
1033 DRM_FORMAT_YUV420,
1034 DRM_FORMAT_YUV422,
1035 };
1036
1037 static const u32 tegra124_overlay_formats[] = {
1038 DRM_FORMAT_ARGB4444,
1039 DRM_FORMAT_ARGB1555,
1040 DRM_FORMAT_RGB565,
1041 DRM_FORMAT_RGBA5551,
1042 DRM_FORMAT_ABGR8888,
1043 DRM_FORMAT_ARGB8888,
1044 /* new on Tegra114 */
1045 DRM_FORMAT_ABGR4444,
1046 DRM_FORMAT_ABGR1555,
1047 DRM_FORMAT_BGRA5551,
1048 DRM_FORMAT_XRGB1555,
1049 DRM_FORMAT_RGBX5551,
1050 DRM_FORMAT_XBGR1555,
1051 DRM_FORMAT_BGRX5551,
1052 DRM_FORMAT_BGR565,
1053 DRM_FORMAT_BGRA8888,
1054 DRM_FORMAT_RGBA8888,
1055 DRM_FORMAT_XRGB8888,
1056 DRM_FORMAT_XBGR8888,
1057 /* new on Tegra124 */
1058 DRM_FORMAT_RGBX8888,
1059 DRM_FORMAT_BGRX8888,
1060 /* planar formats */
1061 DRM_FORMAT_UYVY,
1062 DRM_FORMAT_YUYV,
1063 DRM_FORMAT_YUV420,
1064 DRM_FORMAT_YUV422,
1065 };
1066
1067 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1068 struct tegra_dc *dc,
1069 unsigned int index,
1070 bool cursor)
1071 {
1072 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1073 struct tegra_plane *plane;
1074 unsigned int num_formats;
1075 enum drm_plane_type type;
1076 const u32 *formats;
1077 int err;
1078
1079 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1080 if (!plane)
1081 return ERR_PTR(-ENOMEM);
1082
1083 plane->offset = 0xa00 + 0x200 * index;
1084 plane->index = index;
1085 plane->dc = dc;
1086
1087 num_formats = dc->soc->num_overlay_formats;
1088 formats = dc->soc->overlay_formats;
1089
1090 if (!cursor)
1091 type = DRM_PLANE_TYPE_OVERLAY;
1092 else
1093 type = DRM_PLANE_TYPE_CURSOR;
1094
1095 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1096 &tegra_plane_funcs, formats,
1097 num_formats, NULL, type, NULL);
1098 if (err < 0) {
1099 kfree(plane);
1100 return ERR_PTR(err);
1101 }
1102
1103 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1104 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1105
1106 err = drm_plane_create_rotation_property(&plane->base,
1107 DRM_MODE_ROTATE_0,
1108 DRM_MODE_ROTATE_0 |
1109 DRM_MODE_ROTATE_180 |
1110 DRM_MODE_REFLECT_X |
1111 DRM_MODE_REFLECT_Y);
1112 if (err < 0)
1113 dev_err(dc->dev, "failed to create rotation property: %d\n",
1114 err);
1115
1116 return &plane->base;
1117 }
1118
1119 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1120 struct tegra_dc *dc)
1121 {
1122 struct drm_plane *plane, *primary = NULL;
1123 unsigned int i, j;
1124
1125 for (i = 0; i < dc->soc->num_wgrps; i++) {
1126 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1127
1128 if (wgrp->dc == dc->pipe) {
1129 for (j = 0; j < wgrp->num_windows; j++) {
1130 unsigned int index = wgrp->windows[j];
1131
1132 plane = tegra_shared_plane_create(drm, dc,
1133 wgrp->index,
1134 index);
1135 if (IS_ERR(plane))
1136 return plane;
1137
1138 /*
1139 * Choose the first shared plane owned by this
1140 * head as the primary plane.
1141 */
1142 if (!primary) {
1143 plane->type = DRM_PLANE_TYPE_PRIMARY;
1144 primary = plane;
1145 }
1146 }
1147 }
1148 }
1149
1150 return primary;
1151 }
1152
1153 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1154 struct tegra_dc *dc)
1155 {
1156 struct drm_plane *planes[2], *primary;
1157 unsigned int planes_num;
1158 unsigned int i;
1159 int err;
1160
1161 primary = tegra_primary_plane_create(drm, dc);
1162 if (IS_ERR(primary))
1163 return primary;
1164
1165 if (dc->soc->supports_cursor)
1166 planes_num = 2;
1167 else
1168 planes_num = 1;
1169
1170 for (i = 0; i < planes_num; i++) {
1171 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1172 false);
1173 if (IS_ERR(planes[i])) {
1174 err = PTR_ERR(planes[i]);
1175
1176 while (i--)
1177 tegra_plane_funcs.destroy(planes[i]);
1178
1179 tegra_plane_funcs.destroy(primary);
1180 return ERR_PTR(err);
1181 }
1182 }
1183
1184 return primary;
1185 }
1186
1187 static void tegra_dc_destroy(struct drm_crtc *crtc)
1188 {
1189 drm_crtc_cleanup(crtc);
1190 }
1191
1192 static void tegra_crtc_reset(struct drm_crtc *crtc)
1193 {
1194 struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
1195
1196 if (crtc->state)
1197 tegra_crtc_atomic_destroy_state(crtc, crtc->state);
1198
1199 __drm_atomic_helper_crtc_reset(crtc, &state->base);
1200 }
1201
1202 static struct drm_crtc_state *
1203 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1204 {
1205 struct tegra_dc_state *state = to_dc_state(crtc->state);
1206 struct tegra_dc_state *copy;
1207
1208 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1209 if (!copy)
1210 return NULL;
1211
1212 __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1213 copy->clk = state->clk;
1214 copy->pclk = state->pclk;
1215 copy->div = state->div;
1216 copy->planes = state->planes;
1217
1218 return &copy->base;
1219 }
1220
1221 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1222 struct drm_crtc_state *state)
1223 {
1224 __drm_atomic_helper_crtc_destroy_state(state);
1225 kfree(state);
1226 }
1227
1228 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1229
1230 static const struct debugfs_reg32 tegra_dc_regs[] = {
1231 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1232 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1233 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1234 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1235 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1236 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1237 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1238 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1239 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1240 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1241 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1242 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1243 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1244 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1245 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1246 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1247 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1248 DEBUGFS_REG32(DC_CMD_INT_STATUS),
1249 DEBUGFS_REG32(DC_CMD_INT_MASK),
1250 DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1251 DEBUGFS_REG32(DC_CMD_INT_TYPE),
1252 DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1253 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1254 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1255 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1256 DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1257 DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1258 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1259 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1260 DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1261 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1262 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1263 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1264 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1265 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1266 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1267 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1268 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1269 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1270 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1271 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1272 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1273 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1274 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1275 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1276 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1277 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1278 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1279 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1280 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1281 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1282 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1283 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1284 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1285 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1286 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1287 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1288 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1289 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1290 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1291 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1292 DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1293 DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1294 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1295 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1296 DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1297 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1298 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1299 DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1300 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1301 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1302 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1303 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1304 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1305 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1306 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1307 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1308 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1309 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1310 DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1311 DEBUGFS_REG32(DC_DISP_ACTIVE),
1312 DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1313 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1314 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1315 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1316 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1317 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1318 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1319 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1320 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1321 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1322 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1323 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1324 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1325 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1326 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1327 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1328 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1329 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1330 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1331 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1332 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1333 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1334 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1335 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1336 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1337 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1338 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1339 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1340 DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1341 DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1342 DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1343 DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1344 DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1345 DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1346 DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1347 DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1348 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1349 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1350 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1351 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1352 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1353 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1354 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1355 DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1356 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1357 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1358 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1359 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1360 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1361 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1362 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1363 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1364 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1365 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1366 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1367 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1368 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1369 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1370 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1371 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1372 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1373 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1374 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1375 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1376 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1377 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1378 DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1379 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1380 DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1381 DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1382 DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1383 DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1384 DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1385 DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1386 DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1387 DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1388 DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1389 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1390 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1391 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1392 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1393 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1394 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1395 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1396 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1397 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1398 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1399 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1400 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1401 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1402 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1403 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1404 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1405 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1406 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1407 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1408 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1409 DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1410 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1411 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1412 DEBUGFS_REG32(DC_WIN_POSITION),
1413 DEBUGFS_REG32(DC_WIN_SIZE),
1414 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1415 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1416 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1417 DEBUGFS_REG32(DC_WIN_DDA_INC),
1418 DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1419 DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1420 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1421 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1422 DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1423 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1424 DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1425 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1426 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1427 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1428 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1429 DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1430 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1431 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1432 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1433 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1434 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1435 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1436 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1437 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1438 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1439 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1440 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1441 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1442 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1443 };
1444
1445 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1446 {
1447 struct drm_info_node *node = s->private;
1448 struct tegra_dc *dc = node->info_ent->data;
1449 unsigned int i;
1450 int err = 0;
1451
1452 drm_modeset_lock(&dc->base.mutex, NULL);
1453
1454 if (!dc->base.state->active) {
1455 err = -EBUSY;
1456 goto unlock;
1457 }
1458
1459 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1460 unsigned int offset = tegra_dc_regs[i].offset;
1461
1462 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1463 offset, tegra_dc_readl(dc, offset));
1464 }
1465
1466 unlock:
1467 drm_modeset_unlock(&dc->base.mutex);
1468 return err;
1469 }
1470
1471 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1472 {
1473 struct drm_info_node *node = s->private;
1474 struct tegra_dc *dc = node->info_ent->data;
1475 int err = 0;
1476 u32 value;
1477
1478 drm_modeset_lock(&dc->base.mutex, NULL);
1479
1480 if (!dc->base.state->active) {
1481 err = -EBUSY;
1482 goto unlock;
1483 }
1484
1485 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1486 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1487 tegra_dc_commit(dc);
1488
1489 drm_crtc_wait_one_vblank(&dc->base);
1490 drm_crtc_wait_one_vblank(&dc->base);
1491
1492 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1493 seq_printf(s, "%08x\n", value);
1494
1495 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1496
1497 unlock:
1498 drm_modeset_unlock(&dc->base.mutex);
1499 return err;
1500 }
1501
1502 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1503 {
1504 struct drm_info_node *node = s->private;
1505 struct tegra_dc *dc = node->info_ent->data;
1506
1507 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1508 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1509 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1510 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1511
1512 return 0;
1513 }
1514
1515 static struct drm_info_list debugfs_files[] = {
1516 { "regs", tegra_dc_show_regs, 0, NULL },
1517 { "crc", tegra_dc_show_crc, 0, NULL },
1518 { "stats", tegra_dc_show_stats, 0, NULL },
1519 };
1520
1521 static int tegra_dc_late_register(struct drm_crtc *crtc)
1522 {
1523 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1524 struct drm_minor *minor = crtc->dev->primary;
1525 struct dentry *root;
1526 struct tegra_dc *dc = to_tegra_dc(crtc);
1527
1528 #ifdef CONFIG_DEBUG_FS
1529 root = crtc->debugfs_entry;
1530 #else
1531 root = NULL;
1532 #endif
1533
1534 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1535 GFP_KERNEL);
1536 if (!dc->debugfs_files)
1537 return -ENOMEM;
1538
1539 for (i = 0; i < count; i++)
1540 dc->debugfs_files[i].data = dc;
1541
1542 drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1543
1544 return 0;
1545 }
1546
1547 static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1548 {
1549 unsigned int count = ARRAY_SIZE(debugfs_files);
1550 struct drm_minor *minor = crtc->dev->primary;
1551 struct tegra_dc *dc = to_tegra_dc(crtc);
1552
1553 drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1554 kfree(dc->debugfs_files);
1555 dc->debugfs_files = NULL;
1556 }
1557
1558 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1559 {
1560 struct tegra_dc *dc = to_tegra_dc(crtc);
1561
1562 /* XXX vblank syncpoints don't work with nvdisplay yet */
1563 if (dc->syncpt && !dc->soc->has_nvdisplay)
1564 return host1x_syncpt_read(dc->syncpt);
1565
1566 /* fallback to software emulated VBLANK counter */
1567 return (u32)drm_crtc_vblank_count(&dc->base);
1568 }
1569
1570 static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1571 {
1572 struct tegra_dc *dc = to_tegra_dc(crtc);
1573 u32 value;
1574
1575 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1576 value |= VBLANK_INT;
1577 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1578
1579 return 0;
1580 }
1581
1582 static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1583 {
1584 struct tegra_dc *dc = to_tegra_dc(crtc);
1585 u32 value;
1586
1587 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1588 value &= ~VBLANK_INT;
1589 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1590 }
1591
1592 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1593 .page_flip = drm_atomic_helper_page_flip,
1594 .set_config = drm_atomic_helper_set_config,
1595 .destroy = tegra_dc_destroy,
1596 .reset = tegra_crtc_reset,
1597 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1598 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1599 .late_register = tegra_dc_late_register,
1600 .early_unregister = tegra_dc_early_unregister,
1601 .get_vblank_counter = tegra_dc_get_vblank_counter,
1602 .enable_vblank = tegra_dc_enable_vblank,
1603 .disable_vblank = tegra_dc_disable_vblank,
1604 };
1605
1606 static int tegra_dc_set_timings(struct tegra_dc *dc,
1607 struct drm_display_mode *mode)
1608 {
1609 unsigned int h_ref_to_sync = 1;
1610 unsigned int v_ref_to_sync = 1;
1611 unsigned long value;
1612
1613 if (!dc->soc->has_nvdisplay) {
1614 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1615
1616 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1617 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1618 }
1619
1620 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1621 ((mode->hsync_end - mode->hsync_start) << 0);
1622 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1623
1624 value = ((mode->vtotal - mode->vsync_end) << 16) |
1625 ((mode->htotal - mode->hsync_end) << 0);
1626 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1627
1628 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1629 ((mode->hsync_start - mode->hdisplay) << 0);
1630 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1631
1632 value = (mode->vdisplay << 16) | mode->hdisplay;
1633 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1634
1635 return 0;
1636 }
1637
1638 /**
1639 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1640 * state
1641 * @dc: display controller
1642 * @crtc_state: CRTC atomic state
1643 * @clk: parent clock for display controller
1644 * @pclk: pixel clock
1645 * @div: shift clock divider
1646 *
1647 * Returns:
1648 * 0 on success or a negative error-code on failure.
1649 */
1650 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1651 struct drm_crtc_state *crtc_state,
1652 struct clk *clk, unsigned long pclk,
1653 unsigned int div)
1654 {
1655 struct tegra_dc_state *state = to_dc_state(crtc_state);
1656
1657 if (!clk_has_parent(dc->clk, clk))
1658 return -EINVAL;
1659
1660 state->clk = clk;
1661 state->pclk = pclk;
1662 state->div = div;
1663
1664 return 0;
1665 }
1666
1667 static void tegra_dc_commit_state(struct tegra_dc *dc,
1668 struct tegra_dc_state *state)
1669 {
1670 u32 value;
1671 int err;
1672
1673 err = clk_set_parent(dc->clk, state->clk);
1674 if (err < 0)
1675 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1676
1677 /*
1678 * Outputs may not want to change the parent clock rate. This is only
1679 * relevant to Tegra20 where only a single display PLL is available.
1680 * Since that PLL would typically be used for HDMI, an internal LVDS
1681 * panel would need to be driven by some other clock such as PLL_P
1682 * which is shared with other peripherals. Changing the clock rate
1683 * should therefore be avoided.
1684 */
1685 if (state->pclk > 0) {
1686 err = clk_set_rate(state->clk, state->pclk);
1687 if (err < 0)
1688 dev_err(dc->dev,
1689 "failed to set clock rate to %lu Hz\n",
1690 state->pclk);
1691 }
1692
1693 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1694 state->div);
1695 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1696
1697 if (!dc->soc->has_nvdisplay) {
1698 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1699 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1700 }
1701
1702 err = clk_set_rate(dc->clk, state->pclk);
1703 if (err < 0)
1704 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1705 dc->clk, state->pclk, err);
1706 }
1707
1708 static void tegra_dc_stop(struct tegra_dc *dc)
1709 {
1710 u32 value;
1711
1712 /* stop the display controller */
1713 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1714 value &= ~DISP_CTRL_MODE_MASK;
1715 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1716
1717 tegra_dc_commit(dc);
1718 }
1719
1720 static bool tegra_dc_idle(struct tegra_dc *dc)
1721 {
1722 u32 value;
1723
1724 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1725
1726 return (value & DISP_CTRL_MODE_MASK) == 0;
1727 }
1728
1729 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1730 {
1731 timeout = jiffies + msecs_to_jiffies(timeout);
1732
1733 while (time_before(jiffies, timeout)) {
1734 if (tegra_dc_idle(dc))
1735 return 0;
1736
1737 usleep_range(1000, 2000);
1738 }
1739
1740 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1741 return -ETIMEDOUT;
1742 }
1743
1744 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1745 struct drm_atomic_state *state)
1746 {
1747 struct tegra_dc *dc = to_tegra_dc(crtc);
1748 u32 value;
1749 int err;
1750
1751 if (!tegra_dc_idle(dc)) {
1752 tegra_dc_stop(dc);
1753
1754 /*
1755 * Ignore the return value, there isn't anything useful to do
1756 * in case this fails.
1757 */
1758 tegra_dc_wait_idle(dc, 100);
1759 }
1760
1761 /*
1762 * This should really be part of the RGB encoder driver, but clearing
1763 * these bits has the side-effect of stopping the display controller.
1764 * When that happens no VBLANK interrupts will be raised. At the same
1765 * time the encoder is disabled before the display controller, so the
1766 * above code is always going to timeout waiting for the controller
1767 * to go idle.
1768 *
1769 * Given the close coupling between the RGB encoder and the display
1770 * controller doing it here is still kind of okay. None of the other
1771 * encoder drivers require these bits to be cleared.
1772 *
1773 * XXX: Perhaps given that the display controller is switched off at
1774 * this point anyway maybe clearing these bits isn't even useful for
1775 * the RGB encoder?
1776 */
1777 if (dc->rgb) {
1778 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1779 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1780 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1781 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1782 }
1783
1784 tegra_dc_stats_reset(&dc->stats);
1785 drm_crtc_vblank_off(crtc);
1786
1787 spin_lock_irq(&crtc->dev->event_lock);
1788
1789 if (crtc->state->event) {
1790 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1791 crtc->state->event = NULL;
1792 }
1793
1794 spin_unlock_irq(&crtc->dev->event_lock);
1795
1796 err = host1x_client_suspend(&dc->client);
1797 if (err < 0)
1798 dev_err(dc->dev, "failed to suspend: %d\n", err);
1799 }
1800
1801 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1802 struct drm_atomic_state *state)
1803 {
1804 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1805 struct tegra_dc_state *crtc_state = to_dc_state(crtc->state);
1806 struct tegra_dc *dc = to_tegra_dc(crtc);
1807 u32 value;
1808 int err;
1809
1810 err = host1x_client_resume(&dc->client);
1811 if (err < 0) {
1812 dev_err(dc->dev, "failed to resume: %d\n", err);
1813 return;
1814 }
1815
1816 /* initialize display controller */
1817 if (dc->syncpt) {
1818 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
1819
1820 if (dc->soc->has_nvdisplay)
1821 enable = 1 << 31;
1822 else
1823 enable = 1 << 8;
1824
1825 value = SYNCPT_CNTRL_NO_STALL;
1826 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1827
1828 value = enable | syncpt;
1829 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1830 }
1831
1832 if (dc->soc->has_nvdisplay) {
1833 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1834 DSC_OBUF_UF_INT;
1835 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1836
1837 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1838 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
1839 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
1840 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
1841 VBLANK_INT | FRAME_END_INT;
1842 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1843
1844 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1845 FRAME_END_INT;
1846 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1847
1848 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1849 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1850
1851 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
1852 } else {
1853 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1854 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1855 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1856
1857 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1858 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1859 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1860
1861 /* initialize timer */
1862 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1863 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1864 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1865
1866 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1867 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1868 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1869
1870 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1871 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1872 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1873
1874 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1875 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1876 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1877 }
1878
1879 if (dc->soc->supports_background_color)
1880 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
1881 else
1882 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1883
1884 /* apply PLL and pixel clock changes */
1885 tegra_dc_commit_state(dc, crtc_state);
1886
1887 /* program display mode */
1888 tegra_dc_set_timings(dc, mode);
1889
1890 /* interlacing isn't supported yet, so disable it */
1891 if (dc->soc->supports_interlacing) {
1892 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1893 value &= ~INTERLACE_ENABLE;
1894 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1895 }
1896
1897 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1898 value &= ~DISP_CTRL_MODE_MASK;
1899 value |= DISP_CTRL_MODE_C_DISPLAY;
1900 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1901
1902 if (!dc->soc->has_nvdisplay) {
1903 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1904 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1905 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1906 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1907 }
1908
1909 /* enable underflow reporting and display red for missing pixels */
1910 if (dc->soc->has_nvdisplay) {
1911 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1912 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1913 }
1914
1915 tegra_dc_commit(dc);
1916
1917 drm_crtc_vblank_on(crtc);
1918 }
1919
1920 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1921 struct drm_atomic_state *state)
1922 {
1923 unsigned long flags;
1924
1925 if (crtc->state->event) {
1926 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1927
1928 if (drm_crtc_vblank_get(crtc) != 0)
1929 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1930 else
1931 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
1932
1933 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1934
1935 crtc->state->event = NULL;
1936 }
1937 }
1938
1939 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1940 struct drm_atomic_state *state)
1941 {
1942 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1943 crtc);
1944 struct tegra_dc_state *dc_state = to_dc_state(crtc_state);
1945 struct tegra_dc *dc = to_tegra_dc(crtc);
1946 u32 value;
1947
1948 value = dc_state->planes << 8 | GENERAL_UPDATE;
1949 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1950 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1951
1952 value = dc_state->planes | GENERAL_ACT_REQ;
1953 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1954 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1955 }
1956
1957 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1958 .atomic_begin = tegra_crtc_atomic_begin,
1959 .atomic_flush = tegra_crtc_atomic_flush,
1960 .atomic_enable = tegra_crtc_atomic_enable,
1961 .atomic_disable = tegra_crtc_atomic_disable,
1962 };
1963
1964 static irqreturn_t tegra_dc_irq(int irq, void *data)
1965 {
1966 struct tegra_dc *dc = data;
1967 unsigned long status;
1968
1969 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1970 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1971
1972 if (status & FRAME_END_INT) {
1973 /*
1974 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1975 */
1976 dc->stats.frames++;
1977 }
1978
1979 if (status & VBLANK_INT) {
1980 /*
1981 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1982 */
1983 drm_crtc_handle_vblank(&dc->base);
1984 dc->stats.vblank++;
1985 }
1986
1987 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1988 /*
1989 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1990 */
1991 dc->stats.underflow++;
1992 }
1993
1994 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1995 /*
1996 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1997 */
1998 dc->stats.overflow++;
1999 }
2000
2001 if (status & HEAD_UF_INT) {
2002 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
2003 dc->stats.underflow++;
2004 }
2005
2006 return IRQ_HANDLED;
2007 }
2008
2009 static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
2010 {
2011 unsigned int i;
2012
2013 if (!dc->soc->wgrps)
2014 return true;
2015
2016 for (i = 0; i < dc->soc->num_wgrps; i++) {
2017 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
2018
2019 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
2020 return true;
2021 }
2022
2023 return false;
2024 }
2025
2026 static int tegra_dc_init(struct host1x_client *client)
2027 {
2028 struct drm_device *drm = dev_get_drvdata(client->host);
2029 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
2030 struct tegra_dc *dc = host1x_client_to_dc(client);
2031 struct tegra_drm *tegra = drm->dev_private;
2032 struct drm_plane *primary = NULL;
2033 struct drm_plane *cursor = NULL;
2034 int err;
2035
2036 /*
2037 * XXX do not register DCs with no window groups because we cannot
2038 * assign a primary plane to them, which in turn will cause KMS to
2039 * crash.
2040 */
2041 if (!tegra_dc_has_window_groups(dc))
2042 return 0;
2043
2044 /*
2045 * Set the display hub as the host1x client parent for the display
2046 * controller. This is needed for the runtime reference counting that
2047 * ensures the display hub is always powered when any of the display
2048 * controllers are.
2049 */
2050 if (dc->soc->has_nvdisplay)
2051 client->parent = &tegra->hub->client;
2052
2053 dc->syncpt = host1x_syncpt_request(client, flags);
2054 if (!dc->syncpt)
2055 dev_warn(dc->dev, "failed to allocate syncpoint\n");
2056
2057 err = host1x_client_iommu_attach(client);
2058 if (err < 0 && err != -ENODEV) {
2059 dev_err(client->dev, "failed to attach to domain: %d\n", err);
2060 return err;
2061 }
2062
2063 if (dc->soc->wgrps)
2064 primary = tegra_dc_add_shared_planes(drm, dc);
2065 else
2066 primary = tegra_dc_add_planes(drm, dc);
2067
2068 if (IS_ERR(primary)) {
2069 err = PTR_ERR(primary);
2070 goto cleanup;
2071 }
2072
2073 if (dc->soc->supports_cursor) {
2074 cursor = tegra_dc_cursor_plane_create(drm, dc);
2075 if (IS_ERR(cursor)) {
2076 err = PTR_ERR(cursor);
2077 goto cleanup;
2078 }
2079 } else {
2080 /* dedicate one overlay to mouse cursor */
2081 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2082 if (IS_ERR(cursor)) {
2083 err = PTR_ERR(cursor);
2084 goto cleanup;
2085 }
2086 }
2087
2088 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2089 &tegra_crtc_funcs, NULL);
2090 if (err < 0)
2091 goto cleanup;
2092
2093 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2094
2095 /*
2096 * Keep track of the minimum pitch alignment across all display
2097 * controllers.
2098 */
2099 if (dc->soc->pitch_align > tegra->pitch_align)
2100 tegra->pitch_align = dc->soc->pitch_align;
2101
2102 err = tegra_dc_rgb_init(drm, dc);
2103 if (err < 0 && err != -ENODEV) {
2104 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2105 goto cleanup;
2106 }
2107
2108 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2109 dev_name(dc->dev), dc);
2110 if (err < 0) {
2111 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2112 err);
2113 goto cleanup;
2114 }
2115
2116 /*
2117 * Inherit the DMA parameters (such as maximum segment size) from the
2118 * parent host1x device.
2119 */
2120 client->dev->dma_parms = client->host->dma_parms;
2121
2122 return 0;
2123
2124 cleanup:
2125 if (!IS_ERR_OR_NULL(cursor))
2126 drm_plane_cleanup(cursor);
2127
2128 if (!IS_ERR(primary))
2129 drm_plane_cleanup(primary);
2130
2131 host1x_client_iommu_detach(client);
2132 host1x_syncpt_free(dc->syncpt);
2133
2134 return err;
2135 }
2136
2137 static int tegra_dc_exit(struct host1x_client *client)
2138 {
2139 struct tegra_dc *dc = host1x_client_to_dc(client);
2140 int err;
2141
2142 if (!tegra_dc_has_window_groups(dc))
2143 return 0;
2144
2145 /* avoid a dangling pointer just in case this disappears */
2146 client->dev->dma_parms = NULL;
2147
2148 devm_free_irq(dc->dev, dc->irq, dc);
2149
2150 err = tegra_dc_rgb_exit(dc);
2151 if (err) {
2152 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2153 return err;
2154 }
2155
2156 host1x_client_iommu_detach(client);
2157 host1x_syncpt_free(dc->syncpt);
2158
2159 return 0;
2160 }
2161
2162 static int tegra_dc_runtime_suspend(struct host1x_client *client)
2163 {
2164 struct tegra_dc *dc = host1x_client_to_dc(client);
2165 struct device *dev = client->dev;
2166 int err;
2167
2168 err = reset_control_assert(dc->rst);
2169 if (err < 0) {
2170 dev_err(dev, "failed to assert reset: %d\n", err);
2171 return err;
2172 }
2173
2174 if (dc->soc->has_powergate)
2175 tegra_powergate_power_off(dc->powergate);
2176
2177 clk_disable_unprepare(dc->clk);
2178 pm_runtime_put_sync(dev);
2179
2180 return 0;
2181 }
2182
2183 static int tegra_dc_runtime_resume(struct host1x_client *client)
2184 {
2185 struct tegra_dc *dc = host1x_client_to_dc(client);
2186 struct device *dev = client->dev;
2187 int err;
2188
2189 err = pm_runtime_resume_and_get(dev);
2190 if (err < 0) {
2191 dev_err(dev, "failed to get runtime PM: %d\n", err);
2192 return err;
2193 }
2194
2195 if (dc->soc->has_powergate) {
2196 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2197 dc->rst);
2198 if (err < 0) {
2199 dev_err(dev, "failed to power partition: %d\n", err);
2200 goto put_rpm;
2201 }
2202 } else {
2203 err = clk_prepare_enable(dc->clk);
2204 if (err < 0) {
2205 dev_err(dev, "failed to enable clock: %d\n", err);
2206 goto put_rpm;
2207 }
2208
2209 err = reset_control_deassert(dc->rst);
2210 if (err < 0) {
2211 dev_err(dev, "failed to deassert reset: %d\n", err);
2212 goto disable_clk;
2213 }
2214 }
2215
2216 return 0;
2217
2218 disable_clk:
2219 clk_disable_unprepare(dc->clk);
2220 put_rpm:
2221 pm_runtime_put_sync(dev);
2222 return err;
2223 }
2224
2225 static const struct host1x_client_ops dc_client_ops = {
2226 .init = tegra_dc_init,
2227 .exit = tegra_dc_exit,
2228 .suspend = tegra_dc_runtime_suspend,
2229 .resume = tegra_dc_runtime_resume,
2230 };
2231
2232 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2233 .supports_background_color = false,
2234 .supports_interlacing = false,
2235 .supports_cursor = false,
2236 .supports_block_linear = false,
2237 .has_legacy_blending = true,
2238 .pitch_align = 8,
2239 .has_powergate = false,
2240 .coupled_pm = true,
2241 .has_nvdisplay = false,
2242 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2243 .primary_formats = tegra20_primary_formats,
2244 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2245 .overlay_formats = tegra20_overlay_formats,
2246 .modifiers = tegra20_modifiers,
2247 .has_win_a_without_filters = true,
2248 .has_win_c_without_vert_filter = true,
2249 };
2250
2251 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2252 .supports_background_color = false,
2253 .supports_interlacing = false,
2254 .supports_cursor = false,
2255 .supports_block_linear = false,
2256 .has_legacy_blending = true,
2257 .pitch_align = 8,
2258 .has_powergate = false,
2259 .coupled_pm = false,
2260 .has_nvdisplay = false,
2261 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2262 .primary_formats = tegra20_primary_formats,
2263 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2264 .overlay_formats = tegra20_overlay_formats,
2265 .modifiers = tegra20_modifiers,
2266 .has_win_a_without_filters = false,
2267 .has_win_c_without_vert_filter = false,
2268 };
2269
2270 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2271 .supports_background_color = false,
2272 .supports_interlacing = false,
2273 .supports_cursor = false,
2274 .supports_block_linear = false,
2275 .has_legacy_blending = true,
2276 .pitch_align = 64,
2277 .has_powergate = true,
2278 .coupled_pm = false,
2279 .has_nvdisplay = false,
2280 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2281 .primary_formats = tegra114_primary_formats,
2282 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2283 .overlay_formats = tegra114_overlay_formats,
2284 .modifiers = tegra20_modifiers,
2285 .has_win_a_without_filters = false,
2286 .has_win_c_without_vert_filter = false,
2287 };
2288
2289 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2290 .supports_background_color = true,
2291 .supports_interlacing = true,
2292 .supports_cursor = true,
2293 .supports_block_linear = true,
2294 .has_legacy_blending = false,
2295 .pitch_align = 64,
2296 .has_powergate = true,
2297 .coupled_pm = false,
2298 .has_nvdisplay = false,
2299 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2300 .primary_formats = tegra124_primary_formats,
2301 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2302 .overlay_formats = tegra124_overlay_formats,
2303 .modifiers = tegra124_modifiers,
2304 .has_win_a_without_filters = false,
2305 .has_win_c_without_vert_filter = false,
2306 };
2307
2308 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2309 .supports_background_color = true,
2310 .supports_interlacing = true,
2311 .supports_cursor = true,
2312 .supports_block_linear = true,
2313 .has_legacy_blending = false,
2314 .pitch_align = 64,
2315 .has_powergate = true,
2316 .coupled_pm = false,
2317 .has_nvdisplay = false,
2318 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2319 .primary_formats = tegra114_primary_formats,
2320 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2321 .overlay_formats = tegra114_overlay_formats,
2322 .modifiers = tegra124_modifiers,
2323 .has_win_a_without_filters = false,
2324 .has_win_c_without_vert_filter = false,
2325 };
2326
2327 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2328 {
2329 .index = 0,
2330 .dc = 0,
2331 .windows = (const unsigned int[]) { 0 },
2332 .num_windows = 1,
2333 }, {
2334 .index = 1,
2335 .dc = 1,
2336 .windows = (const unsigned int[]) { 1 },
2337 .num_windows = 1,
2338 }, {
2339 .index = 2,
2340 .dc = 1,
2341 .windows = (const unsigned int[]) { 2 },
2342 .num_windows = 1,
2343 }, {
2344 .index = 3,
2345 .dc = 2,
2346 .windows = (const unsigned int[]) { 3 },
2347 .num_windows = 1,
2348 }, {
2349 .index = 4,
2350 .dc = 2,
2351 .windows = (const unsigned int[]) { 4 },
2352 .num_windows = 1,
2353 }, {
2354 .index = 5,
2355 .dc = 2,
2356 .windows = (const unsigned int[]) { 5 },
2357 .num_windows = 1,
2358 },
2359 };
2360
2361 static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2362 .supports_background_color = true,
2363 .supports_interlacing = true,
2364 .supports_cursor = true,
2365 .supports_block_linear = true,
2366 .has_legacy_blending = false,
2367 .pitch_align = 64,
2368 .has_powergate = false,
2369 .coupled_pm = false,
2370 .has_nvdisplay = true,
2371 .wgrps = tegra186_dc_wgrps,
2372 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2373 };
2374
2375 static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
2376 {
2377 .index = 0,
2378 .dc = 0,
2379 .windows = (const unsigned int[]) { 0 },
2380 .num_windows = 1,
2381 }, {
2382 .index = 1,
2383 .dc = 1,
2384 .windows = (const unsigned int[]) { 1 },
2385 .num_windows = 1,
2386 }, {
2387 .index = 2,
2388 .dc = 1,
2389 .windows = (const unsigned int[]) { 2 },
2390 .num_windows = 1,
2391 }, {
2392 .index = 3,
2393 .dc = 2,
2394 .windows = (const unsigned int[]) { 3 },
2395 .num_windows = 1,
2396 }, {
2397 .index = 4,
2398 .dc = 2,
2399 .windows = (const unsigned int[]) { 4 },
2400 .num_windows = 1,
2401 }, {
2402 .index = 5,
2403 .dc = 2,
2404 .windows = (const unsigned int[]) { 5 },
2405 .num_windows = 1,
2406 },
2407 };
2408
2409 static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
2410 .supports_background_color = true,
2411 .supports_interlacing = true,
2412 .supports_cursor = true,
2413 .supports_block_linear = true,
2414 .has_legacy_blending = false,
2415 .pitch_align = 64,
2416 .has_powergate = false,
2417 .coupled_pm = false,
2418 .has_nvdisplay = true,
2419 .wgrps = tegra194_dc_wgrps,
2420 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
2421 };
2422
2423 static const struct of_device_id tegra_dc_of_match[] = {
2424 {
2425 .compatible = "nvidia,tegra194-dc",
2426 .data = &tegra194_dc_soc_info,
2427 }, {
2428 .compatible = "nvidia,tegra186-dc",
2429 .data = &tegra186_dc_soc_info,
2430 }, {
2431 .compatible = "nvidia,tegra210-dc",
2432 .data = &tegra210_dc_soc_info,
2433 }, {
2434 .compatible = "nvidia,tegra124-dc",
2435 .data = &tegra124_dc_soc_info,
2436 }, {
2437 .compatible = "nvidia,tegra114-dc",
2438 .data = &tegra114_dc_soc_info,
2439 }, {
2440 .compatible = "nvidia,tegra30-dc",
2441 .data = &tegra30_dc_soc_info,
2442 }, {
2443 .compatible = "nvidia,tegra20-dc",
2444 .data = &tegra20_dc_soc_info,
2445 }, {
2446 /* sentinel */
2447 }
2448 };
2449 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
2450
2451 static int tegra_dc_parse_dt(struct tegra_dc *dc)
2452 {
2453 struct device_node *np;
2454 u32 value = 0;
2455 int err;
2456
2457 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
2458 if (err < 0) {
2459 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
2460
2461 /*
2462 * If the nvidia,head property isn't present, try to find the
2463 * correct head number by looking up the position of this
2464 * display controller's node within the device tree. Assuming
2465 * that the nodes are ordered properly in the DTS file and
2466 * that the translation into a flattened device tree blob
2467 * preserves that ordering this will actually yield the right
2468 * head number.
2469 *
2470 * If those assumptions don't hold, this will still work for
2471 * cases where only a single display controller is used.
2472 */
2473 for_each_matching_node(np, tegra_dc_of_match) {
2474 if (np == dc->dev->of_node) {
2475 of_node_put(np);
2476 break;
2477 }
2478
2479 value++;
2480 }
2481 }
2482
2483 dc->pipe = value;
2484
2485 return 0;
2486 }
2487
2488 static int tegra_dc_match_by_pipe(struct device *dev, const void *data)
2489 {
2490 struct tegra_dc *dc = dev_get_drvdata(dev);
2491 unsigned int pipe = (unsigned long)(void *)data;
2492
2493 return dc->pipe == pipe;
2494 }
2495
2496 static int tegra_dc_couple(struct tegra_dc *dc)
2497 {
2498 /*
2499 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
2500 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
2501 * POWER_CONTROL registers during CRTC enabling.
2502 */
2503 if (dc->soc->coupled_pm && dc->pipe == 1) {
2504 u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_CONSUMER;
2505 struct device_link *link;
2506 struct device *partner;
2507
2508 partner = driver_find_device(dc->dev->driver, NULL, NULL,
2509 tegra_dc_match_by_pipe);
2510 if (!partner)
2511 return -EPROBE_DEFER;
2512
2513 link = device_link_add(dc->dev, partner, flags);
2514 if (!link) {
2515 dev_err(dc->dev, "failed to link controllers\n");
2516 return -EINVAL;
2517 }
2518
2519 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));
2520 }
2521
2522 return 0;
2523 }
2524
2525 static int tegra_dc_probe(struct platform_device *pdev)
2526 {
2527 struct tegra_dc *dc;
2528 int err;
2529
2530 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
2531 if (!dc)
2532 return -ENOMEM;
2533
2534 dc->soc = of_device_get_match_data(&pdev->dev);
2535
2536 INIT_LIST_HEAD(&dc->list);
2537 dc->dev = &pdev->dev;
2538
2539 err = tegra_dc_parse_dt(dc);
2540 if (err < 0)
2541 return err;
2542
2543 err = tegra_dc_couple(dc);
2544 if (err < 0)
2545 return err;
2546
2547 dc->clk = devm_clk_get(&pdev->dev, NULL);
2548 if (IS_ERR(dc->clk)) {
2549 dev_err(&pdev->dev, "failed to get clock\n");
2550 return PTR_ERR(dc->clk);
2551 }
2552
2553 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2554 if (IS_ERR(dc->rst)) {
2555 dev_err(&pdev->dev, "failed to get reset\n");
2556 return PTR_ERR(dc->rst);
2557 }
2558
2559 /* assert reset and disable clock */
2560 err = clk_prepare_enable(dc->clk);
2561 if (err < 0)
2562 return err;
2563
2564 usleep_range(2000, 4000);
2565
2566 err = reset_control_assert(dc->rst);
2567 if (err < 0)
2568 return err;
2569
2570 usleep_range(2000, 4000);
2571
2572 clk_disable_unprepare(dc->clk);
2573
2574 if (dc->soc->has_powergate) {
2575 if (dc->pipe == 0)
2576 dc->powergate = TEGRA_POWERGATE_DIS;
2577 else
2578 dc->powergate = TEGRA_POWERGATE_DISB;
2579
2580 tegra_powergate_power_off(dc->powergate);
2581 }
2582
2583 dc->regs = devm_platform_ioremap_resource(pdev, 0);
2584 if (IS_ERR(dc->regs))
2585 return PTR_ERR(dc->regs);
2586
2587 dc->irq = platform_get_irq(pdev, 0);
2588 if (dc->irq < 0)
2589 return -ENXIO;
2590
2591 err = tegra_dc_rgb_probe(dc);
2592 if (err < 0 && err != -ENODEV) {
2593 const char *level = KERN_ERR;
2594
2595 if (err == -EPROBE_DEFER)
2596 level = KERN_DEBUG;
2597
2598 dev_printk(level, dc->dev, "failed to probe RGB output: %d\n",
2599 err);
2600 return err;
2601 }
2602
2603 platform_set_drvdata(pdev, dc);
2604 pm_runtime_enable(&pdev->dev);
2605
2606 INIT_LIST_HEAD(&dc->client.list);
2607 dc->client.ops = &dc_client_ops;
2608 dc->client.dev = &pdev->dev;
2609
2610 err = host1x_client_register(&dc->client);
2611 if (err < 0) {
2612 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2613 err);
2614 goto disable_pm;
2615 }
2616
2617 return 0;
2618
2619 disable_pm:
2620 pm_runtime_disable(&pdev->dev);
2621 tegra_dc_rgb_remove(dc);
2622
2623 return err;
2624 }
2625
2626 static int tegra_dc_remove(struct platform_device *pdev)
2627 {
2628 struct tegra_dc *dc = platform_get_drvdata(pdev);
2629 int err;
2630
2631 err = host1x_client_unregister(&dc->client);
2632 if (err < 0) {
2633 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2634 err);
2635 return err;
2636 }
2637
2638 err = tegra_dc_rgb_remove(dc);
2639 if (err < 0) {
2640 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2641 return err;
2642 }
2643
2644 pm_runtime_disable(&pdev->dev);
2645
2646 return 0;
2647 }
2648
2649 struct platform_driver tegra_dc_driver = {
2650 .driver = {
2651 .name = "tegra-dc",
2652 .of_match_table = tegra_dc_of_match,
2653 },
2654 .probe = tegra_dc_probe,
2655 .remove = tegra_dc_remove,
2656 };
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