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Merge tag 'h8300-for-linus-20190617' of git://git.sourceforge.jp/gitroot/uclinux...
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / tegra / dc.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/debugfs.h>
9 #include <linux/iommu.h>
10 #include <linux/of_device.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/reset.h>
13
14 #include <soc/tegra/pmc.h>
15
16 #include "dc.h"
17 #include "drm.h"
18 #include "gem.h"
19 #include "hub.h"
20 #include "plane.h"
21
22 #include <drm/drm_atomic.h>
23 #include <drm/drm_atomic_helper.h>
24 #include <drm/drm_plane_helper.h>
25
26 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
27 struct drm_crtc_state *state);
28
29 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
30 {
31 stats->frames = 0;
32 stats->vblank = 0;
33 stats->underflow = 0;
34 stats->overflow = 0;
35 }
36
37 /* Reads the active copy of a register. */
38 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
39 {
40 u32 value;
41
42 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
43 value = tegra_dc_readl(dc, offset);
44 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
45
46 return value;
47 }
48
49 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
50 unsigned int offset)
51 {
52 if (offset >= 0x500 && offset <= 0x638) {
53 offset = 0x000 + (offset - 0x500);
54 return plane->offset + offset;
55 }
56
57 if (offset >= 0x700 && offset <= 0x719) {
58 offset = 0x180 + (offset - 0x700);
59 return plane->offset + offset;
60 }
61
62 if (offset >= 0x800 && offset <= 0x839) {
63 offset = 0x1c0 + (offset - 0x800);
64 return plane->offset + offset;
65 }
66
67 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
68
69 return plane->offset + offset;
70 }
71
72 static inline u32 tegra_plane_readl(struct tegra_plane *plane,
73 unsigned int offset)
74 {
75 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
76 }
77
78 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
79 unsigned int offset)
80 {
81 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
82 }
83
84 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
85 {
86 struct device_node *np = dc->dev->of_node;
87 struct of_phandle_iterator it;
88 int err;
89
90 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
91 if (it.node == dev->of_node)
92 return true;
93
94 return false;
95 }
96
97 /*
98 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
99 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
100 * Latching happens mmediately if the display controller is in STOP mode or
101 * on the next frame boundary otherwise.
102 *
103 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
104 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
105 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
106 * into the ACTIVE copy, either immediately if the display controller is in
107 * STOP mode, or at the next frame boundary otherwise.
108 */
109 void tegra_dc_commit(struct tegra_dc *dc)
110 {
111 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
112 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
113 }
114
115 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
116 unsigned int bpp)
117 {
118 fixed20_12 outf = dfixed_init(out);
119 fixed20_12 inf = dfixed_init(in);
120 u32 dda_inc;
121 int max;
122
123 if (v)
124 max = 15;
125 else {
126 switch (bpp) {
127 case 2:
128 max = 8;
129 break;
130
131 default:
132 WARN_ON_ONCE(1);
133 /* fallthrough */
134 case 4:
135 max = 4;
136 break;
137 }
138 }
139
140 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
141 inf.full -= dfixed_const(1);
142
143 dda_inc = dfixed_div(inf, outf);
144 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
145
146 return dda_inc;
147 }
148
149 static inline u32 compute_initial_dda(unsigned int in)
150 {
151 fixed20_12 inf = dfixed_init(in);
152 return dfixed_frac(inf);
153 }
154
155 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
156 {
157 u32 background[3] = {
158 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
159 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
160 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
161 };
162 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
163 BLEND_COLOR_KEY_NONE;
164 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
165 struct tegra_plane_state *state;
166 u32 blending[2];
167 unsigned int i;
168
169 /* disable blending for non-overlapping case */
170 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
171 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
172
173 state = to_tegra_plane_state(plane->base.state);
174
175 if (state->opaque) {
176 /*
177 * Since custom fix-weight blending isn't utilized and weight
178 * of top window is set to max, we can enforce dependent
179 * blending which in this case results in transparent bottom
180 * window if top window is opaque and if top window enables
181 * alpha blending, then bottom window is getting alpha value
182 * of 1 minus the sum of alpha components of the overlapping
183 * plane.
184 */
185 background[0] |= BLEND_CONTROL_DEPENDENT;
186 background[1] |= BLEND_CONTROL_DEPENDENT;
187
188 /*
189 * The region where three windows overlap is the intersection
190 * of the two regions where two windows overlap. It contributes
191 * to the area if all of the windows on top of it have an alpha
192 * component.
193 */
194 switch (state->base.normalized_zpos) {
195 case 0:
196 if (state->blending[0].alpha &&
197 state->blending[1].alpha)
198 background[2] |= BLEND_CONTROL_DEPENDENT;
199 break;
200
201 case 1:
202 background[2] |= BLEND_CONTROL_DEPENDENT;
203 break;
204 }
205 } else {
206 /*
207 * Enable alpha blending if pixel format has an alpha
208 * component.
209 */
210 foreground |= BLEND_CONTROL_ALPHA;
211
212 /*
213 * If any of the windows on top of this window is opaque, it
214 * will completely conceal this window within that area. If
215 * top window has an alpha component, it is blended over the
216 * bottom window.
217 */
218 for (i = 0; i < 2; i++) {
219 if (state->blending[i].alpha &&
220 state->blending[i].top)
221 background[i] |= BLEND_CONTROL_DEPENDENT;
222 }
223
224 switch (state->base.normalized_zpos) {
225 case 0:
226 if (state->blending[0].alpha &&
227 state->blending[1].alpha)
228 background[2] |= BLEND_CONTROL_DEPENDENT;
229 break;
230
231 case 1:
232 /*
233 * When both middle and topmost windows have an alpha,
234 * these windows a mixed together and then the result
235 * is blended over the bottom window.
236 */
237 if (state->blending[0].alpha &&
238 state->blending[0].top)
239 background[2] |= BLEND_CONTROL_ALPHA;
240
241 if (state->blending[1].alpha &&
242 state->blending[1].top)
243 background[2] |= BLEND_CONTROL_ALPHA;
244 break;
245 }
246 }
247
248 switch (state->base.normalized_zpos) {
249 case 0:
250 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
251 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
252 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
253 break;
254
255 case 1:
256 /*
257 * If window B / C is topmost, then X / Y registers are
258 * matching the order of blending[...] state indices,
259 * otherwise a swap is required.
260 */
261 if (!state->blending[0].top && state->blending[1].top) {
262 blending[0] = foreground;
263 blending[1] = background[1];
264 } else {
265 blending[0] = background[0];
266 blending[1] = foreground;
267 }
268
269 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
270 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
271 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
272 break;
273
274 case 2:
275 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
276 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
277 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
278 break;
279 }
280 }
281
282 static void tegra_plane_setup_blending(struct tegra_plane *plane,
283 const struct tegra_dc_window *window)
284 {
285 u32 value;
286
287 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
288 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
289 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
290 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
291
292 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
293 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
294 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
295 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
296
297 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
298 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
299 }
300
301 static bool
302 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
303 const struct tegra_dc_window *window)
304 {
305 struct tegra_dc *dc = plane->dc;
306
307 if (window->src.w == window->dst.w)
308 return false;
309
310 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
311 return false;
312
313 return true;
314 }
315
316 static bool
317 tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
318 const struct tegra_dc_window *window)
319 {
320 struct tegra_dc *dc = plane->dc;
321
322 if (window->src.h == window->dst.h)
323 return false;
324
325 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
326 return false;
327
328 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
329 return false;
330
331 return true;
332 }
333
334 static void tegra_dc_setup_window(struct tegra_plane *plane,
335 const struct tegra_dc_window *window)
336 {
337 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
338 struct tegra_dc *dc = plane->dc;
339 bool yuv, planar;
340 u32 value;
341
342 /*
343 * For YUV planar modes, the number of bytes per pixel takes into
344 * account only the luma component and therefore is 1.
345 */
346 yuv = tegra_plane_format_is_yuv(window->format, &planar);
347 if (!yuv)
348 bpp = window->bits_per_pixel / 8;
349 else
350 bpp = planar ? 1 : 2;
351
352 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
353 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
354
355 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
356 tegra_plane_writel(plane, value, DC_WIN_POSITION);
357
358 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
359 tegra_plane_writel(plane, value, DC_WIN_SIZE);
360
361 h_offset = window->src.x * bpp;
362 v_offset = window->src.y;
363 h_size = window->src.w * bpp;
364 v_size = window->src.h;
365
366 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
367 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
368
369 /*
370 * For DDA computations the number of bytes per pixel for YUV planar
371 * modes needs to take into account all Y, U and V components.
372 */
373 if (yuv && planar)
374 bpp = 2;
375
376 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
377 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
378
379 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
380 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
381
382 h_dda = compute_initial_dda(window->src.x);
383 v_dda = compute_initial_dda(window->src.y);
384
385 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
386 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
387
388 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
389 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
390
391 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
392
393 if (yuv && planar) {
394 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
395 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
396 value = window->stride[1] << 16 | window->stride[0];
397 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
398 } else {
399 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
400 }
401
402 if (window->bottom_up)
403 v_offset += window->src.h - 1;
404
405 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
406 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
407
408 if (dc->soc->supports_block_linear) {
409 unsigned long height = window->tiling.value;
410
411 switch (window->tiling.mode) {
412 case TEGRA_BO_TILING_MODE_PITCH:
413 value = DC_WINBUF_SURFACE_KIND_PITCH;
414 break;
415
416 case TEGRA_BO_TILING_MODE_TILED:
417 value = DC_WINBUF_SURFACE_KIND_TILED;
418 break;
419
420 case TEGRA_BO_TILING_MODE_BLOCK:
421 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
422 DC_WINBUF_SURFACE_KIND_BLOCK;
423 break;
424 }
425
426 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
427 } else {
428 switch (window->tiling.mode) {
429 case TEGRA_BO_TILING_MODE_PITCH:
430 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
431 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
432 break;
433
434 case TEGRA_BO_TILING_MODE_TILED:
435 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
436 DC_WIN_BUFFER_ADDR_MODE_TILE;
437 break;
438
439 case TEGRA_BO_TILING_MODE_BLOCK:
440 /*
441 * No need to handle this here because ->atomic_check
442 * will already have filtered it out.
443 */
444 break;
445 }
446
447 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
448 }
449
450 value = WIN_ENABLE;
451
452 if (yuv) {
453 /* setup default colorspace conversion coefficients */
454 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
455 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
456 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
457 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
458 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
459 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
460 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
461 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
462
463 value |= CSC_ENABLE;
464 } else if (window->bits_per_pixel < 24) {
465 value |= COLOR_EXPAND;
466 }
467
468 if (window->bottom_up)
469 value |= V_DIRECTION;
470
471 if (tegra_plane_use_horizontal_filtering(plane, window)) {
472 /*
473 * Enable horizontal 6-tap filter and set filtering
474 * coefficients to the default values defined in TRM.
475 */
476 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
477 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
478 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
479 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
480 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
481 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
482 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
483 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
484 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
485 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
486 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
487 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
488 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
489 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
490 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
491 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
492
493 value |= H_FILTER;
494 }
495
496 if (tegra_plane_use_vertical_filtering(plane, window)) {
497 unsigned int i, k;
498
499 /*
500 * Enable vertical 2-tap filter and set filtering
501 * coefficients to the default values defined in TRM.
502 */
503 for (i = 0, k = 128; i < 16; i++, k -= 8)
504 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
505
506 value |= V_FILTER;
507 }
508
509 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
510
511 if (dc->soc->has_legacy_blending)
512 tegra_plane_setup_blending_legacy(plane);
513 else
514 tegra_plane_setup_blending(plane, window);
515 }
516
517 static const u32 tegra20_primary_formats[] = {
518 DRM_FORMAT_ARGB4444,
519 DRM_FORMAT_ARGB1555,
520 DRM_FORMAT_RGB565,
521 DRM_FORMAT_RGBA5551,
522 DRM_FORMAT_ABGR8888,
523 DRM_FORMAT_ARGB8888,
524 /* non-native formats */
525 DRM_FORMAT_XRGB1555,
526 DRM_FORMAT_RGBX5551,
527 DRM_FORMAT_XBGR8888,
528 DRM_FORMAT_XRGB8888,
529 };
530
531 static const u64 tegra20_modifiers[] = {
532 DRM_FORMAT_MOD_LINEAR,
533 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
534 DRM_FORMAT_MOD_INVALID
535 };
536
537 static const u32 tegra114_primary_formats[] = {
538 DRM_FORMAT_ARGB4444,
539 DRM_FORMAT_ARGB1555,
540 DRM_FORMAT_RGB565,
541 DRM_FORMAT_RGBA5551,
542 DRM_FORMAT_ABGR8888,
543 DRM_FORMAT_ARGB8888,
544 /* new on Tegra114 */
545 DRM_FORMAT_ABGR4444,
546 DRM_FORMAT_ABGR1555,
547 DRM_FORMAT_BGRA5551,
548 DRM_FORMAT_XRGB1555,
549 DRM_FORMAT_RGBX5551,
550 DRM_FORMAT_XBGR1555,
551 DRM_FORMAT_BGRX5551,
552 DRM_FORMAT_BGR565,
553 DRM_FORMAT_BGRA8888,
554 DRM_FORMAT_RGBA8888,
555 DRM_FORMAT_XRGB8888,
556 DRM_FORMAT_XBGR8888,
557 };
558
559 static const u32 tegra124_primary_formats[] = {
560 DRM_FORMAT_ARGB4444,
561 DRM_FORMAT_ARGB1555,
562 DRM_FORMAT_RGB565,
563 DRM_FORMAT_RGBA5551,
564 DRM_FORMAT_ABGR8888,
565 DRM_FORMAT_ARGB8888,
566 /* new on Tegra114 */
567 DRM_FORMAT_ABGR4444,
568 DRM_FORMAT_ABGR1555,
569 DRM_FORMAT_BGRA5551,
570 DRM_FORMAT_XRGB1555,
571 DRM_FORMAT_RGBX5551,
572 DRM_FORMAT_XBGR1555,
573 DRM_FORMAT_BGRX5551,
574 DRM_FORMAT_BGR565,
575 DRM_FORMAT_BGRA8888,
576 DRM_FORMAT_RGBA8888,
577 DRM_FORMAT_XRGB8888,
578 DRM_FORMAT_XBGR8888,
579 /* new on Tegra124 */
580 DRM_FORMAT_RGBX8888,
581 DRM_FORMAT_BGRX8888,
582 };
583
584 static const u64 tegra124_modifiers[] = {
585 DRM_FORMAT_MOD_LINEAR,
586 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
587 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
588 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
589 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
590 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
591 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
592 DRM_FORMAT_MOD_INVALID
593 };
594
595 static int tegra_plane_atomic_check(struct drm_plane *plane,
596 struct drm_plane_state *state)
597 {
598 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
599 unsigned int rotation = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_Y;
600 struct tegra_bo_tiling *tiling = &plane_state->tiling;
601 struct tegra_plane *tegra = to_tegra_plane(plane);
602 struct tegra_dc *dc = to_tegra_dc(state->crtc);
603 int err;
604
605 /* no need for further checks if the plane is being disabled */
606 if (!state->crtc)
607 return 0;
608
609 err = tegra_plane_format(state->fb->format->format,
610 &plane_state->format,
611 &plane_state->swap);
612 if (err < 0)
613 return err;
614
615 /*
616 * Tegra20 and Tegra30 are special cases here because they support
617 * only variants of specific formats with an alpha component, but not
618 * the corresponding opaque formats. However, the opaque formats can
619 * be emulated by disabling alpha blending for the plane.
620 */
621 if (dc->soc->has_legacy_blending) {
622 err = tegra_plane_setup_legacy_state(tegra, plane_state);
623 if (err < 0)
624 return err;
625 }
626
627 err = tegra_fb_get_tiling(state->fb, tiling);
628 if (err < 0)
629 return err;
630
631 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
632 !dc->soc->supports_block_linear) {
633 DRM_ERROR("hardware doesn't support block linear mode\n");
634 return -EINVAL;
635 }
636
637 rotation = drm_rotation_simplify(state->rotation, rotation);
638
639 if (rotation & DRM_MODE_REFLECT_Y)
640 plane_state->bottom_up = true;
641 else
642 plane_state->bottom_up = false;
643
644 /*
645 * Tegra doesn't support different strides for U and V planes so we
646 * error out if the user tries to display a framebuffer with such a
647 * configuration.
648 */
649 if (state->fb->format->num_planes > 2) {
650 if (state->fb->pitches[2] != state->fb->pitches[1]) {
651 DRM_ERROR("unsupported UV-plane configuration\n");
652 return -EINVAL;
653 }
654 }
655
656 err = tegra_plane_state_add(tegra, state);
657 if (err < 0)
658 return err;
659
660 return 0;
661 }
662
663 static void tegra_plane_atomic_disable(struct drm_plane *plane,
664 struct drm_plane_state *old_state)
665 {
666 struct tegra_plane *p = to_tegra_plane(plane);
667 u32 value;
668
669 /* rien ne va plus */
670 if (!old_state || !old_state->crtc)
671 return;
672
673 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
674 value &= ~WIN_ENABLE;
675 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
676 }
677
678 static void tegra_plane_atomic_update(struct drm_plane *plane,
679 struct drm_plane_state *old_state)
680 {
681 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
682 struct drm_framebuffer *fb = plane->state->fb;
683 struct tegra_plane *p = to_tegra_plane(plane);
684 struct tegra_dc_window window;
685 unsigned int i;
686
687 /* rien ne va plus */
688 if (!plane->state->crtc || !plane->state->fb)
689 return;
690
691 if (!plane->state->visible)
692 return tegra_plane_atomic_disable(plane, old_state);
693
694 memset(&window, 0, sizeof(window));
695 window.src.x = plane->state->src.x1 >> 16;
696 window.src.y = plane->state->src.y1 >> 16;
697 window.src.w = drm_rect_width(&plane->state->src) >> 16;
698 window.src.h = drm_rect_height(&plane->state->src) >> 16;
699 window.dst.x = plane->state->dst.x1;
700 window.dst.y = plane->state->dst.y1;
701 window.dst.w = drm_rect_width(&plane->state->dst);
702 window.dst.h = drm_rect_height(&plane->state->dst);
703 window.bits_per_pixel = fb->format->cpp[0] * 8;
704 window.bottom_up = tegra_fb_is_bottom_up(fb) || state->bottom_up;
705
706 /* copy from state */
707 window.zpos = plane->state->normalized_zpos;
708 window.tiling = state->tiling;
709 window.format = state->format;
710 window.swap = state->swap;
711
712 for (i = 0; i < fb->format->num_planes; i++) {
713 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
714
715 window.base[i] = bo->paddr + fb->offsets[i];
716
717 /*
718 * Tegra uses a shared stride for UV planes. Framebuffers are
719 * already checked for this in the tegra_plane_atomic_check()
720 * function, so it's safe to ignore the V-plane pitch here.
721 */
722 if (i < 2)
723 window.stride[i] = fb->pitches[i];
724 }
725
726 tegra_dc_setup_window(p, &window);
727 }
728
729 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
730 .atomic_check = tegra_plane_atomic_check,
731 .atomic_disable = tegra_plane_atomic_disable,
732 .atomic_update = tegra_plane_atomic_update,
733 };
734
735 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
736 {
737 /*
738 * Ideally this would use drm_crtc_mask(), but that would require the
739 * CRTC to already be in the mode_config's list of CRTCs. However, it
740 * will only be added to that list in the drm_crtc_init_with_planes()
741 * (in tegra_dc_init()), which in turn requires registration of these
742 * planes. So we have ourselves a nice little chicken and egg problem
743 * here.
744 *
745 * We work around this by manually creating the mask from the number
746 * of CRTCs that have been registered, and should therefore always be
747 * the same as drm_crtc_index() after registration.
748 */
749 return 1 << drm->mode_config.num_crtc;
750 }
751
752 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
753 struct tegra_dc *dc)
754 {
755 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
756 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
757 struct tegra_plane *plane;
758 unsigned int num_formats;
759 const u64 *modifiers;
760 const u32 *formats;
761 int err;
762
763 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
764 if (!plane)
765 return ERR_PTR(-ENOMEM);
766
767 /* Always use window A as primary window */
768 plane->offset = 0xa00;
769 plane->index = 0;
770 plane->dc = dc;
771
772 num_formats = dc->soc->num_primary_formats;
773 formats = dc->soc->primary_formats;
774 modifiers = dc->soc->modifiers;
775
776 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
777 &tegra_plane_funcs, formats,
778 num_formats, modifiers, type, NULL);
779 if (err < 0) {
780 kfree(plane);
781 return ERR_PTR(err);
782 }
783
784 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
785 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
786
787 err = drm_plane_create_rotation_property(&plane->base,
788 DRM_MODE_ROTATE_0,
789 DRM_MODE_ROTATE_0 |
790 DRM_MODE_REFLECT_Y);
791 if (err < 0)
792 dev_err(dc->dev, "failed to create rotation property: %d\n",
793 err);
794
795 return &plane->base;
796 }
797
798 static const u32 tegra_cursor_plane_formats[] = {
799 DRM_FORMAT_RGBA8888,
800 };
801
802 static int tegra_cursor_atomic_check(struct drm_plane *plane,
803 struct drm_plane_state *state)
804 {
805 struct tegra_plane *tegra = to_tegra_plane(plane);
806 int err;
807
808 /* no need for further checks if the plane is being disabled */
809 if (!state->crtc)
810 return 0;
811
812 /* scaling not supported for cursor */
813 if ((state->src_w >> 16 != state->crtc_w) ||
814 (state->src_h >> 16 != state->crtc_h))
815 return -EINVAL;
816
817 /* only square cursors supported */
818 if (state->src_w != state->src_h)
819 return -EINVAL;
820
821 if (state->crtc_w != 32 && state->crtc_w != 64 &&
822 state->crtc_w != 128 && state->crtc_w != 256)
823 return -EINVAL;
824
825 err = tegra_plane_state_add(tegra, state);
826 if (err < 0)
827 return err;
828
829 return 0;
830 }
831
832 static void tegra_cursor_atomic_update(struct drm_plane *plane,
833 struct drm_plane_state *old_state)
834 {
835 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
836 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
837 struct drm_plane_state *state = plane->state;
838 u32 value = CURSOR_CLIP_DISPLAY;
839
840 /* rien ne va plus */
841 if (!plane->state->crtc || !plane->state->fb)
842 return;
843
844 switch (state->crtc_w) {
845 case 32:
846 value |= CURSOR_SIZE_32x32;
847 break;
848
849 case 64:
850 value |= CURSOR_SIZE_64x64;
851 break;
852
853 case 128:
854 value |= CURSOR_SIZE_128x128;
855 break;
856
857 case 256:
858 value |= CURSOR_SIZE_256x256;
859 break;
860
861 default:
862 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
863 state->crtc_h);
864 return;
865 }
866
867 value |= (bo->paddr >> 10) & 0x3fffff;
868 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
869
870 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
871 value = (bo->paddr >> 32) & 0x3;
872 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
873 #endif
874
875 /* enable cursor and set blend mode */
876 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
877 value |= CURSOR_ENABLE;
878 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
879
880 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
881 value &= ~CURSOR_DST_BLEND_MASK;
882 value &= ~CURSOR_SRC_BLEND_MASK;
883 value |= CURSOR_MODE_NORMAL;
884 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
885 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
886 value |= CURSOR_ALPHA;
887 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
888
889 /* position the cursor */
890 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
891 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
892 }
893
894 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
895 struct drm_plane_state *old_state)
896 {
897 struct tegra_dc *dc;
898 u32 value;
899
900 /* rien ne va plus */
901 if (!old_state || !old_state->crtc)
902 return;
903
904 dc = to_tegra_dc(old_state->crtc);
905
906 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
907 value &= ~CURSOR_ENABLE;
908 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
909 }
910
911 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
912 .atomic_check = tegra_cursor_atomic_check,
913 .atomic_update = tegra_cursor_atomic_update,
914 .atomic_disable = tegra_cursor_atomic_disable,
915 };
916
917 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
918 struct tegra_dc *dc)
919 {
920 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
921 struct tegra_plane *plane;
922 unsigned int num_formats;
923 const u32 *formats;
924 int err;
925
926 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
927 if (!plane)
928 return ERR_PTR(-ENOMEM);
929
930 /*
931 * This index is kind of fake. The cursor isn't a regular plane, but
932 * its update and activation request bits in DC_CMD_STATE_CONTROL do
933 * use the same programming. Setting this fake index here allows the
934 * code in tegra_add_plane_state() to do the right thing without the
935 * need to special-casing the cursor plane.
936 */
937 plane->index = 6;
938 plane->dc = dc;
939
940 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
941 formats = tegra_cursor_plane_formats;
942
943 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
944 &tegra_plane_funcs, formats,
945 num_formats, NULL,
946 DRM_PLANE_TYPE_CURSOR, NULL);
947 if (err < 0) {
948 kfree(plane);
949 return ERR_PTR(err);
950 }
951
952 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
953
954 return &plane->base;
955 }
956
957 static const u32 tegra20_overlay_formats[] = {
958 DRM_FORMAT_ARGB4444,
959 DRM_FORMAT_ARGB1555,
960 DRM_FORMAT_RGB565,
961 DRM_FORMAT_RGBA5551,
962 DRM_FORMAT_ABGR8888,
963 DRM_FORMAT_ARGB8888,
964 /* non-native formats */
965 DRM_FORMAT_XRGB1555,
966 DRM_FORMAT_RGBX5551,
967 DRM_FORMAT_XBGR8888,
968 DRM_FORMAT_XRGB8888,
969 /* planar formats */
970 DRM_FORMAT_UYVY,
971 DRM_FORMAT_YUYV,
972 DRM_FORMAT_YUV420,
973 DRM_FORMAT_YUV422,
974 };
975
976 static const u32 tegra114_overlay_formats[] = {
977 DRM_FORMAT_ARGB4444,
978 DRM_FORMAT_ARGB1555,
979 DRM_FORMAT_RGB565,
980 DRM_FORMAT_RGBA5551,
981 DRM_FORMAT_ABGR8888,
982 DRM_FORMAT_ARGB8888,
983 /* new on Tegra114 */
984 DRM_FORMAT_ABGR4444,
985 DRM_FORMAT_ABGR1555,
986 DRM_FORMAT_BGRA5551,
987 DRM_FORMAT_XRGB1555,
988 DRM_FORMAT_RGBX5551,
989 DRM_FORMAT_XBGR1555,
990 DRM_FORMAT_BGRX5551,
991 DRM_FORMAT_BGR565,
992 DRM_FORMAT_BGRA8888,
993 DRM_FORMAT_RGBA8888,
994 DRM_FORMAT_XRGB8888,
995 DRM_FORMAT_XBGR8888,
996 /* planar formats */
997 DRM_FORMAT_UYVY,
998 DRM_FORMAT_YUYV,
999 DRM_FORMAT_YUV420,
1000 DRM_FORMAT_YUV422,
1001 };
1002
1003 static const u32 tegra124_overlay_formats[] = {
1004 DRM_FORMAT_ARGB4444,
1005 DRM_FORMAT_ARGB1555,
1006 DRM_FORMAT_RGB565,
1007 DRM_FORMAT_RGBA5551,
1008 DRM_FORMAT_ABGR8888,
1009 DRM_FORMAT_ARGB8888,
1010 /* new on Tegra114 */
1011 DRM_FORMAT_ABGR4444,
1012 DRM_FORMAT_ABGR1555,
1013 DRM_FORMAT_BGRA5551,
1014 DRM_FORMAT_XRGB1555,
1015 DRM_FORMAT_RGBX5551,
1016 DRM_FORMAT_XBGR1555,
1017 DRM_FORMAT_BGRX5551,
1018 DRM_FORMAT_BGR565,
1019 DRM_FORMAT_BGRA8888,
1020 DRM_FORMAT_RGBA8888,
1021 DRM_FORMAT_XRGB8888,
1022 DRM_FORMAT_XBGR8888,
1023 /* new on Tegra124 */
1024 DRM_FORMAT_RGBX8888,
1025 DRM_FORMAT_BGRX8888,
1026 /* planar formats */
1027 DRM_FORMAT_UYVY,
1028 DRM_FORMAT_YUYV,
1029 DRM_FORMAT_YUV420,
1030 DRM_FORMAT_YUV422,
1031 };
1032
1033 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1034 struct tegra_dc *dc,
1035 unsigned int index,
1036 bool cursor)
1037 {
1038 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1039 struct tegra_plane *plane;
1040 unsigned int num_formats;
1041 enum drm_plane_type type;
1042 const u32 *formats;
1043 int err;
1044
1045 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1046 if (!plane)
1047 return ERR_PTR(-ENOMEM);
1048
1049 plane->offset = 0xa00 + 0x200 * index;
1050 plane->index = index;
1051 plane->dc = dc;
1052
1053 num_formats = dc->soc->num_overlay_formats;
1054 formats = dc->soc->overlay_formats;
1055
1056 if (!cursor)
1057 type = DRM_PLANE_TYPE_OVERLAY;
1058 else
1059 type = DRM_PLANE_TYPE_CURSOR;
1060
1061 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1062 &tegra_plane_funcs, formats,
1063 num_formats, NULL, type, NULL);
1064 if (err < 0) {
1065 kfree(plane);
1066 return ERR_PTR(err);
1067 }
1068
1069 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1070 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1071
1072 err = drm_plane_create_rotation_property(&plane->base,
1073 DRM_MODE_ROTATE_0,
1074 DRM_MODE_ROTATE_0 |
1075 DRM_MODE_REFLECT_Y);
1076 if (err < 0)
1077 dev_err(dc->dev, "failed to create rotation property: %d\n",
1078 err);
1079
1080 return &plane->base;
1081 }
1082
1083 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1084 struct tegra_dc *dc)
1085 {
1086 struct drm_plane *plane, *primary = NULL;
1087 unsigned int i, j;
1088
1089 for (i = 0; i < dc->soc->num_wgrps; i++) {
1090 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1091
1092 if (wgrp->dc == dc->pipe) {
1093 for (j = 0; j < wgrp->num_windows; j++) {
1094 unsigned int index = wgrp->windows[j];
1095
1096 plane = tegra_shared_plane_create(drm, dc,
1097 wgrp->index,
1098 index);
1099 if (IS_ERR(plane))
1100 return plane;
1101
1102 /*
1103 * Choose the first shared plane owned by this
1104 * head as the primary plane.
1105 */
1106 if (!primary) {
1107 plane->type = DRM_PLANE_TYPE_PRIMARY;
1108 primary = plane;
1109 }
1110 }
1111 }
1112 }
1113
1114 return primary;
1115 }
1116
1117 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1118 struct tegra_dc *dc)
1119 {
1120 struct drm_plane *planes[2], *primary;
1121 unsigned int planes_num;
1122 unsigned int i;
1123 int err;
1124
1125 primary = tegra_primary_plane_create(drm, dc);
1126 if (IS_ERR(primary))
1127 return primary;
1128
1129 if (dc->soc->supports_cursor)
1130 planes_num = 2;
1131 else
1132 planes_num = 1;
1133
1134 for (i = 0; i < planes_num; i++) {
1135 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1136 false);
1137 if (IS_ERR(planes[i])) {
1138 err = PTR_ERR(planes[i]);
1139
1140 while (i--)
1141 tegra_plane_funcs.destroy(planes[i]);
1142
1143 tegra_plane_funcs.destroy(primary);
1144 return ERR_PTR(err);
1145 }
1146 }
1147
1148 return primary;
1149 }
1150
1151 static void tegra_dc_destroy(struct drm_crtc *crtc)
1152 {
1153 drm_crtc_cleanup(crtc);
1154 }
1155
1156 static void tegra_crtc_reset(struct drm_crtc *crtc)
1157 {
1158 struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
1159
1160 if (crtc->state)
1161 tegra_crtc_atomic_destroy_state(crtc, crtc->state);
1162
1163 __drm_atomic_helper_crtc_reset(crtc, &state->base);
1164 drm_crtc_vblank_reset(crtc);
1165 }
1166
1167 static struct drm_crtc_state *
1168 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1169 {
1170 struct tegra_dc_state *state = to_dc_state(crtc->state);
1171 struct tegra_dc_state *copy;
1172
1173 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1174 if (!copy)
1175 return NULL;
1176
1177 __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1178 copy->clk = state->clk;
1179 copy->pclk = state->pclk;
1180 copy->div = state->div;
1181 copy->planes = state->planes;
1182
1183 return &copy->base;
1184 }
1185
1186 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1187 struct drm_crtc_state *state)
1188 {
1189 __drm_atomic_helper_crtc_destroy_state(state);
1190 kfree(state);
1191 }
1192
1193 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1194
1195 static const struct debugfs_reg32 tegra_dc_regs[] = {
1196 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1197 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1198 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1199 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1200 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1201 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1202 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1203 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1204 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1205 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1206 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1207 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1208 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1209 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1210 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1211 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1212 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1213 DEBUGFS_REG32(DC_CMD_INT_STATUS),
1214 DEBUGFS_REG32(DC_CMD_INT_MASK),
1215 DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1216 DEBUGFS_REG32(DC_CMD_INT_TYPE),
1217 DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1218 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1219 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1220 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1221 DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1222 DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1223 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1224 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1225 DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1226 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1227 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1228 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1229 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1230 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1231 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1232 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1233 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1234 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1235 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1236 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1237 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1238 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1239 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1240 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1241 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1242 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1243 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1244 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1245 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1246 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1247 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1248 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1249 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1250 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1251 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1252 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1253 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1254 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1255 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1256 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1257 DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1258 DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1259 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1260 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1261 DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1262 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1263 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1264 DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1265 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1266 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1267 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1268 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1269 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1270 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1271 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1272 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1273 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1274 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1275 DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1276 DEBUGFS_REG32(DC_DISP_ACTIVE),
1277 DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1278 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1279 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1280 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1281 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1282 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1283 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1284 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1285 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1286 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1287 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1288 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1289 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1290 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1291 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1292 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1293 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1294 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1295 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1296 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1297 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1298 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1299 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1300 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1301 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1302 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1303 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1304 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1305 DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1306 DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1307 DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1308 DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1309 DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1310 DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1311 DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1312 DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1313 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1314 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1315 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1316 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1317 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1318 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1319 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1320 DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1321 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1322 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1323 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1324 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1325 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1326 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1327 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1328 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1329 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1330 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1331 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1332 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1333 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1334 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1335 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1336 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1337 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1338 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1339 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1340 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1341 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1342 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1343 DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1344 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1345 DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1346 DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1347 DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1348 DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1349 DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1350 DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1351 DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1352 DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1353 DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1354 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1355 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1356 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1357 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1358 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1359 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1360 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1361 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1362 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1363 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1364 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1365 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1366 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1367 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1368 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1369 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1370 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1371 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1372 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1373 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1374 DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1375 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1376 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1377 DEBUGFS_REG32(DC_WIN_POSITION),
1378 DEBUGFS_REG32(DC_WIN_SIZE),
1379 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1380 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1381 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1382 DEBUGFS_REG32(DC_WIN_DDA_INC),
1383 DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1384 DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1385 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1386 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1387 DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1388 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1389 DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1390 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1391 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1392 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1393 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1394 DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1395 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1396 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1397 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1398 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1399 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1400 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1401 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1402 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1403 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1404 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1405 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1406 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1407 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1408 };
1409
1410 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1411 {
1412 struct drm_info_node *node = s->private;
1413 struct tegra_dc *dc = node->info_ent->data;
1414 unsigned int i;
1415 int err = 0;
1416
1417 drm_modeset_lock(&dc->base.mutex, NULL);
1418
1419 if (!dc->base.state->active) {
1420 err = -EBUSY;
1421 goto unlock;
1422 }
1423
1424 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1425 unsigned int offset = tegra_dc_regs[i].offset;
1426
1427 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1428 offset, tegra_dc_readl(dc, offset));
1429 }
1430
1431 unlock:
1432 drm_modeset_unlock(&dc->base.mutex);
1433 return err;
1434 }
1435
1436 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1437 {
1438 struct drm_info_node *node = s->private;
1439 struct tegra_dc *dc = node->info_ent->data;
1440 int err = 0;
1441 u32 value;
1442
1443 drm_modeset_lock(&dc->base.mutex, NULL);
1444
1445 if (!dc->base.state->active) {
1446 err = -EBUSY;
1447 goto unlock;
1448 }
1449
1450 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1451 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1452 tegra_dc_commit(dc);
1453
1454 drm_crtc_wait_one_vblank(&dc->base);
1455 drm_crtc_wait_one_vblank(&dc->base);
1456
1457 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1458 seq_printf(s, "%08x\n", value);
1459
1460 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1461
1462 unlock:
1463 drm_modeset_unlock(&dc->base.mutex);
1464 return err;
1465 }
1466
1467 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1468 {
1469 struct drm_info_node *node = s->private;
1470 struct tegra_dc *dc = node->info_ent->data;
1471
1472 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1473 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1474 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1475 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1476
1477 return 0;
1478 }
1479
1480 static struct drm_info_list debugfs_files[] = {
1481 { "regs", tegra_dc_show_regs, 0, NULL },
1482 { "crc", tegra_dc_show_crc, 0, NULL },
1483 { "stats", tegra_dc_show_stats, 0, NULL },
1484 };
1485
1486 static int tegra_dc_late_register(struct drm_crtc *crtc)
1487 {
1488 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1489 struct drm_minor *minor = crtc->dev->primary;
1490 struct dentry *root;
1491 struct tegra_dc *dc = to_tegra_dc(crtc);
1492 int err;
1493
1494 #ifdef CONFIG_DEBUG_FS
1495 root = crtc->debugfs_entry;
1496 #else
1497 root = NULL;
1498 #endif
1499
1500 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1501 GFP_KERNEL);
1502 if (!dc->debugfs_files)
1503 return -ENOMEM;
1504
1505 for (i = 0; i < count; i++)
1506 dc->debugfs_files[i].data = dc;
1507
1508 err = drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1509 if (err < 0)
1510 goto free;
1511
1512 return 0;
1513
1514 free:
1515 kfree(dc->debugfs_files);
1516 dc->debugfs_files = NULL;
1517
1518 return err;
1519 }
1520
1521 static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1522 {
1523 unsigned int count = ARRAY_SIZE(debugfs_files);
1524 struct drm_minor *minor = crtc->dev->primary;
1525 struct tegra_dc *dc = to_tegra_dc(crtc);
1526
1527 drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1528 kfree(dc->debugfs_files);
1529 dc->debugfs_files = NULL;
1530 }
1531
1532 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1533 {
1534 struct tegra_dc *dc = to_tegra_dc(crtc);
1535
1536 /* XXX vblank syncpoints don't work with nvdisplay yet */
1537 if (dc->syncpt && !dc->soc->has_nvdisplay)
1538 return host1x_syncpt_read(dc->syncpt);
1539
1540 /* fallback to software emulated VBLANK counter */
1541 return (u32)drm_crtc_vblank_count(&dc->base);
1542 }
1543
1544 static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1545 {
1546 struct tegra_dc *dc = to_tegra_dc(crtc);
1547 u32 value;
1548
1549 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1550 value |= VBLANK_INT;
1551 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1552
1553 return 0;
1554 }
1555
1556 static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1557 {
1558 struct tegra_dc *dc = to_tegra_dc(crtc);
1559 u32 value;
1560
1561 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1562 value &= ~VBLANK_INT;
1563 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1564 }
1565
1566 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1567 .page_flip = drm_atomic_helper_page_flip,
1568 .set_config = drm_atomic_helper_set_config,
1569 .destroy = tegra_dc_destroy,
1570 .reset = tegra_crtc_reset,
1571 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1572 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1573 .late_register = tegra_dc_late_register,
1574 .early_unregister = tegra_dc_early_unregister,
1575 .get_vblank_counter = tegra_dc_get_vblank_counter,
1576 .enable_vblank = tegra_dc_enable_vblank,
1577 .disable_vblank = tegra_dc_disable_vblank,
1578 };
1579
1580 static int tegra_dc_set_timings(struct tegra_dc *dc,
1581 struct drm_display_mode *mode)
1582 {
1583 unsigned int h_ref_to_sync = 1;
1584 unsigned int v_ref_to_sync = 1;
1585 unsigned long value;
1586
1587 if (!dc->soc->has_nvdisplay) {
1588 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1589
1590 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1591 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1592 }
1593
1594 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1595 ((mode->hsync_end - mode->hsync_start) << 0);
1596 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1597
1598 value = ((mode->vtotal - mode->vsync_end) << 16) |
1599 ((mode->htotal - mode->hsync_end) << 0);
1600 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1601
1602 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1603 ((mode->hsync_start - mode->hdisplay) << 0);
1604 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1605
1606 value = (mode->vdisplay << 16) | mode->hdisplay;
1607 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1608
1609 return 0;
1610 }
1611
1612 /**
1613 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1614 * state
1615 * @dc: display controller
1616 * @crtc_state: CRTC atomic state
1617 * @clk: parent clock for display controller
1618 * @pclk: pixel clock
1619 * @div: shift clock divider
1620 *
1621 * Returns:
1622 * 0 on success or a negative error-code on failure.
1623 */
1624 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1625 struct drm_crtc_state *crtc_state,
1626 struct clk *clk, unsigned long pclk,
1627 unsigned int div)
1628 {
1629 struct tegra_dc_state *state = to_dc_state(crtc_state);
1630
1631 if (!clk_has_parent(dc->clk, clk))
1632 return -EINVAL;
1633
1634 state->clk = clk;
1635 state->pclk = pclk;
1636 state->div = div;
1637
1638 return 0;
1639 }
1640
1641 static void tegra_dc_commit_state(struct tegra_dc *dc,
1642 struct tegra_dc_state *state)
1643 {
1644 u32 value;
1645 int err;
1646
1647 err = clk_set_parent(dc->clk, state->clk);
1648 if (err < 0)
1649 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1650
1651 /*
1652 * Outputs may not want to change the parent clock rate. This is only
1653 * relevant to Tegra20 where only a single display PLL is available.
1654 * Since that PLL would typically be used for HDMI, an internal LVDS
1655 * panel would need to be driven by some other clock such as PLL_P
1656 * which is shared with other peripherals. Changing the clock rate
1657 * should therefore be avoided.
1658 */
1659 if (state->pclk > 0) {
1660 err = clk_set_rate(state->clk, state->pclk);
1661 if (err < 0)
1662 dev_err(dc->dev,
1663 "failed to set clock rate to %lu Hz\n",
1664 state->pclk);
1665 }
1666
1667 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1668 state->div);
1669 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1670
1671 if (!dc->soc->has_nvdisplay) {
1672 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1673 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1674 }
1675
1676 err = clk_set_rate(dc->clk, state->pclk);
1677 if (err < 0)
1678 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1679 dc->clk, state->pclk, err);
1680 }
1681
1682 static void tegra_dc_stop(struct tegra_dc *dc)
1683 {
1684 u32 value;
1685
1686 /* stop the display controller */
1687 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1688 value &= ~DISP_CTRL_MODE_MASK;
1689 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1690
1691 tegra_dc_commit(dc);
1692 }
1693
1694 static bool tegra_dc_idle(struct tegra_dc *dc)
1695 {
1696 u32 value;
1697
1698 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1699
1700 return (value & DISP_CTRL_MODE_MASK) == 0;
1701 }
1702
1703 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1704 {
1705 timeout = jiffies + msecs_to_jiffies(timeout);
1706
1707 while (time_before(jiffies, timeout)) {
1708 if (tegra_dc_idle(dc))
1709 return 0;
1710
1711 usleep_range(1000, 2000);
1712 }
1713
1714 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1715 return -ETIMEDOUT;
1716 }
1717
1718 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1719 struct drm_crtc_state *old_state)
1720 {
1721 struct tegra_dc *dc = to_tegra_dc(crtc);
1722 u32 value;
1723
1724 if (!tegra_dc_idle(dc)) {
1725 tegra_dc_stop(dc);
1726
1727 /*
1728 * Ignore the return value, there isn't anything useful to do
1729 * in case this fails.
1730 */
1731 tegra_dc_wait_idle(dc, 100);
1732 }
1733
1734 /*
1735 * This should really be part of the RGB encoder driver, but clearing
1736 * these bits has the side-effect of stopping the display controller.
1737 * When that happens no VBLANK interrupts will be raised. At the same
1738 * time the encoder is disabled before the display controller, so the
1739 * above code is always going to timeout waiting for the controller
1740 * to go idle.
1741 *
1742 * Given the close coupling between the RGB encoder and the display
1743 * controller doing it here is still kind of okay. None of the other
1744 * encoder drivers require these bits to be cleared.
1745 *
1746 * XXX: Perhaps given that the display controller is switched off at
1747 * this point anyway maybe clearing these bits isn't even useful for
1748 * the RGB encoder?
1749 */
1750 if (dc->rgb) {
1751 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1752 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1753 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1754 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1755 }
1756
1757 tegra_dc_stats_reset(&dc->stats);
1758 drm_crtc_vblank_off(crtc);
1759
1760 spin_lock_irq(&crtc->dev->event_lock);
1761
1762 if (crtc->state->event) {
1763 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1764 crtc->state->event = NULL;
1765 }
1766
1767 spin_unlock_irq(&crtc->dev->event_lock);
1768
1769 pm_runtime_put_sync(dc->dev);
1770 }
1771
1772 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1773 struct drm_crtc_state *old_state)
1774 {
1775 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1776 struct tegra_dc_state *state = to_dc_state(crtc->state);
1777 struct tegra_dc *dc = to_tegra_dc(crtc);
1778 u32 value;
1779
1780 pm_runtime_get_sync(dc->dev);
1781
1782 /* initialize display controller */
1783 if (dc->syncpt) {
1784 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
1785
1786 if (dc->soc->has_nvdisplay)
1787 enable = 1 << 31;
1788 else
1789 enable = 1 << 8;
1790
1791 value = SYNCPT_CNTRL_NO_STALL;
1792 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1793
1794 value = enable | syncpt;
1795 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1796 }
1797
1798 if (dc->soc->has_nvdisplay) {
1799 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1800 DSC_OBUF_UF_INT;
1801 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1802
1803 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1804 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
1805 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
1806 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
1807 VBLANK_INT | FRAME_END_INT;
1808 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1809
1810 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1811 FRAME_END_INT;
1812 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1813
1814 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1815 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1816
1817 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
1818 } else {
1819 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1820 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1821 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1822
1823 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1824 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1825 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1826
1827 /* initialize timer */
1828 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1829 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1830 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1831
1832 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1833 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1834 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1835
1836 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1837 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1838 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1839
1840 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1841 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1842 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1843 }
1844
1845 if (dc->soc->supports_background_color)
1846 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
1847 else
1848 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1849
1850 /* apply PLL and pixel clock changes */
1851 tegra_dc_commit_state(dc, state);
1852
1853 /* program display mode */
1854 tegra_dc_set_timings(dc, mode);
1855
1856 /* interlacing isn't supported yet, so disable it */
1857 if (dc->soc->supports_interlacing) {
1858 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1859 value &= ~INTERLACE_ENABLE;
1860 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1861 }
1862
1863 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1864 value &= ~DISP_CTRL_MODE_MASK;
1865 value |= DISP_CTRL_MODE_C_DISPLAY;
1866 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1867
1868 if (!dc->soc->has_nvdisplay) {
1869 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1870 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1871 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1872 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1873 }
1874
1875 /* enable underflow reporting and display red for missing pixels */
1876 if (dc->soc->has_nvdisplay) {
1877 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1878 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1879 }
1880
1881 tegra_dc_commit(dc);
1882
1883 drm_crtc_vblank_on(crtc);
1884 }
1885
1886 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1887 struct drm_crtc_state *old_crtc_state)
1888 {
1889 unsigned long flags;
1890
1891 if (crtc->state->event) {
1892 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1893
1894 if (drm_crtc_vblank_get(crtc) != 0)
1895 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1896 else
1897 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
1898
1899 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1900
1901 crtc->state->event = NULL;
1902 }
1903 }
1904
1905 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1906 struct drm_crtc_state *old_crtc_state)
1907 {
1908 struct tegra_dc_state *state = to_dc_state(crtc->state);
1909 struct tegra_dc *dc = to_tegra_dc(crtc);
1910 u32 value;
1911
1912 value = state->planes << 8 | GENERAL_UPDATE;
1913 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1914 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1915
1916 value = state->planes | GENERAL_ACT_REQ;
1917 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1918 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1919 }
1920
1921 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1922 .atomic_begin = tegra_crtc_atomic_begin,
1923 .atomic_flush = tegra_crtc_atomic_flush,
1924 .atomic_enable = tegra_crtc_atomic_enable,
1925 .atomic_disable = tegra_crtc_atomic_disable,
1926 };
1927
1928 static irqreturn_t tegra_dc_irq(int irq, void *data)
1929 {
1930 struct tegra_dc *dc = data;
1931 unsigned long status;
1932
1933 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1934 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1935
1936 if (status & FRAME_END_INT) {
1937 /*
1938 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1939 */
1940 dc->stats.frames++;
1941 }
1942
1943 if (status & VBLANK_INT) {
1944 /*
1945 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1946 */
1947 drm_crtc_handle_vblank(&dc->base);
1948 dc->stats.vblank++;
1949 }
1950
1951 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1952 /*
1953 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1954 */
1955 dc->stats.underflow++;
1956 }
1957
1958 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1959 /*
1960 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1961 */
1962 dc->stats.overflow++;
1963 }
1964
1965 if (status & HEAD_UF_INT) {
1966 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
1967 dc->stats.underflow++;
1968 }
1969
1970 return IRQ_HANDLED;
1971 }
1972
1973 static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
1974 {
1975 unsigned int i;
1976
1977 if (!dc->soc->wgrps)
1978 return true;
1979
1980 for (i = 0; i < dc->soc->num_wgrps; i++) {
1981 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1982
1983 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
1984 return true;
1985 }
1986
1987 return false;
1988 }
1989
1990 static int tegra_dc_init(struct host1x_client *client)
1991 {
1992 struct drm_device *drm = dev_get_drvdata(client->parent);
1993 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1994 struct tegra_dc *dc = host1x_client_to_dc(client);
1995 struct tegra_drm *tegra = drm->dev_private;
1996 struct drm_plane *primary = NULL;
1997 struct drm_plane *cursor = NULL;
1998 int err;
1999
2000 /*
2001 * XXX do not register DCs with no window groups because we cannot
2002 * assign a primary plane to them, which in turn will cause KMS to
2003 * crash.
2004 */
2005 if (!tegra_dc_has_window_groups(dc))
2006 return 0;
2007
2008 dc->syncpt = host1x_syncpt_request(client, flags);
2009 if (!dc->syncpt)
2010 dev_warn(dc->dev, "failed to allocate syncpoint\n");
2011
2012 dc->group = host1x_client_iommu_attach(client, true);
2013 if (IS_ERR(dc->group)) {
2014 err = PTR_ERR(dc->group);
2015 dev_err(client->dev, "failed to attach to domain: %d\n", err);
2016 return err;
2017 }
2018
2019 if (dc->soc->wgrps)
2020 primary = tegra_dc_add_shared_planes(drm, dc);
2021 else
2022 primary = tegra_dc_add_planes(drm, dc);
2023
2024 if (IS_ERR(primary)) {
2025 err = PTR_ERR(primary);
2026 goto cleanup;
2027 }
2028
2029 if (dc->soc->supports_cursor) {
2030 cursor = tegra_dc_cursor_plane_create(drm, dc);
2031 if (IS_ERR(cursor)) {
2032 err = PTR_ERR(cursor);
2033 goto cleanup;
2034 }
2035 } else {
2036 /* dedicate one overlay to mouse cursor */
2037 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2038 if (IS_ERR(cursor)) {
2039 err = PTR_ERR(cursor);
2040 goto cleanup;
2041 }
2042 }
2043
2044 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2045 &tegra_crtc_funcs, NULL);
2046 if (err < 0)
2047 goto cleanup;
2048
2049 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2050
2051 /*
2052 * Keep track of the minimum pitch alignment across all display
2053 * controllers.
2054 */
2055 if (dc->soc->pitch_align > tegra->pitch_align)
2056 tegra->pitch_align = dc->soc->pitch_align;
2057
2058 err = tegra_dc_rgb_init(drm, dc);
2059 if (err < 0 && err != -ENODEV) {
2060 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2061 goto cleanup;
2062 }
2063
2064 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2065 dev_name(dc->dev), dc);
2066 if (err < 0) {
2067 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2068 err);
2069 goto cleanup;
2070 }
2071
2072 return 0;
2073
2074 cleanup:
2075 if (!IS_ERR_OR_NULL(cursor))
2076 drm_plane_cleanup(cursor);
2077
2078 if (!IS_ERR(primary))
2079 drm_plane_cleanup(primary);
2080
2081 host1x_client_iommu_detach(client, dc->group);
2082 host1x_syncpt_free(dc->syncpt);
2083
2084 return err;
2085 }
2086
2087 static int tegra_dc_exit(struct host1x_client *client)
2088 {
2089 struct tegra_dc *dc = host1x_client_to_dc(client);
2090 int err;
2091
2092 if (!tegra_dc_has_window_groups(dc))
2093 return 0;
2094
2095 devm_free_irq(dc->dev, dc->irq, dc);
2096
2097 err = tegra_dc_rgb_exit(dc);
2098 if (err) {
2099 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2100 return err;
2101 }
2102
2103 host1x_client_iommu_detach(client, dc->group);
2104 host1x_syncpt_free(dc->syncpt);
2105
2106 return 0;
2107 }
2108
2109 static const struct host1x_client_ops dc_client_ops = {
2110 .init = tegra_dc_init,
2111 .exit = tegra_dc_exit,
2112 };
2113
2114 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2115 .supports_background_color = false,
2116 .supports_interlacing = false,
2117 .supports_cursor = false,
2118 .supports_block_linear = false,
2119 .has_legacy_blending = true,
2120 .pitch_align = 8,
2121 .has_powergate = false,
2122 .coupled_pm = true,
2123 .has_nvdisplay = false,
2124 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2125 .primary_formats = tegra20_primary_formats,
2126 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2127 .overlay_formats = tegra20_overlay_formats,
2128 .modifiers = tegra20_modifiers,
2129 .has_win_a_without_filters = true,
2130 .has_win_c_without_vert_filter = true,
2131 };
2132
2133 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2134 .supports_background_color = false,
2135 .supports_interlacing = false,
2136 .supports_cursor = false,
2137 .supports_block_linear = false,
2138 .has_legacy_blending = true,
2139 .pitch_align = 8,
2140 .has_powergate = false,
2141 .coupled_pm = false,
2142 .has_nvdisplay = false,
2143 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2144 .primary_formats = tegra20_primary_formats,
2145 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2146 .overlay_formats = tegra20_overlay_formats,
2147 .modifiers = tegra20_modifiers,
2148 .has_win_a_without_filters = false,
2149 .has_win_c_without_vert_filter = false,
2150 };
2151
2152 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2153 .supports_background_color = false,
2154 .supports_interlacing = false,
2155 .supports_cursor = false,
2156 .supports_block_linear = false,
2157 .has_legacy_blending = true,
2158 .pitch_align = 64,
2159 .has_powergate = true,
2160 .coupled_pm = false,
2161 .has_nvdisplay = false,
2162 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2163 .primary_formats = tegra114_primary_formats,
2164 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2165 .overlay_formats = tegra114_overlay_formats,
2166 .modifiers = tegra20_modifiers,
2167 .has_win_a_without_filters = false,
2168 .has_win_c_without_vert_filter = false,
2169 };
2170
2171 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2172 .supports_background_color = true,
2173 .supports_interlacing = true,
2174 .supports_cursor = true,
2175 .supports_block_linear = true,
2176 .has_legacy_blending = false,
2177 .pitch_align = 64,
2178 .has_powergate = true,
2179 .coupled_pm = false,
2180 .has_nvdisplay = false,
2181 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2182 .primary_formats = tegra124_primary_formats,
2183 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2184 .overlay_formats = tegra124_overlay_formats,
2185 .modifiers = tegra124_modifiers,
2186 .has_win_a_without_filters = false,
2187 .has_win_c_without_vert_filter = false,
2188 };
2189
2190 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2191 .supports_background_color = true,
2192 .supports_interlacing = true,
2193 .supports_cursor = true,
2194 .supports_block_linear = true,
2195 .has_legacy_blending = false,
2196 .pitch_align = 64,
2197 .has_powergate = true,
2198 .coupled_pm = false,
2199 .has_nvdisplay = false,
2200 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2201 .primary_formats = tegra114_primary_formats,
2202 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2203 .overlay_formats = tegra114_overlay_formats,
2204 .modifiers = tegra124_modifiers,
2205 .has_win_a_without_filters = false,
2206 .has_win_c_without_vert_filter = false,
2207 };
2208
2209 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2210 {
2211 .index = 0,
2212 .dc = 0,
2213 .windows = (const unsigned int[]) { 0 },
2214 .num_windows = 1,
2215 }, {
2216 .index = 1,
2217 .dc = 1,
2218 .windows = (const unsigned int[]) { 1 },
2219 .num_windows = 1,
2220 }, {
2221 .index = 2,
2222 .dc = 1,
2223 .windows = (const unsigned int[]) { 2 },
2224 .num_windows = 1,
2225 }, {
2226 .index = 3,
2227 .dc = 2,
2228 .windows = (const unsigned int[]) { 3 },
2229 .num_windows = 1,
2230 }, {
2231 .index = 4,
2232 .dc = 2,
2233 .windows = (const unsigned int[]) { 4 },
2234 .num_windows = 1,
2235 }, {
2236 .index = 5,
2237 .dc = 2,
2238 .windows = (const unsigned int[]) { 5 },
2239 .num_windows = 1,
2240 },
2241 };
2242
2243 static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2244 .supports_background_color = true,
2245 .supports_interlacing = true,
2246 .supports_cursor = true,
2247 .supports_block_linear = true,
2248 .has_legacy_blending = false,
2249 .pitch_align = 64,
2250 .has_powergate = false,
2251 .coupled_pm = false,
2252 .has_nvdisplay = true,
2253 .wgrps = tegra186_dc_wgrps,
2254 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2255 };
2256
2257 static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
2258 {
2259 .index = 0,
2260 .dc = 0,
2261 .windows = (const unsigned int[]) { 0 },
2262 .num_windows = 1,
2263 }, {
2264 .index = 1,
2265 .dc = 1,
2266 .windows = (const unsigned int[]) { 1 },
2267 .num_windows = 1,
2268 }, {
2269 .index = 2,
2270 .dc = 1,
2271 .windows = (const unsigned int[]) { 2 },
2272 .num_windows = 1,
2273 }, {
2274 .index = 3,
2275 .dc = 2,
2276 .windows = (const unsigned int[]) { 3 },
2277 .num_windows = 1,
2278 }, {
2279 .index = 4,
2280 .dc = 2,
2281 .windows = (const unsigned int[]) { 4 },
2282 .num_windows = 1,
2283 }, {
2284 .index = 5,
2285 .dc = 2,
2286 .windows = (const unsigned int[]) { 5 },
2287 .num_windows = 1,
2288 },
2289 };
2290
2291 static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
2292 .supports_background_color = true,
2293 .supports_interlacing = true,
2294 .supports_cursor = true,
2295 .supports_block_linear = true,
2296 .has_legacy_blending = false,
2297 .pitch_align = 64,
2298 .has_powergate = false,
2299 .coupled_pm = false,
2300 .has_nvdisplay = true,
2301 .wgrps = tegra194_dc_wgrps,
2302 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
2303 };
2304
2305 static const struct of_device_id tegra_dc_of_match[] = {
2306 {
2307 .compatible = "nvidia,tegra194-dc",
2308 .data = &tegra194_dc_soc_info,
2309 }, {
2310 .compatible = "nvidia,tegra186-dc",
2311 .data = &tegra186_dc_soc_info,
2312 }, {
2313 .compatible = "nvidia,tegra210-dc",
2314 .data = &tegra210_dc_soc_info,
2315 }, {
2316 .compatible = "nvidia,tegra124-dc",
2317 .data = &tegra124_dc_soc_info,
2318 }, {
2319 .compatible = "nvidia,tegra114-dc",
2320 .data = &tegra114_dc_soc_info,
2321 }, {
2322 .compatible = "nvidia,tegra30-dc",
2323 .data = &tegra30_dc_soc_info,
2324 }, {
2325 .compatible = "nvidia,tegra20-dc",
2326 .data = &tegra20_dc_soc_info,
2327 }, {
2328 /* sentinel */
2329 }
2330 };
2331 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
2332
2333 static int tegra_dc_parse_dt(struct tegra_dc *dc)
2334 {
2335 struct device_node *np;
2336 u32 value = 0;
2337 int err;
2338
2339 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
2340 if (err < 0) {
2341 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
2342
2343 /*
2344 * If the nvidia,head property isn't present, try to find the
2345 * correct head number by looking up the position of this
2346 * display controller's node within the device tree. Assuming
2347 * that the nodes are ordered properly in the DTS file and
2348 * that the translation into a flattened device tree blob
2349 * preserves that ordering this will actually yield the right
2350 * head number.
2351 *
2352 * If those assumptions don't hold, this will still work for
2353 * cases where only a single display controller is used.
2354 */
2355 for_each_matching_node(np, tegra_dc_of_match) {
2356 if (np == dc->dev->of_node) {
2357 of_node_put(np);
2358 break;
2359 }
2360
2361 value++;
2362 }
2363 }
2364
2365 dc->pipe = value;
2366
2367 return 0;
2368 }
2369
2370 static int tegra_dc_match_by_pipe(struct device *dev, const void *data)
2371 {
2372 struct tegra_dc *dc = dev_get_drvdata(dev);
2373 unsigned int pipe = (unsigned long)(void *)data;
2374
2375 return dc->pipe == pipe;
2376 }
2377
2378 static int tegra_dc_couple(struct tegra_dc *dc)
2379 {
2380 /*
2381 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
2382 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
2383 * POWER_CONTROL registers during CRTC enabling.
2384 */
2385 if (dc->soc->coupled_pm && dc->pipe == 1) {
2386 u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_CONSUMER;
2387 struct device_link *link;
2388 struct device *partner;
2389
2390 partner = driver_find_device(dc->dev->driver, NULL, NULL,
2391 tegra_dc_match_by_pipe);
2392 if (!partner)
2393 return -EPROBE_DEFER;
2394
2395 link = device_link_add(dc->dev, partner, flags);
2396 if (!link) {
2397 dev_err(dc->dev, "failed to link controllers\n");
2398 return -EINVAL;
2399 }
2400
2401 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));
2402 }
2403
2404 return 0;
2405 }
2406
2407 static int tegra_dc_probe(struct platform_device *pdev)
2408 {
2409 struct resource *regs;
2410 struct tegra_dc *dc;
2411 int err;
2412
2413 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
2414 if (!dc)
2415 return -ENOMEM;
2416
2417 dc->soc = of_device_get_match_data(&pdev->dev);
2418
2419 INIT_LIST_HEAD(&dc->list);
2420 dc->dev = &pdev->dev;
2421
2422 err = tegra_dc_parse_dt(dc);
2423 if (err < 0)
2424 return err;
2425
2426 err = tegra_dc_couple(dc);
2427 if (err < 0)
2428 return err;
2429
2430 dc->clk = devm_clk_get(&pdev->dev, NULL);
2431 if (IS_ERR(dc->clk)) {
2432 dev_err(&pdev->dev, "failed to get clock\n");
2433 return PTR_ERR(dc->clk);
2434 }
2435
2436 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2437 if (IS_ERR(dc->rst)) {
2438 dev_err(&pdev->dev, "failed to get reset\n");
2439 return PTR_ERR(dc->rst);
2440 }
2441
2442 /* assert reset and disable clock */
2443 err = clk_prepare_enable(dc->clk);
2444 if (err < 0)
2445 return err;
2446
2447 usleep_range(2000, 4000);
2448
2449 err = reset_control_assert(dc->rst);
2450 if (err < 0)
2451 return err;
2452
2453 usleep_range(2000, 4000);
2454
2455 clk_disable_unprepare(dc->clk);
2456
2457 if (dc->soc->has_powergate) {
2458 if (dc->pipe == 0)
2459 dc->powergate = TEGRA_POWERGATE_DIS;
2460 else
2461 dc->powergate = TEGRA_POWERGATE_DISB;
2462
2463 tegra_powergate_power_off(dc->powergate);
2464 }
2465
2466 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2467 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2468 if (IS_ERR(dc->regs))
2469 return PTR_ERR(dc->regs);
2470
2471 dc->irq = platform_get_irq(pdev, 0);
2472 if (dc->irq < 0) {
2473 dev_err(&pdev->dev, "failed to get IRQ\n");
2474 return -ENXIO;
2475 }
2476
2477 err = tegra_dc_rgb_probe(dc);
2478 if (err < 0 && err != -ENODEV) {
2479 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2480 return err;
2481 }
2482
2483 platform_set_drvdata(pdev, dc);
2484 pm_runtime_enable(&pdev->dev);
2485
2486 INIT_LIST_HEAD(&dc->client.list);
2487 dc->client.ops = &dc_client_ops;
2488 dc->client.dev = &pdev->dev;
2489
2490 err = host1x_client_register(&dc->client);
2491 if (err < 0) {
2492 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2493 err);
2494 return err;
2495 }
2496
2497 return 0;
2498 }
2499
2500 static int tegra_dc_remove(struct platform_device *pdev)
2501 {
2502 struct tegra_dc *dc = platform_get_drvdata(pdev);
2503 int err;
2504
2505 err = host1x_client_unregister(&dc->client);
2506 if (err < 0) {
2507 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2508 err);
2509 return err;
2510 }
2511
2512 err = tegra_dc_rgb_remove(dc);
2513 if (err < 0) {
2514 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2515 return err;
2516 }
2517
2518 pm_runtime_disable(&pdev->dev);
2519
2520 return 0;
2521 }
2522
2523 #ifdef CONFIG_PM
2524 static int tegra_dc_suspend(struct device *dev)
2525 {
2526 struct tegra_dc *dc = dev_get_drvdata(dev);
2527 int err;
2528
2529 err = reset_control_assert(dc->rst);
2530 if (err < 0) {
2531 dev_err(dev, "failed to assert reset: %d\n", err);
2532 return err;
2533 }
2534
2535 if (dc->soc->has_powergate)
2536 tegra_powergate_power_off(dc->powergate);
2537
2538 clk_disable_unprepare(dc->clk);
2539
2540 return 0;
2541 }
2542
2543 static int tegra_dc_resume(struct device *dev)
2544 {
2545 struct tegra_dc *dc = dev_get_drvdata(dev);
2546 int err;
2547
2548 if (dc->soc->has_powergate) {
2549 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2550 dc->rst);
2551 if (err < 0) {
2552 dev_err(dev, "failed to power partition: %d\n", err);
2553 return err;
2554 }
2555 } else {
2556 err = clk_prepare_enable(dc->clk);
2557 if (err < 0) {
2558 dev_err(dev, "failed to enable clock: %d\n", err);
2559 return err;
2560 }
2561
2562 err = reset_control_deassert(dc->rst);
2563 if (err < 0) {
2564 dev_err(dev, "failed to deassert reset: %d\n", err);
2565 return err;
2566 }
2567 }
2568
2569 return 0;
2570 }
2571 #endif
2572
2573 static const struct dev_pm_ops tegra_dc_pm_ops = {
2574 SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
2575 };
2576
2577 struct platform_driver tegra_dc_driver = {
2578 .driver = {
2579 .name = "tegra-dc",
2580 .of_match_table = tegra_dc_of_match,
2581 .pm = &tegra_dc_pm_ops,
2582 },
2583 .probe = tegra_dc_probe,
2584 .remove = tegra_dc_remove,
2585 };
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