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drm/tegra: Add support for tiled buffer objects
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / tegra / dc.c
1 /*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/clk/tegra.h>
12 #include <linux/debugfs.h>
13
14 #include "dc.h"
15 #include "drm.h"
16 #include "gem.h"
17
18 struct tegra_plane {
19 struct drm_plane base;
20 unsigned int index;
21 };
22
23 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
24 {
25 return container_of(plane, struct tegra_plane, base);
26 }
27
28 static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
29 struct drm_framebuffer *fb, int crtc_x,
30 int crtc_y, unsigned int crtc_w,
31 unsigned int crtc_h, uint32_t src_x,
32 uint32_t src_y, uint32_t src_w, uint32_t src_h)
33 {
34 struct tegra_plane *p = to_tegra_plane(plane);
35 struct tegra_dc *dc = to_tegra_dc(crtc);
36 struct tegra_dc_window window;
37 unsigned int i;
38
39 memset(&window, 0, sizeof(window));
40 window.src.x = src_x >> 16;
41 window.src.y = src_y >> 16;
42 window.src.w = src_w >> 16;
43 window.src.h = src_h >> 16;
44 window.dst.x = crtc_x;
45 window.dst.y = crtc_y;
46 window.dst.w = crtc_w;
47 window.dst.h = crtc_h;
48 window.format = tegra_dc_format(fb->pixel_format);
49 window.bits_per_pixel = fb->bits_per_pixel;
50 window.tiled = tegra_fb_is_tiled(fb);
51
52 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
53 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
54
55 window.base[i] = bo->paddr + fb->offsets[i];
56
57 /*
58 * Tegra doesn't support different strides for U and V planes
59 * so we display a warning if the user tries to display a
60 * framebuffer with such a configuration.
61 */
62 if (i >= 2) {
63 if (fb->pitches[i] != window.stride[1])
64 DRM_ERROR("unsupported UV-plane configuration\n");
65 } else {
66 window.stride[i] = fb->pitches[i];
67 }
68 }
69
70 return tegra_dc_setup_window(dc, p->index, &window);
71 }
72
73 static int tegra_plane_disable(struct drm_plane *plane)
74 {
75 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
76 struct tegra_plane *p = to_tegra_plane(plane);
77 unsigned long value;
78
79 if (!plane->crtc)
80 return 0;
81
82 value = WINDOW_A_SELECT << p->index;
83 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
84
85 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
86 value &= ~WIN_ENABLE;
87 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
88
89 tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL);
90 tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL);
91
92 return 0;
93 }
94
95 static void tegra_plane_destroy(struct drm_plane *plane)
96 {
97 struct tegra_plane *p = to_tegra_plane(plane);
98
99 tegra_plane_disable(plane);
100 drm_plane_cleanup(plane);
101 kfree(p);
102 }
103
104 static const struct drm_plane_funcs tegra_plane_funcs = {
105 .update_plane = tegra_plane_update,
106 .disable_plane = tegra_plane_disable,
107 .destroy = tegra_plane_destroy,
108 };
109
110 static const uint32_t plane_formats[] = {
111 DRM_FORMAT_XBGR8888,
112 DRM_FORMAT_XRGB8888,
113 DRM_FORMAT_RGB565,
114 DRM_FORMAT_UYVY,
115 DRM_FORMAT_YUV420,
116 DRM_FORMAT_YUV422,
117 };
118
119 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
120 {
121 unsigned int i;
122 int err = 0;
123
124 for (i = 0; i < 2; i++) {
125 struct tegra_plane *plane;
126
127 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
128 if (!plane)
129 return -ENOMEM;
130
131 plane->index = 1 + i;
132
133 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
134 &tegra_plane_funcs, plane_formats,
135 ARRAY_SIZE(plane_formats), false);
136 if (err < 0) {
137 kfree(plane);
138 return err;
139 }
140 }
141
142 return 0;
143 }
144
145 static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
146 struct drm_framebuffer *fb)
147 {
148 unsigned int format = tegra_dc_format(fb->pixel_format);
149 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
150 unsigned long value;
151
152 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
153
154 value = fb->offsets[0] + y * fb->pitches[0] +
155 x * fb->bits_per_pixel / 8;
156
157 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
158 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
159 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
160
161 if (tegra_fb_is_tiled(fb)) {
162 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
163 DC_WIN_BUFFER_ADDR_MODE_TILE;
164 } else {
165 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
166 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
167 }
168
169 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
170
171 value = GENERAL_UPDATE | WIN_A_UPDATE;
172 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
173
174 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
175 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
176
177 return 0;
178 }
179
180 void tegra_dc_enable_vblank(struct tegra_dc *dc)
181 {
182 unsigned long value, flags;
183
184 spin_lock_irqsave(&dc->lock, flags);
185
186 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
187 value |= VBLANK_INT;
188 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
189
190 spin_unlock_irqrestore(&dc->lock, flags);
191 }
192
193 void tegra_dc_disable_vblank(struct tegra_dc *dc)
194 {
195 unsigned long value, flags;
196
197 spin_lock_irqsave(&dc->lock, flags);
198
199 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
200 value &= ~VBLANK_INT;
201 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
202
203 spin_unlock_irqrestore(&dc->lock, flags);
204 }
205
206 static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
207 {
208 struct drm_device *drm = dc->base.dev;
209 struct drm_crtc *crtc = &dc->base;
210 unsigned long flags, base;
211 struct tegra_bo *bo;
212
213 if (!dc->event)
214 return;
215
216 bo = tegra_fb_get_plane(crtc->fb, 0);
217
218 /* check if new start address has been latched */
219 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
220 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
221 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
222
223 if (base == bo->paddr + crtc->fb->offsets[0]) {
224 spin_lock_irqsave(&drm->event_lock, flags);
225 drm_send_vblank_event(drm, dc->pipe, dc->event);
226 drm_vblank_put(drm, dc->pipe);
227 dc->event = NULL;
228 spin_unlock_irqrestore(&drm->event_lock, flags);
229 }
230 }
231
232 void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
233 {
234 struct tegra_dc *dc = to_tegra_dc(crtc);
235 struct drm_device *drm = crtc->dev;
236 unsigned long flags;
237
238 spin_lock_irqsave(&drm->event_lock, flags);
239
240 if (dc->event && dc->event->base.file_priv == file) {
241 dc->event->base.destroy(&dc->event->base);
242 drm_vblank_put(drm, dc->pipe);
243 dc->event = NULL;
244 }
245
246 spin_unlock_irqrestore(&drm->event_lock, flags);
247 }
248
249 static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
250 struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
251 {
252 struct tegra_dc *dc = to_tegra_dc(crtc);
253 struct drm_device *drm = crtc->dev;
254
255 if (dc->event)
256 return -EBUSY;
257
258 if (event) {
259 event->pipe = dc->pipe;
260 dc->event = event;
261 drm_vblank_get(drm, dc->pipe);
262 }
263
264 tegra_dc_set_base(dc, 0, 0, fb);
265 crtc->fb = fb;
266
267 return 0;
268 }
269
270 static void drm_crtc_clear(struct drm_crtc *crtc)
271 {
272 memset(crtc, 0, sizeof(*crtc));
273 }
274
275 static void tegra_dc_destroy(struct drm_crtc *crtc)
276 {
277 drm_crtc_cleanup(crtc);
278 drm_crtc_clear(crtc);
279 }
280
281 static const struct drm_crtc_funcs tegra_crtc_funcs = {
282 .page_flip = tegra_dc_page_flip,
283 .set_config = drm_crtc_helper_set_config,
284 .destroy = tegra_dc_destroy,
285 };
286
287 static void tegra_crtc_disable(struct drm_crtc *crtc)
288 {
289 struct tegra_dc *dc = to_tegra_dc(crtc);
290 struct drm_device *drm = crtc->dev;
291 struct drm_plane *plane;
292
293 list_for_each_entry(plane, &drm->mode_config.plane_list, head) {
294 if (plane->crtc == crtc) {
295 tegra_plane_disable(plane);
296 plane->crtc = NULL;
297
298 if (plane->fb) {
299 drm_framebuffer_unreference(plane->fb);
300 plane->fb = NULL;
301 }
302 }
303 }
304
305 drm_vblank_off(drm, dc->pipe);
306 }
307
308 static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
309 const struct drm_display_mode *mode,
310 struct drm_display_mode *adjusted)
311 {
312 return true;
313 }
314
315 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
316 unsigned int bpp)
317 {
318 fixed20_12 outf = dfixed_init(out);
319 fixed20_12 inf = dfixed_init(in);
320 u32 dda_inc;
321 int max;
322
323 if (v)
324 max = 15;
325 else {
326 switch (bpp) {
327 case 2:
328 max = 8;
329 break;
330
331 default:
332 WARN_ON_ONCE(1);
333 /* fallthrough */
334 case 4:
335 max = 4;
336 break;
337 }
338 }
339
340 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
341 inf.full -= dfixed_const(1);
342
343 dda_inc = dfixed_div(inf, outf);
344 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
345
346 return dda_inc;
347 }
348
349 static inline u32 compute_initial_dda(unsigned int in)
350 {
351 fixed20_12 inf = dfixed_init(in);
352 return dfixed_frac(inf);
353 }
354
355 static int tegra_dc_set_timings(struct tegra_dc *dc,
356 struct drm_display_mode *mode)
357 {
358 /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
359 unsigned int h_ref_to_sync = 0;
360 unsigned int v_ref_to_sync = 0;
361 unsigned long value;
362
363 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
364
365 value = (v_ref_to_sync << 16) | h_ref_to_sync;
366 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
367
368 value = ((mode->vsync_end - mode->vsync_start) << 16) |
369 ((mode->hsync_end - mode->hsync_start) << 0);
370 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
371
372 value = ((mode->vtotal - mode->vsync_end) << 16) |
373 ((mode->htotal - mode->hsync_end) << 0);
374 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
375
376 value = ((mode->vsync_start - mode->vdisplay) << 16) |
377 ((mode->hsync_start - mode->hdisplay) << 0);
378 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
379
380 value = (mode->vdisplay << 16) | mode->hdisplay;
381 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
382
383 return 0;
384 }
385
386 static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
387 struct drm_display_mode *mode,
388 unsigned long *div)
389 {
390 unsigned long pclk = mode->clock * 1000, rate;
391 struct tegra_dc *dc = to_tegra_dc(crtc);
392 struct tegra_output *output = NULL;
393 struct drm_encoder *encoder;
394 long err;
395
396 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
397 if (encoder->crtc == crtc) {
398 output = encoder_to_output(encoder);
399 break;
400 }
401
402 if (!output)
403 return -ENODEV;
404
405 /*
406 * This assumes that the display controller will divide its parent
407 * clock by 2 to generate the pixel clock.
408 */
409 err = tegra_output_setup_clock(output, dc->clk, pclk * 2);
410 if (err < 0) {
411 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
412 return err;
413 }
414
415 rate = clk_get_rate(dc->clk);
416 *div = (rate * 2 / pclk) - 2;
417
418 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
419
420 return 0;
421 }
422
423 static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
424 {
425 switch (format) {
426 case WIN_COLOR_DEPTH_YCbCr422:
427 case WIN_COLOR_DEPTH_YUV422:
428 if (planar)
429 *planar = false;
430
431 return true;
432
433 case WIN_COLOR_DEPTH_YCbCr420P:
434 case WIN_COLOR_DEPTH_YUV420P:
435 case WIN_COLOR_DEPTH_YCbCr422P:
436 case WIN_COLOR_DEPTH_YUV422P:
437 case WIN_COLOR_DEPTH_YCbCr422R:
438 case WIN_COLOR_DEPTH_YUV422R:
439 case WIN_COLOR_DEPTH_YCbCr422RA:
440 case WIN_COLOR_DEPTH_YUV422RA:
441 if (planar)
442 *planar = true;
443
444 return true;
445 }
446
447 return false;
448 }
449
450 int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
451 const struct tegra_dc_window *window)
452 {
453 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
454 unsigned long value;
455 bool yuv, planar;
456
457 /*
458 * For YUV planar modes, the number of bytes per pixel takes into
459 * account only the luma component and therefore is 1.
460 */
461 yuv = tegra_dc_format_is_yuv(window->format, &planar);
462 if (!yuv)
463 bpp = window->bits_per_pixel / 8;
464 else
465 bpp = planar ? 1 : 2;
466
467 value = WINDOW_A_SELECT << index;
468 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
469
470 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
471 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
472
473 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
474 tegra_dc_writel(dc, value, DC_WIN_POSITION);
475
476 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
477 tegra_dc_writel(dc, value, DC_WIN_SIZE);
478
479 h_offset = window->src.x * bpp;
480 v_offset = window->src.y;
481 h_size = window->src.w * bpp;
482 v_size = window->src.h;
483
484 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
485 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
486
487 /*
488 * For DDA computations the number of bytes per pixel for YUV planar
489 * modes needs to take into account all Y, U and V components.
490 */
491 if (yuv && planar)
492 bpp = 2;
493
494 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
495 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
496
497 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
498 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
499
500 h_dda = compute_initial_dda(window->src.x);
501 v_dda = compute_initial_dda(window->src.y);
502
503 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
504 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
505
506 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
507 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
508
509 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
510
511 if (yuv && planar) {
512 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
513 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
514 value = window->stride[1] << 16 | window->stride[0];
515 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
516 } else {
517 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
518 }
519
520 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
521 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
522
523 if (window->tiled) {
524 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
525 DC_WIN_BUFFER_ADDR_MODE_TILE;
526 } else {
527 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
528 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
529 }
530
531 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
532
533 value = WIN_ENABLE;
534
535 if (yuv) {
536 /* setup default colorspace conversion coefficients */
537 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
538 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
539 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
540 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
541 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
542 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
543 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
544 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
545
546 value |= CSC_ENABLE;
547 } else if (window->bits_per_pixel < 24) {
548 value |= COLOR_EXPAND;
549 }
550
551 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
552
553 /*
554 * Disable blending and assume Window A is the bottom-most window,
555 * Window C is the top-most window and Window B is in the middle.
556 */
557 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
558 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
559
560 switch (index) {
561 case 0:
562 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
563 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
564 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
565 break;
566
567 case 1:
568 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
569 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
570 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
571 break;
572
573 case 2:
574 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
575 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
576 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
577 break;
578 }
579
580 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
581 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
582
583 return 0;
584 }
585
586 unsigned int tegra_dc_format(uint32_t format)
587 {
588 switch (format) {
589 case DRM_FORMAT_XBGR8888:
590 return WIN_COLOR_DEPTH_R8G8B8A8;
591
592 case DRM_FORMAT_XRGB8888:
593 return WIN_COLOR_DEPTH_B8G8R8A8;
594
595 case DRM_FORMAT_RGB565:
596 return WIN_COLOR_DEPTH_B5G6R5;
597
598 case DRM_FORMAT_UYVY:
599 return WIN_COLOR_DEPTH_YCbCr422;
600
601 case DRM_FORMAT_YUV420:
602 return WIN_COLOR_DEPTH_YCbCr420P;
603
604 case DRM_FORMAT_YUV422:
605 return WIN_COLOR_DEPTH_YCbCr422P;
606
607 default:
608 break;
609 }
610
611 WARN(1, "unsupported pixel format %u, using default\n", format);
612 return WIN_COLOR_DEPTH_B8G8R8A8;
613 }
614
615 static int tegra_crtc_mode_set(struct drm_crtc *crtc,
616 struct drm_display_mode *mode,
617 struct drm_display_mode *adjusted,
618 int x, int y, struct drm_framebuffer *old_fb)
619 {
620 struct tegra_bo *bo = tegra_fb_get_plane(crtc->fb, 0);
621 struct tegra_dc *dc = to_tegra_dc(crtc);
622 struct tegra_dc_window window;
623 unsigned long div, value;
624 int err;
625
626 drm_vblank_pre_modeset(crtc->dev, dc->pipe);
627
628 err = tegra_crtc_setup_clk(crtc, mode, &div);
629 if (err) {
630 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
631 return err;
632 }
633
634 /* program display mode */
635 tegra_dc_set_timings(dc, mode);
636
637 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
638 tegra_dc_writel(dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
639
640 value = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY(1));
641 value &= ~LVS_OUTPUT_POLARITY_LOW;
642 value &= ~LHS_OUTPUT_POLARITY_LOW;
643 tegra_dc_writel(dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
644
645 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
646 DISP_ORDER_RED_BLUE;
647 tegra_dc_writel(dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
648
649 tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS);
650
651 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
652 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
653
654 /* setup window parameters */
655 memset(&window, 0, sizeof(window));
656 window.src.x = 0;
657 window.src.y = 0;
658 window.src.w = mode->hdisplay;
659 window.src.h = mode->vdisplay;
660 window.dst.x = 0;
661 window.dst.y = 0;
662 window.dst.w = mode->hdisplay;
663 window.dst.h = mode->vdisplay;
664 window.format = tegra_dc_format(crtc->fb->pixel_format);
665 window.bits_per_pixel = crtc->fb->bits_per_pixel;
666 window.stride[0] = crtc->fb->pitches[0];
667 window.base[0] = bo->paddr;
668
669 err = tegra_dc_setup_window(dc, 0, &window);
670 if (err < 0)
671 dev_err(dc->dev, "failed to enable root plane\n");
672
673 return 0;
674 }
675
676 static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
677 struct drm_framebuffer *old_fb)
678 {
679 struct tegra_dc *dc = to_tegra_dc(crtc);
680
681 return tegra_dc_set_base(dc, x, y, crtc->fb);
682 }
683
684 static void tegra_crtc_prepare(struct drm_crtc *crtc)
685 {
686 struct tegra_dc *dc = to_tegra_dc(crtc);
687 unsigned int syncpt;
688 unsigned long value;
689
690 /* hardware initialization */
691 tegra_periph_reset_deassert(dc->clk);
692 usleep_range(10000, 20000);
693
694 if (dc->pipe)
695 syncpt = SYNCPT_VBLANK1;
696 else
697 syncpt = SYNCPT_VBLANK0;
698
699 /* initialize display controller */
700 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
701 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
702
703 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
704 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
705
706 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
707 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
708 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
709
710 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
711 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
712 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
713
714 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
715 value |= DISP_CTRL_MODE_C_DISPLAY;
716 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
717
718 /* initialize timer */
719 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
720 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
721 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
722
723 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
724 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
725 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
726
727 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
728 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
729
730 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
731 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
732 }
733
734 static void tegra_crtc_commit(struct drm_crtc *crtc)
735 {
736 struct tegra_dc *dc = to_tegra_dc(crtc);
737 unsigned long value;
738
739 value = GENERAL_UPDATE | WIN_A_UPDATE;
740 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
741
742 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
743 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
744
745 drm_vblank_post_modeset(crtc->dev, dc->pipe);
746 }
747
748 static void tegra_crtc_load_lut(struct drm_crtc *crtc)
749 {
750 }
751
752 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
753 .disable = tegra_crtc_disable,
754 .mode_fixup = tegra_crtc_mode_fixup,
755 .mode_set = tegra_crtc_mode_set,
756 .mode_set_base = tegra_crtc_mode_set_base,
757 .prepare = tegra_crtc_prepare,
758 .commit = tegra_crtc_commit,
759 .load_lut = tegra_crtc_load_lut,
760 };
761
762 static irqreturn_t tegra_dc_irq(int irq, void *data)
763 {
764 struct tegra_dc *dc = data;
765 unsigned long status;
766
767 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
768 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
769
770 if (status & FRAME_END_INT) {
771 /*
772 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
773 */
774 }
775
776 if (status & VBLANK_INT) {
777 /*
778 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
779 */
780 drm_handle_vblank(dc->base.dev, dc->pipe);
781 tegra_dc_finish_page_flip(dc);
782 }
783
784 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
785 /*
786 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
787 */
788 }
789
790 return IRQ_HANDLED;
791 }
792
793 static int tegra_dc_show_regs(struct seq_file *s, void *data)
794 {
795 struct drm_info_node *node = s->private;
796 struct tegra_dc *dc = node->info_ent->data;
797
798 #define DUMP_REG(name) \
799 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
800 tegra_dc_readl(dc, name))
801
802 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
803 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
804 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
805 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
806 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
807 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
808 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
809 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
810 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
811 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
812 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
813 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
814 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
815 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
816 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
817 DUMP_REG(DC_CMD_SIGNAL_RAISE);
818 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
819 DUMP_REG(DC_CMD_INT_STATUS);
820 DUMP_REG(DC_CMD_INT_MASK);
821 DUMP_REG(DC_CMD_INT_ENABLE);
822 DUMP_REG(DC_CMD_INT_TYPE);
823 DUMP_REG(DC_CMD_INT_POLARITY);
824 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
825 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
826 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
827 DUMP_REG(DC_CMD_STATE_ACCESS);
828 DUMP_REG(DC_CMD_STATE_CONTROL);
829 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
830 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
831 DUMP_REG(DC_COM_CRC_CONTROL);
832 DUMP_REG(DC_COM_CRC_CHECKSUM);
833 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
834 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
835 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
836 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
837 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
838 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
839 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
840 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
841 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
842 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
843 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
844 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
845 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
846 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
847 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
848 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
849 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
850 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
851 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
852 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
853 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
854 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
855 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
856 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
857 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
858 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
859 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
860 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
861 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
862 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
863 DUMP_REG(DC_COM_SPI_CONTROL);
864 DUMP_REG(DC_COM_SPI_START_BYTE);
865 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
866 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
867 DUMP_REG(DC_COM_HSPI_CS_DC);
868 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
869 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
870 DUMP_REG(DC_COM_GPIO_CTRL);
871 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
872 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
873 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
874 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
875 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
876 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
877 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
878 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
879 DUMP_REG(DC_DISP_REF_TO_SYNC);
880 DUMP_REG(DC_DISP_SYNC_WIDTH);
881 DUMP_REG(DC_DISP_BACK_PORCH);
882 DUMP_REG(DC_DISP_ACTIVE);
883 DUMP_REG(DC_DISP_FRONT_PORCH);
884 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
885 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
886 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
887 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
888 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
889 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
890 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
891 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
892 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
893 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
894 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
895 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
896 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
897 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
898 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
899 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
900 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
901 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
902 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
903 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
904 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
905 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
906 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
907 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
908 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
909 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
910 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
911 DUMP_REG(DC_DISP_M0_CONTROL);
912 DUMP_REG(DC_DISP_M1_CONTROL);
913 DUMP_REG(DC_DISP_DI_CONTROL);
914 DUMP_REG(DC_DISP_PP_CONTROL);
915 DUMP_REG(DC_DISP_PP_SELECT_A);
916 DUMP_REG(DC_DISP_PP_SELECT_B);
917 DUMP_REG(DC_DISP_PP_SELECT_C);
918 DUMP_REG(DC_DISP_PP_SELECT_D);
919 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
920 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
921 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
922 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
923 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
924 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
925 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
926 DUMP_REG(DC_DISP_BORDER_COLOR);
927 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
928 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
929 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
930 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
931 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
932 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
933 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
934 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
935 DUMP_REG(DC_DISP_CURSOR_POSITION);
936 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
937 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
938 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
939 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
940 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
941 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
942 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
943 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
944 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
945 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
946 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
947 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
948 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
949 DUMP_REG(DC_DISP_SD_CONTROL);
950 DUMP_REG(DC_DISP_SD_CSC_COEFF);
951 DUMP_REG(DC_DISP_SD_LUT(0));
952 DUMP_REG(DC_DISP_SD_LUT(1));
953 DUMP_REG(DC_DISP_SD_LUT(2));
954 DUMP_REG(DC_DISP_SD_LUT(3));
955 DUMP_REG(DC_DISP_SD_LUT(4));
956 DUMP_REG(DC_DISP_SD_LUT(5));
957 DUMP_REG(DC_DISP_SD_LUT(6));
958 DUMP_REG(DC_DISP_SD_LUT(7));
959 DUMP_REG(DC_DISP_SD_LUT(8));
960 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
961 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
962 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
963 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
964 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
965 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
966 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
967 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
968 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
969 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
970 DUMP_REG(DC_DISP_SD_BL_TF(0));
971 DUMP_REG(DC_DISP_SD_BL_TF(1));
972 DUMP_REG(DC_DISP_SD_BL_TF(2));
973 DUMP_REG(DC_DISP_SD_BL_TF(3));
974 DUMP_REG(DC_DISP_SD_BL_CONTROL);
975 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
976 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
977 DUMP_REG(DC_WIN_WIN_OPTIONS);
978 DUMP_REG(DC_WIN_BYTE_SWAP);
979 DUMP_REG(DC_WIN_BUFFER_CONTROL);
980 DUMP_REG(DC_WIN_COLOR_DEPTH);
981 DUMP_REG(DC_WIN_POSITION);
982 DUMP_REG(DC_WIN_SIZE);
983 DUMP_REG(DC_WIN_PRESCALED_SIZE);
984 DUMP_REG(DC_WIN_H_INITIAL_DDA);
985 DUMP_REG(DC_WIN_V_INITIAL_DDA);
986 DUMP_REG(DC_WIN_DDA_INC);
987 DUMP_REG(DC_WIN_LINE_STRIDE);
988 DUMP_REG(DC_WIN_BUF_STRIDE);
989 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
990 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
991 DUMP_REG(DC_WIN_DV_CONTROL);
992 DUMP_REG(DC_WIN_BLEND_NOKEY);
993 DUMP_REG(DC_WIN_BLEND_1WIN);
994 DUMP_REG(DC_WIN_BLEND_2WIN_X);
995 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
996 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
997 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
998 DUMP_REG(DC_WINBUF_START_ADDR);
999 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1000 DUMP_REG(DC_WINBUF_START_ADDR_U);
1001 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1002 DUMP_REG(DC_WINBUF_START_ADDR_V);
1003 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1004 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1005 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1006 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1007 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1008 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1009 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1010 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1011 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1012
1013 #undef DUMP_REG
1014
1015 return 0;
1016 }
1017
1018 static struct drm_info_list debugfs_files[] = {
1019 { "regs", tegra_dc_show_regs, 0, NULL },
1020 };
1021
1022 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1023 {
1024 unsigned int i;
1025 char *name;
1026 int err;
1027
1028 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1029 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1030 kfree(name);
1031
1032 if (!dc->debugfs)
1033 return -ENOMEM;
1034
1035 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1036 GFP_KERNEL);
1037 if (!dc->debugfs_files) {
1038 err = -ENOMEM;
1039 goto remove;
1040 }
1041
1042 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1043 dc->debugfs_files[i].data = dc;
1044
1045 err = drm_debugfs_create_files(dc->debugfs_files,
1046 ARRAY_SIZE(debugfs_files),
1047 dc->debugfs, minor);
1048 if (err < 0)
1049 goto free;
1050
1051 dc->minor = minor;
1052
1053 return 0;
1054
1055 free:
1056 kfree(dc->debugfs_files);
1057 dc->debugfs_files = NULL;
1058 remove:
1059 debugfs_remove(dc->debugfs);
1060 dc->debugfs = NULL;
1061
1062 return err;
1063 }
1064
1065 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1066 {
1067 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1068 dc->minor);
1069 dc->minor = NULL;
1070
1071 kfree(dc->debugfs_files);
1072 dc->debugfs_files = NULL;
1073
1074 debugfs_remove(dc->debugfs);
1075 dc->debugfs = NULL;
1076
1077 return 0;
1078 }
1079
1080 static int tegra_dc_init(struct host1x_client *client)
1081 {
1082 struct tegra_drm *tegra = dev_get_drvdata(client->parent);
1083 struct tegra_dc *dc = host1x_client_to_dc(client);
1084 int err;
1085
1086 dc->pipe = tegra->drm->mode_config.num_crtc;
1087
1088 drm_crtc_init(tegra->drm, &dc->base, &tegra_crtc_funcs);
1089 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1090 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1091
1092 err = tegra_dc_rgb_init(tegra->drm, dc);
1093 if (err < 0 && err != -ENODEV) {
1094 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1095 return err;
1096 }
1097
1098 err = tegra_dc_add_planes(tegra->drm, dc);
1099 if (err < 0)
1100 return err;
1101
1102 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1103 err = tegra_dc_debugfs_init(dc, tegra->drm->primary);
1104 if (err < 0)
1105 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1106 }
1107
1108 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1109 dev_name(dc->dev), dc);
1110 if (err < 0) {
1111 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1112 err);
1113 return err;
1114 }
1115
1116 return 0;
1117 }
1118
1119 static int tegra_dc_exit(struct host1x_client *client)
1120 {
1121 struct tegra_dc *dc = host1x_client_to_dc(client);
1122 int err;
1123
1124 devm_free_irq(dc->dev, dc->irq, dc);
1125
1126 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1127 err = tegra_dc_debugfs_exit(dc);
1128 if (err < 0)
1129 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1130 }
1131
1132 err = tegra_dc_rgb_exit(dc);
1133 if (err) {
1134 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1135 return err;
1136 }
1137
1138 return 0;
1139 }
1140
1141 static const struct host1x_client_ops dc_client_ops = {
1142 .init = tegra_dc_init,
1143 .exit = tegra_dc_exit,
1144 };
1145
1146 static int tegra_dc_probe(struct platform_device *pdev)
1147 {
1148 struct resource *regs;
1149 struct tegra_dc *dc;
1150 int err;
1151
1152 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1153 if (!dc)
1154 return -ENOMEM;
1155
1156 spin_lock_init(&dc->lock);
1157 INIT_LIST_HEAD(&dc->list);
1158 dc->dev = &pdev->dev;
1159
1160 dc->clk = devm_clk_get(&pdev->dev, NULL);
1161 if (IS_ERR(dc->clk)) {
1162 dev_err(&pdev->dev, "failed to get clock\n");
1163 return PTR_ERR(dc->clk);
1164 }
1165
1166 err = clk_prepare_enable(dc->clk);
1167 if (err < 0)
1168 return err;
1169
1170 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1171 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1172 if (IS_ERR(dc->regs))
1173 return PTR_ERR(dc->regs);
1174
1175 dc->irq = platform_get_irq(pdev, 0);
1176 if (dc->irq < 0) {
1177 dev_err(&pdev->dev, "failed to get IRQ\n");
1178 return -ENXIO;
1179 }
1180
1181 INIT_LIST_HEAD(&dc->client.list);
1182 dc->client.ops = &dc_client_ops;
1183 dc->client.dev = &pdev->dev;
1184
1185 err = tegra_dc_rgb_probe(dc);
1186 if (err < 0 && err != -ENODEV) {
1187 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1188 return err;
1189 }
1190
1191 err = host1x_client_register(&dc->client);
1192 if (err < 0) {
1193 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1194 err);
1195 return err;
1196 }
1197
1198 platform_set_drvdata(pdev, dc);
1199
1200 return 0;
1201 }
1202
1203 static int tegra_dc_remove(struct platform_device *pdev)
1204 {
1205 struct tegra_dc *dc = platform_get_drvdata(pdev);
1206 int err;
1207
1208 err = host1x_client_unregister(&dc->client);
1209 if (err < 0) {
1210 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1211 err);
1212 return err;
1213 }
1214
1215 err = tegra_dc_rgb_remove(dc);
1216 if (err < 0) {
1217 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
1218 return err;
1219 }
1220
1221 clk_disable_unprepare(dc->clk);
1222
1223 return 0;
1224 }
1225
1226 static struct of_device_id tegra_dc_of_match[] = {
1227 { .compatible = "nvidia,tegra30-dc", },
1228 { .compatible = "nvidia,tegra20-dc", },
1229 { },
1230 };
1231
1232 struct platform_driver tegra_dc_driver = {
1233 .driver = {
1234 .name = "tegra-dc",
1235 .owner = THIS_MODULE,
1236 .of_match_table = tegra_dc_of_match,
1237 },
1238 .probe = tegra_dc_probe,
1239 .remove = tegra_dc_remove,
1240 };
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