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[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / tegra / dc.c
1 /*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/iommu.h>
13 #include <linux/of_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/reset.h>
16
17 #include <soc/tegra/pmc.h>
18
19 #include "dc.h"
20 #include "drm.h"
21 #include "gem.h"
22 #include "hub.h"
23 #include "plane.h"
24
25 #include <drm/drm_atomic.h>
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_plane_helper.h>
28
29 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
30 {
31 stats->frames = 0;
32 stats->vblank = 0;
33 stats->underflow = 0;
34 stats->overflow = 0;
35 }
36
37 /* Reads the active copy of a register. */
38 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
39 {
40 u32 value;
41
42 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
43 value = tegra_dc_readl(dc, offset);
44 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
45
46 return value;
47 }
48
49 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
50 unsigned int offset)
51 {
52 if (offset >= 0x500 && offset <= 0x638) {
53 offset = 0x000 + (offset - 0x500);
54 return plane->offset + offset;
55 }
56
57 if (offset >= 0x700 && offset <= 0x719) {
58 offset = 0x180 + (offset - 0x700);
59 return plane->offset + offset;
60 }
61
62 if (offset >= 0x800 && offset <= 0x839) {
63 offset = 0x1c0 + (offset - 0x800);
64 return plane->offset + offset;
65 }
66
67 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
68
69 return plane->offset + offset;
70 }
71
72 static inline u32 tegra_plane_readl(struct tegra_plane *plane,
73 unsigned int offset)
74 {
75 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
76 }
77
78 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
79 unsigned int offset)
80 {
81 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
82 }
83
84 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
85 {
86 struct device_node *np = dc->dev->of_node;
87 struct of_phandle_iterator it;
88 int err;
89
90 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
91 if (it.node == dev->of_node)
92 return true;
93
94 return false;
95 }
96
97 /*
98 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
99 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
100 * Latching happens mmediately if the display controller is in STOP mode or
101 * on the next frame boundary otherwise.
102 *
103 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
104 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
105 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
106 * into the ACTIVE copy, either immediately if the display controller is in
107 * STOP mode, or at the next frame boundary otherwise.
108 */
109 void tegra_dc_commit(struct tegra_dc *dc)
110 {
111 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
112 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
113 }
114
115 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
116 unsigned int bpp)
117 {
118 fixed20_12 outf = dfixed_init(out);
119 fixed20_12 inf = dfixed_init(in);
120 u32 dda_inc;
121 int max;
122
123 if (v)
124 max = 15;
125 else {
126 switch (bpp) {
127 case 2:
128 max = 8;
129 break;
130
131 default:
132 WARN_ON_ONCE(1);
133 /* fallthrough */
134 case 4:
135 max = 4;
136 break;
137 }
138 }
139
140 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
141 inf.full -= dfixed_const(1);
142
143 dda_inc = dfixed_div(inf, outf);
144 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
145
146 return dda_inc;
147 }
148
149 static inline u32 compute_initial_dda(unsigned int in)
150 {
151 fixed20_12 inf = dfixed_init(in);
152 return dfixed_frac(inf);
153 }
154
155 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
156 {
157 u32 background[3] = {
158 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
159 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
160 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
161 };
162 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
163 BLEND_COLOR_KEY_NONE;
164 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
165 struct tegra_plane_state *state;
166 unsigned int i;
167
168 state = to_tegra_plane_state(plane->base.state);
169
170 /* alpha contribution is 1 minus sum of overlapping windows */
171 for (i = 0; i < 3; i++) {
172 if (state->dependent[i])
173 background[i] |= BLEND_CONTROL_DEPENDENT;
174 }
175
176 /* enable alpha blending if pixel format has an alpha component */
177 if (!state->opaque)
178 foreground |= BLEND_CONTROL_ALPHA;
179
180 /*
181 * Disable blending and assume Window A is the bottom-most window,
182 * Window C is the top-most window and Window B is in the middle.
183 */
184 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
185 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
186
187 switch (plane->index) {
188 case 0:
189 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
190 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
191 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
192 break;
193
194 case 1:
195 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
196 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
197 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
198 break;
199
200 case 2:
201 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
202 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
203 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
204 break;
205 }
206 }
207
208 static void tegra_plane_setup_blending(struct tegra_plane *plane,
209 const struct tegra_dc_window *window)
210 {
211 u32 value;
212
213 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
214 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
215 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
216 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
217
218 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
219 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
220 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
221 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
222
223 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
224 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
225 }
226
227 static void tegra_dc_setup_window(struct tegra_plane *plane,
228 const struct tegra_dc_window *window)
229 {
230 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
231 struct tegra_dc *dc = plane->dc;
232 bool yuv, planar;
233 u32 value;
234
235 /*
236 * For YUV planar modes, the number of bytes per pixel takes into
237 * account only the luma component and therefore is 1.
238 */
239 yuv = tegra_plane_format_is_yuv(window->format, &planar);
240 if (!yuv)
241 bpp = window->bits_per_pixel / 8;
242 else
243 bpp = planar ? 1 : 2;
244
245 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
246 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
247
248 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
249 tegra_plane_writel(plane, value, DC_WIN_POSITION);
250
251 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
252 tegra_plane_writel(plane, value, DC_WIN_SIZE);
253
254 h_offset = window->src.x * bpp;
255 v_offset = window->src.y;
256 h_size = window->src.w * bpp;
257 v_size = window->src.h;
258
259 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
260 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
261
262 /*
263 * For DDA computations the number of bytes per pixel for YUV planar
264 * modes needs to take into account all Y, U and V components.
265 */
266 if (yuv && planar)
267 bpp = 2;
268
269 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
270 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
271
272 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
273 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
274
275 h_dda = compute_initial_dda(window->src.x);
276 v_dda = compute_initial_dda(window->src.y);
277
278 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
279 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
280
281 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
282 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
283
284 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
285
286 if (yuv && planar) {
287 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
288 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
289 value = window->stride[1] << 16 | window->stride[0];
290 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
291 } else {
292 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
293 }
294
295 if (window->bottom_up)
296 v_offset += window->src.h - 1;
297
298 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
299 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
300
301 if (dc->soc->supports_block_linear) {
302 unsigned long height = window->tiling.value;
303
304 switch (window->tiling.mode) {
305 case TEGRA_BO_TILING_MODE_PITCH:
306 value = DC_WINBUF_SURFACE_KIND_PITCH;
307 break;
308
309 case TEGRA_BO_TILING_MODE_TILED:
310 value = DC_WINBUF_SURFACE_KIND_TILED;
311 break;
312
313 case TEGRA_BO_TILING_MODE_BLOCK:
314 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
315 DC_WINBUF_SURFACE_KIND_BLOCK;
316 break;
317 }
318
319 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
320 } else {
321 switch (window->tiling.mode) {
322 case TEGRA_BO_TILING_MODE_PITCH:
323 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
324 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
325 break;
326
327 case TEGRA_BO_TILING_MODE_TILED:
328 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
329 DC_WIN_BUFFER_ADDR_MODE_TILE;
330 break;
331
332 case TEGRA_BO_TILING_MODE_BLOCK:
333 /*
334 * No need to handle this here because ->atomic_check
335 * will already have filtered it out.
336 */
337 break;
338 }
339
340 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
341 }
342
343 value = WIN_ENABLE;
344
345 if (yuv) {
346 /* setup default colorspace conversion coefficients */
347 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
348 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
349 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
350 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
351 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
352 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
353 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
354 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
355
356 value |= CSC_ENABLE;
357 } else if (window->bits_per_pixel < 24) {
358 value |= COLOR_EXPAND;
359 }
360
361 if (window->bottom_up)
362 value |= V_DIRECTION;
363
364 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
365
366 if (dc->soc->supports_blending)
367 tegra_plane_setup_blending(plane, window);
368 else
369 tegra_plane_setup_blending_legacy(plane);
370 }
371
372 static const u32 tegra20_primary_formats[] = {
373 DRM_FORMAT_ARGB4444,
374 DRM_FORMAT_ARGB1555,
375 DRM_FORMAT_RGB565,
376 DRM_FORMAT_RGBA5551,
377 DRM_FORMAT_ABGR8888,
378 DRM_FORMAT_ARGB8888,
379 /* non-native formats */
380 DRM_FORMAT_XRGB1555,
381 DRM_FORMAT_RGBX5551,
382 DRM_FORMAT_XBGR8888,
383 DRM_FORMAT_XRGB8888,
384 };
385
386 static const u32 tegra114_primary_formats[] = {
387 DRM_FORMAT_ARGB4444,
388 DRM_FORMAT_ARGB1555,
389 DRM_FORMAT_RGB565,
390 DRM_FORMAT_RGBA5551,
391 DRM_FORMAT_ABGR8888,
392 DRM_FORMAT_ARGB8888,
393 /* new on Tegra114 */
394 DRM_FORMAT_ABGR4444,
395 DRM_FORMAT_ABGR1555,
396 DRM_FORMAT_BGRA5551,
397 DRM_FORMAT_XRGB1555,
398 DRM_FORMAT_RGBX5551,
399 DRM_FORMAT_XBGR1555,
400 DRM_FORMAT_BGRX5551,
401 DRM_FORMAT_BGR565,
402 DRM_FORMAT_BGRA8888,
403 DRM_FORMAT_RGBA8888,
404 DRM_FORMAT_XRGB8888,
405 DRM_FORMAT_XBGR8888,
406 };
407
408 static const u32 tegra124_primary_formats[] = {
409 DRM_FORMAT_ARGB4444,
410 DRM_FORMAT_ARGB1555,
411 DRM_FORMAT_RGB565,
412 DRM_FORMAT_RGBA5551,
413 DRM_FORMAT_ABGR8888,
414 DRM_FORMAT_ARGB8888,
415 /* new on Tegra114 */
416 DRM_FORMAT_ABGR4444,
417 DRM_FORMAT_ABGR1555,
418 DRM_FORMAT_BGRA5551,
419 DRM_FORMAT_XRGB1555,
420 DRM_FORMAT_RGBX5551,
421 DRM_FORMAT_XBGR1555,
422 DRM_FORMAT_BGRX5551,
423 DRM_FORMAT_BGR565,
424 DRM_FORMAT_BGRA8888,
425 DRM_FORMAT_RGBA8888,
426 DRM_FORMAT_XRGB8888,
427 DRM_FORMAT_XBGR8888,
428 /* new on Tegra124 */
429 DRM_FORMAT_RGBX8888,
430 DRM_FORMAT_BGRX8888,
431 };
432
433 static int tegra_plane_atomic_check(struct drm_plane *plane,
434 struct drm_plane_state *state)
435 {
436 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
437 struct tegra_bo_tiling *tiling = &plane_state->tiling;
438 struct tegra_plane *tegra = to_tegra_plane(plane);
439 struct tegra_dc *dc = to_tegra_dc(state->crtc);
440 unsigned int format;
441 int err;
442
443 /* no need for further checks if the plane is being disabled */
444 if (!state->crtc)
445 return 0;
446
447 err = tegra_plane_format(state->fb->format->format, &format,
448 &plane_state->swap);
449 if (err < 0)
450 return err;
451
452 /*
453 * Tegra20 and Tegra30 are special cases here because they support
454 * only variants of specific formats with an alpha component, but not
455 * the corresponding opaque formats. However, the opaque formats can
456 * be emulated by disabling alpha blending for the plane.
457 */
458 if (!dc->soc->supports_blending) {
459 if (!tegra_plane_format_has_alpha(format)) {
460 err = tegra_plane_format_get_alpha(format, &format);
461 if (err < 0)
462 return err;
463
464 plane_state->opaque = true;
465 } else {
466 plane_state->opaque = false;
467 }
468
469 tegra_plane_check_dependent(tegra, plane_state);
470 }
471
472 plane_state->format = format;
473
474 err = tegra_fb_get_tiling(state->fb, tiling);
475 if (err < 0)
476 return err;
477
478 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
479 !dc->soc->supports_block_linear) {
480 DRM_ERROR("hardware doesn't support block linear mode\n");
481 return -EINVAL;
482 }
483
484 /*
485 * Tegra doesn't support different strides for U and V planes so we
486 * error out if the user tries to display a framebuffer with such a
487 * configuration.
488 */
489 if (state->fb->format->num_planes > 2) {
490 if (state->fb->pitches[2] != state->fb->pitches[1]) {
491 DRM_ERROR("unsupported UV-plane configuration\n");
492 return -EINVAL;
493 }
494 }
495
496 err = tegra_plane_state_add(tegra, state);
497 if (err < 0)
498 return err;
499
500 return 0;
501 }
502
503 static void tegra_plane_atomic_disable(struct drm_plane *plane,
504 struct drm_plane_state *old_state)
505 {
506 struct tegra_plane *p = to_tegra_plane(plane);
507 u32 value;
508
509 /* rien ne va plus */
510 if (!old_state || !old_state->crtc)
511 return;
512
513 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
514 value &= ~WIN_ENABLE;
515 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
516 }
517
518 static void tegra_plane_atomic_update(struct drm_plane *plane,
519 struct drm_plane_state *old_state)
520 {
521 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
522 struct drm_framebuffer *fb = plane->state->fb;
523 struct tegra_plane *p = to_tegra_plane(plane);
524 struct tegra_dc_window window;
525 unsigned int i;
526
527 /* rien ne va plus */
528 if (!plane->state->crtc || !plane->state->fb)
529 return;
530
531 if (!plane->state->visible)
532 return tegra_plane_atomic_disable(plane, old_state);
533
534 memset(&window, 0, sizeof(window));
535 window.src.x = plane->state->src.x1 >> 16;
536 window.src.y = plane->state->src.y1 >> 16;
537 window.src.w = drm_rect_width(&plane->state->src) >> 16;
538 window.src.h = drm_rect_height(&plane->state->src) >> 16;
539 window.dst.x = plane->state->dst.x1;
540 window.dst.y = plane->state->dst.y1;
541 window.dst.w = drm_rect_width(&plane->state->dst);
542 window.dst.h = drm_rect_height(&plane->state->dst);
543 window.bits_per_pixel = fb->format->cpp[0] * 8;
544 window.bottom_up = tegra_fb_is_bottom_up(fb);
545
546 /* copy from state */
547 window.zpos = plane->state->normalized_zpos;
548 window.tiling = state->tiling;
549 window.format = state->format;
550 window.swap = state->swap;
551
552 for (i = 0; i < fb->format->num_planes; i++) {
553 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
554
555 window.base[i] = bo->paddr + fb->offsets[i];
556
557 /*
558 * Tegra uses a shared stride for UV planes. Framebuffers are
559 * already checked for this in the tegra_plane_atomic_check()
560 * function, so it's safe to ignore the V-plane pitch here.
561 */
562 if (i < 2)
563 window.stride[i] = fb->pitches[i];
564 }
565
566 tegra_dc_setup_window(p, &window);
567 }
568
569 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
570 .atomic_check = tegra_plane_atomic_check,
571 .atomic_disable = tegra_plane_atomic_disable,
572 .atomic_update = tegra_plane_atomic_update,
573 };
574
575 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
576 {
577 /*
578 * Ideally this would use drm_crtc_mask(), but that would require the
579 * CRTC to already be in the mode_config's list of CRTCs. However, it
580 * will only be added to that list in the drm_crtc_init_with_planes()
581 * (in tegra_dc_init()), which in turn requires registration of these
582 * planes. So we have ourselves a nice little chicken and egg problem
583 * here.
584 *
585 * We work around this by manually creating the mask from the number
586 * of CRTCs that have been registered, and should therefore always be
587 * the same as drm_crtc_index() after registration.
588 */
589 return 1 << drm->mode_config.num_crtc;
590 }
591
592 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
593 struct tegra_dc *dc)
594 {
595 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
596 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
597 struct tegra_plane *plane;
598 unsigned int num_formats;
599 const u32 *formats;
600 int err;
601
602 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
603 if (!plane)
604 return ERR_PTR(-ENOMEM);
605
606 /* Always use window A as primary window */
607 plane->offset = 0xa00;
608 plane->index = 0;
609 plane->dc = dc;
610
611 num_formats = dc->soc->num_primary_formats;
612 formats = dc->soc->primary_formats;
613
614 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
615 &tegra_plane_funcs, formats,
616 num_formats, NULL, type, NULL);
617 if (err < 0) {
618 kfree(plane);
619 return ERR_PTR(err);
620 }
621
622 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
623
624 if (dc->soc->supports_blending)
625 drm_plane_create_zpos_property(&plane->base, 0, 0, 255);
626
627 return &plane->base;
628 }
629
630 static const u32 tegra_cursor_plane_formats[] = {
631 DRM_FORMAT_RGBA8888,
632 };
633
634 static int tegra_cursor_atomic_check(struct drm_plane *plane,
635 struct drm_plane_state *state)
636 {
637 struct tegra_plane *tegra = to_tegra_plane(plane);
638 int err;
639
640 /* no need for further checks if the plane is being disabled */
641 if (!state->crtc)
642 return 0;
643
644 /* scaling not supported for cursor */
645 if ((state->src_w >> 16 != state->crtc_w) ||
646 (state->src_h >> 16 != state->crtc_h))
647 return -EINVAL;
648
649 /* only square cursors supported */
650 if (state->src_w != state->src_h)
651 return -EINVAL;
652
653 if (state->crtc_w != 32 && state->crtc_w != 64 &&
654 state->crtc_w != 128 && state->crtc_w != 256)
655 return -EINVAL;
656
657 err = tegra_plane_state_add(tegra, state);
658 if (err < 0)
659 return err;
660
661 return 0;
662 }
663
664 static void tegra_cursor_atomic_update(struct drm_plane *plane,
665 struct drm_plane_state *old_state)
666 {
667 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
668 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
669 struct drm_plane_state *state = plane->state;
670 u32 value = CURSOR_CLIP_DISPLAY;
671
672 /* rien ne va plus */
673 if (!plane->state->crtc || !plane->state->fb)
674 return;
675
676 switch (state->crtc_w) {
677 case 32:
678 value |= CURSOR_SIZE_32x32;
679 break;
680
681 case 64:
682 value |= CURSOR_SIZE_64x64;
683 break;
684
685 case 128:
686 value |= CURSOR_SIZE_128x128;
687 break;
688
689 case 256:
690 value |= CURSOR_SIZE_256x256;
691 break;
692
693 default:
694 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
695 state->crtc_h);
696 return;
697 }
698
699 value |= (bo->paddr >> 10) & 0x3fffff;
700 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
701
702 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
703 value = (bo->paddr >> 32) & 0x3;
704 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
705 #endif
706
707 /* enable cursor and set blend mode */
708 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
709 value |= CURSOR_ENABLE;
710 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
711
712 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
713 value &= ~CURSOR_DST_BLEND_MASK;
714 value &= ~CURSOR_SRC_BLEND_MASK;
715 value |= CURSOR_MODE_NORMAL;
716 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
717 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
718 value |= CURSOR_ALPHA;
719 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
720
721 /* position the cursor */
722 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
723 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
724 }
725
726 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
727 struct drm_plane_state *old_state)
728 {
729 struct tegra_dc *dc;
730 u32 value;
731
732 /* rien ne va plus */
733 if (!old_state || !old_state->crtc)
734 return;
735
736 dc = to_tegra_dc(old_state->crtc);
737
738 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
739 value &= ~CURSOR_ENABLE;
740 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
741 }
742
743 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
744 .atomic_check = tegra_cursor_atomic_check,
745 .atomic_update = tegra_cursor_atomic_update,
746 .atomic_disable = tegra_cursor_atomic_disable,
747 };
748
749 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
750 struct tegra_dc *dc)
751 {
752 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
753 struct tegra_plane *plane;
754 unsigned int num_formats;
755 const u32 *formats;
756 int err;
757
758 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
759 if (!plane)
760 return ERR_PTR(-ENOMEM);
761
762 /*
763 * This index is kind of fake. The cursor isn't a regular plane, but
764 * its update and activation request bits in DC_CMD_STATE_CONTROL do
765 * use the same programming. Setting this fake index here allows the
766 * code in tegra_add_plane_state() to do the right thing without the
767 * need to special-casing the cursor plane.
768 */
769 plane->index = 6;
770 plane->dc = dc;
771
772 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
773 formats = tegra_cursor_plane_formats;
774
775 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
776 &tegra_plane_funcs, formats,
777 num_formats, NULL,
778 DRM_PLANE_TYPE_CURSOR, NULL);
779 if (err < 0) {
780 kfree(plane);
781 return ERR_PTR(err);
782 }
783
784 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
785
786 return &plane->base;
787 }
788
789 static const u32 tegra20_overlay_formats[] = {
790 DRM_FORMAT_ARGB4444,
791 DRM_FORMAT_ARGB1555,
792 DRM_FORMAT_RGB565,
793 DRM_FORMAT_RGBA5551,
794 DRM_FORMAT_ABGR8888,
795 DRM_FORMAT_ARGB8888,
796 /* non-native formats */
797 DRM_FORMAT_XRGB1555,
798 DRM_FORMAT_RGBX5551,
799 DRM_FORMAT_XBGR8888,
800 DRM_FORMAT_XRGB8888,
801 /* planar formats */
802 DRM_FORMAT_UYVY,
803 DRM_FORMAT_YUYV,
804 DRM_FORMAT_YUV420,
805 DRM_FORMAT_YUV422,
806 };
807
808 static const u32 tegra114_overlay_formats[] = {
809 DRM_FORMAT_ARGB4444,
810 DRM_FORMAT_ARGB1555,
811 DRM_FORMAT_RGB565,
812 DRM_FORMAT_RGBA5551,
813 DRM_FORMAT_ABGR8888,
814 DRM_FORMAT_ARGB8888,
815 /* new on Tegra114 */
816 DRM_FORMAT_ABGR4444,
817 DRM_FORMAT_ABGR1555,
818 DRM_FORMAT_BGRA5551,
819 DRM_FORMAT_XRGB1555,
820 DRM_FORMAT_RGBX5551,
821 DRM_FORMAT_XBGR1555,
822 DRM_FORMAT_BGRX5551,
823 DRM_FORMAT_BGR565,
824 DRM_FORMAT_BGRA8888,
825 DRM_FORMAT_RGBA8888,
826 DRM_FORMAT_XRGB8888,
827 DRM_FORMAT_XBGR8888,
828 /* planar formats */
829 DRM_FORMAT_UYVY,
830 DRM_FORMAT_YUYV,
831 DRM_FORMAT_YUV420,
832 DRM_FORMAT_YUV422,
833 };
834
835 static const u32 tegra124_overlay_formats[] = {
836 DRM_FORMAT_ARGB4444,
837 DRM_FORMAT_ARGB1555,
838 DRM_FORMAT_RGB565,
839 DRM_FORMAT_RGBA5551,
840 DRM_FORMAT_ABGR8888,
841 DRM_FORMAT_ARGB8888,
842 /* new on Tegra114 */
843 DRM_FORMAT_ABGR4444,
844 DRM_FORMAT_ABGR1555,
845 DRM_FORMAT_BGRA5551,
846 DRM_FORMAT_XRGB1555,
847 DRM_FORMAT_RGBX5551,
848 DRM_FORMAT_XBGR1555,
849 DRM_FORMAT_BGRX5551,
850 DRM_FORMAT_BGR565,
851 DRM_FORMAT_BGRA8888,
852 DRM_FORMAT_RGBA8888,
853 DRM_FORMAT_XRGB8888,
854 DRM_FORMAT_XBGR8888,
855 /* new on Tegra124 */
856 DRM_FORMAT_RGBX8888,
857 DRM_FORMAT_BGRX8888,
858 /* planar formats */
859 DRM_FORMAT_UYVY,
860 DRM_FORMAT_YUYV,
861 DRM_FORMAT_YUV420,
862 DRM_FORMAT_YUV422,
863 };
864
865 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
866 struct tegra_dc *dc,
867 unsigned int index)
868 {
869 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
870 struct tegra_plane *plane;
871 unsigned int num_formats;
872 const u32 *formats;
873 int err;
874
875 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
876 if (!plane)
877 return ERR_PTR(-ENOMEM);
878
879 plane->offset = 0xa00 + 0x200 * index;
880 plane->index = index;
881 plane->dc = dc;
882
883 num_formats = dc->soc->num_overlay_formats;
884 formats = dc->soc->overlay_formats;
885
886 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
887 &tegra_plane_funcs, formats,
888 num_formats, NULL,
889 DRM_PLANE_TYPE_OVERLAY, NULL);
890 if (err < 0) {
891 kfree(plane);
892 return ERR_PTR(err);
893 }
894
895 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
896
897 if (dc->soc->supports_blending)
898 drm_plane_create_zpos_property(&plane->base, 0, 0, 255);
899
900 return &plane->base;
901 }
902
903 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
904 struct tegra_dc *dc)
905 {
906 struct drm_plane *plane, *primary = NULL;
907 unsigned int i, j;
908
909 for (i = 0; i < dc->soc->num_wgrps; i++) {
910 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
911
912 if (wgrp->dc == dc->pipe) {
913 for (j = 0; j < wgrp->num_windows; j++) {
914 unsigned int index = wgrp->windows[j];
915
916 plane = tegra_shared_plane_create(drm, dc,
917 wgrp->index,
918 index);
919 if (IS_ERR(plane))
920 return plane;
921
922 /*
923 * Choose the first shared plane owned by this
924 * head as the primary plane.
925 */
926 if (!primary) {
927 plane->type = DRM_PLANE_TYPE_PRIMARY;
928 primary = plane;
929 }
930 }
931 }
932 }
933
934 return primary;
935 }
936
937 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
938 struct tegra_dc *dc)
939 {
940 struct drm_plane *planes[2], *primary;
941 unsigned int i;
942 int err;
943
944 primary = tegra_primary_plane_create(drm, dc);
945 if (IS_ERR(primary))
946 return primary;
947
948 for (i = 0; i < 2; i++) {
949 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
950 if (IS_ERR(planes[i])) {
951 err = PTR_ERR(planes[i]);
952
953 while (i--)
954 tegra_plane_funcs.destroy(planes[i]);
955
956 tegra_plane_funcs.destroy(primary);
957 return ERR_PTR(err);
958 }
959 }
960
961 return primary;
962 }
963
964 static void tegra_dc_destroy(struct drm_crtc *crtc)
965 {
966 drm_crtc_cleanup(crtc);
967 }
968
969 static void tegra_crtc_reset(struct drm_crtc *crtc)
970 {
971 struct tegra_dc_state *state;
972
973 if (crtc->state)
974 __drm_atomic_helper_crtc_destroy_state(crtc->state);
975
976 kfree(crtc->state);
977 crtc->state = NULL;
978
979 state = kzalloc(sizeof(*state), GFP_KERNEL);
980 if (state) {
981 crtc->state = &state->base;
982 crtc->state->crtc = crtc;
983 }
984
985 drm_crtc_vblank_reset(crtc);
986 }
987
988 static struct drm_crtc_state *
989 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
990 {
991 struct tegra_dc_state *state = to_dc_state(crtc->state);
992 struct tegra_dc_state *copy;
993
994 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
995 if (!copy)
996 return NULL;
997
998 __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
999 copy->clk = state->clk;
1000 copy->pclk = state->pclk;
1001 copy->div = state->div;
1002 copy->planes = state->planes;
1003
1004 return &copy->base;
1005 }
1006
1007 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1008 struct drm_crtc_state *state)
1009 {
1010 __drm_atomic_helper_crtc_destroy_state(state);
1011 kfree(state);
1012 }
1013
1014 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1015
1016 static const struct debugfs_reg32 tegra_dc_regs[] = {
1017 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1018 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1019 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1020 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1021 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1022 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1023 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1024 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1025 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1026 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1027 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1028 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1029 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1030 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1031 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1032 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1033 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1034 DEBUGFS_REG32(DC_CMD_INT_STATUS),
1035 DEBUGFS_REG32(DC_CMD_INT_MASK),
1036 DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1037 DEBUGFS_REG32(DC_CMD_INT_TYPE),
1038 DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1039 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1040 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1041 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1042 DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1043 DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1044 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1045 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1046 DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1047 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1048 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1049 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1050 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1051 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1052 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1053 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1054 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1055 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1056 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1057 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1058 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1059 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1060 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1061 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1062 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1063 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1064 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1065 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1066 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1067 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1068 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1069 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1070 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1071 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1072 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1073 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1074 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1075 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1076 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1077 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1078 DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1079 DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1080 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1081 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1082 DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1083 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1084 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1085 DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1086 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1087 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1088 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1089 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1090 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1091 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1092 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1093 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1094 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1095 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1096 DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1097 DEBUGFS_REG32(DC_DISP_ACTIVE),
1098 DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1099 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1100 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1101 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1102 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1103 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1104 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1105 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1106 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1107 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1108 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1109 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1110 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1111 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1112 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1113 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1114 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1115 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1116 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1117 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1118 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1119 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1120 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1121 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1122 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1123 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1124 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1125 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1126 DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1127 DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1128 DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1129 DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1130 DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1131 DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1132 DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1133 DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1134 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1135 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1136 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1137 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1138 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1139 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1140 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1141 DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1142 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1143 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1144 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1145 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1146 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1147 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1148 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1149 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1150 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1151 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1152 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1153 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1154 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1155 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1156 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1157 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1158 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1159 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1160 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1161 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1162 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1163 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1164 DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1165 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1166 DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1167 DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1168 DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1169 DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1170 DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1171 DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1172 DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1173 DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1174 DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1175 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1176 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1177 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1178 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1179 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1180 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1181 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1182 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1183 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1184 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1185 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1186 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1187 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1188 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1189 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1190 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1191 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1192 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1193 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1194 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1195 DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1196 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1197 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1198 DEBUGFS_REG32(DC_WIN_POSITION),
1199 DEBUGFS_REG32(DC_WIN_SIZE),
1200 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1201 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1202 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1203 DEBUGFS_REG32(DC_WIN_DDA_INC),
1204 DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1205 DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1206 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1207 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1208 DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1209 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1210 DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1211 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1212 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1213 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1214 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1215 DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1216 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1217 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1218 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1219 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1220 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1221 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1222 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1223 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1224 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1225 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1226 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1227 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1228 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1229 };
1230
1231 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1232 {
1233 struct drm_info_node *node = s->private;
1234 struct tegra_dc *dc = node->info_ent->data;
1235 unsigned int i;
1236 int err = 0;
1237
1238 drm_modeset_lock(&dc->base.mutex, NULL);
1239
1240 if (!dc->base.state->active) {
1241 err = -EBUSY;
1242 goto unlock;
1243 }
1244
1245 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1246 unsigned int offset = tegra_dc_regs[i].offset;
1247
1248 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1249 offset, tegra_dc_readl(dc, offset));
1250 }
1251
1252 unlock:
1253 drm_modeset_unlock(&dc->base.mutex);
1254 return err;
1255 }
1256
1257 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1258 {
1259 struct drm_info_node *node = s->private;
1260 struct tegra_dc *dc = node->info_ent->data;
1261 int err = 0;
1262 u32 value;
1263
1264 drm_modeset_lock(&dc->base.mutex, NULL);
1265
1266 if (!dc->base.state->active) {
1267 err = -EBUSY;
1268 goto unlock;
1269 }
1270
1271 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1272 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1273 tegra_dc_commit(dc);
1274
1275 drm_crtc_wait_one_vblank(&dc->base);
1276 drm_crtc_wait_one_vblank(&dc->base);
1277
1278 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1279 seq_printf(s, "%08x\n", value);
1280
1281 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1282
1283 unlock:
1284 drm_modeset_unlock(&dc->base.mutex);
1285 return err;
1286 }
1287
1288 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1289 {
1290 struct drm_info_node *node = s->private;
1291 struct tegra_dc *dc = node->info_ent->data;
1292
1293 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1294 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1295 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1296 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1297
1298 return 0;
1299 }
1300
1301 static struct drm_info_list debugfs_files[] = {
1302 { "regs", tegra_dc_show_regs, 0, NULL },
1303 { "crc", tegra_dc_show_crc, 0, NULL },
1304 { "stats", tegra_dc_show_stats, 0, NULL },
1305 };
1306
1307 static int tegra_dc_late_register(struct drm_crtc *crtc)
1308 {
1309 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1310 struct drm_minor *minor = crtc->dev->primary;
1311 struct dentry *root;
1312 struct tegra_dc *dc = to_tegra_dc(crtc);
1313 int err;
1314
1315 #ifdef CONFIG_DEBUG_FS
1316 root = crtc->debugfs_entry;
1317 #else
1318 root = NULL;
1319 #endif
1320
1321 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1322 GFP_KERNEL);
1323 if (!dc->debugfs_files)
1324 return -ENOMEM;
1325
1326 for (i = 0; i < count; i++)
1327 dc->debugfs_files[i].data = dc;
1328
1329 err = drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1330 if (err < 0)
1331 goto free;
1332
1333 return 0;
1334
1335 free:
1336 kfree(dc->debugfs_files);
1337 dc->debugfs_files = NULL;
1338
1339 return err;
1340 }
1341
1342 static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1343 {
1344 unsigned int count = ARRAY_SIZE(debugfs_files);
1345 struct drm_minor *minor = crtc->dev->primary;
1346 struct tegra_dc *dc = to_tegra_dc(crtc);
1347
1348 drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1349 kfree(dc->debugfs_files);
1350 dc->debugfs_files = NULL;
1351 }
1352
1353 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1354 {
1355 struct tegra_dc *dc = to_tegra_dc(crtc);
1356
1357 /* XXX vblank syncpoints don't work with nvdisplay yet */
1358 if (dc->syncpt && !dc->soc->has_nvdisplay)
1359 return host1x_syncpt_read(dc->syncpt);
1360
1361 /* fallback to software emulated VBLANK counter */
1362 return drm_crtc_vblank_count(&dc->base);
1363 }
1364
1365 static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1366 {
1367 struct tegra_dc *dc = to_tegra_dc(crtc);
1368 u32 value;
1369
1370 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1371 value |= VBLANK_INT;
1372 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1373
1374 return 0;
1375 }
1376
1377 static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1378 {
1379 struct tegra_dc *dc = to_tegra_dc(crtc);
1380 u32 value;
1381
1382 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1383 value &= ~VBLANK_INT;
1384 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1385 }
1386
1387 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1388 .page_flip = drm_atomic_helper_page_flip,
1389 .set_config = drm_atomic_helper_set_config,
1390 .destroy = tegra_dc_destroy,
1391 .reset = tegra_crtc_reset,
1392 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1393 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1394 .late_register = tegra_dc_late_register,
1395 .early_unregister = tegra_dc_early_unregister,
1396 .get_vblank_counter = tegra_dc_get_vblank_counter,
1397 .enable_vblank = tegra_dc_enable_vblank,
1398 .disable_vblank = tegra_dc_disable_vblank,
1399 };
1400
1401 static int tegra_dc_set_timings(struct tegra_dc *dc,
1402 struct drm_display_mode *mode)
1403 {
1404 unsigned int h_ref_to_sync = 1;
1405 unsigned int v_ref_to_sync = 1;
1406 unsigned long value;
1407
1408 if (!dc->soc->has_nvdisplay) {
1409 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1410
1411 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1412 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1413 }
1414
1415 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1416 ((mode->hsync_end - mode->hsync_start) << 0);
1417 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1418
1419 value = ((mode->vtotal - mode->vsync_end) << 16) |
1420 ((mode->htotal - mode->hsync_end) << 0);
1421 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1422
1423 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1424 ((mode->hsync_start - mode->hdisplay) << 0);
1425 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1426
1427 value = (mode->vdisplay << 16) | mode->hdisplay;
1428 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1429
1430 return 0;
1431 }
1432
1433 /**
1434 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1435 * state
1436 * @dc: display controller
1437 * @crtc_state: CRTC atomic state
1438 * @clk: parent clock for display controller
1439 * @pclk: pixel clock
1440 * @div: shift clock divider
1441 *
1442 * Returns:
1443 * 0 on success or a negative error-code on failure.
1444 */
1445 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1446 struct drm_crtc_state *crtc_state,
1447 struct clk *clk, unsigned long pclk,
1448 unsigned int div)
1449 {
1450 struct tegra_dc_state *state = to_dc_state(crtc_state);
1451
1452 if (!clk_has_parent(dc->clk, clk))
1453 return -EINVAL;
1454
1455 state->clk = clk;
1456 state->pclk = pclk;
1457 state->div = div;
1458
1459 return 0;
1460 }
1461
1462 static void tegra_dc_commit_state(struct tegra_dc *dc,
1463 struct tegra_dc_state *state)
1464 {
1465 u32 value;
1466 int err;
1467
1468 err = clk_set_parent(dc->clk, state->clk);
1469 if (err < 0)
1470 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1471
1472 /*
1473 * Outputs may not want to change the parent clock rate. This is only
1474 * relevant to Tegra20 where only a single display PLL is available.
1475 * Since that PLL would typically be used for HDMI, an internal LVDS
1476 * panel would need to be driven by some other clock such as PLL_P
1477 * which is shared with other peripherals. Changing the clock rate
1478 * should therefore be avoided.
1479 */
1480 if (state->pclk > 0) {
1481 err = clk_set_rate(state->clk, state->pclk);
1482 if (err < 0)
1483 dev_err(dc->dev,
1484 "failed to set clock rate to %lu Hz\n",
1485 state->pclk);
1486 }
1487
1488 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1489 state->div);
1490 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1491
1492 if (!dc->soc->has_nvdisplay) {
1493 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1494 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1495 }
1496
1497 err = clk_set_rate(dc->clk, state->pclk);
1498 if (err < 0)
1499 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1500 dc->clk, state->pclk, err);
1501 }
1502
1503 static void tegra_dc_stop(struct tegra_dc *dc)
1504 {
1505 u32 value;
1506
1507 /* stop the display controller */
1508 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1509 value &= ~DISP_CTRL_MODE_MASK;
1510 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1511
1512 tegra_dc_commit(dc);
1513 }
1514
1515 static bool tegra_dc_idle(struct tegra_dc *dc)
1516 {
1517 u32 value;
1518
1519 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1520
1521 return (value & DISP_CTRL_MODE_MASK) == 0;
1522 }
1523
1524 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1525 {
1526 timeout = jiffies + msecs_to_jiffies(timeout);
1527
1528 while (time_before(jiffies, timeout)) {
1529 if (tegra_dc_idle(dc))
1530 return 0;
1531
1532 usleep_range(1000, 2000);
1533 }
1534
1535 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1536 return -ETIMEDOUT;
1537 }
1538
1539 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1540 struct drm_crtc_state *old_state)
1541 {
1542 struct tegra_dc *dc = to_tegra_dc(crtc);
1543 u32 value;
1544
1545 if (!tegra_dc_idle(dc)) {
1546 tegra_dc_stop(dc);
1547
1548 /*
1549 * Ignore the return value, there isn't anything useful to do
1550 * in case this fails.
1551 */
1552 tegra_dc_wait_idle(dc, 100);
1553 }
1554
1555 /*
1556 * This should really be part of the RGB encoder driver, but clearing
1557 * these bits has the side-effect of stopping the display controller.
1558 * When that happens no VBLANK interrupts will be raised. At the same
1559 * time the encoder is disabled before the display controller, so the
1560 * above code is always going to timeout waiting for the controller
1561 * to go idle.
1562 *
1563 * Given the close coupling between the RGB encoder and the display
1564 * controller doing it here is still kind of okay. None of the other
1565 * encoder drivers require these bits to be cleared.
1566 *
1567 * XXX: Perhaps given that the display controller is switched off at
1568 * this point anyway maybe clearing these bits isn't even useful for
1569 * the RGB encoder?
1570 */
1571 if (dc->rgb) {
1572 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1573 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1574 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1575 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1576 }
1577
1578 tegra_dc_stats_reset(&dc->stats);
1579 drm_crtc_vblank_off(crtc);
1580
1581 spin_lock_irq(&crtc->dev->event_lock);
1582
1583 if (crtc->state->event) {
1584 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1585 crtc->state->event = NULL;
1586 }
1587
1588 spin_unlock_irq(&crtc->dev->event_lock);
1589
1590 pm_runtime_put_sync(dc->dev);
1591 }
1592
1593 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1594 struct drm_crtc_state *old_state)
1595 {
1596 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1597 struct tegra_dc_state *state = to_dc_state(crtc->state);
1598 struct tegra_dc *dc = to_tegra_dc(crtc);
1599 u32 value;
1600
1601 pm_runtime_get_sync(dc->dev);
1602
1603 /* initialize display controller */
1604 if (dc->syncpt) {
1605 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
1606
1607 if (dc->soc->has_nvdisplay)
1608 enable = 1 << 31;
1609 else
1610 enable = 1 << 8;
1611
1612 value = SYNCPT_CNTRL_NO_STALL;
1613 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1614
1615 value = enable | syncpt;
1616 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1617 }
1618
1619 if (dc->soc->has_nvdisplay) {
1620 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1621 DSC_OBUF_UF_INT;
1622 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1623
1624 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1625 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
1626 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
1627 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
1628 VBLANK_INT | FRAME_END_INT;
1629 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1630
1631 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1632 FRAME_END_INT;
1633 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1634
1635 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1636 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1637
1638 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
1639 } else {
1640 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1641 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1642 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1643
1644 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1645 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1646 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1647
1648 /* initialize timer */
1649 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1650 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1651 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1652
1653 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1654 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1655 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1656
1657 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1658 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1659 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1660
1661 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1662 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1663 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1664 }
1665
1666 if (dc->soc->supports_background_color)
1667 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
1668 else
1669 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1670
1671 /* apply PLL and pixel clock changes */
1672 tegra_dc_commit_state(dc, state);
1673
1674 /* program display mode */
1675 tegra_dc_set_timings(dc, mode);
1676
1677 /* interlacing isn't supported yet, so disable it */
1678 if (dc->soc->supports_interlacing) {
1679 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1680 value &= ~INTERLACE_ENABLE;
1681 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1682 }
1683
1684 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1685 value &= ~DISP_CTRL_MODE_MASK;
1686 value |= DISP_CTRL_MODE_C_DISPLAY;
1687 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1688
1689 if (!dc->soc->has_nvdisplay) {
1690 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1691 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1692 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1693 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1694 }
1695
1696 /* enable underflow reporting and display red for missing pixels */
1697 if (dc->soc->has_nvdisplay) {
1698 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1699 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1700 }
1701
1702 tegra_dc_commit(dc);
1703
1704 drm_crtc_vblank_on(crtc);
1705 }
1706
1707 static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1708 struct drm_crtc_state *state)
1709 {
1710 struct tegra_atomic_state *s = to_tegra_atomic_state(state->state);
1711 struct tegra_dc_state *tegra = to_dc_state(state);
1712
1713 /*
1714 * The display hub display clock needs to be fed by the display clock
1715 * with the highest frequency to ensure proper functioning of all the
1716 * displays.
1717 *
1718 * Note that this isn't used before Tegra186, but it doesn't hurt and
1719 * conditionalizing it would make the code less clean.
1720 */
1721 if (state->active) {
1722 if (!s->clk_disp || tegra->pclk > s->rate) {
1723 s->dc = to_tegra_dc(crtc);
1724 s->clk_disp = s->dc->clk;
1725 s->rate = tegra->pclk;
1726 }
1727 }
1728
1729 return 0;
1730 }
1731
1732 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1733 struct drm_crtc_state *old_crtc_state)
1734 {
1735 unsigned long flags;
1736
1737 if (crtc->state->event) {
1738 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1739
1740 if (drm_crtc_vblank_get(crtc) != 0)
1741 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1742 else
1743 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
1744
1745 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1746
1747 crtc->state->event = NULL;
1748 }
1749 }
1750
1751 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1752 struct drm_crtc_state *old_crtc_state)
1753 {
1754 struct tegra_dc_state *state = to_dc_state(crtc->state);
1755 struct tegra_dc *dc = to_tegra_dc(crtc);
1756 u32 value;
1757
1758 value = state->planes << 8 | GENERAL_UPDATE;
1759 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1760 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1761
1762 value = state->planes | GENERAL_ACT_REQ;
1763 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1764 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1765 }
1766
1767 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1768 .atomic_check = tegra_crtc_atomic_check,
1769 .atomic_begin = tegra_crtc_atomic_begin,
1770 .atomic_flush = tegra_crtc_atomic_flush,
1771 .atomic_enable = tegra_crtc_atomic_enable,
1772 .atomic_disable = tegra_crtc_atomic_disable,
1773 };
1774
1775 static irqreturn_t tegra_dc_irq(int irq, void *data)
1776 {
1777 struct tegra_dc *dc = data;
1778 unsigned long status;
1779
1780 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1781 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1782
1783 if (status & FRAME_END_INT) {
1784 /*
1785 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1786 */
1787 dc->stats.frames++;
1788 }
1789
1790 if (status & VBLANK_INT) {
1791 /*
1792 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1793 */
1794 drm_crtc_handle_vblank(&dc->base);
1795 dc->stats.vblank++;
1796 }
1797
1798 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1799 /*
1800 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1801 */
1802 dc->stats.underflow++;
1803 }
1804
1805 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1806 /*
1807 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1808 */
1809 dc->stats.overflow++;
1810 }
1811
1812 if (status & HEAD_UF_INT) {
1813 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
1814 dc->stats.underflow++;
1815 }
1816
1817 return IRQ_HANDLED;
1818 }
1819
1820 static int tegra_dc_init(struct host1x_client *client)
1821 {
1822 struct drm_device *drm = dev_get_drvdata(client->parent);
1823 struct iommu_group *group = iommu_group_get(client->dev);
1824 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1825 struct tegra_dc *dc = host1x_client_to_dc(client);
1826 struct tegra_drm *tegra = drm->dev_private;
1827 struct drm_plane *primary = NULL;
1828 struct drm_plane *cursor = NULL;
1829 int err;
1830
1831 dc->syncpt = host1x_syncpt_request(client, flags);
1832 if (!dc->syncpt)
1833 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1834
1835 if (group && tegra->domain) {
1836 if (group != tegra->group) {
1837 err = iommu_attach_group(tegra->domain, group);
1838 if (err < 0) {
1839 dev_err(dc->dev,
1840 "failed to attach to domain: %d\n",
1841 err);
1842 return err;
1843 }
1844
1845 tegra->group = group;
1846 }
1847
1848 dc->domain = tegra->domain;
1849 }
1850
1851 if (dc->soc->wgrps)
1852 primary = tegra_dc_add_shared_planes(drm, dc);
1853 else
1854 primary = tegra_dc_add_planes(drm, dc);
1855
1856 if (IS_ERR(primary)) {
1857 err = PTR_ERR(primary);
1858 goto cleanup;
1859 }
1860
1861 if (dc->soc->supports_cursor) {
1862 cursor = tegra_dc_cursor_plane_create(drm, dc);
1863 if (IS_ERR(cursor)) {
1864 err = PTR_ERR(cursor);
1865 goto cleanup;
1866 }
1867 }
1868
1869 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1870 &tegra_crtc_funcs, NULL);
1871 if (err < 0)
1872 goto cleanup;
1873
1874 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1875
1876 /*
1877 * Keep track of the minimum pitch alignment across all display
1878 * controllers.
1879 */
1880 if (dc->soc->pitch_align > tegra->pitch_align)
1881 tegra->pitch_align = dc->soc->pitch_align;
1882
1883 err = tegra_dc_rgb_init(drm, dc);
1884 if (err < 0 && err != -ENODEV) {
1885 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1886 goto cleanup;
1887 }
1888
1889 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1890 dev_name(dc->dev), dc);
1891 if (err < 0) {
1892 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1893 err);
1894 goto cleanup;
1895 }
1896
1897 return 0;
1898
1899 cleanup:
1900 if (!IS_ERR_OR_NULL(cursor))
1901 drm_plane_cleanup(cursor);
1902
1903 if (!IS_ERR(primary))
1904 drm_plane_cleanup(primary);
1905
1906 if (group && dc->domain) {
1907 if (group == tegra->group) {
1908 iommu_detach_group(dc->domain, group);
1909 tegra->group = NULL;
1910 }
1911
1912 dc->domain = NULL;
1913 }
1914
1915 return err;
1916 }
1917
1918 static int tegra_dc_exit(struct host1x_client *client)
1919 {
1920 struct drm_device *drm = dev_get_drvdata(client->parent);
1921 struct iommu_group *group = iommu_group_get(client->dev);
1922 struct tegra_dc *dc = host1x_client_to_dc(client);
1923 struct tegra_drm *tegra = drm->dev_private;
1924 int err;
1925
1926 devm_free_irq(dc->dev, dc->irq, dc);
1927
1928 err = tegra_dc_rgb_exit(dc);
1929 if (err) {
1930 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1931 return err;
1932 }
1933
1934 if (group && dc->domain) {
1935 if (group == tegra->group) {
1936 iommu_detach_group(dc->domain, group);
1937 tegra->group = NULL;
1938 }
1939
1940 dc->domain = NULL;
1941 }
1942
1943 host1x_syncpt_free(dc->syncpt);
1944
1945 return 0;
1946 }
1947
1948 static const struct host1x_client_ops dc_client_ops = {
1949 .init = tegra_dc_init,
1950 .exit = tegra_dc_exit,
1951 };
1952
1953 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1954 .supports_background_color = false,
1955 .supports_interlacing = false,
1956 .supports_cursor = false,
1957 .supports_block_linear = false,
1958 .supports_blending = false,
1959 .pitch_align = 8,
1960 .has_powergate = false,
1961 .coupled_pm = true,
1962 .has_nvdisplay = false,
1963 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
1964 .primary_formats = tegra20_primary_formats,
1965 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
1966 .overlay_formats = tegra20_overlay_formats,
1967 };
1968
1969 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1970 .supports_background_color = false,
1971 .supports_interlacing = false,
1972 .supports_cursor = false,
1973 .supports_block_linear = false,
1974 .supports_blending = false,
1975 .pitch_align = 8,
1976 .has_powergate = false,
1977 .coupled_pm = false,
1978 .has_nvdisplay = false,
1979 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
1980 .primary_formats = tegra20_primary_formats,
1981 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
1982 .overlay_formats = tegra20_overlay_formats,
1983 };
1984
1985 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1986 .supports_background_color = false,
1987 .supports_interlacing = false,
1988 .supports_cursor = false,
1989 .supports_block_linear = false,
1990 .supports_blending = false,
1991 .pitch_align = 64,
1992 .has_powergate = true,
1993 .coupled_pm = false,
1994 .has_nvdisplay = false,
1995 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
1996 .primary_formats = tegra114_primary_formats,
1997 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
1998 .overlay_formats = tegra114_overlay_formats,
1999 };
2000
2001 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2002 .supports_background_color = true,
2003 .supports_interlacing = true,
2004 .supports_cursor = true,
2005 .supports_block_linear = true,
2006 .supports_blending = true,
2007 .pitch_align = 64,
2008 .has_powergate = true,
2009 .coupled_pm = false,
2010 .has_nvdisplay = false,
2011 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2012 .primary_formats = tegra114_primary_formats,
2013 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2014 .overlay_formats = tegra114_overlay_formats,
2015 };
2016
2017 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2018 .supports_background_color = true,
2019 .supports_interlacing = true,
2020 .supports_cursor = true,
2021 .supports_block_linear = true,
2022 .supports_blending = true,
2023 .pitch_align = 64,
2024 .has_powergate = true,
2025 .coupled_pm = false,
2026 .has_nvdisplay = false,
2027 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2028 .primary_formats = tegra114_primary_formats,
2029 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2030 .overlay_formats = tegra114_overlay_formats,
2031 };
2032
2033 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2034 {
2035 .index = 0,
2036 .dc = 0,
2037 .windows = (const unsigned int[]) { 0 },
2038 .num_windows = 1,
2039 }, {
2040 .index = 1,
2041 .dc = 1,
2042 .windows = (const unsigned int[]) { 1 },
2043 .num_windows = 1,
2044 }, {
2045 .index = 2,
2046 .dc = 1,
2047 .windows = (const unsigned int[]) { 2 },
2048 .num_windows = 1,
2049 }, {
2050 .index = 3,
2051 .dc = 2,
2052 .windows = (const unsigned int[]) { 3 },
2053 .num_windows = 1,
2054 }, {
2055 .index = 4,
2056 .dc = 2,
2057 .windows = (const unsigned int[]) { 4 },
2058 .num_windows = 1,
2059 }, {
2060 .index = 5,
2061 .dc = 2,
2062 .windows = (const unsigned int[]) { 5 },
2063 .num_windows = 1,
2064 },
2065 };
2066
2067 static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2068 .supports_background_color = true,
2069 .supports_interlacing = true,
2070 .supports_cursor = true,
2071 .supports_block_linear = true,
2072 .supports_blending = true,
2073 .pitch_align = 64,
2074 .has_powergate = false,
2075 .coupled_pm = false,
2076 .has_nvdisplay = true,
2077 .wgrps = tegra186_dc_wgrps,
2078 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2079 };
2080
2081 static const struct of_device_id tegra_dc_of_match[] = {
2082 {
2083 .compatible = "nvidia,tegra186-dc",
2084 .data = &tegra186_dc_soc_info,
2085 }, {
2086 .compatible = "nvidia,tegra210-dc",
2087 .data = &tegra210_dc_soc_info,
2088 }, {
2089 .compatible = "nvidia,tegra124-dc",
2090 .data = &tegra124_dc_soc_info,
2091 }, {
2092 .compatible = "nvidia,tegra114-dc",
2093 .data = &tegra114_dc_soc_info,
2094 }, {
2095 .compatible = "nvidia,tegra30-dc",
2096 .data = &tegra30_dc_soc_info,
2097 }, {
2098 .compatible = "nvidia,tegra20-dc",
2099 .data = &tegra20_dc_soc_info,
2100 }, {
2101 /* sentinel */
2102 }
2103 };
2104 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
2105
2106 static int tegra_dc_parse_dt(struct tegra_dc *dc)
2107 {
2108 struct device_node *np;
2109 u32 value = 0;
2110 int err;
2111
2112 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
2113 if (err < 0) {
2114 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
2115
2116 /*
2117 * If the nvidia,head property isn't present, try to find the
2118 * correct head number by looking up the position of this
2119 * display controller's node within the device tree. Assuming
2120 * that the nodes are ordered properly in the DTS file and
2121 * that the translation into a flattened device tree blob
2122 * preserves that ordering this will actually yield the right
2123 * head number.
2124 *
2125 * If those assumptions don't hold, this will still work for
2126 * cases where only a single display controller is used.
2127 */
2128 for_each_matching_node(np, tegra_dc_of_match) {
2129 if (np == dc->dev->of_node) {
2130 of_node_put(np);
2131 break;
2132 }
2133
2134 value++;
2135 }
2136 }
2137
2138 dc->pipe = value;
2139
2140 return 0;
2141 }
2142
2143 static int tegra_dc_match_by_pipe(struct device *dev, void *data)
2144 {
2145 struct tegra_dc *dc = dev_get_drvdata(dev);
2146 unsigned int pipe = (unsigned long)data;
2147
2148 return dc->pipe == pipe;
2149 }
2150
2151 static int tegra_dc_couple(struct tegra_dc *dc)
2152 {
2153 /*
2154 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
2155 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
2156 * POWER_CONTROL registers during CRTC enabling.
2157 */
2158 if (dc->soc->coupled_pm && dc->pipe == 1) {
2159 u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE;
2160 struct device_link *link;
2161 struct device *partner;
2162
2163 partner = driver_find_device(dc->dev->driver, NULL, 0,
2164 tegra_dc_match_by_pipe);
2165 if (!partner)
2166 return -EPROBE_DEFER;
2167
2168 link = device_link_add(dc->dev, partner, flags);
2169 if (!link) {
2170 dev_err(dc->dev, "failed to link controllers\n");
2171 return -EINVAL;
2172 }
2173
2174 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));
2175 }
2176
2177 return 0;
2178 }
2179
2180 static int tegra_dc_probe(struct platform_device *pdev)
2181 {
2182 struct resource *regs;
2183 struct tegra_dc *dc;
2184 int err;
2185
2186 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
2187 if (!dc)
2188 return -ENOMEM;
2189
2190 dc->soc = of_device_get_match_data(&pdev->dev);
2191
2192 INIT_LIST_HEAD(&dc->list);
2193 dc->dev = &pdev->dev;
2194
2195 err = tegra_dc_parse_dt(dc);
2196 if (err < 0)
2197 return err;
2198
2199 err = tegra_dc_couple(dc);
2200 if (err < 0)
2201 return err;
2202
2203 dc->clk = devm_clk_get(&pdev->dev, NULL);
2204 if (IS_ERR(dc->clk)) {
2205 dev_err(&pdev->dev, "failed to get clock\n");
2206 return PTR_ERR(dc->clk);
2207 }
2208
2209 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2210 if (IS_ERR(dc->rst)) {
2211 dev_err(&pdev->dev, "failed to get reset\n");
2212 return PTR_ERR(dc->rst);
2213 }
2214
2215 /* assert reset and disable clock */
2216 err = clk_prepare_enable(dc->clk);
2217 if (err < 0)
2218 return err;
2219
2220 usleep_range(2000, 4000);
2221
2222 err = reset_control_assert(dc->rst);
2223 if (err < 0)
2224 return err;
2225
2226 usleep_range(2000, 4000);
2227
2228 clk_disable_unprepare(dc->clk);
2229
2230 if (dc->soc->has_powergate) {
2231 if (dc->pipe == 0)
2232 dc->powergate = TEGRA_POWERGATE_DIS;
2233 else
2234 dc->powergate = TEGRA_POWERGATE_DISB;
2235
2236 tegra_powergate_power_off(dc->powergate);
2237 }
2238
2239 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2240 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2241 if (IS_ERR(dc->regs))
2242 return PTR_ERR(dc->regs);
2243
2244 dc->irq = platform_get_irq(pdev, 0);
2245 if (dc->irq < 0) {
2246 dev_err(&pdev->dev, "failed to get IRQ\n");
2247 return -ENXIO;
2248 }
2249
2250 err = tegra_dc_rgb_probe(dc);
2251 if (err < 0 && err != -ENODEV) {
2252 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2253 return err;
2254 }
2255
2256 platform_set_drvdata(pdev, dc);
2257 pm_runtime_enable(&pdev->dev);
2258
2259 INIT_LIST_HEAD(&dc->client.list);
2260 dc->client.ops = &dc_client_ops;
2261 dc->client.dev = &pdev->dev;
2262
2263 err = host1x_client_register(&dc->client);
2264 if (err < 0) {
2265 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2266 err);
2267 return err;
2268 }
2269
2270 return 0;
2271 }
2272
2273 static int tegra_dc_remove(struct platform_device *pdev)
2274 {
2275 struct tegra_dc *dc = platform_get_drvdata(pdev);
2276 int err;
2277
2278 err = host1x_client_unregister(&dc->client);
2279 if (err < 0) {
2280 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2281 err);
2282 return err;
2283 }
2284
2285 err = tegra_dc_rgb_remove(dc);
2286 if (err < 0) {
2287 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2288 return err;
2289 }
2290
2291 pm_runtime_disable(&pdev->dev);
2292
2293 return 0;
2294 }
2295
2296 #ifdef CONFIG_PM
2297 static int tegra_dc_suspend(struct device *dev)
2298 {
2299 struct tegra_dc *dc = dev_get_drvdata(dev);
2300 int err;
2301
2302 err = reset_control_assert(dc->rst);
2303 if (err < 0) {
2304 dev_err(dev, "failed to assert reset: %d\n", err);
2305 return err;
2306 }
2307
2308 if (dc->soc->has_powergate)
2309 tegra_powergate_power_off(dc->powergate);
2310
2311 clk_disable_unprepare(dc->clk);
2312
2313 return 0;
2314 }
2315
2316 static int tegra_dc_resume(struct device *dev)
2317 {
2318 struct tegra_dc *dc = dev_get_drvdata(dev);
2319 int err;
2320
2321 if (dc->soc->has_powergate) {
2322 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2323 dc->rst);
2324 if (err < 0) {
2325 dev_err(dev, "failed to power partition: %d\n", err);
2326 return err;
2327 }
2328 } else {
2329 err = clk_prepare_enable(dc->clk);
2330 if (err < 0) {
2331 dev_err(dev, "failed to enable clock: %d\n", err);
2332 return err;
2333 }
2334
2335 err = reset_control_deassert(dc->rst);
2336 if (err < 0) {
2337 dev_err(dev, "failed to deassert reset: %d\n", err);
2338 return err;
2339 }
2340 }
2341
2342 return 0;
2343 }
2344 #endif
2345
2346 static const struct dev_pm_ops tegra_dc_pm_ops = {
2347 SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
2348 };
2349
2350 struct platform_driver tegra_dc_driver = {
2351 .driver = {
2352 .name = "tegra-dc",
2353 .of_match_table = tegra_dc_of_match,
2354 .pm = &tegra_dc_pm_ops,
2355 },
2356 .probe = tegra_dc_probe,
2357 .remove = tegra_dc_remove,
2358 };
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