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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / tegra / dsi.c
1 /*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/debugfs.h>
11 #include <linux/host1x.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_platform.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/reset.h>
18
19 #include <linux/regulator/consumer.h>
20
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_mipi_dsi.h>
23 #include <drm/drm_panel.h>
24
25 #include <video/mipi_display.h>
26
27 #include "dc.h"
28 #include "drm.h"
29 #include "dsi.h"
30 #include "mipi-phy.h"
31 #include "trace.h"
32
33 struct tegra_dsi_state {
34 struct drm_connector_state base;
35
36 struct mipi_dphy_timing timing;
37 unsigned long period;
38
39 unsigned int vrefresh;
40 unsigned int lanes;
41 unsigned long pclk;
42 unsigned long bclk;
43
44 enum tegra_dsi_format format;
45 unsigned int mul;
46 unsigned int div;
47 };
48
49 static inline struct tegra_dsi_state *
50 to_dsi_state(struct drm_connector_state *state)
51 {
52 return container_of(state, struct tegra_dsi_state, base);
53 }
54
55 struct tegra_dsi {
56 struct host1x_client client;
57 struct tegra_output output;
58 struct device *dev;
59
60 void __iomem *regs;
61
62 struct reset_control *rst;
63 struct clk *clk_parent;
64 struct clk *clk_lp;
65 struct clk *clk;
66
67 struct drm_info_list *debugfs_files;
68 struct drm_minor *minor;
69 struct dentry *debugfs;
70
71 unsigned long flags;
72 enum mipi_dsi_pixel_format format;
73 unsigned int lanes;
74
75 struct tegra_mipi_device *mipi;
76 struct mipi_dsi_host host;
77
78 struct regulator *vdd;
79
80 unsigned int video_fifo_depth;
81 unsigned int host_fifo_depth;
82
83 /* for ganged-mode support */
84 struct tegra_dsi *master;
85 struct tegra_dsi *slave;
86 };
87
88 static inline struct tegra_dsi *
89 host1x_client_to_dsi(struct host1x_client *client)
90 {
91 return container_of(client, struct tegra_dsi, client);
92 }
93
94 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
95 {
96 return container_of(host, struct tegra_dsi, host);
97 }
98
99 static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
100 {
101 return container_of(output, struct tegra_dsi, output);
102 }
103
104 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
105 {
106 return to_dsi_state(dsi->output.connector.state);
107 }
108
109 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset)
110 {
111 u32 value = readl(dsi->regs + (offset << 2));
112
113 trace_dsi_readl(dsi->dev, offset, value);
114
115 return value;
116 }
117
118 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
119 unsigned int offset)
120 {
121 trace_dsi_writel(dsi->dev, offset, value);
122 writel(value, dsi->regs + (offset << 2));
123 }
124
125 static int tegra_dsi_show_regs(struct seq_file *s, void *data)
126 {
127 struct drm_info_node *node = s->private;
128 struct tegra_dsi *dsi = node->info_ent->data;
129 struct drm_crtc *crtc = dsi->output.encoder.crtc;
130 struct drm_device *drm = node->minor->dev;
131 int err = 0;
132
133 drm_modeset_lock_all(drm);
134
135 if (!crtc || !crtc->state->active) {
136 err = -EBUSY;
137 goto unlock;
138 }
139
140 #define DUMP_REG(name) \
141 seq_printf(s, "%-32s %#05x %08x\n", #name, name, \
142 tegra_dsi_readl(dsi, name))
143
144 DUMP_REG(DSI_INCR_SYNCPT);
145 DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
146 DUMP_REG(DSI_INCR_SYNCPT_ERROR);
147 DUMP_REG(DSI_CTXSW);
148 DUMP_REG(DSI_RD_DATA);
149 DUMP_REG(DSI_WR_DATA);
150 DUMP_REG(DSI_POWER_CONTROL);
151 DUMP_REG(DSI_INT_ENABLE);
152 DUMP_REG(DSI_INT_STATUS);
153 DUMP_REG(DSI_INT_MASK);
154 DUMP_REG(DSI_HOST_CONTROL);
155 DUMP_REG(DSI_CONTROL);
156 DUMP_REG(DSI_SOL_DELAY);
157 DUMP_REG(DSI_MAX_THRESHOLD);
158 DUMP_REG(DSI_TRIGGER);
159 DUMP_REG(DSI_TX_CRC);
160 DUMP_REG(DSI_STATUS);
161
162 DUMP_REG(DSI_INIT_SEQ_CONTROL);
163 DUMP_REG(DSI_INIT_SEQ_DATA_0);
164 DUMP_REG(DSI_INIT_SEQ_DATA_1);
165 DUMP_REG(DSI_INIT_SEQ_DATA_2);
166 DUMP_REG(DSI_INIT_SEQ_DATA_3);
167 DUMP_REG(DSI_INIT_SEQ_DATA_4);
168 DUMP_REG(DSI_INIT_SEQ_DATA_5);
169 DUMP_REG(DSI_INIT_SEQ_DATA_6);
170 DUMP_REG(DSI_INIT_SEQ_DATA_7);
171
172 DUMP_REG(DSI_PKT_SEQ_0_LO);
173 DUMP_REG(DSI_PKT_SEQ_0_HI);
174 DUMP_REG(DSI_PKT_SEQ_1_LO);
175 DUMP_REG(DSI_PKT_SEQ_1_HI);
176 DUMP_REG(DSI_PKT_SEQ_2_LO);
177 DUMP_REG(DSI_PKT_SEQ_2_HI);
178 DUMP_REG(DSI_PKT_SEQ_3_LO);
179 DUMP_REG(DSI_PKT_SEQ_3_HI);
180 DUMP_REG(DSI_PKT_SEQ_4_LO);
181 DUMP_REG(DSI_PKT_SEQ_4_HI);
182 DUMP_REG(DSI_PKT_SEQ_5_LO);
183 DUMP_REG(DSI_PKT_SEQ_5_HI);
184
185 DUMP_REG(DSI_DCS_CMDS);
186
187 DUMP_REG(DSI_PKT_LEN_0_1);
188 DUMP_REG(DSI_PKT_LEN_2_3);
189 DUMP_REG(DSI_PKT_LEN_4_5);
190 DUMP_REG(DSI_PKT_LEN_6_7);
191
192 DUMP_REG(DSI_PHY_TIMING_0);
193 DUMP_REG(DSI_PHY_TIMING_1);
194 DUMP_REG(DSI_PHY_TIMING_2);
195 DUMP_REG(DSI_BTA_TIMING);
196
197 DUMP_REG(DSI_TIMEOUT_0);
198 DUMP_REG(DSI_TIMEOUT_1);
199 DUMP_REG(DSI_TO_TALLY);
200
201 DUMP_REG(DSI_PAD_CONTROL_0);
202 DUMP_REG(DSI_PAD_CONTROL_CD);
203 DUMP_REG(DSI_PAD_CD_STATUS);
204 DUMP_REG(DSI_VIDEO_MODE_CONTROL);
205 DUMP_REG(DSI_PAD_CONTROL_1);
206 DUMP_REG(DSI_PAD_CONTROL_2);
207 DUMP_REG(DSI_PAD_CONTROL_3);
208 DUMP_REG(DSI_PAD_CONTROL_4);
209
210 DUMP_REG(DSI_GANGED_MODE_CONTROL);
211 DUMP_REG(DSI_GANGED_MODE_START);
212 DUMP_REG(DSI_GANGED_MODE_SIZE);
213
214 DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
215 DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
216
217 DUMP_REG(DSI_INIT_SEQ_DATA_8);
218 DUMP_REG(DSI_INIT_SEQ_DATA_9);
219 DUMP_REG(DSI_INIT_SEQ_DATA_10);
220 DUMP_REG(DSI_INIT_SEQ_DATA_11);
221 DUMP_REG(DSI_INIT_SEQ_DATA_12);
222 DUMP_REG(DSI_INIT_SEQ_DATA_13);
223 DUMP_REG(DSI_INIT_SEQ_DATA_14);
224 DUMP_REG(DSI_INIT_SEQ_DATA_15);
225
226 #undef DUMP_REG
227
228 unlock:
229 drm_modeset_unlock_all(drm);
230 return err;
231 }
232
233 static struct drm_info_list debugfs_files[] = {
234 { "regs", tegra_dsi_show_regs, 0, NULL },
235 };
236
237 static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
238 struct drm_minor *minor)
239 {
240 const char *name = dev_name(dsi->dev);
241 unsigned int i;
242 int err;
243
244 dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
245 if (!dsi->debugfs)
246 return -ENOMEM;
247
248 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
249 GFP_KERNEL);
250 if (!dsi->debugfs_files) {
251 err = -ENOMEM;
252 goto remove;
253 }
254
255 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
256 dsi->debugfs_files[i].data = dsi;
257
258 err = drm_debugfs_create_files(dsi->debugfs_files,
259 ARRAY_SIZE(debugfs_files),
260 dsi->debugfs, minor);
261 if (err < 0)
262 goto free;
263
264 dsi->minor = minor;
265
266 return 0;
267
268 free:
269 kfree(dsi->debugfs_files);
270 dsi->debugfs_files = NULL;
271 remove:
272 debugfs_remove(dsi->debugfs);
273 dsi->debugfs = NULL;
274
275 return err;
276 }
277
278 static void tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
279 {
280 drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
281 dsi->minor);
282 dsi->minor = NULL;
283
284 kfree(dsi->debugfs_files);
285 dsi->debugfs_files = NULL;
286
287 debugfs_remove(dsi->debugfs);
288 dsi->debugfs = NULL;
289 }
290
291 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
292 #define PKT_LEN0(len) (((len) & 0x07) << 0)
293 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
294 #define PKT_LEN1(len) (((len) & 0x07) << 10)
295 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
296 #define PKT_LEN2(len) (((len) & 0x07) << 20)
297
298 #define PKT_LP (1 << 30)
299 #define NUM_PKT_SEQ 12
300
301 /*
302 * non-burst mode with sync pulses
303 */
304 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
305 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
306 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
307 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
308 PKT_LP,
309 [ 1] = 0,
310 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
311 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
312 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
313 PKT_LP,
314 [ 3] = 0,
315 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
316 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
317 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
318 PKT_LP,
319 [ 5] = 0,
320 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
321 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
322 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
323 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
324 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
325 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
326 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
327 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
328 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
329 PKT_LP,
330 [ 9] = 0,
331 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
332 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
333 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
334 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
335 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
336 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
337 };
338
339 /*
340 * non-burst mode with sync events
341 */
342 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
343 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
344 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
345 PKT_LP,
346 [ 1] = 0,
347 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
348 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
349 PKT_LP,
350 [ 3] = 0,
351 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
352 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
353 PKT_LP,
354 [ 5] = 0,
355 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
356 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
357 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
358 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
359 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
360 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
361 PKT_LP,
362 [ 9] = 0,
363 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
364 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
365 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
366 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
367 };
368
369 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
370 [ 0] = 0,
371 [ 1] = 0,
372 [ 2] = 0,
373 [ 3] = 0,
374 [ 4] = 0,
375 [ 5] = 0,
376 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
377 [ 7] = 0,
378 [ 8] = 0,
379 [ 9] = 0,
380 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
381 [11] = 0,
382 };
383
384 static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
385 unsigned long period,
386 const struct mipi_dphy_timing *timing)
387 {
388 u32 value;
389
390 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
391 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
392 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
393 DSI_TIMING_FIELD(timing->hsprepare, period, 1);
394 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
395
396 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
397 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
398 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
399 DSI_TIMING_FIELD(timing->lpx, period, 1);
400 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
401
402 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
403 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
404 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
405 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
406
407 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
408 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
409 DSI_TIMING_FIELD(timing->tago, period, 1);
410 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
411
412 if (dsi->slave)
413 tegra_dsi_set_phy_timing(dsi->slave, period, timing);
414 }
415
416 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
417 unsigned int *mulp, unsigned int *divp)
418 {
419 switch (format) {
420 case MIPI_DSI_FMT_RGB666_PACKED:
421 case MIPI_DSI_FMT_RGB888:
422 *mulp = 3;
423 *divp = 1;
424 break;
425
426 case MIPI_DSI_FMT_RGB565:
427 *mulp = 2;
428 *divp = 1;
429 break;
430
431 case MIPI_DSI_FMT_RGB666:
432 *mulp = 9;
433 *divp = 4;
434 break;
435
436 default:
437 return -EINVAL;
438 }
439
440 return 0;
441 }
442
443 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
444 enum tegra_dsi_format *fmt)
445 {
446 switch (format) {
447 case MIPI_DSI_FMT_RGB888:
448 *fmt = TEGRA_DSI_FORMAT_24P;
449 break;
450
451 case MIPI_DSI_FMT_RGB666:
452 *fmt = TEGRA_DSI_FORMAT_18NP;
453 break;
454
455 case MIPI_DSI_FMT_RGB666_PACKED:
456 *fmt = TEGRA_DSI_FORMAT_18P;
457 break;
458
459 case MIPI_DSI_FMT_RGB565:
460 *fmt = TEGRA_DSI_FORMAT_16P;
461 break;
462
463 default:
464 return -EINVAL;
465 }
466
467 return 0;
468 }
469
470 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
471 unsigned int size)
472 {
473 u32 value;
474
475 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
476 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
477
478 value = DSI_GANGED_MODE_CONTROL_ENABLE;
479 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
480 }
481
482 static void tegra_dsi_enable(struct tegra_dsi *dsi)
483 {
484 u32 value;
485
486 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
487 value |= DSI_POWER_CONTROL_ENABLE;
488 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
489
490 if (dsi->slave)
491 tegra_dsi_enable(dsi->slave);
492 }
493
494 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
495 {
496 if (dsi->master)
497 return dsi->master->lanes + dsi->lanes;
498
499 if (dsi->slave)
500 return dsi->lanes + dsi->slave->lanes;
501
502 return dsi->lanes;
503 }
504
505 static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
506 const struct drm_display_mode *mode)
507 {
508 unsigned int hact, hsw, hbp, hfp, i, mul, div;
509 struct tegra_dsi_state *state;
510 const u32 *pkt_seq;
511 u32 value;
512
513 /* XXX: pass in state into this function? */
514 if (dsi->master)
515 state = tegra_dsi_get_state(dsi->master);
516 else
517 state = tegra_dsi_get_state(dsi);
518
519 mul = state->mul;
520 div = state->div;
521
522 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
523 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
524 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
525 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
526 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
527 pkt_seq = pkt_seq_video_non_burst_sync_events;
528 } else {
529 DRM_DEBUG_KMS("Command mode\n");
530 pkt_seq = pkt_seq_command_mode;
531 }
532
533 value = DSI_CONTROL_CHANNEL(0) |
534 DSI_CONTROL_FORMAT(state->format) |
535 DSI_CONTROL_LANES(dsi->lanes - 1) |
536 DSI_CONTROL_SOURCE(pipe);
537 tegra_dsi_writel(dsi, value, DSI_CONTROL);
538
539 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
540
541 value = DSI_HOST_CONTROL_HS;
542 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
543
544 value = tegra_dsi_readl(dsi, DSI_CONTROL);
545
546 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
547 value |= DSI_CONTROL_HS_CLK_CTRL;
548
549 value &= ~DSI_CONTROL_TX_TRIG(3);
550
551 /* enable DCS commands for command mode */
552 if (dsi->flags & MIPI_DSI_MODE_VIDEO)
553 value &= ~DSI_CONTROL_DCS_ENABLE;
554 else
555 value |= DSI_CONTROL_DCS_ENABLE;
556
557 value |= DSI_CONTROL_VIDEO_ENABLE;
558 value &= ~DSI_CONTROL_HOST_ENABLE;
559 tegra_dsi_writel(dsi, value, DSI_CONTROL);
560
561 for (i = 0; i < NUM_PKT_SEQ; i++)
562 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
563
564 if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
565 /* horizontal active pixels */
566 hact = mode->hdisplay * mul / div;
567
568 /* horizontal sync width */
569 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
570
571 /* horizontal back porch */
572 hbp = (mode->htotal - mode->hsync_end) * mul / div;
573
574 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
575 hbp += hsw;
576
577 /* horizontal front porch */
578 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
579
580 /* subtract packet overhead */
581 hsw -= 10;
582 hbp -= 14;
583 hfp -= 8;
584
585 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
586 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
587 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
588 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
589
590 /* set SOL delay (for non-burst mode only) */
591 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
592
593 /* TODO: implement ganged mode */
594 } else {
595 u16 bytes;
596
597 if (dsi->master || dsi->slave) {
598 /*
599 * For ganged mode, assume symmetric left-right mode.
600 */
601 bytes = 1 + (mode->hdisplay / 2) * mul / div;
602 } else {
603 /* 1 byte (DCS command) + pixel data */
604 bytes = 1 + mode->hdisplay * mul / div;
605 }
606
607 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
608 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
609 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
610 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
611
612 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
613 MIPI_DCS_WRITE_MEMORY_CONTINUE;
614 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
615
616 /* set SOL delay */
617 if (dsi->master || dsi->slave) {
618 unsigned long delay, bclk, bclk_ganged;
619 unsigned int lanes = state->lanes;
620
621 /* SOL to valid, valid to FIFO and FIFO write delay */
622 delay = 4 + 4 + 2;
623 delay = DIV_ROUND_UP(delay * mul, div * lanes);
624 /* FIFO read delay */
625 delay = delay + 6;
626
627 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
628 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
629 value = bclk - bclk_ganged + delay + 20;
630 } else {
631 /* TODO: revisit for non-ganged mode */
632 value = 8 * mul / div;
633 }
634
635 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
636 }
637
638 if (dsi->slave) {
639 tegra_dsi_configure(dsi->slave, pipe, mode);
640
641 /*
642 * TODO: Support modes other than symmetrical left-right
643 * split.
644 */
645 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
646 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
647 mode->hdisplay / 2);
648 }
649 }
650
651 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
652 {
653 u32 value;
654
655 timeout = jiffies + msecs_to_jiffies(timeout);
656
657 while (time_before(jiffies, timeout)) {
658 value = tegra_dsi_readl(dsi, DSI_STATUS);
659 if (value & DSI_STATUS_IDLE)
660 return 0;
661
662 usleep_range(1000, 2000);
663 }
664
665 return -ETIMEDOUT;
666 }
667
668 static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
669 {
670 u32 value;
671
672 value = tegra_dsi_readl(dsi, DSI_CONTROL);
673 value &= ~DSI_CONTROL_VIDEO_ENABLE;
674 tegra_dsi_writel(dsi, value, DSI_CONTROL);
675
676 if (dsi->slave)
677 tegra_dsi_video_disable(dsi->slave);
678 }
679
680 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
681 {
682 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
683 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
684 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
685 }
686
687 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
688 {
689 u32 value;
690
691 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
692 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
693
694 return 0;
695 }
696
697 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
698 {
699 u32 value;
700
701 /*
702 * XXX Is this still needed? The module reset is deasserted right
703 * before this function is called.
704 */
705 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
706 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
707 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
708 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
709 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
710
711 /* start calibration */
712 tegra_dsi_pad_enable(dsi);
713
714 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
715 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
716 DSI_PAD_OUT_CLK(0x0);
717 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
718
719 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
720 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
721 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
722
723 return tegra_mipi_calibrate(dsi->mipi);
724 }
725
726 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
727 unsigned int vrefresh)
728 {
729 unsigned int timeout;
730 u32 value;
731
732 /* one frame high-speed transmission timeout */
733 timeout = (bclk / vrefresh) / 512;
734 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
735 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
736
737 /* 2 ms peripheral timeout for panel */
738 timeout = 2 * bclk / 512 * 1000;
739 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
740 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
741
742 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
743 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
744
745 if (dsi->slave)
746 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
747 }
748
749 static void tegra_dsi_disable(struct tegra_dsi *dsi)
750 {
751 u32 value;
752
753 if (dsi->slave) {
754 tegra_dsi_ganged_disable(dsi->slave);
755 tegra_dsi_ganged_disable(dsi);
756 }
757
758 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
759 value &= ~DSI_POWER_CONTROL_ENABLE;
760 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
761
762 if (dsi->slave)
763 tegra_dsi_disable(dsi->slave);
764
765 usleep_range(5000, 10000);
766 }
767
768 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
769 {
770 u32 value;
771
772 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
773 value &= ~DSI_POWER_CONTROL_ENABLE;
774 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
775
776 usleep_range(300, 1000);
777
778 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
779 value |= DSI_POWER_CONTROL_ENABLE;
780 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
781
782 usleep_range(300, 1000);
783
784 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
785 if (value)
786 tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
787
788 if (dsi->slave)
789 tegra_dsi_soft_reset(dsi->slave);
790 }
791
792 static void tegra_dsi_connector_reset(struct drm_connector *connector)
793 {
794 struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
795
796 if (!state)
797 return;
798
799 if (connector->state) {
800 __drm_atomic_helper_connector_destroy_state(connector->state);
801 kfree(connector->state);
802 }
803
804 __drm_atomic_helper_connector_reset(connector, &state->base);
805 }
806
807 static struct drm_connector_state *
808 tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
809 {
810 struct tegra_dsi_state *state = to_dsi_state(connector->state);
811 struct tegra_dsi_state *copy;
812
813 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
814 if (!copy)
815 return NULL;
816
817 __drm_atomic_helper_connector_duplicate_state(connector,
818 &copy->base);
819
820 return &copy->base;
821 }
822
823 static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
824 .reset = tegra_dsi_connector_reset,
825 .detect = tegra_output_connector_detect,
826 .fill_modes = drm_helper_probe_single_connector_modes,
827 .destroy = tegra_output_connector_destroy,
828 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
829 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
830 };
831
832 static enum drm_mode_status
833 tegra_dsi_connector_mode_valid(struct drm_connector *connector,
834 struct drm_display_mode *mode)
835 {
836 return MODE_OK;
837 }
838
839 static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
840 .get_modes = tegra_output_connector_get_modes,
841 .mode_valid = tegra_dsi_connector_mode_valid,
842 };
843
844 static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = {
845 .destroy = tegra_output_encoder_destroy,
846 };
847
848 static void tegra_dsi_unprepare(struct tegra_dsi *dsi)
849 {
850 int err;
851
852 if (dsi->slave)
853 tegra_dsi_unprepare(dsi->slave);
854
855 err = tegra_mipi_disable(dsi->mipi);
856 if (err < 0)
857 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n",
858 err);
859
860 pm_runtime_put(dsi->dev);
861 }
862
863 static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
864 {
865 struct tegra_output *output = encoder_to_output(encoder);
866 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
867 struct tegra_dsi *dsi = to_dsi(output);
868 u32 value;
869 int err;
870
871 if (output->panel)
872 drm_panel_disable(output->panel);
873
874 tegra_dsi_video_disable(dsi);
875
876 /*
877 * The following accesses registers of the display controller, so make
878 * sure it's only executed when the output is attached to one.
879 */
880 if (dc) {
881 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
882 value &= ~DSI_ENABLE;
883 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
884
885 tegra_dc_commit(dc);
886 }
887
888 err = tegra_dsi_wait_idle(dsi, 100);
889 if (err < 0)
890 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
891
892 tegra_dsi_soft_reset(dsi);
893
894 if (output->panel)
895 drm_panel_unprepare(output->panel);
896
897 tegra_dsi_disable(dsi);
898
899 tegra_dsi_unprepare(dsi);
900 }
901
902 static void tegra_dsi_prepare(struct tegra_dsi *dsi)
903 {
904 int err;
905
906 pm_runtime_get_sync(dsi->dev);
907
908 err = tegra_mipi_enable(dsi->mipi);
909 if (err < 0)
910 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n",
911 err);
912
913 err = tegra_dsi_pad_calibrate(dsi);
914 if (err < 0)
915 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
916
917 if (dsi->slave)
918 tegra_dsi_prepare(dsi->slave);
919 }
920
921 static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
922 {
923 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
924 struct tegra_output *output = encoder_to_output(encoder);
925 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
926 struct tegra_dsi *dsi = to_dsi(output);
927 struct tegra_dsi_state *state;
928 u32 value;
929
930 tegra_dsi_prepare(dsi);
931
932 state = tegra_dsi_get_state(dsi);
933
934 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
935
936 /*
937 * The D-PHY timing fields are expressed in byte-clock cycles, so
938 * multiply the period by 8.
939 */
940 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
941
942 if (output->panel)
943 drm_panel_prepare(output->panel);
944
945 tegra_dsi_configure(dsi, dc->pipe, mode);
946
947 /* enable display controller */
948 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
949 value |= DSI_ENABLE;
950 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
951
952 tegra_dc_commit(dc);
953
954 /* enable DSI controller */
955 tegra_dsi_enable(dsi);
956
957 if (output->panel)
958 drm_panel_enable(output->panel);
959 }
960
961 static int
962 tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
963 struct drm_crtc_state *crtc_state,
964 struct drm_connector_state *conn_state)
965 {
966 struct tegra_output *output = encoder_to_output(encoder);
967 struct tegra_dsi_state *state = to_dsi_state(conn_state);
968 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
969 struct tegra_dsi *dsi = to_dsi(output);
970 unsigned int scdiv;
971 unsigned long plld;
972 int err;
973
974 state->pclk = crtc_state->mode.clock * 1000;
975
976 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
977 if (err < 0)
978 return err;
979
980 state->lanes = tegra_dsi_get_lanes(dsi);
981
982 err = tegra_dsi_get_format(dsi->format, &state->format);
983 if (err < 0)
984 return err;
985
986 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);
987
988 /* compute byte clock */
989 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
990
991 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
992 state->lanes);
993 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
994 state->vrefresh);
995 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
996
997 /*
998 * Compute bit clock and round up to the next MHz.
999 */
1000 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
1001 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
1002
1003 err = mipi_dphy_timing_get_default(&state->timing, state->period);
1004 if (err < 0)
1005 return err;
1006
1007 err = mipi_dphy_timing_validate(&state->timing, state->period);
1008 if (err < 0) {
1009 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
1010 return err;
1011 }
1012
1013 /*
1014 * We divide the frequency by two here, but we make up for that by
1015 * setting the shift clock divider (further below) to half of the
1016 * correct value.
1017 */
1018 plld /= 2;
1019
1020 /*
1021 * Derive pixel clock from bit clock using the shift clock divider.
1022 * Note that this is only half of what we would expect, but we need
1023 * that to make up for the fact that we divided the bit clock by a
1024 * factor of two above.
1025 *
1026 * It's not clear exactly why this is necessary, but the display is
1027 * not working properly otherwise. Perhaps the PLLs cannot generate
1028 * frequencies sufficiently high.
1029 */
1030 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
1031
1032 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
1033 plld, scdiv);
1034 if (err < 0) {
1035 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1036 return err;
1037 }
1038
1039 return err;
1040 }
1041
1042 static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
1043 .disable = tegra_dsi_encoder_disable,
1044 .enable = tegra_dsi_encoder_enable,
1045 .atomic_check = tegra_dsi_encoder_atomic_check,
1046 };
1047
1048 static int tegra_dsi_init(struct host1x_client *client)
1049 {
1050 struct drm_device *drm = dev_get_drvdata(client->parent);
1051 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1052 int err;
1053
1054 /* Gangsters must not register their own outputs. */
1055 if (!dsi->master) {
1056 dsi->output.dev = client->dev;
1057
1058 drm_connector_init(drm, &dsi->output.connector,
1059 &tegra_dsi_connector_funcs,
1060 DRM_MODE_CONNECTOR_DSI);
1061 drm_connector_helper_add(&dsi->output.connector,
1062 &tegra_dsi_connector_helper_funcs);
1063 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1064
1065 drm_encoder_init(drm, &dsi->output.encoder,
1066 &tegra_dsi_encoder_funcs,
1067 DRM_MODE_ENCODER_DSI, NULL);
1068 drm_encoder_helper_add(&dsi->output.encoder,
1069 &tegra_dsi_encoder_helper_funcs);
1070
1071 drm_mode_connector_attach_encoder(&dsi->output.connector,
1072 &dsi->output.encoder);
1073 drm_connector_register(&dsi->output.connector);
1074
1075 err = tegra_output_init(drm, &dsi->output);
1076 if (err < 0)
1077 dev_err(dsi->dev, "failed to initialize output: %d\n",
1078 err);
1079
1080 dsi->output.encoder.possible_crtcs = 0x3;
1081 }
1082
1083 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1084 err = tegra_dsi_debugfs_init(dsi, drm->primary);
1085 if (err < 0)
1086 dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
1087 }
1088
1089 return 0;
1090 }
1091
1092 static int tegra_dsi_exit(struct host1x_client *client)
1093 {
1094 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1095
1096 tegra_output_exit(&dsi->output);
1097
1098 if (IS_ENABLED(CONFIG_DEBUG_FS))
1099 tegra_dsi_debugfs_exit(dsi);
1100
1101 regulator_disable(dsi->vdd);
1102
1103 return 0;
1104 }
1105
1106 static const struct host1x_client_ops dsi_client_ops = {
1107 .init = tegra_dsi_init,
1108 .exit = tegra_dsi_exit,
1109 };
1110
1111 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1112 {
1113 struct clk *parent;
1114 int err;
1115
1116 parent = clk_get_parent(dsi->clk);
1117 if (!parent)
1118 return -EINVAL;
1119
1120 err = clk_set_parent(parent, dsi->clk_parent);
1121 if (err < 0)
1122 return err;
1123
1124 return 0;
1125 }
1126
1127 static const char * const error_report[16] = {
1128 "SoT Error",
1129 "SoT Sync Error",
1130 "EoT Sync Error",
1131 "Escape Mode Entry Command Error",
1132 "Low-Power Transmit Sync Error",
1133 "Peripheral Timeout Error",
1134 "False Control Error",
1135 "Contention Detected",
1136 "ECC Error, single-bit",
1137 "ECC Error, multi-bit",
1138 "Checksum Error",
1139 "DSI Data Type Not Recognized",
1140 "DSI VC ID Invalid",
1141 "Invalid Transmission Length",
1142 "Reserved",
1143 "DSI Protocol Violation",
1144 };
1145
1146 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1147 const struct mipi_dsi_msg *msg,
1148 size_t count)
1149 {
1150 u8 *rx = msg->rx_buf;
1151 unsigned int i, j, k;
1152 size_t size = 0;
1153 u16 errors;
1154 u32 value;
1155
1156 /* read and parse packet header */
1157 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1158
1159 switch (value & 0x3f) {
1160 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1161 errors = (value >> 8) & 0xffff;
1162 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1163 errors);
1164 for (i = 0; i < ARRAY_SIZE(error_report); i++)
1165 if (errors & BIT(i))
1166 dev_dbg(dsi->dev, " %2u: %s\n", i,
1167 error_report[i]);
1168 break;
1169
1170 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1171 rx[0] = (value >> 8) & 0xff;
1172 size = 1;
1173 break;
1174
1175 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1176 rx[0] = (value >> 8) & 0xff;
1177 rx[1] = (value >> 16) & 0xff;
1178 size = 2;
1179 break;
1180
1181 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1182 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1183 break;
1184
1185 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1186 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1187 break;
1188
1189 default:
1190 dev_err(dsi->dev, "unhandled response type: %02x\n",
1191 value & 0x3f);
1192 return -EPROTO;
1193 }
1194
1195 size = min(size, msg->rx_len);
1196
1197 if (msg->rx_buf && size > 0) {
1198 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1199 u8 *rx = msg->rx_buf + j;
1200
1201 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1202
1203 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1204 rx[j + k] = (value >> (k << 3)) & 0xff;
1205 }
1206 }
1207
1208 return size;
1209 }
1210
1211 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1212 {
1213 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1214
1215 timeout = jiffies + msecs_to_jiffies(timeout);
1216
1217 while (time_before(jiffies, timeout)) {
1218 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1219 if ((value & DSI_TRIGGER_HOST) == 0)
1220 return 0;
1221
1222 usleep_range(1000, 2000);
1223 }
1224
1225 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1226 return -ETIMEDOUT;
1227 }
1228
1229 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1230 unsigned long timeout)
1231 {
1232 timeout = jiffies + msecs_to_jiffies(250);
1233
1234 while (time_before(jiffies, timeout)) {
1235 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1236 u8 count = value & 0x1f;
1237
1238 if (count > 0)
1239 return count;
1240
1241 usleep_range(1000, 2000);
1242 }
1243
1244 DRM_DEBUG_KMS("peripheral returned no data\n");
1245 return -ETIMEDOUT;
1246 }
1247
1248 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1249 const void *buffer, size_t size)
1250 {
1251 const u8 *buf = buffer;
1252 size_t i, j;
1253 u32 value;
1254
1255 for (j = 0; j < size; j += 4) {
1256 value = 0;
1257
1258 for (i = 0; i < 4 && j + i < size; i++)
1259 value |= buf[j + i] << (i << 3);
1260
1261 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1262 }
1263 }
1264
1265 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1266 const struct mipi_dsi_msg *msg)
1267 {
1268 struct tegra_dsi *dsi = host_to_tegra(host);
1269 struct mipi_dsi_packet packet;
1270 const u8 *header;
1271 size_t count;
1272 ssize_t err;
1273 u32 value;
1274
1275 err = mipi_dsi_create_packet(&packet, msg);
1276 if (err < 0)
1277 return err;
1278
1279 header = packet.header;
1280
1281 /* maximum FIFO depth is 1920 words */
1282 if (packet.size > dsi->video_fifo_depth * 4)
1283 return -ENOSPC;
1284
1285 /* reset underflow/overflow flags */
1286 value = tegra_dsi_readl(dsi, DSI_STATUS);
1287 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1288 value = DSI_HOST_CONTROL_FIFO_RESET;
1289 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1290 usleep_range(10, 20);
1291 }
1292
1293 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1294 value |= DSI_POWER_CONTROL_ENABLE;
1295 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1296
1297 usleep_range(5000, 10000);
1298
1299 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1300 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1301
1302 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1303 value |= DSI_HOST_CONTROL_HS;
1304
1305 /*
1306 * The host FIFO has a maximum of 64 words, so larger transmissions
1307 * need to use the video FIFO.
1308 */
1309 if (packet.size > dsi->host_fifo_depth * 4)
1310 value |= DSI_HOST_CONTROL_FIFO_SEL;
1311
1312 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1313
1314 /*
1315 * For reads and messages with explicitly requested ACK, generate a
1316 * BTA sequence after the transmission of the packet.
1317 */
1318 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1319 (msg->rx_buf && msg->rx_len > 0)) {
1320 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1321 value |= DSI_HOST_CONTROL_PKT_BTA;
1322 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1323 }
1324
1325 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1326 tegra_dsi_writel(dsi, value, DSI_CONTROL);
1327
1328 /* write packet header, ECC is generated by hardware */
1329 value = header[2] << 16 | header[1] << 8 | header[0];
1330 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1331
1332 /* write payload (if any) */
1333 if (packet.payload_length > 0)
1334 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1335 packet.payload_length);
1336
1337 err = tegra_dsi_transmit(dsi, 250);
1338 if (err < 0)
1339 return err;
1340
1341 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1342 (msg->rx_buf && msg->rx_len > 0)) {
1343 err = tegra_dsi_wait_for_response(dsi, 250);
1344 if (err < 0)
1345 return err;
1346
1347 count = err;
1348
1349 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1350 switch (value) {
1351 case 0x84:
1352 /*
1353 dev_dbg(dsi->dev, "ACK\n");
1354 */
1355 break;
1356
1357 case 0x87:
1358 /*
1359 dev_dbg(dsi->dev, "ESCAPE\n");
1360 */
1361 break;
1362
1363 default:
1364 dev_err(dsi->dev, "unknown status: %08x\n", value);
1365 break;
1366 }
1367
1368 if (count > 1) {
1369 err = tegra_dsi_read_response(dsi, msg, count);
1370 if (err < 0)
1371 dev_err(dsi->dev,
1372 "failed to parse response: %zd\n",
1373 err);
1374 else {
1375 /*
1376 * For read commands, return the number of
1377 * bytes returned by the peripheral.
1378 */
1379 count = err;
1380 }
1381 }
1382 } else {
1383 /*
1384 * For write commands, we have transmitted the 4-byte header
1385 * plus the variable-length payload.
1386 */
1387 count = 4 + packet.payload_length;
1388 }
1389
1390 return count;
1391 }
1392
1393 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1394 {
1395 struct clk *parent;
1396 int err;
1397
1398 /* make sure both DSI controllers share the same PLL */
1399 parent = clk_get_parent(dsi->slave->clk);
1400 if (!parent)
1401 return -EINVAL;
1402
1403 err = clk_set_parent(parent, dsi->clk_parent);
1404 if (err < 0)
1405 return err;
1406
1407 return 0;
1408 }
1409
1410 static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1411 struct mipi_dsi_device *device)
1412 {
1413 struct tegra_dsi *dsi = host_to_tegra(host);
1414
1415 dsi->flags = device->mode_flags;
1416 dsi->format = device->format;
1417 dsi->lanes = device->lanes;
1418
1419 if (dsi->slave) {
1420 int err;
1421
1422 dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1423 dev_name(&device->dev));
1424
1425 err = tegra_dsi_ganged_setup(dsi);
1426 if (err < 0) {
1427 dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1428 err);
1429 return err;
1430 }
1431 }
1432
1433 /*
1434 * Slaves don't have a panel associated with them, so they provide
1435 * merely the second channel.
1436 */
1437 if (!dsi->master) {
1438 struct tegra_output *output = &dsi->output;
1439
1440 output->panel = of_drm_find_panel(device->dev.of_node);
1441 if (output->panel && output->connector.dev) {
1442 drm_panel_attach(output->panel, &output->connector);
1443 drm_helper_hpd_irq_event(output->connector.dev);
1444 }
1445 }
1446
1447 return 0;
1448 }
1449
1450 static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1451 struct mipi_dsi_device *device)
1452 {
1453 struct tegra_dsi *dsi = host_to_tegra(host);
1454 struct tegra_output *output = &dsi->output;
1455
1456 if (output->panel && &device->dev == output->panel->dev) {
1457 output->panel = NULL;
1458
1459 if (output->connector.dev)
1460 drm_helper_hpd_irq_event(output->connector.dev);
1461 }
1462
1463 return 0;
1464 }
1465
1466 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1467 .attach = tegra_dsi_host_attach,
1468 .detach = tegra_dsi_host_detach,
1469 .transfer = tegra_dsi_host_transfer,
1470 };
1471
1472 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1473 {
1474 struct device_node *np;
1475
1476 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1477 if (np) {
1478 struct platform_device *gangster = of_find_device_by_node(np);
1479
1480 dsi->slave = platform_get_drvdata(gangster);
1481 of_node_put(np);
1482
1483 if (!dsi->slave)
1484 return -EPROBE_DEFER;
1485
1486 dsi->slave->master = dsi;
1487 }
1488
1489 return 0;
1490 }
1491
1492 static int tegra_dsi_probe(struct platform_device *pdev)
1493 {
1494 struct tegra_dsi *dsi;
1495 struct resource *regs;
1496 int err;
1497
1498 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1499 if (!dsi)
1500 return -ENOMEM;
1501
1502 dsi->output.dev = dsi->dev = &pdev->dev;
1503 dsi->video_fifo_depth = 1920;
1504 dsi->host_fifo_depth = 64;
1505
1506 err = tegra_dsi_ganged_probe(dsi);
1507 if (err < 0)
1508 return err;
1509
1510 err = tegra_output_probe(&dsi->output);
1511 if (err < 0)
1512 return err;
1513
1514 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1515
1516 /*
1517 * Assume these values by default. When a DSI peripheral driver
1518 * attaches to the DSI host, the parameters will be taken from
1519 * the attached device.
1520 */
1521 dsi->flags = MIPI_DSI_MODE_VIDEO;
1522 dsi->format = MIPI_DSI_FMT_RGB888;
1523 dsi->lanes = 4;
1524
1525 if (!pdev->dev.pm_domain) {
1526 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1527 if (IS_ERR(dsi->rst))
1528 return PTR_ERR(dsi->rst);
1529 }
1530
1531 dsi->clk = devm_clk_get(&pdev->dev, NULL);
1532 if (IS_ERR(dsi->clk)) {
1533 dev_err(&pdev->dev, "cannot get DSI clock\n");
1534 return PTR_ERR(dsi->clk);
1535 }
1536
1537 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1538 if (IS_ERR(dsi->clk_lp)) {
1539 dev_err(&pdev->dev, "cannot get low-power clock\n");
1540 return PTR_ERR(dsi->clk_lp);
1541 }
1542
1543 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1544 if (IS_ERR(dsi->clk_parent)) {
1545 dev_err(&pdev->dev, "cannot get parent clock\n");
1546 return PTR_ERR(dsi->clk_parent);
1547 }
1548
1549 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1550 if (IS_ERR(dsi->vdd)) {
1551 dev_err(&pdev->dev, "cannot get VDD supply\n");
1552 return PTR_ERR(dsi->vdd);
1553 }
1554
1555 err = tegra_dsi_setup_clocks(dsi);
1556 if (err < 0) {
1557 dev_err(&pdev->dev, "cannot setup clocks\n");
1558 return err;
1559 }
1560
1561 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1562 dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
1563 if (IS_ERR(dsi->regs))
1564 return PTR_ERR(dsi->regs);
1565
1566 dsi->mipi = tegra_mipi_request(&pdev->dev);
1567 if (IS_ERR(dsi->mipi))
1568 return PTR_ERR(dsi->mipi);
1569
1570 dsi->host.ops = &tegra_dsi_host_ops;
1571 dsi->host.dev = &pdev->dev;
1572
1573 err = mipi_dsi_host_register(&dsi->host);
1574 if (err < 0) {
1575 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
1576 goto mipi_free;
1577 }
1578
1579 platform_set_drvdata(pdev, dsi);
1580 pm_runtime_enable(&pdev->dev);
1581
1582 INIT_LIST_HEAD(&dsi->client.list);
1583 dsi->client.ops = &dsi_client_ops;
1584 dsi->client.dev = &pdev->dev;
1585
1586 err = host1x_client_register(&dsi->client);
1587 if (err < 0) {
1588 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1589 err);
1590 goto unregister;
1591 }
1592
1593 return 0;
1594
1595 unregister:
1596 mipi_dsi_host_unregister(&dsi->host);
1597 mipi_free:
1598 tegra_mipi_free(dsi->mipi);
1599 return err;
1600 }
1601
1602 static int tegra_dsi_remove(struct platform_device *pdev)
1603 {
1604 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1605 int err;
1606
1607 pm_runtime_disable(&pdev->dev);
1608
1609 err = host1x_client_unregister(&dsi->client);
1610 if (err < 0) {
1611 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1612 err);
1613 return err;
1614 }
1615
1616 tegra_output_remove(&dsi->output);
1617
1618 mipi_dsi_host_unregister(&dsi->host);
1619 tegra_mipi_free(dsi->mipi);
1620
1621 return 0;
1622 }
1623
1624 #ifdef CONFIG_PM
1625 static int tegra_dsi_suspend(struct device *dev)
1626 {
1627 struct tegra_dsi *dsi = dev_get_drvdata(dev);
1628 int err;
1629
1630 if (dsi->rst) {
1631 err = reset_control_assert(dsi->rst);
1632 if (err < 0) {
1633 dev_err(dev, "failed to assert reset: %d\n", err);
1634 return err;
1635 }
1636 }
1637
1638 usleep_range(1000, 2000);
1639
1640 clk_disable_unprepare(dsi->clk_lp);
1641 clk_disable_unprepare(dsi->clk);
1642
1643 regulator_disable(dsi->vdd);
1644
1645 return 0;
1646 }
1647
1648 static int tegra_dsi_resume(struct device *dev)
1649 {
1650 struct tegra_dsi *dsi = dev_get_drvdata(dev);
1651 int err;
1652
1653 err = regulator_enable(dsi->vdd);
1654 if (err < 0) {
1655 dev_err(dsi->dev, "failed to enable VDD supply: %d\n", err);
1656 return err;
1657 }
1658
1659 err = clk_prepare_enable(dsi->clk);
1660 if (err < 0) {
1661 dev_err(dev, "cannot enable DSI clock: %d\n", err);
1662 goto disable_vdd;
1663 }
1664
1665 err = clk_prepare_enable(dsi->clk_lp);
1666 if (err < 0) {
1667 dev_err(dev, "cannot enable low-power clock: %d\n", err);
1668 goto disable_clk;
1669 }
1670
1671 usleep_range(1000, 2000);
1672
1673 if (dsi->rst) {
1674 err = reset_control_deassert(dsi->rst);
1675 if (err < 0) {
1676 dev_err(dev, "cannot assert reset: %d\n", err);
1677 goto disable_clk_lp;
1678 }
1679 }
1680
1681 return 0;
1682
1683 disable_clk_lp:
1684 clk_disable_unprepare(dsi->clk_lp);
1685 disable_clk:
1686 clk_disable_unprepare(dsi->clk);
1687 disable_vdd:
1688 regulator_disable(dsi->vdd);
1689 return err;
1690 }
1691 #endif
1692
1693 static const struct dev_pm_ops tegra_dsi_pm_ops = {
1694 SET_RUNTIME_PM_OPS(tegra_dsi_suspend, tegra_dsi_resume, NULL)
1695 };
1696
1697 static const struct of_device_id tegra_dsi_of_match[] = {
1698 { .compatible = "nvidia,tegra210-dsi", },
1699 { .compatible = "nvidia,tegra132-dsi", },
1700 { .compatible = "nvidia,tegra124-dsi", },
1701 { .compatible = "nvidia,tegra114-dsi", },
1702 { },
1703 };
1704 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
1705
1706 struct platform_driver tegra_dsi_driver = {
1707 .driver = {
1708 .name = "tegra-dsi",
1709 .of_match_table = tegra_dsi_of_match,
1710 .pm = &tegra_dsi_pm_ops,
1711 },
1712 .probe = tegra_dsi_probe,
1713 .remove = tegra_dsi_remove,
1714 };
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