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[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / tegra / hdmi.c
1 /*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/gpio.h>
13 #include <linux/hdmi.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/reset.h>
16
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20
21 #include "hdmi.h"
22 #include "drm.h"
23 #include "dc.h"
24
25 struct tmds_config {
26 unsigned int pclk;
27 u32 pll0;
28 u32 pll1;
29 u32 pe_current;
30 u32 drive_current;
31 u32 peak_current;
32 };
33
34 struct tegra_hdmi_config {
35 const struct tmds_config *tmds;
36 unsigned int num_tmds;
37
38 unsigned long fuse_override_offset;
39 u32 fuse_override_value;
40
41 bool has_sor_io_peak_current;
42 };
43
44 struct tegra_hdmi {
45 struct host1x_client client;
46 struct tegra_output output;
47 struct device *dev;
48
49 struct regulator *hdmi;
50 struct regulator *pll;
51 struct regulator *vdd;
52
53 void __iomem *regs;
54 unsigned int irq;
55
56 struct clk *clk_parent;
57 struct clk *clk;
58 struct reset_control *rst;
59
60 const struct tegra_hdmi_config *config;
61
62 unsigned int audio_source;
63 unsigned int audio_freq;
64 bool stereo;
65 bool dvi;
66
67 struct drm_info_list *debugfs_files;
68 struct drm_minor *minor;
69 struct dentry *debugfs;
70 };
71
72 static inline struct tegra_hdmi *
73 host1x_client_to_hdmi(struct host1x_client *client)
74 {
75 return container_of(client, struct tegra_hdmi, client);
76 }
77
78 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
79 {
80 return container_of(output, struct tegra_hdmi, output);
81 }
82
83 #define HDMI_AUDIOCLK_FREQ 216000000
84 #define HDMI_REKEY_DEFAULT 56
85
86 enum {
87 AUTO = 0,
88 SPDIF,
89 HDA,
90 };
91
92 static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
93 unsigned long offset)
94 {
95 return readl(hdmi->regs + (offset << 2));
96 }
97
98 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
99 unsigned long offset)
100 {
101 writel(value, hdmi->regs + (offset << 2));
102 }
103
104 struct tegra_hdmi_audio_config {
105 unsigned int pclk;
106 unsigned int n;
107 unsigned int cts;
108 unsigned int aval;
109 };
110
111 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
112 { 25200000, 4096, 25200, 24000 },
113 { 27000000, 4096, 27000, 24000 },
114 { 74250000, 4096, 74250, 24000 },
115 { 148500000, 4096, 148500, 24000 },
116 { 0, 0, 0, 0 },
117 };
118
119 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
120 { 25200000, 5880, 26250, 25000 },
121 { 27000000, 5880, 28125, 25000 },
122 { 74250000, 4704, 61875, 20000 },
123 { 148500000, 4704, 123750, 20000 },
124 { 0, 0, 0, 0 },
125 };
126
127 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
128 { 25200000, 6144, 25200, 24000 },
129 { 27000000, 6144, 27000, 24000 },
130 { 74250000, 6144, 74250, 24000 },
131 { 148500000, 6144, 148500, 24000 },
132 { 0, 0, 0, 0 },
133 };
134
135 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
136 { 25200000, 11760, 26250, 25000 },
137 { 27000000, 11760, 28125, 25000 },
138 { 74250000, 9408, 61875, 20000 },
139 { 148500000, 9408, 123750, 20000 },
140 { 0, 0, 0, 0 },
141 };
142
143 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
144 { 25200000, 12288, 25200, 24000 },
145 { 27000000, 12288, 27000, 24000 },
146 { 74250000, 12288, 74250, 24000 },
147 { 148500000, 12288, 148500, 24000 },
148 { 0, 0, 0, 0 },
149 };
150
151 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
152 { 25200000, 23520, 26250, 25000 },
153 { 27000000, 23520, 28125, 25000 },
154 { 74250000, 18816, 61875, 20000 },
155 { 148500000, 18816, 123750, 20000 },
156 { 0, 0, 0, 0 },
157 };
158
159 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
160 { 25200000, 24576, 25200, 24000 },
161 { 27000000, 24576, 27000, 24000 },
162 { 74250000, 24576, 74250, 24000 },
163 { 148500000, 24576, 148500, 24000 },
164 { 0, 0, 0, 0 },
165 };
166
167 static const struct tmds_config tegra20_tmds_config[] = {
168 { /* slow pixel clock modes */
169 .pclk = 27000000,
170 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
171 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
172 SOR_PLL_TX_REG_LOAD(3),
173 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
174 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
175 PE_CURRENT1(PE_CURRENT_0_0_mA) |
176 PE_CURRENT2(PE_CURRENT_0_0_mA) |
177 PE_CURRENT3(PE_CURRENT_0_0_mA),
178 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
179 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
180 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
181 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
182 },
183 { /* high pixel clock modes */
184 .pclk = UINT_MAX,
185 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
186 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
187 SOR_PLL_TX_REG_LOAD(3),
188 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
189 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
190 PE_CURRENT1(PE_CURRENT_6_0_mA) |
191 PE_CURRENT2(PE_CURRENT_6_0_mA) |
192 PE_CURRENT3(PE_CURRENT_6_0_mA),
193 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
194 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
195 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
196 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
197 },
198 };
199
200 static const struct tmds_config tegra30_tmds_config[] = {
201 { /* 480p modes */
202 .pclk = 27000000,
203 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
204 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
205 SOR_PLL_TX_REG_LOAD(0),
206 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
207 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
208 PE_CURRENT1(PE_CURRENT_0_0_mA) |
209 PE_CURRENT2(PE_CURRENT_0_0_mA) |
210 PE_CURRENT3(PE_CURRENT_0_0_mA),
211 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
212 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
213 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
214 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
215 }, { /* 720p modes */
216 .pclk = 74250000,
217 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
218 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
219 SOR_PLL_TX_REG_LOAD(0),
220 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
221 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
222 PE_CURRENT1(PE_CURRENT_5_0_mA) |
223 PE_CURRENT2(PE_CURRENT_5_0_mA) |
224 PE_CURRENT3(PE_CURRENT_5_0_mA),
225 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
226 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
227 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
228 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
229 }, { /* 1080p modes */
230 .pclk = UINT_MAX,
231 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
232 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
233 SOR_PLL_TX_REG_LOAD(0),
234 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
235 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
236 PE_CURRENT1(PE_CURRENT_5_0_mA) |
237 PE_CURRENT2(PE_CURRENT_5_0_mA) |
238 PE_CURRENT3(PE_CURRENT_5_0_mA),
239 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
240 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
241 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
242 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
243 },
244 };
245
246 static const struct tmds_config tegra114_tmds_config[] = {
247 { /* 480p/576p / 25.2MHz/27MHz modes */
248 .pclk = 27000000,
249 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
250 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
251 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
252 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
253 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
254 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
255 PE_CURRENT3(PE_CURRENT_0_mA_T114),
256 .drive_current =
257 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
258 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
259 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
260 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
261 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
262 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
263 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
264 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
265 }, { /* 720p / 74.25MHz modes */
266 .pclk = 74250000,
267 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
268 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
269 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
270 SOR_PLL_TMDS_TERMADJ(0),
271 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
272 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
273 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
274 PE_CURRENT3(PE_CURRENT_15_mA_T114),
275 .drive_current =
276 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
277 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
278 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
279 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
280 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
281 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
282 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
283 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
284 }, { /* 1080p / 148.5MHz modes */
285 .pclk = 148500000,
286 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
287 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
288 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
289 SOR_PLL_TMDS_TERMADJ(0),
290 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
291 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
292 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
293 PE_CURRENT3(PE_CURRENT_10_mA_T114),
294 .drive_current =
295 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
296 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
297 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
298 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
299 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
300 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
301 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
302 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
303 }, { /* 225/297MHz modes */
304 .pclk = UINT_MAX,
305 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
306 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
307 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
308 | SOR_PLL_TMDS_TERM_ENABLE,
309 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
310 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
311 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
312 PE_CURRENT3(PE_CURRENT_0_mA_T114),
313 .drive_current =
314 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
315 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
316 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
317 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
318 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
319 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
320 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
321 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
322 },
323 };
324
325 static const struct tmds_config tegra124_tmds_config[] = {
326 { /* 480p/576p / 25.2MHz/27MHz modes */
327 .pclk = 27000000,
328 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
329 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
330 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
331 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
332 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
333 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
334 PE_CURRENT3(PE_CURRENT_0_mA_T114),
335 .drive_current =
336 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
337 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
338 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
339 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
340 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
341 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
342 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
343 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
344 }, { /* 720p / 74.25MHz modes */
345 .pclk = 74250000,
346 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
347 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
348 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
349 SOR_PLL_TMDS_TERMADJ(0),
350 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
351 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
352 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
353 PE_CURRENT3(PE_CURRENT_15_mA_T114),
354 .drive_current =
355 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
356 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
357 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
358 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
359 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
360 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
361 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
362 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
363 }, { /* 1080p / 148.5MHz modes */
364 .pclk = 148500000,
365 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
366 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
367 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
368 SOR_PLL_TMDS_TERMADJ(0),
369 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
370 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
371 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
372 PE_CURRENT3(PE_CURRENT_10_mA_T114),
373 .drive_current =
374 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
375 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
376 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
377 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
378 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
379 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
380 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
381 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
382 }, { /* 225/297MHz modes */
383 .pclk = UINT_MAX,
384 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
385 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
386 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
387 | SOR_PLL_TMDS_TERM_ENABLE,
388 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
389 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
390 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
391 PE_CURRENT3(PE_CURRENT_0_mA_T114),
392 .drive_current =
393 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
394 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
395 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
396 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
397 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
398 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
399 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
400 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
401 },
402 };
403
404 static const struct tegra_hdmi_audio_config *
405 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
406 {
407 const struct tegra_hdmi_audio_config *table;
408
409 switch (audio_freq) {
410 case 32000:
411 table = tegra_hdmi_audio_32k;
412 break;
413
414 case 44100:
415 table = tegra_hdmi_audio_44_1k;
416 break;
417
418 case 48000:
419 table = tegra_hdmi_audio_48k;
420 break;
421
422 case 88200:
423 table = tegra_hdmi_audio_88_2k;
424 break;
425
426 case 96000:
427 table = tegra_hdmi_audio_96k;
428 break;
429
430 case 176400:
431 table = tegra_hdmi_audio_176_4k;
432 break;
433
434 case 192000:
435 table = tegra_hdmi_audio_192k;
436 break;
437
438 default:
439 return NULL;
440 }
441
442 while (table->pclk) {
443 if (table->pclk == pclk)
444 return table;
445
446 table++;
447 }
448
449 return NULL;
450 }
451
452 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
453 {
454 const unsigned int freqs[] = {
455 32000, 44100, 48000, 88200, 96000, 176400, 192000
456 };
457 unsigned int i;
458
459 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
460 unsigned int f = freqs[i];
461 unsigned int eight_half;
462 unsigned int delta;
463 u32 value;
464
465 if (f > 96000)
466 delta = 2;
467 else if (f > 48000)
468 delta = 6;
469 else
470 delta = 9;
471
472 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
473 value = AUDIO_FS_LOW(eight_half - delta) |
474 AUDIO_FS_HIGH(eight_half + delta);
475 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
476 }
477 }
478
479 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk)
480 {
481 struct device_node *node = hdmi->dev->of_node;
482 const struct tegra_hdmi_audio_config *config;
483 unsigned int offset = 0;
484 u32 value;
485
486 switch (hdmi->audio_source) {
487 case HDA:
488 value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
489 break;
490
491 case SPDIF:
492 value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
493 break;
494
495 default:
496 value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
497 break;
498 }
499
500 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
501 value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
502 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
503 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
504 } else {
505 value |= AUDIO_CNTRL0_INJECT_NULLSMPL;
506 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
507
508 value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
509 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
510 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
511 }
512
513 config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk);
514 if (!config) {
515 dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n",
516 hdmi->audio_freq, pclk);
517 return -EINVAL;
518 }
519
520 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
521
522 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
523 AUDIO_N_VALUE(config->n - 1);
524 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
525
526 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
527 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
528
529 value = ACR_SUBPACK_CTS(config->cts);
530 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
531
532 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
533 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
534
535 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
536 value &= ~AUDIO_N_RESETF;
537 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
538
539 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
540 switch (hdmi->audio_freq) {
541 case 32000:
542 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320;
543 break;
544
545 case 44100:
546 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441;
547 break;
548
549 case 48000:
550 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480;
551 break;
552
553 case 88200:
554 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882;
555 break;
556
557 case 96000:
558 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960;
559 break;
560
561 case 176400:
562 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764;
563 break;
564
565 case 192000:
566 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920;
567 break;
568 }
569
570 tegra_hdmi_writel(hdmi, config->aval, offset);
571 }
572
573 tegra_hdmi_setup_audio_fs_tables(hdmi);
574
575 return 0;
576 }
577
578 static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
579 {
580 u32 value = 0;
581 size_t i;
582
583 for (i = size; i > 0; i--)
584 value = (value << 8) | ptr[i - 1];
585
586 return value;
587 }
588
589 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
590 size_t size)
591 {
592 const u8 *ptr = data;
593 unsigned long offset;
594 size_t i, j;
595 u32 value;
596
597 switch (ptr[0]) {
598 case HDMI_INFOFRAME_TYPE_AVI:
599 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
600 break;
601
602 case HDMI_INFOFRAME_TYPE_AUDIO:
603 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
604 break;
605
606 case HDMI_INFOFRAME_TYPE_VENDOR:
607 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
608 break;
609
610 default:
611 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
612 ptr[0]);
613 return;
614 }
615
616 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
617 INFOFRAME_HEADER_VERSION(ptr[1]) |
618 INFOFRAME_HEADER_LEN(ptr[2]);
619 tegra_hdmi_writel(hdmi, value, offset);
620 offset++;
621
622 /*
623 * Each subpack contains 7 bytes, divided into:
624 * - subpack_low: bytes 0 - 3
625 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
626 */
627 for (i = 3, j = 0; i < size; i += 7, j += 8) {
628 size_t rem = size - i, num = min_t(size_t, rem, 4);
629
630 value = tegra_hdmi_subpack(&ptr[i], num);
631 tegra_hdmi_writel(hdmi, value, offset++);
632
633 num = min_t(size_t, rem - num, 3);
634
635 value = tegra_hdmi_subpack(&ptr[i + 4], num);
636 tegra_hdmi_writel(hdmi, value, offset++);
637 }
638 }
639
640 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
641 struct drm_display_mode *mode)
642 {
643 struct hdmi_avi_infoframe frame;
644 u8 buffer[17];
645 ssize_t err;
646
647 if (hdmi->dvi) {
648 tegra_hdmi_writel(hdmi, 0,
649 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
650 return;
651 }
652
653 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
654 if (err < 0) {
655 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
656 return;
657 }
658
659 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
660 if (err < 0) {
661 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
662 return;
663 }
664
665 tegra_hdmi_write_infopack(hdmi, buffer, err);
666
667 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
668 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
669 }
670
671 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
672 {
673 struct hdmi_audio_infoframe frame;
674 u8 buffer[14];
675 ssize_t err;
676
677 if (hdmi->dvi) {
678 tegra_hdmi_writel(hdmi, 0,
679 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
680 return;
681 }
682
683 err = hdmi_audio_infoframe_init(&frame);
684 if (err < 0) {
685 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
686 err);
687 return;
688 }
689
690 frame.channels = 2;
691
692 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
693 if (err < 0) {
694 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
695 err);
696 return;
697 }
698
699 /*
700 * The audio infoframe has only one set of subpack registers, so the
701 * infoframe needs to be truncated. One set of subpack registers can
702 * contain 7 bytes. Including the 3 byte header only the first 10
703 * bytes can be programmed.
704 */
705 tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
706
707 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
708 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
709 }
710
711 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
712 {
713 struct hdmi_vendor_infoframe frame;
714 u8 buffer[10];
715 ssize_t err;
716 u32 value;
717
718 if (!hdmi->stereo) {
719 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
720 value &= ~GENERIC_CTRL_ENABLE;
721 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
722 return;
723 }
724
725 hdmi_vendor_infoframe_init(&frame);
726 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
727
728 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
729 if (err < 0) {
730 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
731 err);
732 return;
733 }
734
735 tegra_hdmi_write_infopack(hdmi, buffer, err);
736
737 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
738 value |= GENERIC_CTRL_ENABLE;
739 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
740 }
741
742 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
743 const struct tmds_config *tmds)
744 {
745 u32 value;
746
747 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
748 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
749 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
750
751 tegra_hdmi_writel(hdmi, tmds->drive_current,
752 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
753
754 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
755 value |= hdmi->config->fuse_override_value;
756 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
757
758 if (hdmi->config->has_sor_io_peak_current)
759 tegra_hdmi_writel(hdmi, tmds->peak_current,
760 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
761 }
762
763 static bool tegra_output_is_hdmi(struct tegra_output *output)
764 {
765 struct edid *edid;
766
767 if (!output->connector.edid_blob_ptr)
768 return false;
769
770 edid = (struct edid *)output->connector.edid_blob_ptr->data;
771
772 return drm_detect_hdmi_monitor(edid);
773 }
774
775 static void tegra_hdmi_connector_dpms(struct drm_connector *connector,
776 int mode)
777 {
778 }
779
780 static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
781 .dpms = tegra_hdmi_connector_dpms,
782 .reset = drm_atomic_helper_connector_reset,
783 .detect = tegra_output_connector_detect,
784 .fill_modes = drm_helper_probe_single_connector_modes,
785 .destroy = tegra_output_connector_destroy,
786 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
787 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
788 };
789
790 static enum drm_mode_status
791 tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
792 struct drm_display_mode *mode)
793 {
794 struct tegra_output *output = connector_to_output(connector);
795 struct tegra_hdmi *hdmi = to_hdmi(output);
796 unsigned long pclk = mode->clock * 1000;
797 enum drm_mode_status status = MODE_OK;
798 struct clk *parent;
799 long err;
800
801 parent = clk_get_parent(hdmi->clk_parent);
802
803 err = clk_round_rate(parent, pclk * 4);
804 if (err <= 0)
805 status = MODE_NOCLOCK;
806
807 return status;
808 }
809
810 static const struct drm_connector_helper_funcs
811 tegra_hdmi_connector_helper_funcs = {
812 .get_modes = tegra_output_connector_get_modes,
813 .mode_valid = tegra_hdmi_connector_mode_valid,
814 .best_encoder = tegra_output_connector_best_encoder,
815 };
816
817 static const struct drm_encoder_funcs tegra_hdmi_encoder_funcs = {
818 .destroy = tegra_output_encoder_destroy,
819 };
820
821 static void tegra_hdmi_encoder_dpms(struct drm_encoder *encoder, int mode)
822 {
823 }
824
825 static void tegra_hdmi_encoder_prepare(struct drm_encoder *encoder)
826 {
827 }
828
829 static void tegra_hdmi_encoder_commit(struct drm_encoder *encoder)
830 {
831 }
832
833 static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder,
834 struct drm_display_mode *mode,
835 struct drm_display_mode *adjusted)
836 {
837 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
838 struct tegra_output *output = encoder_to_output(encoder);
839 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
840 struct device_node *node = output->dev->of_node;
841 struct tegra_hdmi *hdmi = to_hdmi(output);
842 unsigned int pulse_start, div82, pclk;
843 int retries = 1000;
844 u32 value;
845 int err;
846
847 hdmi->dvi = !tegra_output_is_hdmi(output);
848
849 pclk = mode->clock * 1000;
850 h_sync_width = mode->hsync_end - mode->hsync_start;
851 h_back_porch = mode->htotal - mode->hsync_end;
852 h_front_porch = mode->hsync_start - mode->hdisplay;
853
854 /* power up sequence */
855 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
856 value &= ~SOR_PLL_PDBG;
857 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
858
859 usleep_range(10, 20);
860
861 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
862 value &= ~SOR_PLL_PWR;
863 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
864
865 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
866 DC_DISP_DISP_TIMING_OPTIONS);
867 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
868 DC_DISP_DISP_COLOR_CONTROL);
869
870 /* video_preamble uses h_pulse2 */
871 pulse_start = 1 + h_sync_width + h_back_porch - 10;
872
873 tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
874
875 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
876 PULSE_LAST_END_A;
877 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
878
879 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
880 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
881
882 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
883 VSYNC_WINDOW_ENABLE;
884 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
885
886 if (dc->pipe)
887 value = HDMI_SRC_DISPLAYB;
888 else
889 value = HDMI_SRC_DISPLAYA;
890
891 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
892 (mode->vdisplay == 576)))
893 tegra_hdmi_writel(hdmi,
894 value | ARM_VIDEO_RANGE_FULL,
895 HDMI_NV_PDISP_INPUT_CONTROL);
896 else
897 tegra_hdmi_writel(hdmi,
898 value | ARM_VIDEO_RANGE_LIMITED,
899 HDMI_NV_PDISP_INPUT_CONTROL);
900
901 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
902 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
903 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
904
905 if (!hdmi->dvi) {
906 err = tegra_hdmi_setup_audio(hdmi, pclk);
907 if (err < 0)
908 hdmi->dvi = true;
909 }
910
911 if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) {
912 /*
913 * TODO: add ELD support
914 */
915 }
916
917 rekey = HDMI_REKEY_DEFAULT;
918 value = HDMI_CTRL_REKEY(rekey);
919 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
920 h_front_porch - rekey - 18) / 32);
921
922 if (!hdmi->dvi)
923 value |= HDMI_CTRL_ENABLE;
924
925 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
926
927 if (hdmi->dvi)
928 tegra_hdmi_writel(hdmi, 0x0,
929 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
930 else
931 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
932 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
933
934 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
935 tegra_hdmi_setup_audio_infoframe(hdmi);
936 tegra_hdmi_setup_stereo_infoframe(hdmi);
937
938 /* TMDS CONFIG */
939 for (i = 0; i < hdmi->config->num_tmds; i++) {
940 if (pclk <= hdmi->config->tmds[i].pclk) {
941 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
942 break;
943 }
944 }
945
946 tegra_hdmi_writel(hdmi,
947 SOR_SEQ_CTL_PU_PC(0) |
948 SOR_SEQ_PU_PC_ALT(0) |
949 SOR_SEQ_PD_PC(8) |
950 SOR_SEQ_PD_PC_ALT(8),
951 HDMI_NV_PDISP_SOR_SEQ_CTL);
952
953 value = SOR_SEQ_INST_WAIT_TIME(1) |
954 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
955 SOR_SEQ_INST_HALT |
956 SOR_SEQ_INST_PIN_A_LOW |
957 SOR_SEQ_INST_PIN_B_LOW |
958 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
959
960 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
961 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
962
963 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
964 value &= ~SOR_CSTM_ROTCLK(~0);
965 value |= SOR_CSTM_ROTCLK(2);
966 value |= SOR_CSTM_PLLDIV;
967 value &= ~SOR_CSTM_LVDS_ENABLE;
968 value &= ~SOR_CSTM_MODE_MASK;
969 value |= SOR_CSTM_MODE_TMDS;
970 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
971
972 /* start SOR */
973 tegra_hdmi_writel(hdmi,
974 SOR_PWR_NORMAL_STATE_PU |
975 SOR_PWR_NORMAL_START_NORMAL |
976 SOR_PWR_SAFE_STATE_PD |
977 SOR_PWR_SETTING_NEW_TRIGGER,
978 HDMI_NV_PDISP_SOR_PWR);
979 tegra_hdmi_writel(hdmi,
980 SOR_PWR_NORMAL_STATE_PU |
981 SOR_PWR_NORMAL_START_NORMAL |
982 SOR_PWR_SAFE_STATE_PD |
983 SOR_PWR_SETTING_NEW_DONE,
984 HDMI_NV_PDISP_SOR_PWR);
985
986 do {
987 BUG_ON(--retries < 0);
988 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
989 } while (value & SOR_PWR_SETTING_NEW_PENDING);
990
991 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
992 SOR_STATE_ASY_OWNER_HEAD0 |
993 SOR_STATE_ASY_SUBOWNER_BOTH |
994 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
995 SOR_STATE_ASY_DEPOL_POS;
996
997 /* setup sync polarities */
998 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
999 value |= SOR_STATE_ASY_HSYNCPOL_POS;
1000
1001 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1002 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
1003
1004 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1005 value |= SOR_STATE_ASY_VSYNCPOL_POS;
1006
1007 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1008 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
1009
1010 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
1011
1012 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1013 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
1014
1015 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1016 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1017 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
1018 HDMI_NV_PDISP_SOR_STATE1);
1019 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1020
1021 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1022 value |= HDMI_ENABLE;
1023 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1024
1025 tegra_dc_commit(dc);
1026
1027 /* TODO: add HDCP support */
1028 }
1029
1030 static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
1031 {
1032 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1033 u32 value;
1034
1035 /*
1036 * The following accesses registers of the display controller, so make
1037 * sure it's only executed when the output is attached to one.
1038 */
1039 if (dc) {
1040 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1041 value &= ~HDMI_ENABLE;
1042 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1043
1044 tegra_dc_commit(dc);
1045 }
1046 }
1047
1048 static int
1049 tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1050 struct drm_crtc_state *crtc_state,
1051 struct drm_connector_state *conn_state)
1052 {
1053 struct tegra_output *output = encoder_to_output(encoder);
1054 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1055 unsigned long pclk = crtc_state->mode.clock * 1000;
1056 struct tegra_hdmi *hdmi = to_hdmi(output);
1057 int err;
1058
1059 err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
1060 pclk, 0);
1061 if (err < 0) {
1062 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1063 return err;
1064 }
1065
1066 return err;
1067 }
1068
1069 static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
1070 .dpms = tegra_hdmi_encoder_dpms,
1071 .prepare = tegra_hdmi_encoder_prepare,
1072 .commit = tegra_hdmi_encoder_commit,
1073 .mode_set = tegra_hdmi_encoder_mode_set,
1074 .disable = tegra_hdmi_encoder_disable,
1075 .atomic_check = tegra_hdmi_encoder_atomic_check,
1076 };
1077
1078 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1079 {
1080 struct drm_info_node *node = s->private;
1081 struct tegra_hdmi *hdmi = node->info_ent->data;
1082 int err;
1083
1084 err = clk_prepare_enable(hdmi->clk);
1085 if (err)
1086 return err;
1087
1088 #define DUMP_REG(name) \
1089 seq_printf(s, "%-56s %#05x %08x\n", #name, name, \
1090 tegra_hdmi_readl(hdmi, name))
1091
1092 DUMP_REG(HDMI_CTXSW);
1093 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
1094 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
1095 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
1096 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
1097 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
1098 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
1099 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
1100 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
1101 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
1102 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
1103 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
1104 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
1105 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
1106 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
1107 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
1108 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
1109 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
1110 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
1111 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
1112 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
1113 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
1114 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
1115 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
1116 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
1117 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
1118 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
1119 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
1120 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
1121 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
1122 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
1123 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
1124 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
1125 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
1126 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
1127 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1128 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
1129 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
1130 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1131 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
1132 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
1133 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
1134 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1135 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
1136 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
1137 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
1138 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
1139 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
1140 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
1141 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
1142 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
1143 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
1144 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
1145 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
1146 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
1147 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
1148 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
1149 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
1150 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
1151 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
1152 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
1153 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
1154 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
1155 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
1156 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
1157 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
1158 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
1159 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
1160 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
1161 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
1162 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1163 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
1164 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
1165 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
1166 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
1167 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
1168 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
1169 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
1170 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
1171 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
1172 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
1173 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
1174 DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
1175 DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
1176 DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
1177 DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
1178 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
1179 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
1180 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
1181 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
1182 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
1183 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
1184 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
1185 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
1186 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
1187 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
1188 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
1189 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
1190 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
1191 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
1192 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
1193 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
1194 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
1195 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
1196 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1197 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1198 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1199 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1200 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1201 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1202 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1203 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1204 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1205 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1206 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1207 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1208 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1209 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1210 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1211 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1212 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1213 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1214 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1215 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1216 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1217 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1218 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1219 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1220 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1221 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1222 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1223 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1224 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1225 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1226 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1227 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1228 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1229 DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1230 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1231 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1232 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1233 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1234 DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1235 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1236 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1237 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1238 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1239 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1240 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1241 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1242 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1243 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1244 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1245 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1246 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1247 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1248 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1249 DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
1250
1251 #undef DUMP_REG
1252
1253 clk_disable_unprepare(hdmi->clk);
1254
1255 return 0;
1256 }
1257
1258 static struct drm_info_list debugfs_files[] = {
1259 { "regs", tegra_hdmi_show_regs, 0, NULL },
1260 };
1261
1262 static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1263 struct drm_minor *minor)
1264 {
1265 unsigned int i;
1266 int err;
1267
1268 hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1269 if (!hdmi->debugfs)
1270 return -ENOMEM;
1271
1272 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1273 GFP_KERNEL);
1274 if (!hdmi->debugfs_files) {
1275 err = -ENOMEM;
1276 goto remove;
1277 }
1278
1279 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1280 hdmi->debugfs_files[i].data = hdmi;
1281
1282 err = drm_debugfs_create_files(hdmi->debugfs_files,
1283 ARRAY_SIZE(debugfs_files),
1284 hdmi->debugfs, minor);
1285 if (err < 0)
1286 goto free;
1287
1288 hdmi->minor = minor;
1289
1290 return 0;
1291
1292 free:
1293 kfree(hdmi->debugfs_files);
1294 hdmi->debugfs_files = NULL;
1295 remove:
1296 debugfs_remove(hdmi->debugfs);
1297 hdmi->debugfs = NULL;
1298
1299 return err;
1300 }
1301
1302 static void tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1303 {
1304 drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1305 hdmi->minor);
1306 hdmi->minor = NULL;
1307
1308 kfree(hdmi->debugfs_files);
1309 hdmi->debugfs_files = NULL;
1310
1311 debugfs_remove(hdmi->debugfs);
1312 hdmi->debugfs = NULL;
1313 }
1314
1315 static int tegra_hdmi_init(struct host1x_client *client)
1316 {
1317 struct drm_device *drm = dev_get_drvdata(client->parent);
1318 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1319 int err;
1320
1321 hdmi->output.dev = client->dev;
1322
1323 drm_connector_init(drm, &hdmi->output.connector,
1324 &tegra_hdmi_connector_funcs,
1325 DRM_MODE_CONNECTOR_HDMIA);
1326 drm_connector_helper_add(&hdmi->output.connector,
1327 &tegra_hdmi_connector_helper_funcs);
1328 hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1329
1330 drm_encoder_init(drm, &hdmi->output.encoder, &tegra_hdmi_encoder_funcs,
1331 DRM_MODE_ENCODER_TMDS);
1332 drm_encoder_helper_add(&hdmi->output.encoder,
1333 &tegra_hdmi_encoder_helper_funcs);
1334
1335 drm_mode_connector_attach_encoder(&hdmi->output.connector,
1336 &hdmi->output.encoder);
1337 drm_connector_register(&hdmi->output.connector);
1338
1339 err = tegra_output_init(drm, &hdmi->output);
1340 if (err < 0) {
1341 dev_err(client->dev, "failed to initialize output: %d\n", err);
1342 return err;
1343 }
1344
1345 hdmi->output.encoder.possible_crtcs = 0x3;
1346
1347 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1348 err = tegra_hdmi_debugfs_init(hdmi, drm->primary);
1349 if (err < 0)
1350 dev_err(client->dev, "debugfs setup failed: %d\n", err);
1351 }
1352
1353 err = regulator_enable(hdmi->hdmi);
1354 if (err < 0) {
1355 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1356 err);
1357 return err;
1358 }
1359
1360 err = regulator_enable(hdmi->pll);
1361 if (err < 0) {
1362 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
1363 return err;
1364 }
1365
1366 err = regulator_enable(hdmi->vdd);
1367 if (err < 0) {
1368 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
1369 return err;
1370 }
1371
1372 err = clk_prepare_enable(hdmi->clk);
1373 if (err < 0) {
1374 dev_err(hdmi->dev, "failed to enable clock: %d\n", err);
1375 return err;
1376 }
1377
1378 reset_control_deassert(hdmi->rst);
1379
1380 return 0;
1381 }
1382
1383 static int tegra_hdmi_exit(struct host1x_client *client)
1384 {
1385 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1386
1387 tegra_output_exit(&hdmi->output);
1388
1389 clk_disable_unprepare(hdmi->clk);
1390 reset_control_assert(hdmi->rst);
1391
1392 regulator_disable(hdmi->vdd);
1393 regulator_disable(hdmi->pll);
1394 regulator_disable(hdmi->hdmi);
1395
1396 if (IS_ENABLED(CONFIG_DEBUG_FS))
1397 tegra_hdmi_debugfs_exit(hdmi);
1398
1399 return 0;
1400 }
1401
1402 static const struct host1x_client_ops hdmi_client_ops = {
1403 .init = tegra_hdmi_init,
1404 .exit = tegra_hdmi_exit,
1405 };
1406
1407 static const struct tegra_hdmi_config tegra20_hdmi_config = {
1408 .tmds = tegra20_tmds_config,
1409 .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1410 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1411 .fuse_override_value = 1 << 31,
1412 .has_sor_io_peak_current = false,
1413 };
1414
1415 static const struct tegra_hdmi_config tegra30_hdmi_config = {
1416 .tmds = tegra30_tmds_config,
1417 .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1418 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1419 .fuse_override_value = 1 << 31,
1420 .has_sor_io_peak_current = false,
1421 };
1422
1423 static const struct tegra_hdmi_config tegra114_hdmi_config = {
1424 .tmds = tegra114_tmds_config,
1425 .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1426 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1427 .fuse_override_value = 1 << 31,
1428 .has_sor_io_peak_current = true,
1429 };
1430
1431 static const struct tegra_hdmi_config tegra124_hdmi_config = {
1432 .tmds = tegra124_tmds_config,
1433 .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1434 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1435 .fuse_override_value = 1 << 31,
1436 .has_sor_io_peak_current = true,
1437 };
1438
1439 static const struct of_device_id tegra_hdmi_of_match[] = {
1440 { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
1441 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1442 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1443 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1444 { },
1445 };
1446 MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
1447
1448 static int tegra_hdmi_probe(struct platform_device *pdev)
1449 {
1450 const struct of_device_id *match;
1451 struct tegra_hdmi *hdmi;
1452 struct resource *regs;
1453 int err;
1454
1455 match = of_match_node(tegra_hdmi_of_match, pdev->dev.of_node);
1456 if (!match)
1457 return -ENODEV;
1458
1459 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1460 if (!hdmi)
1461 return -ENOMEM;
1462
1463 hdmi->config = match->data;
1464 hdmi->dev = &pdev->dev;
1465 hdmi->audio_source = AUTO;
1466 hdmi->audio_freq = 44100;
1467 hdmi->stereo = false;
1468 hdmi->dvi = false;
1469
1470 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1471 if (IS_ERR(hdmi->clk)) {
1472 dev_err(&pdev->dev, "failed to get clock\n");
1473 return PTR_ERR(hdmi->clk);
1474 }
1475
1476 hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1477 if (IS_ERR(hdmi->rst)) {
1478 dev_err(&pdev->dev, "failed to get reset\n");
1479 return PTR_ERR(hdmi->rst);
1480 }
1481
1482 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1483 if (IS_ERR(hdmi->clk_parent))
1484 return PTR_ERR(hdmi->clk_parent);
1485
1486 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1487 if (err < 0) {
1488 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1489 return err;
1490 }
1491
1492 hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1493 if (IS_ERR(hdmi->hdmi)) {
1494 dev_err(&pdev->dev, "failed to get HDMI regulator\n");
1495 return PTR_ERR(hdmi->hdmi);
1496 }
1497
1498 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1499 if (IS_ERR(hdmi->pll)) {
1500 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1501 return PTR_ERR(hdmi->pll);
1502 }
1503
1504 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1505 if (IS_ERR(hdmi->vdd)) {
1506 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1507 return PTR_ERR(hdmi->vdd);
1508 }
1509
1510 hdmi->output.dev = &pdev->dev;
1511
1512 err = tegra_output_probe(&hdmi->output);
1513 if (err < 0)
1514 return err;
1515
1516 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1517 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1518 if (IS_ERR(hdmi->regs))
1519 return PTR_ERR(hdmi->regs);
1520
1521 err = platform_get_irq(pdev, 0);
1522 if (err < 0)
1523 return err;
1524
1525 hdmi->irq = err;
1526
1527 INIT_LIST_HEAD(&hdmi->client.list);
1528 hdmi->client.ops = &hdmi_client_ops;
1529 hdmi->client.dev = &pdev->dev;
1530
1531 err = host1x_client_register(&hdmi->client);
1532 if (err < 0) {
1533 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1534 err);
1535 return err;
1536 }
1537
1538 platform_set_drvdata(pdev, hdmi);
1539
1540 return 0;
1541 }
1542
1543 static int tegra_hdmi_remove(struct platform_device *pdev)
1544 {
1545 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1546 int err;
1547
1548 err = host1x_client_unregister(&hdmi->client);
1549 if (err < 0) {
1550 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1551 err);
1552 return err;
1553 }
1554
1555 tegra_output_remove(&hdmi->output);
1556
1557 clk_disable_unprepare(hdmi->clk_parent);
1558 clk_disable_unprepare(hdmi->clk);
1559
1560 return 0;
1561 }
1562
1563 struct platform_driver tegra_hdmi_driver = {
1564 .driver = {
1565 .name = "tegra-hdmi",
1566 .owner = THIS_MODULE,
1567 .of_match_table = tegra_hdmi_of_match,
1568 },
1569 .probe = tegra_hdmi_probe,
1570 .remove = tegra_hdmi_remove,
1571 };
Ubuntu Hirsute Linux kernel mirror