]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/gpu/drm/tegra/sor.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm: Nuke drm_atomic_helper_connector_dpms
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / tegra / sor.c
1 /*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/debugfs.h>
12 #include <linux/gpio.h>
13 #include <linux/io.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/reset.h>
19
20 #include <soc/tegra/pmc.h>
21
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_dp_helper.h>
24 #include <drm/drm_panel.h>
25
26 #include "dc.h"
27 #include "drm.h"
28 #include "sor.h"
29
30 #define SOR_REKEY 0x38
31
32 struct tegra_sor_hdmi_settings {
33 unsigned long frequency;
34
35 u8 vcocap;
36 u8 ichpmp;
37 u8 loadadj;
38 u8 termadj;
39 u8 tx_pu;
40 u8 bg_vref;
41
42 u8 drive_current[4];
43 u8 preemphasis[4];
44 };
45
46 #if 1
47 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
48 {
49 .frequency = 54000000,
50 .vcocap = 0x0,
51 .ichpmp = 0x1,
52 .loadadj = 0x3,
53 .termadj = 0x9,
54 .tx_pu = 0x10,
55 .bg_vref = 0x8,
56 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
57 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
58 }, {
59 .frequency = 75000000,
60 .vcocap = 0x3,
61 .ichpmp = 0x1,
62 .loadadj = 0x3,
63 .termadj = 0x9,
64 .tx_pu = 0x40,
65 .bg_vref = 0x8,
66 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
67 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
68 }, {
69 .frequency = 150000000,
70 .vcocap = 0x3,
71 .ichpmp = 0x1,
72 .loadadj = 0x3,
73 .termadj = 0x9,
74 .tx_pu = 0x66,
75 .bg_vref = 0x8,
76 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
77 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
78 }, {
79 .frequency = 300000000,
80 .vcocap = 0x3,
81 .ichpmp = 0x1,
82 .loadadj = 0x3,
83 .termadj = 0x9,
84 .tx_pu = 0x66,
85 .bg_vref = 0xa,
86 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
87 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
88 }, {
89 .frequency = 600000000,
90 .vcocap = 0x3,
91 .ichpmp = 0x1,
92 .loadadj = 0x3,
93 .termadj = 0x9,
94 .tx_pu = 0x66,
95 .bg_vref = 0x8,
96 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
97 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
98 },
99 };
100 #else
101 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
102 {
103 .frequency = 75000000,
104 .vcocap = 0x3,
105 .ichpmp = 0x1,
106 .loadadj = 0x3,
107 .termadj = 0x9,
108 .tx_pu = 0x40,
109 .bg_vref = 0x8,
110 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
111 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
112 }, {
113 .frequency = 150000000,
114 .vcocap = 0x3,
115 .ichpmp = 0x1,
116 .loadadj = 0x3,
117 .termadj = 0x9,
118 .tx_pu = 0x66,
119 .bg_vref = 0x8,
120 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
121 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
122 }, {
123 .frequency = 300000000,
124 .vcocap = 0x3,
125 .ichpmp = 0x6,
126 .loadadj = 0x3,
127 .termadj = 0x9,
128 .tx_pu = 0x66,
129 .bg_vref = 0xf,
130 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
131 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
132 }, {
133 .frequency = 600000000,
134 .vcocap = 0x3,
135 .ichpmp = 0xa,
136 .loadadj = 0x3,
137 .termadj = 0xb,
138 .tx_pu = 0x66,
139 .bg_vref = 0xe,
140 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
141 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
142 },
143 };
144 #endif
145
146 struct tegra_sor_soc {
147 bool supports_edp;
148 bool supports_lvds;
149 bool supports_hdmi;
150 bool supports_dp;
151
152 const struct tegra_sor_hdmi_settings *settings;
153 unsigned int num_settings;
154
155 const u8 *xbar_cfg;
156 };
157
158 struct tegra_sor;
159
160 struct tegra_sor_ops {
161 const char *name;
162 int (*probe)(struct tegra_sor *sor);
163 int (*remove)(struct tegra_sor *sor);
164 };
165
166 struct tegra_sor {
167 struct host1x_client client;
168 struct tegra_output output;
169 struct device *dev;
170
171 const struct tegra_sor_soc *soc;
172 void __iomem *regs;
173
174 struct reset_control *rst;
175 struct clk *clk_parent;
176 struct clk *clk_brick;
177 struct clk *clk_safe;
178 struct clk *clk_src;
179 struct clk *clk_dp;
180 struct clk *clk;
181
182 struct drm_dp_aux *aux;
183
184 struct drm_info_list *debugfs_files;
185 struct drm_minor *minor;
186 struct dentry *debugfs;
187
188 const struct tegra_sor_ops *ops;
189
190 /* for HDMI 2.0 */
191 struct tegra_sor_hdmi_settings *settings;
192 unsigned int num_settings;
193
194 struct regulator *avdd_io_supply;
195 struct regulator *vdd_pll_supply;
196 struct regulator *hdmi_supply;
197 };
198
199 struct tegra_sor_state {
200 struct drm_connector_state base;
201
202 unsigned int bpc;
203 };
204
205 static inline struct tegra_sor_state *
206 to_sor_state(struct drm_connector_state *state)
207 {
208 return container_of(state, struct tegra_sor_state, base);
209 }
210
211 struct tegra_sor_config {
212 u32 bits_per_pixel;
213
214 u32 active_polarity;
215 u32 active_count;
216 u32 tu_size;
217 u32 active_frac;
218 u32 watermark;
219
220 u32 hblank_symbols;
221 u32 vblank_symbols;
222 };
223
224 static inline struct tegra_sor *
225 host1x_client_to_sor(struct host1x_client *client)
226 {
227 return container_of(client, struct tegra_sor, client);
228 }
229
230 static inline struct tegra_sor *to_sor(struct tegra_output *output)
231 {
232 return container_of(output, struct tegra_sor, output);
233 }
234
235 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset)
236 {
237 return readl(sor->regs + (offset << 2));
238 }
239
240 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
241 unsigned long offset)
242 {
243 writel(value, sor->regs + (offset << 2));
244 }
245
246 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
247 {
248 int err;
249
250 clk_disable_unprepare(sor->clk);
251
252 err = clk_set_parent(sor->clk, parent);
253 if (err < 0)
254 return err;
255
256 err = clk_prepare_enable(sor->clk);
257 if (err < 0)
258 return err;
259
260 return 0;
261 }
262
263 struct tegra_clk_sor_brick {
264 struct clk_hw hw;
265 struct tegra_sor *sor;
266 };
267
268 static inline struct tegra_clk_sor_brick *to_brick(struct clk_hw *hw)
269 {
270 return container_of(hw, struct tegra_clk_sor_brick, hw);
271 }
272
273 static const char * const tegra_clk_sor_brick_parents[] = {
274 "pll_d2_out0", "pll_dp"
275 };
276
277 static int tegra_clk_sor_brick_set_parent(struct clk_hw *hw, u8 index)
278 {
279 struct tegra_clk_sor_brick *brick = to_brick(hw);
280 struct tegra_sor *sor = brick->sor;
281 u32 value;
282
283 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
284 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
285
286 switch (index) {
287 case 0:
288 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
289 break;
290
291 case 1:
292 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
293 break;
294 }
295
296 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
297
298 return 0;
299 }
300
301 static u8 tegra_clk_sor_brick_get_parent(struct clk_hw *hw)
302 {
303 struct tegra_clk_sor_brick *brick = to_brick(hw);
304 struct tegra_sor *sor = brick->sor;
305 u8 parent = U8_MAX;
306 u32 value;
307
308 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
309
310 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
311 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
312 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
313 parent = 0;
314 break;
315
316 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
317 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
318 parent = 1;
319 break;
320 }
321
322 return parent;
323 }
324
325 static const struct clk_ops tegra_clk_sor_brick_ops = {
326 .set_parent = tegra_clk_sor_brick_set_parent,
327 .get_parent = tegra_clk_sor_brick_get_parent,
328 };
329
330 static struct clk *tegra_clk_sor_brick_register(struct tegra_sor *sor,
331 const char *name)
332 {
333 struct tegra_clk_sor_brick *brick;
334 struct clk_init_data init;
335 struct clk *clk;
336
337 brick = devm_kzalloc(sor->dev, sizeof(*brick), GFP_KERNEL);
338 if (!brick)
339 return ERR_PTR(-ENOMEM);
340
341 brick->sor = sor;
342
343 init.name = name;
344 init.flags = 0;
345 init.parent_names = tegra_clk_sor_brick_parents;
346 init.num_parents = ARRAY_SIZE(tegra_clk_sor_brick_parents);
347 init.ops = &tegra_clk_sor_brick_ops;
348
349 brick->hw.init = &init;
350
351 clk = devm_clk_register(sor->dev, &brick->hw);
352
353 return clk;
354 }
355
356 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
357 struct drm_dp_link *link)
358 {
359 unsigned int i;
360 u8 pattern;
361 u32 value;
362 int err;
363
364 /* setup lane parameters */
365 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
366 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
367 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
368 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
369 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
370
371 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
372 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
373 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
374 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
375 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
376
377 value = SOR_LANE_POSTCURSOR_LANE3(0x00) |
378 SOR_LANE_POSTCURSOR_LANE2(0x00) |
379 SOR_LANE_POSTCURSOR_LANE1(0x00) |
380 SOR_LANE_POSTCURSOR_LANE0(0x00);
381 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0);
382
383 /* disable LVDS mode */
384 tegra_sor_writel(sor, 0, SOR_LVDS);
385
386 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
387 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
388 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
389 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
390 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
391
392 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
393 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
394 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
395 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
396
397 usleep_range(10, 100);
398
399 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
400 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
401 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
402 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
403
404 err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B);
405 if (err < 0)
406 return err;
407
408 for (i = 0, value = 0; i < link->num_lanes; i++) {
409 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
410 SOR_DP_TPG_SCRAMBLER_NONE |
411 SOR_DP_TPG_PATTERN_TRAIN1;
412 value = (value << 8) | lane;
413 }
414
415 tegra_sor_writel(sor, value, SOR_DP_TPG);
416
417 pattern = DP_TRAINING_PATTERN_1;
418
419 err = drm_dp_aux_train(sor->aux, link, pattern);
420 if (err < 0)
421 return err;
422
423 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
424 value |= SOR_DP_SPARE_SEQ_ENABLE;
425 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
426 value |= SOR_DP_SPARE_MACRO_SOR_CLK;
427 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
428
429 for (i = 0, value = 0; i < link->num_lanes; i++) {
430 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
431 SOR_DP_TPG_SCRAMBLER_NONE |
432 SOR_DP_TPG_PATTERN_TRAIN2;
433 value = (value << 8) | lane;
434 }
435
436 tegra_sor_writel(sor, value, SOR_DP_TPG);
437
438 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
439
440 err = drm_dp_aux_train(sor->aux, link, pattern);
441 if (err < 0)
442 return err;
443
444 for (i = 0, value = 0; i < link->num_lanes; i++) {
445 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
446 SOR_DP_TPG_SCRAMBLER_GALIOS |
447 SOR_DP_TPG_PATTERN_NONE;
448 value = (value << 8) | lane;
449 }
450
451 tegra_sor_writel(sor, value, SOR_DP_TPG);
452
453 pattern = DP_TRAINING_PATTERN_DISABLE;
454
455 err = drm_dp_aux_train(sor->aux, link, pattern);
456 if (err < 0)
457 return err;
458
459 return 0;
460 }
461
462 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
463 {
464 u32 mask = 0x08, adj = 0, value;
465
466 /* enable pad calibration logic */
467 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
468 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
469 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
470
471 value = tegra_sor_readl(sor, SOR_PLL1);
472 value |= SOR_PLL1_TMDS_TERM;
473 tegra_sor_writel(sor, value, SOR_PLL1);
474
475 while (mask) {
476 adj |= mask;
477
478 value = tegra_sor_readl(sor, SOR_PLL1);
479 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
480 value |= SOR_PLL1_TMDS_TERMADJ(adj);
481 tegra_sor_writel(sor, value, SOR_PLL1);
482
483 usleep_range(100, 200);
484
485 value = tegra_sor_readl(sor, SOR_PLL1);
486 if (value & SOR_PLL1_TERM_COMPOUT)
487 adj &= ~mask;
488
489 mask >>= 1;
490 }
491
492 value = tegra_sor_readl(sor, SOR_PLL1);
493 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
494 value |= SOR_PLL1_TMDS_TERMADJ(adj);
495 tegra_sor_writel(sor, value, SOR_PLL1);
496
497 /* disable pad calibration logic */
498 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
499 value |= SOR_DP_PADCTL_PAD_CAL_PD;
500 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
501 }
502
503 static void tegra_sor_super_update(struct tegra_sor *sor)
504 {
505 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
506 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
507 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
508 }
509
510 static void tegra_sor_update(struct tegra_sor *sor)
511 {
512 tegra_sor_writel(sor, 0, SOR_STATE0);
513 tegra_sor_writel(sor, 1, SOR_STATE0);
514 tegra_sor_writel(sor, 0, SOR_STATE0);
515 }
516
517 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
518 {
519 u32 value;
520
521 value = tegra_sor_readl(sor, SOR_PWM_DIV);
522 value &= ~SOR_PWM_DIV_MASK;
523 value |= 0x400; /* period */
524 tegra_sor_writel(sor, value, SOR_PWM_DIV);
525
526 value = tegra_sor_readl(sor, SOR_PWM_CTL);
527 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
528 value |= 0x400; /* duty cycle */
529 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
530 value |= SOR_PWM_CTL_TRIGGER;
531 tegra_sor_writel(sor, value, SOR_PWM_CTL);
532
533 timeout = jiffies + msecs_to_jiffies(timeout);
534
535 while (time_before(jiffies, timeout)) {
536 value = tegra_sor_readl(sor, SOR_PWM_CTL);
537 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
538 return 0;
539
540 usleep_range(25, 100);
541 }
542
543 return -ETIMEDOUT;
544 }
545
546 static int tegra_sor_attach(struct tegra_sor *sor)
547 {
548 unsigned long value, timeout;
549
550 /* wake up in normal mode */
551 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
552 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
553 value |= SOR_SUPER_STATE_MODE_NORMAL;
554 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
555 tegra_sor_super_update(sor);
556
557 /* attach */
558 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
559 value |= SOR_SUPER_STATE_ATTACHED;
560 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
561 tegra_sor_super_update(sor);
562
563 timeout = jiffies + msecs_to_jiffies(250);
564
565 while (time_before(jiffies, timeout)) {
566 value = tegra_sor_readl(sor, SOR_TEST);
567 if ((value & SOR_TEST_ATTACHED) != 0)
568 return 0;
569
570 usleep_range(25, 100);
571 }
572
573 return -ETIMEDOUT;
574 }
575
576 static int tegra_sor_wakeup(struct tegra_sor *sor)
577 {
578 unsigned long value, timeout;
579
580 timeout = jiffies + msecs_to_jiffies(250);
581
582 /* wait for head to wake up */
583 while (time_before(jiffies, timeout)) {
584 value = tegra_sor_readl(sor, SOR_TEST);
585 value &= SOR_TEST_HEAD_MODE_MASK;
586
587 if (value == SOR_TEST_HEAD_MODE_AWAKE)
588 return 0;
589
590 usleep_range(25, 100);
591 }
592
593 return -ETIMEDOUT;
594 }
595
596 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
597 {
598 u32 value;
599
600 value = tegra_sor_readl(sor, SOR_PWR);
601 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
602 tegra_sor_writel(sor, value, SOR_PWR);
603
604 timeout = jiffies + msecs_to_jiffies(timeout);
605
606 while (time_before(jiffies, timeout)) {
607 value = tegra_sor_readl(sor, SOR_PWR);
608 if ((value & SOR_PWR_TRIGGER) == 0)
609 return 0;
610
611 usleep_range(25, 100);
612 }
613
614 return -ETIMEDOUT;
615 }
616
617 struct tegra_sor_params {
618 /* number of link clocks per line */
619 unsigned int num_clocks;
620 /* ratio between input and output */
621 u64 ratio;
622 /* precision factor */
623 u64 precision;
624
625 unsigned int active_polarity;
626 unsigned int active_count;
627 unsigned int active_frac;
628 unsigned int tu_size;
629 unsigned int error;
630 };
631
632 static int tegra_sor_compute_params(struct tegra_sor *sor,
633 struct tegra_sor_params *params,
634 unsigned int tu_size)
635 {
636 u64 active_sym, active_count, frac, approx;
637 u32 active_polarity, active_frac = 0;
638 const u64 f = params->precision;
639 s64 error;
640
641 active_sym = params->ratio * tu_size;
642 active_count = div_u64(active_sym, f) * f;
643 frac = active_sym - active_count;
644
645 /* fraction < 0.5 */
646 if (frac >= (f / 2)) {
647 active_polarity = 1;
648 frac = f - frac;
649 } else {
650 active_polarity = 0;
651 }
652
653 if (frac != 0) {
654 frac = div_u64(f * f, frac); /* 1/fraction */
655 if (frac <= (15 * f)) {
656 active_frac = div_u64(frac, f);
657
658 /* round up */
659 if (active_polarity)
660 active_frac++;
661 } else {
662 active_frac = active_polarity ? 1 : 15;
663 }
664 }
665
666 if (active_frac == 1)
667 active_polarity = 0;
668
669 if (active_polarity == 1) {
670 if (active_frac) {
671 approx = active_count + (active_frac * (f - 1)) * f;
672 approx = div_u64(approx, active_frac * f);
673 } else {
674 approx = active_count + f;
675 }
676 } else {
677 if (active_frac)
678 approx = active_count + div_u64(f, active_frac);
679 else
680 approx = active_count;
681 }
682
683 error = div_s64(active_sym - approx, tu_size);
684 error *= params->num_clocks;
685
686 if (error <= 0 && abs(error) < params->error) {
687 params->active_count = div_u64(active_count, f);
688 params->active_polarity = active_polarity;
689 params->active_frac = active_frac;
690 params->error = abs(error);
691 params->tu_size = tu_size;
692
693 if (error == 0)
694 return true;
695 }
696
697 return false;
698 }
699
700 static int tegra_sor_compute_config(struct tegra_sor *sor,
701 const struct drm_display_mode *mode,
702 struct tegra_sor_config *config,
703 struct drm_dp_link *link)
704 {
705 const u64 f = 100000, link_rate = link->rate * 1000;
706 const u64 pclk = mode->clock * 1000;
707 u64 input, output, watermark, num;
708 struct tegra_sor_params params;
709 u32 num_syms_per_line;
710 unsigned int i;
711
712 if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
713 return -EINVAL;
714
715 output = link_rate * 8 * link->num_lanes;
716 input = pclk * config->bits_per_pixel;
717
718 if (input >= output)
719 return -ERANGE;
720
721 memset(&params, 0, sizeof(params));
722 params.ratio = div64_u64(input * f, output);
723 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
724 params.precision = f;
725 params.error = 64 * f;
726 params.tu_size = 64;
727
728 for (i = params.tu_size; i >= 32; i--)
729 if (tegra_sor_compute_params(sor, &params, i))
730 break;
731
732 if (params.active_frac == 0) {
733 config->active_polarity = 0;
734 config->active_count = params.active_count;
735
736 if (!params.active_polarity)
737 config->active_count--;
738
739 config->tu_size = params.tu_size;
740 config->active_frac = 1;
741 } else {
742 config->active_polarity = params.active_polarity;
743 config->active_count = params.active_count;
744 config->active_frac = params.active_frac;
745 config->tu_size = params.tu_size;
746 }
747
748 dev_dbg(sor->dev,
749 "polarity: %d active count: %d tu size: %d active frac: %d\n",
750 config->active_polarity, config->active_count,
751 config->tu_size, config->active_frac);
752
753 watermark = params.ratio * config->tu_size * (f - params.ratio);
754 watermark = div_u64(watermark, f);
755
756 watermark = div_u64(watermark + params.error, f);
757 config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
758 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
759 (link->num_lanes * 8);
760
761 if (config->watermark > 30) {
762 config->watermark = 30;
763 dev_err(sor->dev,
764 "unable to compute TU size, forcing watermark to %u\n",
765 config->watermark);
766 } else if (config->watermark > num_syms_per_line) {
767 config->watermark = num_syms_per_line;
768 dev_err(sor->dev, "watermark too high, forcing to %u\n",
769 config->watermark);
770 }
771
772 /* compute the number of symbols per horizontal blanking interval */
773 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
774 config->hblank_symbols = div_u64(num, pclk);
775
776 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
777 config->hblank_symbols -= 3;
778
779 config->hblank_symbols -= 12 / link->num_lanes;
780
781 /* compute the number of symbols per vertical blanking interval */
782 num = (mode->hdisplay - 25) * link_rate;
783 config->vblank_symbols = div_u64(num, pclk);
784 config->vblank_symbols -= 36 / link->num_lanes + 4;
785
786 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
787 config->vblank_symbols);
788
789 return 0;
790 }
791
792 static void tegra_sor_apply_config(struct tegra_sor *sor,
793 const struct tegra_sor_config *config)
794 {
795 u32 value;
796
797 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
798 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
799 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
800 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
801
802 value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
803 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
804 value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
805
806 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
807 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
808
809 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
810 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
811
812 if (config->active_polarity)
813 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
814 else
815 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
816
817 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
818 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
819 tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
820
821 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
822 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
823 value |= config->hblank_symbols & 0xffff;
824 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
825
826 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
827 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
828 value |= config->vblank_symbols & 0xffff;
829 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
830 }
831
832 static void tegra_sor_mode_set(struct tegra_sor *sor,
833 const struct drm_display_mode *mode,
834 struct tegra_sor_state *state)
835 {
836 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
837 unsigned int vbe, vse, hbe, hse, vbs, hbs;
838 u32 value;
839
840 value = tegra_sor_readl(sor, SOR_STATE1);
841 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
842 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
843 value &= ~SOR_STATE_ASY_OWNER_MASK;
844
845 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
846 SOR_STATE_ASY_OWNER(dc->pipe + 1);
847
848 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
849 value &= ~SOR_STATE_ASY_HSYNCPOL;
850
851 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
852 value |= SOR_STATE_ASY_HSYNCPOL;
853
854 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
855 value &= ~SOR_STATE_ASY_VSYNCPOL;
856
857 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
858 value |= SOR_STATE_ASY_VSYNCPOL;
859
860 switch (state->bpc) {
861 case 16:
862 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
863 break;
864
865 case 12:
866 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
867 break;
868
869 case 10:
870 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
871 break;
872
873 case 8:
874 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
875 break;
876
877 case 6:
878 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
879 break;
880
881 default:
882 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
883 break;
884 }
885
886 tegra_sor_writel(sor, value, SOR_STATE1);
887
888 /*
889 * TODO: The video timing programming below doesn't seem to match the
890 * register definitions.
891 */
892
893 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
894 tegra_sor_writel(sor, value, SOR_HEAD_STATE1(dc->pipe));
895
896 /* sync end = sync width - 1 */
897 vse = mode->vsync_end - mode->vsync_start - 1;
898 hse = mode->hsync_end - mode->hsync_start - 1;
899
900 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
901 tegra_sor_writel(sor, value, SOR_HEAD_STATE2(dc->pipe));
902
903 /* blank end = sync end + back porch */
904 vbe = vse + (mode->vtotal - mode->vsync_end);
905 hbe = hse + (mode->htotal - mode->hsync_end);
906
907 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
908 tegra_sor_writel(sor, value, SOR_HEAD_STATE3(dc->pipe));
909
910 /* blank start = blank end + active */
911 vbs = vbe + mode->vdisplay;
912 hbs = hbe + mode->hdisplay;
913
914 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
915 tegra_sor_writel(sor, value, SOR_HEAD_STATE4(dc->pipe));
916
917 /* XXX interlacing support */
918 tegra_sor_writel(sor, 0x001, SOR_HEAD_STATE5(dc->pipe));
919 }
920
921 static int tegra_sor_detach(struct tegra_sor *sor)
922 {
923 unsigned long value, timeout;
924
925 /* switch to safe mode */
926 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
927 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
928 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
929 tegra_sor_super_update(sor);
930
931 timeout = jiffies + msecs_to_jiffies(250);
932
933 while (time_before(jiffies, timeout)) {
934 value = tegra_sor_readl(sor, SOR_PWR);
935 if (value & SOR_PWR_MODE_SAFE)
936 break;
937 }
938
939 if ((value & SOR_PWR_MODE_SAFE) == 0)
940 return -ETIMEDOUT;
941
942 /* go to sleep */
943 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
944 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
945 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
946 tegra_sor_super_update(sor);
947
948 /* detach */
949 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
950 value &= ~SOR_SUPER_STATE_ATTACHED;
951 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
952 tegra_sor_super_update(sor);
953
954 timeout = jiffies + msecs_to_jiffies(250);
955
956 while (time_before(jiffies, timeout)) {
957 value = tegra_sor_readl(sor, SOR_TEST);
958 if ((value & SOR_TEST_ATTACHED) == 0)
959 break;
960
961 usleep_range(25, 100);
962 }
963
964 if ((value & SOR_TEST_ATTACHED) != 0)
965 return -ETIMEDOUT;
966
967 return 0;
968 }
969
970 static int tegra_sor_power_down(struct tegra_sor *sor)
971 {
972 unsigned long value, timeout;
973 int err;
974
975 value = tegra_sor_readl(sor, SOR_PWR);
976 value &= ~SOR_PWR_NORMAL_STATE_PU;
977 value |= SOR_PWR_TRIGGER;
978 tegra_sor_writel(sor, value, SOR_PWR);
979
980 timeout = jiffies + msecs_to_jiffies(250);
981
982 while (time_before(jiffies, timeout)) {
983 value = tegra_sor_readl(sor, SOR_PWR);
984 if ((value & SOR_PWR_TRIGGER) == 0)
985 return 0;
986
987 usleep_range(25, 100);
988 }
989
990 if ((value & SOR_PWR_TRIGGER) != 0)
991 return -ETIMEDOUT;
992
993 /* switch to safe parent clock */
994 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
995 if (err < 0)
996 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
997
998 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
999 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
1000 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
1001 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1002
1003 /* stop lane sequencer */
1004 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
1005 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
1006 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1007
1008 timeout = jiffies + msecs_to_jiffies(250);
1009
1010 while (time_before(jiffies, timeout)) {
1011 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1012 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1013 break;
1014
1015 usleep_range(25, 100);
1016 }
1017
1018 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
1019 return -ETIMEDOUT;
1020
1021 value = tegra_sor_readl(sor, SOR_PLL2);
1022 value |= SOR_PLL2_PORT_POWERDOWN;
1023 tegra_sor_writel(sor, value, SOR_PLL2);
1024
1025 usleep_range(20, 100);
1026
1027 value = tegra_sor_readl(sor, SOR_PLL0);
1028 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1029 tegra_sor_writel(sor, value, SOR_PLL0);
1030
1031 value = tegra_sor_readl(sor, SOR_PLL2);
1032 value |= SOR_PLL2_SEQ_PLLCAPPD;
1033 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1034 tegra_sor_writel(sor, value, SOR_PLL2);
1035
1036 usleep_range(20, 100);
1037
1038 return 0;
1039 }
1040
1041 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1042 {
1043 u32 value;
1044
1045 timeout = jiffies + msecs_to_jiffies(timeout);
1046
1047 while (time_before(jiffies, timeout)) {
1048 value = tegra_sor_readl(sor, SOR_CRCA);
1049 if (value & SOR_CRCA_VALID)
1050 return 0;
1051
1052 usleep_range(100, 200);
1053 }
1054
1055 return -ETIMEDOUT;
1056 }
1057
1058 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1059 {
1060 struct drm_info_node *node = s->private;
1061 struct tegra_sor *sor = node->info_ent->data;
1062 struct drm_crtc *crtc = sor->output.encoder.crtc;
1063 struct drm_device *drm = node->minor->dev;
1064 int err = 0;
1065 u32 value;
1066
1067 drm_modeset_lock_all(drm);
1068
1069 if (!crtc || !crtc->state->active) {
1070 err = -EBUSY;
1071 goto unlock;
1072 }
1073
1074 value = tegra_sor_readl(sor, SOR_STATE1);
1075 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1076 tegra_sor_writel(sor, value, SOR_STATE1);
1077
1078 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1079 value |= SOR_CRC_CNTRL_ENABLE;
1080 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1081
1082 value = tegra_sor_readl(sor, SOR_TEST);
1083 value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1084 tegra_sor_writel(sor, value, SOR_TEST);
1085
1086 err = tegra_sor_crc_wait(sor, 100);
1087 if (err < 0)
1088 goto unlock;
1089
1090 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1091 value = tegra_sor_readl(sor, SOR_CRCB);
1092
1093 seq_printf(s, "%08x\n", value);
1094
1095 unlock:
1096 drm_modeset_unlock_all(drm);
1097 return err;
1098 }
1099
1100 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1101 {
1102 struct drm_info_node *node = s->private;
1103 struct tegra_sor *sor = node->info_ent->data;
1104 struct drm_crtc *crtc = sor->output.encoder.crtc;
1105 struct drm_device *drm = node->minor->dev;
1106 int err = 0;
1107
1108 drm_modeset_lock_all(drm);
1109
1110 if (!crtc || !crtc->state->active) {
1111 err = -EBUSY;
1112 goto unlock;
1113 }
1114
1115 #define DUMP_REG(name) \
1116 seq_printf(s, "%-38s %#05x %08x\n", #name, name, \
1117 tegra_sor_readl(sor, name))
1118
1119 DUMP_REG(SOR_CTXSW);
1120 DUMP_REG(SOR_SUPER_STATE0);
1121 DUMP_REG(SOR_SUPER_STATE1);
1122 DUMP_REG(SOR_STATE0);
1123 DUMP_REG(SOR_STATE1);
1124 DUMP_REG(SOR_HEAD_STATE0(0));
1125 DUMP_REG(SOR_HEAD_STATE0(1));
1126 DUMP_REG(SOR_HEAD_STATE1(0));
1127 DUMP_REG(SOR_HEAD_STATE1(1));
1128 DUMP_REG(SOR_HEAD_STATE2(0));
1129 DUMP_REG(SOR_HEAD_STATE2(1));
1130 DUMP_REG(SOR_HEAD_STATE3(0));
1131 DUMP_REG(SOR_HEAD_STATE3(1));
1132 DUMP_REG(SOR_HEAD_STATE4(0));
1133 DUMP_REG(SOR_HEAD_STATE4(1));
1134 DUMP_REG(SOR_HEAD_STATE5(0));
1135 DUMP_REG(SOR_HEAD_STATE5(1));
1136 DUMP_REG(SOR_CRC_CNTRL);
1137 DUMP_REG(SOR_DP_DEBUG_MVID);
1138 DUMP_REG(SOR_CLK_CNTRL);
1139 DUMP_REG(SOR_CAP);
1140 DUMP_REG(SOR_PWR);
1141 DUMP_REG(SOR_TEST);
1142 DUMP_REG(SOR_PLL0);
1143 DUMP_REG(SOR_PLL1);
1144 DUMP_REG(SOR_PLL2);
1145 DUMP_REG(SOR_PLL3);
1146 DUMP_REG(SOR_CSTM);
1147 DUMP_REG(SOR_LVDS);
1148 DUMP_REG(SOR_CRCA);
1149 DUMP_REG(SOR_CRCB);
1150 DUMP_REG(SOR_BLANK);
1151 DUMP_REG(SOR_SEQ_CTL);
1152 DUMP_REG(SOR_LANE_SEQ_CTL);
1153 DUMP_REG(SOR_SEQ_INST(0));
1154 DUMP_REG(SOR_SEQ_INST(1));
1155 DUMP_REG(SOR_SEQ_INST(2));
1156 DUMP_REG(SOR_SEQ_INST(3));
1157 DUMP_REG(SOR_SEQ_INST(4));
1158 DUMP_REG(SOR_SEQ_INST(5));
1159 DUMP_REG(SOR_SEQ_INST(6));
1160 DUMP_REG(SOR_SEQ_INST(7));
1161 DUMP_REG(SOR_SEQ_INST(8));
1162 DUMP_REG(SOR_SEQ_INST(9));
1163 DUMP_REG(SOR_SEQ_INST(10));
1164 DUMP_REG(SOR_SEQ_INST(11));
1165 DUMP_REG(SOR_SEQ_INST(12));
1166 DUMP_REG(SOR_SEQ_INST(13));
1167 DUMP_REG(SOR_SEQ_INST(14));
1168 DUMP_REG(SOR_SEQ_INST(15));
1169 DUMP_REG(SOR_PWM_DIV);
1170 DUMP_REG(SOR_PWM_CTL);
1171 DUMP_REG(SOR_VCRC_A0);
1172 DUMP_REG(SOR_VCRC_A1);
1173 DUMP_REG(SOR_VCRC_B0);
1174 DUMP_REG(SOR_VCRC_B1);
1175 DUMP_REG(SOR_CCRC_A0);
1176 DUMP_REG(SOR_CCRC_A1);
1177 DUMP_REG(SOR_CCRC_B0);
1178 DUMP_REG(SOR_CCRC_B1);
1179 DUMP_REG(SOR_EDATA_A0);
1180 DUMP_REG(SOR_EDATA_A1);
1181 DUMP_REG(SOR_EDATA_B0);
1182 DUMP_REG(SOR_EDATA_B1);
1183 DUMP_REG(SOR_COUNT_A0);
1184 DUMP_REG(SOR_COUNT_A1);
1185 DUMP_REG(SOR_COUNT_B0);
1186 DUMP_REG(SOR_COUNT_B1);
1187 DUMP_REG(SOR_DEBUG_A0);
1188 DUMP_REG(SOR_DEBUG_A1);
1189 DUMP_REG(SOR_DEBUG_B0);
1190 DUMP_REG(SOR_DEBUG_B1);
1191 DUMP_REG(SOR_TRIG);
1192 DUMP_REG(SOR_MSCHECK);
1193 DUMP_REG(SOR_XBAR_CTRL);
1194 DUMP_REG(SOR_XBAR_POL);
1195 DUMP_REG(SOR_DP_LINKCTL0);
1196 DUMP_REG(SOR_DP_LINKCTL1);
1197 DUMP_REG(SOR_LANE_DRIVE_CURRENT0);
1198 DUMP_REG(SOR_LANE_DRIVE_CURRENT1);
1199 DUMP_REG(SOR_LANE4_DRIVE_CURRENT0);
1200 DUMP_REG(SOR_LANE4_DRIVE_CURRENT1);
1201 DUMP_REG(SOR_LANE_PREEMPHASIS0);
1202 DUMP_REG(SOR_LANE_PREEMPHASIS1);
1203 DUMP_REG(SOR_LANE4_PREEMPHASIS0);
1204 DUMP_REG(SOR_LANE4_PREEMPHASIS1);
1205 DUMP_REG(SOR_LANE_POSTCURSOR0);
1206 DUMP_REG(SOR_LANE_POSTCURSOR1);
1207 DUMP_REG(SOR_DP_CONFIG0);
1208 DUMP_REG(SOR_DP_CONFIG1);
1209 DUMP_REG(SOR_DP_MN0);
1210 DUMP_REG(SOR_DP_MN1);
1211 DUMP_REG(SOR_DP_PADCTL0);
1212 DUMP_REG(SOR_DP_PADCTL1);
1213 DUMP_REG(SOR_DP_DEBUG0);
1214 DUMP_REG(SOR_DP_DEBUG1);
1215 DUMP_REG(SOR_DP_SPARE0);
1216 DUMP_REG(SOR_DP_SPARE1);
1217 DUMP_REG(SOR_DP_AUDIO_CTRL);
1218 DUMP_REG(SOR_DP_AUDIO_HBLANK_SYMBOLS);
1219 DUMP_REG(SOR_DP_AUDIO_VBLANK_SYMBOLS);
1220 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_HEADER);
1221 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK0);
1222 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK1);
1223 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK2);
1224 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK3);
1225 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK4);
1226 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK5);
1227 DUMP_REG(SOR_DP_GENERIC_INFOFRAME_SUBPACK6);
1228 DUMP_REG(SOR_DP_TPG);
1229 DUMP_REG(SOR_DP_TPG_CONFIG);
1230 DUMP_REG(SOR_DP_LQ_CSTM0);
1231 DUMP_REG(SOR_DP_LQ_CSTM1);
1232 DUMP_REG(SOR_DP_LQ_CSTM2);
1233
1234 #undef DUMP_REG
1235
1236 unlock:
1237 drm_modeset_unlock_all(drm);
1238 return err;
1239 }
1240
1241 static const struct drm_info_list debugfs_files[] = {
1242 { "crc", tegra_sor_show_crc, 0, NULL },
1243 { "regs", tegra_sor_show_regs, 0, NULL },
1244 };
1245
1246 static int tegra_sor_debugfs_init(struct tegra_sor *sor,
1247 struct drm_minor *minor)
1248 {
1249 const char *name = sor->soc->supports_dp ? "sor1" : "sor";
1250 unsigned int i;
1251 int err;
1252
1253 sor->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1254 if (!sor->debugfs)
1255 return -ENOMEM;
1256
1257 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1258 GFP_KERNEL);
1259 if (!sor->debugfs_files) {
1260 err = -ENOMEM;
1261 goto remove;
1262 }
1263
1264 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1265 sor->debugfs_files[i].data = sor;
1266
1267 err = drm_debugfs_create_files(sor->debugfs_files,
1268 ARRAY_SIZE(debugfs_files),
1269 sor->debugfs, minor);
1270 if (err < 0)
1271 goto free;
1272
1273 sor->minor = minor;
1274
1275 return 0;
1276
1277 free:
1278 kfree(sor->debugfs_files);
1279 sor->debugfs_files = NULL;
1280 remove:
1281 debugfs_remove_recursive(sor->debugfs);
1282 sor->debugfs = NULL;
1283 return err;
1284 }
1285
1286 static void tegra_sor_debugfs_exit(struct tegra_sor *sor)
1287 {
1288 drm_debugfs_remove_files(sor->debugfs_files, ARRAY_SIZE(debugfs_files),
1289 sor->minor);
1290 sor->minor = NULL;
1291
1292 kfree(sor->debugfs_files);
1293 sor->debugfs_files = NULL;
1294
1295 debugfs_remove_recursive(sor->debugfs);
1296 sor->debugfs = NULL;
1297 }
1298
1299 static void tegra_sor_connector_reset(struct drm_connector *connector)
1300 {
1301 struct tegra_sor_state *state;
1302
1303 state = kzalloc(sizeof(*state), GFP_KERNEL);
1304 if (!state)
1305 return;
1306
1307 if (connector->state) {
1308 __drm_atomic_helper_connector_destroy_state(connector->state);
1309 kfree(connector->state);
1310 }
1311
1312 __drm_atomic_helper_connector_reset(connector, &state->base);
1313 }
1314
1315 static enum drm_connector_status
1316 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1317 {
1318 struct tegra_output *output = connector_to_output(connector);
1319 struct tegra_sor *sor = to_sor(output);
1320
1321 if (sor->aux)
1322 return drm_dp_aux_detect(sor->aux);
1323
1324 return tegra_output_connector_detect(connector, force);
1325 }
1326
1327 static struct drm_connector_state *
1328 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1329 {
1330 struct tegra_sor_state *state = to_sor_state(connector->state);
1331 struct tegra_sor_state *copy;
1332
1333 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1334 if (!copy)
1335 return NULL;
1336
1337 __drm_atomic_helper_connector_duplicate_state(connector, &copy->base);
1338
1339 return &copy->base;
1340 }
1341
1342 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1343 .reset = tegra_sor_connector_reset,
1344 .detect = tegra_sor_connector_detect,
1345 .fill_modes = drm_helper_probe_single_connector_modes,
1346 .destroy = tegra_output_connector_destroy,
1347 .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1348 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1349 };
1350
1351 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1352 {
1353 struct tegra_output *output = connector_to_output(connector);
1354 struct tegra_sor *sor = to_sor(output);
1355 int err;
1356
1357 if (sor->aux)
1358 drm_dp_aux_enable(sor->aux);
1359
1360 err = tegra_output_connector_get_modes(connector);
1361
1362 if (sor->aux)
1363 drm_dp_aux_disable(sor->aux);
1364
1365 return err;
1366 }
1367
1368 static enum drm_mode_status
1369 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1370 struct drm_display_mode *mode)
1371 {
1372 /* HDMI 2.0 modes are not yet supported */
1373 if (mode->clock > 340000)
1374 return MODE_NOCLOCK;
1375
1376 return MODE_OK;
1377 }
1378
1379 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1380 .get_modes = tegra_sor_connector_get_modes,
1381 .mode_valid = tegra_sor_connector_mode_valid,
1382 };
1383
1384 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1385 .destroy = tegra_output_encoder_destroy,
1386 };
1387
1388 static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1389 {
1390 struct tegra_output *output = encoder_to_output(encoder);
1391 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1392 struct tegra_sor *sor = to_sor(output);
1393 u32 value;
1394 int err;
1395
1396 if (output->panel)
1397 drm_panel_disable(output->panel);
1398
1399 err = tegra_sor_detach(sor);
1400 if (err < 0)
1401 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1402
1403 tegra_sor_writel(sor, 0, SOR_STATE1);
1404 tegra_sor_update(sor);
1405
1406 /*
1407 * The following accesses registers of the display controller, so make
1408 * sure it's only executed when the output is attached to one.
1409 */
1410 if (dc) {
1411 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1412 value &= ~SOR_ENABLE;
1413 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1414
1415 tegra_dc_commit(dc);
1416 }
1417
1418 err = tegra_sor_power_down(sor);
1419 if (err < 0)
1420 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1421
1422 if (sor->aux) {
1423 err = drm_dp_aux_disable(sor->aux);
1424 if (err < 0)
1425 dev_err(sor->dev, "failed to disable DP: %d\n", err);
1426 }
1427
1428 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS);
1429 if (err < 0)
1430 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err);
1431
1432 if (output->panel)
1433 drm_panel_unprepare(output->panel);
1434
1435 pm_runtime_put(sor->dev);
1436 }
1437
1438 #if 0
1439 static int calc_h_ref_to_sync(const struct drm_display_mode *mode,
1440 unsigned int *value)
1441 {
1442 unsigned int hfp, hsw, hbp, a = 0, b;
1443
1444 hfp = mode->hsync_start - mode->hdisplay;
1445 hsw = mode->hsync_end - mode->hsync_start;
1446 hbp = mode->htotal - mode->hsync_end;
1447
1448 pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp);
1449
1450 b = hfp - 1;
1451
1452 pr_info("a: %u, b: %u\n", a, b);
1453 pr_info("a + hsw + hbp = %u\n", a + hsw + hbp);
1454
1455 if (a + hsw + hbp <= 11) {
1456 a = 1 + 11 - hsw - hbp;
1457 pr_info("a: %u\n", a);
1458 }
1459
1460 if (a > b)
1461 return -EINVAL;
1462
1463 if (hsw < 1)
1464 return -EINVAL;
1465
1466 if (mode->hdisplay < 16)
1467 return -EINVAL;
1468
1469 if (value) {
1470 if (b > a && a % 2)
1471 *value = a + 1;
1472 else
1473 *value = a;
1474 }
1475
1476 return 0;
1477 }
1478 #endif
1479
1480 static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1481 {
1482 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1483 struct tegra_output *output = encoder_to_output(encoder);
1484 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1485 struct tegra_sor *sor = to_sor(output);
1486 struct tegra_sor_config config;
1487 struct tegra_sor_state *state;
1488 struct drm_dp_link link;
1489 u8 rate, lanes;
1490 unsigned int i;
1491 int err = 0;
1492 u32 value;
1493
1494 state = to_sor_state(output->connector.state);
1495
1496 pm_runtime_get_sync(sor->dev);
1497
1498 if (output->panel)
1499 drm_panel_prepare(output->panel);
1500
1501 err = drm_dp_aux_enable(sor->aux);
1502 if (err < 0)
1503 dev_err(sor->dev, "failed to enable DP: %d\n", err);
1504
1505 err = drm_dp_link_probe(sor->aux, &link);
1506 if (err < 0) {
1507 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1508 return;
1509 }
1510
1511 /* switch to safe parent clock */
1512 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1513 if (err < 0)
1514 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1515
1516 memset(&config, 0, sizeof(config));
1517 config.bits_per_pixel = state->bpc * 3;
1518
1519 err = tegra_sor_compute_config(sor, mode, &config, &link);
1520 if (err < 0)
1521 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
1522
1523 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1524 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1525 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1526 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1527
1528 value = tegra_sor_readl(sor, SOR_PLL2);
1529 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1530 tegra_sor_writel(sor, value, SOR_PLL2);
1531 usleep_range(20, 100);
1532
1533 value = tegra_sor_readl(sor, SOR_PLL3);
1534 value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1535 tegra_sor_writel(sor, value, SOR_PLL3);
1536
1537 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST |
1538 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT;
1539 tegra_sor_writel(sor, value, SOR_PLL0);
1540
1541 value = tegra_sor_readl(sor, SOR_PLL2);
1542 value |= SOR_PLL2_SEQ_PLLCAPPD;
1543 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1544 value |= SOR_PLL2_LVDS_ENABLE;
1545 tegra_sor_writel(sor, value, SOR_PLL2);
1546
1547 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM;
1548 tegra_sor_writel(sor, value, SOR_PLL1);
1549
1550 while (true) {
1551 value = tegra_sor_readl(sor, SOR_PLL2);
1552 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0)
1553 break;
1554
1555 usleep_range(250, 1000);
1556 }
1557
1558 value = tegra_sor_readl(sor, SOR_PLL2);
1559 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1560 value &= ~SOR_PLL2_PORT_POWERDOWN;
1561 tegra_sor_writel(sor, value, SOR_PLL2);
1562
1563 /*
1564 * power up
1565 */
1566
1567 /* set safe link bandwidth (1.62 Gbps) */
1568 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1569 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1570 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
1571 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1572
1573 /* step 1 */
1574 value = tegra_sor_readl(sor, SOR_PLL2);
1575 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN |
1576 SOR_PLL2_BANDGAP_POWERDOWN;
1577 tegra_sor_writel(sor, value, SOR_PLL2);
1578
1579 value = tegra_sor_readl(sor, SOR_PLL0);
1580 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1581 tegra_sor_writel(sor, value, SOR_PLL0);
1582
1583 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1584 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1585 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1586
1587 /* step 2 */
1588 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
1589 if (err < 0)
1590 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err);
1591
1592 usleep_range(5, 100);
1593
1594 /* step 3 */
1595 value = tegra_sor_readl(sor, SOR_PLL2);
1596 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1597 tegra_sor_writel(sor, value, SOR_PLL2);
1598
1599 usleep_range(20, 100);
1600
1601 /* step 4 */
1602 value = tegra_sor_readl(sor, SOR_PLL0);
1603 value &= ~SOR_PLL0_VCOPD;
1604 value &= ~SOR_PLL0_PWR;
1605 tegra_sor_writel(sor, value, SOR_PLL0);
1606
1607 value = tegra_sor_readl(sor, SOR_PLL2);
1608 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1609 tegra_sor_writel(sor, value, SOR_PLL2);
1610
1611 usleep_range(200, 1000);
1612
1613 /* step 5 */
1614 value = tegra_sor_readl(sor, SOR_PLL2);
1615 value &= ~SOR_PLL2_PORT_POWERDOWN;
1616 tegra_sor_writel(sor, value, SOR_PLL2);
1617
1618 /* XXX not in TRM */
1619 for (value = 0, i = 0; i < 5; i++)
1620 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
1621 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
1622
1623 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1624 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1625
1626 /* switch to DP parent clock */
1627 err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
1628 if (err < 0)
1629 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1630
1631 /* power DP lanes */
1632 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1633
1634 if (link.num_lanes <= 2)
1635 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
1636 else
1637 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
1638
1639 if (link.num_lanes <= 1)
1640 value &= ~SOR_DP_PADCTL_PD_TXD_1;
1641 else
1642 value |= SOR_DP_PADCTL_PD_TXD_1;
1643
1644 if (link.num_lanes == 0)
1645 value &= ~SOR_DP_PADCTL_PD_TXD_0;
1646 else
1647 value |= SOR_DP_PADCTL_PD_TXD_0;
1648
1649 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1650
1651 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1652 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1653 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
1654 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1655
1656 /* start lane sequencer */
1657 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1658 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
1659 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1660
1661 while (true) {
1662 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1663 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1664 break;
1665
1666 usleep_range(250, 1000);
1667 }
1668
1669 /* set link bandwidth */
1670 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1671 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1672 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
1673 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1674
1675 tegra_sor_apply_config(sor, &config);
1676
1677 /* enable link */
1678 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1679 value |= SOR_DP_LINKCTL_ENABLE;
1680 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1681 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1682
1683 for (i = 0, value = 0; i < 4; i++) {
1684 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1685 SOR_DP_TPG_SCRAMBLER_GALIOS |
1686 SOR_DP_TPG_PATTERN_NONE;
1687 value = (value << 8) | lane;
1688 }
1689
1690 tegra_sor_writel(sor, value, SOR_DP_TPG);
1691
1692 /* enable pad calibration logic */
1693 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1694 value |= SOR_DP_PADCTL_PAD_CAL_PD;
1695 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
1696
1697 err = drm_dp_link_probe(sor->aux, &link);
1698 if (err < 0)
1699 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1700
1701 err = drm_dp_link_power_up(sor->aux, &link);
1702 if (err < 0)
1703 dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
1704
1705 err = drm_dp_link_configure(sor->aux, &link);
1706 if (err < 0)
1707 dev_err(sor->dev, "failed to configure eDP link: %d\n", err);
1708
1709 rate = drm_dp_link_rate_to_bw_code(link.rate);
1710 lanes = link.num_lanes;
1711
1712 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1713 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1714 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1715 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1716
1717 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1718 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1719 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1720
1721 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1722 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1723
1724 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1725
1726 /* disable training pattern generator */
1727
1728 for (i = 0; i < link.num_lanes; i++) {
1729 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1730 SOR_DP_TPG_SCRAMBLER_GALIOS |
1731 SOR_DP_TPG_PATTERN_NONE;
1732 value = (value << 8) | lane;
1733 }
1734
1735 tegra_sor_writel(sor, value, SOR_DP_TPG);
1736
1737 err = tegra_sor_dp_train_fast(sor, &link);
1738 if (err < 0)
1739 dev_err(sor->dev, "DP fast link training failed: %d\n", err);
1740
1741 dev_dbg(sor->dev, "fast link training succeeded\n");
1742
1743 err = tegra_sor_power_up(sor, 250);
1744 if (err < 0)
1745 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
1746
1747 /* CSTM (LVDS, link A/B, upper) */
1748 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1749 SOR_CSTM_UPPER;
1750 tegra_sor_writel(sor, value, SOR_CSTM);
1751
1752 /* use DP-A protocol */
1753 value = tegra_sor_readl(sor, SOR_STATE1);
1754 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
1755 value |= SOR_STATE_ASY_PROTOCOL_DP_A;
1756 tegra_sor_writel(sor, value, SOR_STATE1);
1757
1758 tegra_sor_mode_set(sor, mode, state);
1759
1760 /* PWM setup */
1761 err = tegra_sor_setup_pwm(sor, 250);
1762 if (err < 0)
1763 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
1764
1765 tegra_sor_update(sor);
1766
1767 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1768 value |= SOR_ENABLE;
1769 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1770
1771 tegra_dc_commit(dc);
1772
1773 err = tegra_sor_attach(sor);
1774 if (err < 0)
1775 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
1776
1777 err = tegra_sor_wakeup(sor);
1778 if (err < 0)
1779 dev_err(sor->dev, "failed to enable DC: %d\n", err);
1780
1781 if (output->panel)
1782 drm_panel_enable(output->panel);
1783 }
1784
1785 static int
1786 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1787 struct drm_crtc_state *crtc_state,
1788 struct drm_connector_state *conn_state)
1789 {
1790 struct tegra_output *output = encoder_to_output(encoder);
1791 struct tegra_sor_state *state = to_sor_state(conn_state);
1792 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1793 unsigned long pclk = crtc_state->mode.clock * 1000;
1794 struct tegra_sor *sor = to_sor(output);
1795 struct drm_display_info *info;
1796 int err;
1797
1798 info = &output->connector.display_info;
1799
1800 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1801 pclk, 0);
1802 if (err < 0) {
1803 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1804 return err;
1805 }
1806
1807 switch (info->bpc) {
1808 case 8:
1809 case 6:
1810 state->bpc = info->bpc;
1811 break;
1812
1813 default:
1814 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
1815 state->bpc = 8;
1816 break;
1817 }
1818
1819 return 0;
1820 }
1821
1822 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = {
1823 .disable = tegra_sor_edp_disable,
1824 .enable = tegra_sor_edp_enable,
1825 .atomic_check = tegra_sor_encoder_atomic_check,
1826 };
1827
1828 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
1829 {
1830 u32 value = 0;
1831 size_t i;
1832
1833 for (i = size; i > 0; i--)
1834 value = (value << 8) | ptr[i - 1];
1835
1836 return value;
1837 }
1838
1839 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
1840 const void *data, size_t size)
1841 {
1842 const u8 *ptr = data;
1843 unsigned long offset;
1844 size_t i, j;
1845 u32 value;
1846
1847 switch (ptr[0]) {
1848 case HDMI_INFOFRAME_TYPE_AVI:
1849 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
1850 break;
1851
1852 case HDMI_INFOFRAME_TYPE_AUDIO:
1853 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
1854 break;
1855
1856 case HDMI_INFOFRAME_TYPE_VENDOR:
1857 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
1858 break;
1859
1860 default:
1861 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1862 ptr[0]);
1863 return;
1864 }
1865
1866 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1867 INFOFRAME_HEADER_VERSION(ptr[1]) |
1868 INFOFRAME_HEADER_LEN(ptr[2]);
1869 tegra_sor_writel(sor, value, offset);
1870 offset++;
1871
1872 /*
1873 * Each subpack contains 7 bytes, divided into:
1874 * - subpack_low: bytes 0 - 3
1875 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
1876 */
1877 for (i = 3, j = 0; i < size; i += 7, j += 8) {
1878 size_t rem = size - i, num = min_t(size_t, rem, 4);
1879
1880 value = tegra_sor_hdmi_subpack(&ptr[i], num);
1881 tegra_sor_writel(sor, value, offset++);
1882
1883 num = min_t(size_t, rem - num, 3);
1884
1885 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
1886 tegra_sor_writel(sor, value, offset++);
1887 }
1888 }
1889
1890 static int
1891 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
1892 const struct drm_display_mode *mode)
1893 {
1894 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
1895 struct hdmi_avi_infoframe frame;
1896 u32 value;
1897 int err;
1898
1899 /* disable AVI infoframe */
1900 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1901 value &= ~INFOFRAME_CTRL_SINGLE;
1902 value &= ~INFOFRAME_CTRL_OTHER;
1903 value &= ~INFOFRAME_CTRL_ENABLE;
1904 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1905
1906 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1907 if (err < 0) {
1908 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1909 return err;
1910 }
1911
1912 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1913 if (err < 0) {
1914 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
1915 return err;
1916 }
1917
1918 tegra_sor_hdmi_write_infopack(sor, buffer, err);
1919
1920 /* enable AVI infoframe */
1921 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1922 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1923 value |= INFOFRAME_CTRL_ENABLE;
1924 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1925
1926 return 0;
1927 }
1928
1929 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
1930 {
1931 u32 value;
1932
1933 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
1934 value &= ~INFOFRAME_CTRL_ENABLE;
1935 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
1936 }
1937
1938 static struct tegra_sor_hdmi_settings *
1939 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
1940 {
1941 unsigned int i;
1942
1943 for (i = 0; i < sor->num_settings; i++)
1944 if (frequency <= sor->settings[i].frequency)
1945 return &sor->settings[i];
1946
1947 return NULL;
1948 }
1949
1950 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
1951 {
1952 struct tegra_output *output = encoder_to_output(encoder);
1953 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1954 struct tegra_sor *sor = to_sor(output);
1955 u32 value;
1956 int err;
1957
1958 err = tegra_sor_detach(sor);
1959 if (err < 0)
1960 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1961
1962 tegra_sor_writel(sor, 0, SOR_STATE1);
1963 tegra_sor_update(sor);
1964
1965 /* disable display to SOR clock */
1966 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1967 value &= ~SOR1_TIMING_CYA;
1968 value &= ~SOR1_ENABLE;
1969 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1970
1971 tegra_dc_commit(dc);
1972
1973 err = tegra_sor_power_down(sor);
1974 if (err < 0)
1975 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1976
1977 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_HDMI);
1978 if (err < 0)
1979 dev_err(sor->dev, "failed to power off HDMI rail: %d\n", err);
1980
1981 pm_runtime_put(sor->dev);
1982 }
1983
1984 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
1985 {
1986 struct tegra_output *output = encoder_to_output(encoder);
1987 unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
1988 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1989 struct tegra_sor_hdmi_settings *settings;
1990 struct tegra_sor *sor = to_sor(output);
1991 struct tegra_sor_state *state;
1992 struct drm_display_mode *mode;
1993 unsigned int div, i;
1994 u32 value;
1995 int err;
1996
1997 state = to_sor_state(output->connector.state);
1998 mode = &encoder->crtc->state->adjusted_mode;
1999
2000 pm_runtime_get_sync(sor->dev);
2001
2002 /* switch to safe parent clock */
2003 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2004 if (err < 0)
2005 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2006
2007 div = clk_get_rate(sor->clk) / 1000000 * 4;
2008
2009 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_HDMI);
2010 if (err < 0)
2011 dev_err(sor->dev, "failed to power on HDMI rail: %d\n", err);
2012
2013 usleep_range(20, 100);
2014
2015 value = tegra_sor_readl(sor, SOR_PLL2);
2016 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2017 tegra_sor_writel(sor, value, SOR_PLL2);
2018
2019 usleep_range(20, 100);
2020
2021 value = tegra_sor_readl(sor, SOR_PLL3);
2022 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2023 tegra_sor_writel(sor, value, SOR_PLL3);
2024
2025 value = tegra_sor_readl(sor, SOR_PLL0);
2026 value &= ~SOR_PLL0_VCOPD;
2027 value &= ~SOR_PLL0_PWR;
2028 tegra_sor_writel(sor, value, SOR_PLL0);
2029
2030 value = tegra_sor_readl(sor, SOR_PLL2);
2031 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2032 tegra_sor_writel(sor, value, SOR_PLL2);
2033
2034 usleep_range(200, 400);
2035
2036 value = tegra_sor_readl(sor, SOR_PLL2);
2037 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2038 value &= ~SOR_PLL2_PORT_POWERDOWN;
2039 tegra_sor_writel(sor, value, SOR_PLL2);
2040
2041 usleep_range(20, 100);
2042
2043 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2044 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2045 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2046 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2047
2048 while (true) {
2049 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2050 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2051 break;
2052
2053 usleep_range(250, 1000);
2054 }
2055
2056 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2057 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2058 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2059
2060 while (true) {
2061 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2062 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2063 break;
2064
2065 usleep_range(250, 1000);
2066 }
2067
2068 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2069 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2070 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2071
2072 if (mode->clock < 340000)
2073 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2074 else
2075 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2076
2077 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2078 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2079
2080 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2081 value |= SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2082 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2083 value |= SOR_DP_SPARE_SEQ_ENABLE;
2084 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2085
2086 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2087 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2088 tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2089
2090 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2091 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2092 tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2093 tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2094
2095 /* program the reference clock */
2096 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2097 tegra_sor_writel(sor, value, SOR_REFCLK);
2098
2099 /* XXX not in TRM */
2100 for (value = 0, i = 0; i < 5; i++)
2101 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2102 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2103
2104 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2105 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2106
2107 /* switch to parent clock */
2108 err = clk_set_parent(sor->clk_src, sor->clk_parent);
2109 if (err < 0)
2110 dev_err(sor->dev, "failed to set source clock: %d\n", err);
2111
2112 err = tegra_sor_set_parent_clock(sor, sor->clk_src);
2113 if (err < 0)
2114 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2115
2116 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2117
2118 /* XXX is this the proper check? */
2119 if (mode->clock < 75000)
2120 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2121
2122 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2123
2124 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2125
2126 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2127 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2128 tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2129
2130 /* H_PULSE2 setup */
2131 pulse_start = h_ref_to_sync + (mode->hsync_end - mode->hsync_start) +
2132 (mode->htotal - mode->hsync_end) - 10;
2133
2134 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2135 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2136 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2137
2138 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2139 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2140
2141 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2142 value |= H_PULSE2_ENABLE;
2143 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2144
2145 /* infoframe setup */
2146 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2147 if (err < 0)
2148 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2149
2150 /* XXX HDMI audio support not implemented yet */
2151 tegra_sor_hdmi_disable_audio_infoframe(sor);
2152
2153 /* use single TMDS protocol */
2154 value = tegra_sor_readl(sor, SOR_STATE1);
2155 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2156 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2157 tegra_sor_writel(sor, value, SOR_STATE1);
2158
2159 /* power up pad calibration */
2160 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2161 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2162 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2163
2164 /* production settings */
2165 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2166 if (!settings) {
2167 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2168 mode->clock * 1000);
2169 return;
2170 }
2171
2172 value = tegra_sor_readl(sor, SOR_PLL0);
2173 value &= ~SOR_PLL0_ICHPMP_MASK;
2174 value &= ~SOR_PLL0_VCOCAP_MASK;
2175 value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2176 value |= SOR_PLL0_VCOCAP(settings->vcocap);
2177 tegra_sor_writel(sor, value, SOR_PLL0);
2178
2179 tegra_sor_dp_term_calibrate(sor);
2180
2181 value = tegra_sor_readl(sor, SOR_PLL1);
2182 value &= ~SOR_PLL1_LOADADJ_MASK;
2183 value |= SOR_PLL1_LOADADJ(settings->loadadj);
2184 tegra_sor_writel(sor, value, SOR_PLL1);
2185
2186 value = tegra_sor_readl(sor, SOR_PLL3);
2187 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2188 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref);
2189 tegra_sor_writel(sor, value, SOR_PLL3);
2190
2191 value = settings->drive_current[0] << 24 |
2192 settings->drive_current[1] << 16 |
2193 settings->drive_current[2] << 8 |
2194 settings->drive_current[3] << 0;
2195 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2196
2197 value = settings->preemphasis[0] << 24 |
2198 settings->preemphasis[1] << 16 |
2199 settings->preemphasis[2] << 8 |
2200 settings->preemphasis[3] << 0;
2201 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2202
2203 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2204 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2205 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2206 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu);
2207 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2208
2209 /* power down pad calibration */
2210 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
2211 value |= SOR_DP_PADCTL_PAD_CAL_PD;
2212 tegra_sor_writel(sor, value, SOR_DP_PADCTL0);
2213
2214 /* miscellaneous display controller settings */
2215 value = VSYNC_H_POSITION(1);
2216 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2217
2218 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2219 value &= ~DITHER_CONTROL_MASK;
2220 value &= ~BASE_COLOR_SIZE_MASK;
2221
2222 switch (state->bpc) {
2223 case 6:
2224 value |= BASE_COLOR_SIZE_666;
2225 break;
2226
2227 case 8:
2228 value |= BASE_COLOR_SIZE_888;
2229 break;
2230
2231 default:
2232 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2233 value |= BASE_COLOR_SIZE_888;
2234 break;
2235 }
2236
2237 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2238
2239 err = tegra_sor_power_up(sor, 250);
2240 if (err < 0)
2241 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2242
2243 /* configure dynamic range of output */
2244 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe));
2245 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2246 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2247 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe));
2248
2249 /* configure colorspace */
2250 value = tegra_sor_readl(sor, SOR_HEAD_STATE0(dc->pipe));
2251 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2252 value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2253 tegra_sor_writel(sor, value, SOR_HEAD_STATE0(dc->pipe));
2254
2255 tegra_sor_mode_set(sor, mode, state);
2256
2257 tegra_sor_update(sor);
2258
2259 err = tegra_sor_attach(sor);
2260 if (err < 0)
2261 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2262
2263 /* enable display to SOR clock and generate HDMI preamble */
2264 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2265 value |= SOR1_ENABLE | SOR1_TIMING_CYA;
2266 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2267
2268 tegra_dc_commit(dc);
2269
2270 err = tegra_sor_wakeup(sor);
2271 if (err < 0)
2272 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2273 }
2274
2275 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2276 .disable = tegra_sor_hdmi_disable,
2277 .enable = tegra_sor_hdmi_enable,
2278 .atomic_check = tegra_sor_encoder_atomic_check,
2279 };
2280
2281 static int tegra_sor_init(struct host1x_client *client)
2282 {
2283 struct drm_device *drm = dev_get_drvdata(client->parent);
2284 const struct drm_encoder_helper_funcs *helpers = NULL;
2285 struct tegra_sor *sor = host1x_client_to_sor(client);
2286 int connector = DRM_MODE_CONNECTOR_Unknown;
2287 int encoder = DRM_MODE_ENCODER_NONE;
2288 int err;
2289
2290 if (!sor->aux) {
2291 if (sor->soc->supports_hdmi) {
2292 connector = DRM_MODE_CONNECTOR_HDMIA;
2293 encoder = DRM_MODE_ENCODER_TMDS;
2294 helpers = &tegra_sor_hdmi_helpers;
2295 } else if (sor->soc->supports_lvds) {
2296 connector = DRM_MODE_CONNECTOR_LVDS;
2297 encoder = DRM_MODE_ENCODER_LVDS;
2298 }
2299 } else {
2300 if (sor->soc->supports_edp) {
2301 connector = DRM_MODE_CONNECTOR_eDP;
2302 encoder = DRM_MODE_ENCODER_TMDS;
2303 helpers = &tegra_sor_edp_helpers;
2304 } else if (sor->soc->supports_dp) {
2305 connector = DRM_MODE_CONNECTOR_DisplayPort;
2306 encoder = DRM_MODE_ENCODER_TMDS;
2307 }
2308 }
2309
2310 sor->output.dev = sor->dev;
2311
2312 drm_connector_init(drm, &sor->output.connector,
2313 &tegra_sor_connector_funcs,
2314 connector);
2315 drm_connector_helper_add(&sor->output.connector,
2316 &tegra_sor_connector_helper_funcs);
2317 sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
2318
2319 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
2320 encoder, NULL);
2321 drm_encoder_helper_add(&sor->output.encoder, helpers);
2322
2323 drm_mode_connector_attach_encoder(&sor->output.connector,
2324 &sor->output.encoder);
2325 drm_connector_register(&sor->output.connector);
2326
2327 err = tegra_output_init(drm, &sor->output);
2328 if (err < 0) {
2329 dev_err(client->dev, "failed to initialize output: %d\n", err);
2330 return err;
2331 }
2332
2333 sor->output.encoder.possible_crtcs = 0x3;
2334
2335 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2336 err = tegra_sor_debugfs_init(sor, drm->primary);
2337 if (err < 0)
2338 dev_err(sor->dev, "debugfs setup failed: %d\n", err);
2339 }
2340
2341 if (sor->aux) {
2342 err = drm_dp_aux_attach(sor->aux, &sor->output);
2343 if (err < 0) {
2344 dev_err(sor->dev, "failed to attach DP: %d\n", err);
2345 return err;
2346 }
2347 }
2348
2349 /*
2350 * XXX: Remove this reset once proper hand-over from firmware to
2351 * kernel is possible.
2352 */
2353 if (sor->rst) {
2354 err = reset_control_assert(sor->rst);
2355 if (err < 0) {
2356 dev_err(sor->dev, "failed to assert SOR reset: %d\n",
2357 err);
2358 return err;
2359 }
2360 }
2361
2362 err = clk_prepare_enable(sor->clk);
2363 if (err < 0) {
2364 dev_err(sor->dev, "failed to enable clock: %d\n", err);
2365 return err;
2366 }
2367
2368 usleep_range(1000, 3000);
2369
2370 if (sor->rst) {
2371 err = reset_control_deassert(sor->rst);
2372 if (err < 0) {
2373 dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
2374 err);
2375 return err;
2376 }
2377 }
2378
2379 err = clk_prepare_enable(sor->clk_safe);
2380 if (err < 0)
2381 return err;
2382
2383 err = clk_prepare_enable(sor->clk_dp);
2384 if (err < 0)
2385 return err;
2386
2387 return 0;
2388 }
2389
2390 static int tegra_sor_exit(struct host1x_client *client)
2391 {
2392 struct tegra_sor *sor = host1x_client_to_sor(client);
2393 int err;
2394
2395 tegra_output_exit(&sor->output);
2396
2397 if (sor->aux) {
2398 err = drm_dp_aux_detach(sor->aux);
2399 if (err < 0) {
2400 dev_err(sor->dev, "failed to detach DP: %d\n", err);
2401 return err;
2402 }
2403 }
2404
2405 clk_disable_unprepare(sor->clk_safe);
2406 clk_disable_unprepare(sor->clk_dp);
2407 clk_disable_unprepare(sor->clk);
2408
2409 if (IS_ENABLED(CONFIG_DEBUG_FS))
2410 tegra_sor_debugfs_exit(sor);
2411
2412 return 0;
2413 }
2414
2415 static const struct host1x_client_ops sor_client_ops = {
2416 .init = tegra_sor_init,
2417 .exit = tegra_sor_exit,
2418 };
2419
2420 static const struct tegra_sor_ops tegra_sor_edp_ops = {
2421 .name = "eDP",
2422 };
2423
2424 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2425 {
2426 int err;
2427
2428 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
2429 if (IS_ERR(sor->avdd_io_supply)) {
2430 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
2431 PTR_ERR(sor->avdd_io_supply));
2432 return PTR_ERR(sor->avdd_io_supply);
2433 }
2434
2435 err = regulator_enable(sor->avdd_io_supply);
2436 if (err < 0) {
2437 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2438 err);
2439 return err;
2440 }
2441
2442 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
2443 if (IS_ERR(sor->vdd_pll_supply)) {
2444 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
2445 PTR_ERR(sor->vdd_pll_supply));
2446 return PTR_ERR(sor->vdd_pll_supply);
2447 }
2448
2449 err = regulator_enable(sor->vdd_pll_supply);
2450 if (err < 0) {
2451 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2452 err);
2453 return err;
2454 }
2455
2456 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2457 if (IS_ERR(sor->hdmi_supply)) {
2458 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
2459 PTR_ERR(sor->hdmi_supply));
2460 return PTR_ERR(sor->hdmi_supply);
2461 }
2462
2463 err = regulator_enable(sor->hdmi_supply);
2464 if (err < 0) {
2465 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
2466 return err;
2467 }
2468
2469 return 0;
2470 }
2471
2472 static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
2473 {
2474 regulator_disable(sor->hdmi_supply);
2475 regulator_disable(sor->vdd_pll_supply);
2476 regulator_disable(sor->avdd_io_supply);
2477
2478 return 0;
2479 }
2480
2481 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
2482 .name = "HDMI",
2483 .probe = tegra_sor_hdmi_probe,
2484 .remove = tegra_sor_hdmi_remove,
2485 };
2486
2487 static const u8 tegra124_sor_xbar_cfg[5] = {
2488 0, 1, 2, 3, 4
2489 };
2490
2491 static const struct tegra_sor_soc tegra124_sor = {
2492 .supports_edp = true,
2493 .supports_lvds = true,
2494 .supports_hdmi = false,
2495 .supports_dp = false,
2496 .xbar_cfg = tegra124_sor_xbar_cfg,
2497 };
2498
2499 static const struct tegra_sor_soc tegra210_sor = {
2500 .supports_edp = true,
2501 .supports_lvds = false,
2502 .supports_hdmi = false,
2503 .supports_dp = false,
2504 .xbar_cfg = tegra124_sor_xbar_cfg,
2505 };
2506
2507 static const u8 tegra210_sor_xbar_cfg[5] = {
2508 2, 1, 0, 3, 4
2509 };
2510
2511 static const struct tegra_sor_soc tegra210_sor1 = {
2512 .supports_edp = false,
2513 .supports_lvds = false,
2514 .supports_hdmi = true,
2515 .supports_dp = true,
2516
2517 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
2518 .settings = tegra210_sor_hdmi_defaults,
2519
2520 .xbar_cfg = tegra210_sor_xbar_cfg,
2521 };
2522
2523 static const struct of_device_id tegra_sor_of_match[] = {
2524 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
2525 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
2526 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
2527 { },
2528 };
2529 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
2530
2531 static int tegra_sor_probe(struct platform_device *pdev)
2532 {
2533 const struct of_device_id *match;
2534 struct device_node *np;
2535 struct tegra_sor *sor;
2536 struct resource *regs;
2537 int err;
2538
2539 match = of_match_device(tegra_sor_of_match, &pdev->dev);
2540
2541 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
2542 if (!sor)
2543 return -ENOMEM;
2544
2545 sor->output.dev = sor->dev = &pdev->dev;
2546 sor->soc = match->data;
2547
2548 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
2549 sor->soc->num_settings *
2550 sizeof(*sor->settings),
2551 GFP_KERNEL);
2552 if (!sor->settings)
2553 return -ENOMEM;
2554
2555 sor->num_settings = sor->soc->num_settings;
2556
2557 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
2558 if (np) {
2559 sor->aux = drm_dp_aux_find_by_of_node(np);
2560 of_node_put(np);
2561
2562 if (!sor->aux)
2563 return -EPROBE_DEFER;
2564 }
2565
2566 if (!sor->aux) {
2567 if (sor->soc->supports_hdmi) {
2568 sor->ops = &tegra_sor_hdmi_ops;
2569 } else if (sor->soc->supports_lvds) {
2570 dev_err(&pdev->dev, "LVDS not supported yet\n");
2571 return -ENODEV;
2572 } else {
2573 dev_err(&pdev->dev, "unknown (non-DP) support\n");
2574 return -ENODEV;
2575 }
2576 } else {
2577 if (sor->soc->supports_edp) {
2578 sor->ops = &tegra_sor_edp_ops;
2579 } else if (sor->soc->supports_dp) {
2580 dev_err(&pdev->dev, "DisplayPort not supported yet\n");
2581 return -ENODEV;
2582 } else {
2583 dev_err(&pdev->dev, "unknown (DP) support\n");
2584 return -ENODEV;
2585 }
2586 }
2587
2588 err = tegra_output_probe(&sor->output);
2589 if (err < 0) {
2590 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
2591 return err;
2592 }
2593
2594 if (sor->ops && sor->ops->probe) {
2595 err = sor->ops->probe(sor);
2596 if (err < 0) {
2597 dev_err(&pdev->dev, "failed to probe %s: %d\n",
2598 sor->ops->name, err);
2599 goto output;
2600 }
2601 }
2602
2603 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2604 sor->regs = devm_ioremap_resource(&pdev->dev, regs);
2605 if (IS_ERR(sor->regs)) {
2606 err = PTR_ERR(sor->regs);
2607 goto remove;
2608 }
2609
2610 if (!pdev->dev.pm_domain) {
2611 sor->rst = devm_reset_control_get(&pdev->dev, "sor");
2612 if (IS_ERR(sor->rst)) {
2613 err = PTR_ERR(sor->rst);
2614 dev_err(&pdev->dev, "failed to get reset control: %d\n",
2615 err);
2616 goto remove;
2617 }
2618 }
2619
2620 sor->clk = devm_clk_get(&pdev->dev, NULL);
2621 if (IS_ERR(sor->clk)) {
2622 err = PTR_ERR(sor->clk);
2623 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
2624 goto remove;
2625 }
2626
2627 if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
2628 sor->clk_src = devm_clk_get(&pdev->dev, "source");
2629 if (IS_ERR(sor->clk_src)) {
2630 err = PTR_ERR(sor->clk_src);
2631 dev_err(sor->dev, "failed to get source clock: %d\n",
2632 err);
2633 goto remove;
2634 }
2635 }
2636
2637 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
2638 if (IS_ERR(sor->clk_parent)) {
2639 err = PTR_ERR(sor->clk_parent);
2640 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
2641 goto remove;
2642 }
2643
2644 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
2645 if (IS_ERR(sor->clk_safe)) {
2646 err = PTR_ERR(sor->clk_safe);
2647 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
2648 goto remove;
2649 }
2650
2651 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
2652 if (IS_ERR(sor->clk_dp)) {
2653 err = PTR_ERR(sor->clk_dp);
2654 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
2655 goto remove;
2656 }
2657
2658 platform_set_drvdata(pdev, sor);
2659 pm_runtime_enable(&pdev->dev);
2660
2661 pm_runtime_get_sync(&pdev->dev);
2662 sor->clk_brick = tegra_clk_sor_brick_register(sor, "sor1_brick");
2663 pm_runtime_put(&pdev->dev);
2664
2665 if (IS_ERR(sor->clk_brick)) {
2666 err = PTR_ERR(sor->clk_brick);
2667 dev_err(&pdev->dev, "failed to register SOR clock: %d\n", err);
2668 goto remove;
2669 }
2670
2671 INIT_LIST_HEAD(&sor->client.list);
2672 sor->client.ops = &sor_client_ops;
2673 sor->client.dev = &pdev->dev;
2674
2675 err = host1x_client_register(&sor->client);
2676 if (err < 0) {
2677 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2678 err);
2679 goto remove;
2680 }
2681
2682 return 0;
2683
2684 remove:
2685 if (sor->ops && sor->ops->remove)
2686 sor->ops->remove(sor);
2687 output:
2688 tegra_output_remove(&sor->output);
2689 return err;
2690 }
2691
2692 static int tegra_sor_remove(struct platform_device *pdev)
2693 {
2694 struct tegra_sor *sor = platform_get_drvdata(pdev);
2695 int err;
2696
2697 pm_runtime_disable(&pdev->dev);
2698
2699 err = host1x_client_unregister(&sor->client);
2700 if (err < 0) {
2701 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2702 err);
2703 return err;
2704 }
2705
2706 if (sor->ops && sor->ops->remove) {
2707 err = sor->ops->remove(sor);
2708 if (err < 0)
2709 dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
2710 }
2711
2712 tegra_output_remove(&sor->output);
2713
2714 return 0;
2715 }
2716
2717 #ifdef CONFIG_PM
2718 static int tegra_sor_suspend(struct device *dev)
2719 {
2720 struct tegra_sor *sor = dev_get_drvdata(dev);
2721 int err;
2722
2723 if (sor->rst) {
2724 err = reset_control_assert(sor->rst);
2725 if (err < 0) {
2726 dev_err(dev, "failed to assert reset: %d\n", err);
2727 return err;
2728 }
2729 }
2730
2731 usleep_range(1000, 2000);
2732
2733 clk_disable_unprepare(sor->clk);
2734
2735 return 0;
2736 }
2737
2738 static int tegra_sor_resume(struct device *dev)
2739 {
2740 struct tegra_sor *sor = dev_get_drvdata(dev);
2741 int err;
2742
2743 err = clk_prepare_enable(sor->clk);
2744 if (err < 0) {
2745 dev_err(dev, "failed to enable clock: %d\n", err);
2746 return err;
2747 }
2748
2749 usleep_range(1000, 2000);
2750
2751 if (sor->rst) {
2752 err = reset_control_deassert(sor->rst);
2753 if (err < 0) {
2754 dev_err(dev, "failed to deassert reset: %d\n", err);
2755 clk_disable_unprepare(sor->clk);
2756 return err;
2757 }
2758 }
2759
2760 return 0;
2761 }
2762 #endif
2763
2764 static const struct dev_pm_ops tegra_sor_pm_ops = {
2765 SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL)
2766 };
2767
2768 struct platform_driver tegra_sor_driver = {
2769 .driver = {
2770 .name = "tegra-sor",
2771 .of_match_table = tegra_sor_of_match,
2772 .pm = &tegra_sor_pm_ops,
2773 },
2774 .probe = tegra_sor_probe,
2775 .remove = tegra_sor_remove,
2776 };
ubuntu-bionic-kernel mirror