drivers/gpu/drm/tilcdc/tilcdc_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2012 Texas Instruments
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  */
   6
   7 #ifndef __TILCDC_REGS_H__
   8 #define __TILCDC_REGS_H__
   9
  10 /* LCDC register definitions, based on da8xx-fb */
  11
  12 #include <linux/bitops.h>
  13
  14 #include "tilcdc_drv.h"
  15
  16 /* LCDC Status Register */
  17 #define LCDC_END_OF_FRAME1                       BIT(9)
  18 #define LCDC_END_OF_FRAME0                       BIT(8)
  19 #define LCDC_PL_LOAD_DONE                        BIT(6)
  20 #define LCDC_FIFO_UNDERFLOW                      BIT(5)
  21 #define LCDC_SYNC_LOST                           BIT(2)
  22 #define LCDC_FRAME_DONE                          BIT(0)
  23
  24 /* LCDC DMA Control Register */
  25 #define LCDC_DMA_BURST_SIZE(x)                   ((x) << 4)
  26 #define LCDC_DMA_BURST_SIZE_MASK                 ((0x7) << 4)
  27 #define LCDC_DMA_BURST_1                         0x0
  28 #define LCDC_DMA_BURST_2                         0x1
  29 #define LCDC_DMA_BURST_4                         0x2
  30 #define LCDC_DMA_BURST_8                         0x3
  31 #define LCDC_DMA_BURST_16                        0x4
  32 #define LCDC_DMA_FIFO_THRESHOLD(x)               ((x) << 8)
  33 #define LCDC_DMA_FIFO_THRESHOLD_MASK             ((0x3) << 8)
  34 #define LCDC_V1_END_OF_FRAME_INT_ENA             BIT(2)
  35 #define LCDC_V2_END_OF_FRAME0_INT_ENA            BIT(8)
  36 #define LCDC_V2_END_OF_FRAME1_INT_ENA            BIT(9)
  37 #define LCDC_DUAL_FRAME_BUFFER_ENABLE            BIT(0)
  38
  39 /* LCDC Control Register */
  40 #define LCDC_CLK_DIVISOR(x)                      ((x) << 8)
  41 #define LCDC_CLK_DIVISOR_MASK                    ((0xFF) << 8)
  42 #define LCDC_RASTER_MODE                         0x01
  43
  44 /* LCDC Raster Control Register */
  45 #define LCDC_PALETTE_LOAD_MODE(x)                ((x) << 20)
  46 #define LCDC_PALETTE_LOAD_MODE_MASK              ((0x3) << 20)
  47 #define PALETTE_AND_DATA                         0x00
  48 #define PALETTE_ONLY                             0x01
  49 #define DATA_ONLY                                0x02
  50
  51 #define LCDC_MONO_8BIT_MODE                      BIT(9)
  52 #define LCDC_RASTER_ORDER                        BIT(8)
  53 #define LCDC_TFT_MODE                            BIT(7)
  54 #define LCDC_V1_UNDERFLOW_INT_ENA                BIT(6)
  55 #define LCDC_V2_UNDERFLOW_INT_ENA                BIT(5)
  56 #define LCDC_V1_PL_INT_ENA                       BIT(4)
  57 #define LCDC_V2_PL_INT_ENA                       BIT(6)
  58 #define LCDC_V1_SYNC_LOST_INT_ENA                BIT(5)
  59 #define LCDC_V1_FRAME_DONE_INT_ENA               BIT(3)
  60 #define LCDC_MONOCHROME_MODE                     BIT(1)
  61 #define LCDC_RASTER_ENABLE                       BIT(0)
  62 #define LCDC_TFT_ALT_ENABLE                      BIT(23)
  63 #define LCDC_STN_565_ENABLE                      BIT(24)
  64 #define LCDC_V2_DMA_CLK_EN                       BIT(2)
  65 #define LCDC_V2_LIDD_CLK_EN                      BIT(1)
  66 #define LCDC_V2_CORE_CLK_EN                      BIT(0)
  67 #define LCDC_V2_LPP_B10                          26
  68 #define LCDC_V2_TFT_24BPP_MODE                   BIT(25)
  69 #define LCDC_V2_TFT_24BPP_UNPACK                 BIT(26)
  70
  71 /* LCDC Raster Timing 2 Register */
  72 #define LCDC_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
  73 #define LCDC_AC_BIAS_TRANSITIONS_PER_INT_MASK    ((0xF) << 16)
  74 #define LCDC_AC_BIAS_FREQUENCY(x)                ((x) << 8)
  75 #define LCDC_AC_BIAS_FREQUENCY_MASK              ((0xFF) << 8)
  76 #define LCDC_SYNC_CTRL                           BIT(25)
  77 #define LCDC_SYNC_EDGE                           BIT(24)
  78 #define LCDC_INVERT_PIXEL_CLOCK                  BIT(22)
  79 #define LCDC_INVERT_HSYNC                        BIT(21)
  80 #define LCDC_INVERT_VSYNC                        BIT(20)
  81 #define LCDC_LPP_B10                             BIT(26)
  82
  83 /* LCDC Block */
  84 #define LCDC_PID_REG                             0x0
  85 #define LCDC_CTRL_REG                            0x4
  86 #define LCDC_STAT_REG                            0x8
  87 #define LCDC_RASTER_CTRL_REG                     0x28
  88 #define LCDC_RASTER_TIMING_0_REG                 0x2c
  89 #define LCDC_RASTER_TIMING_1_REG                 0x30
  90 #define LCDC_RASTER_TIMING_2_REG                 0x34
  91 #define LCDC_DMA_CTRL_REG                        0x40
  92 #define LCDC_DMA_FB_BASE_ADDR_0_REG              0x44
  93 #define LCDC_DMA_FB_CEILING_ADDR_0_REG           0x48
  94 #define LCDC_DMA_FB_BASE_ADDR_1_REG              0x4c
  95 #define LCDC_DMA_FB_CEILING_ADDR_1_REG           0x50
  96
  97 /* Interrupt Registers available only in Version 2 */
  98 #define LCDC_RAW_STAT_REG                        0x58
  99 #define LCDC_MASKED_STAT_REG                     0x5c
 100 #define LCDC_INT_ENABLE_SET_REG                  0x60
 101 #define LCDC_INT_ENABLE_CLR_REG                  0x64
 102 #define LCDC_END_OF_INT_IND_REG                  0x68
 103
 104 /* Clock registers available only on Version 2 */
 105 #define LCDC_CLK_ENABLE_REG                      0x6c
 106 #define LCDC_CLK_RESET_REG                       0x70
 107 #define LCDC_CLK_MAIN_RESET                      BIT(3)
 108
 109
 110 /*
 111  * Helpers:
 112  */
 113
 114 static inline void tilcdc_write(struct drm_device *dev, u32 reg, u32 data)
 115 {
 116         struct tilcdc_drm_private *priv = dev->dev_private;
 117         iowrite32(data, priv->mmio + reg);
 118 }
 119
 120 static inline void tilcdc_write64(struct drm_device *dev, u32 reg, u64 data)
 121 {
 122         struct tilcdc_drm_private *priv = dev->dev_private;
 123         volatile void __iomem *addr = priv->mmio + reg;
 124
 125 #if defined(iowrite64) && !defined(iowrite64_is_nonatomic)
 126         iowrite64(data, addr);
 127 #else
 128         __iowmb();
 129         /* This compiles to strd (=64-bit write) on ARM7 */
 130         *(volatile u64 __force *)addr = __cpu_to_le64(data);
 131 #endif
 132 }
 133
 134 static inline u32 tilcdc_read(struct drm_device *dev, u32 reg)
 135 {
 136         struct tilcdc_drm_private *priv = dev->dev_private;
 137         return ioread32(priv->mmio + reg);
 138 }
 139
 140 static inline void tilcdc_write_mask(struct drm_device *dev, u32 reg,
 141                                      u32 val, u32 mask)
 142 {
 143         tilcdc_write(dev, reg, (tilcdc_read(dev, reg) & ~mask) | (val & mask));
 144 }
 145
 146 static inline void tilcdc_set(struct drm_device *dev, u32 reg, u32 mask)
 147 {
 148         tilcdc_write(dev, reg, tilcdc_read(dev, reg) | mask);
 149 }
 150
 151 static inline void tilcdc_clear(struct drm_device *dev, u32 reg, u32 mask)
 152 {
 153         tilcdc_write(dev, reg, tilcdc_read(dev, reg) & ~mask);
 154 }
 155
 156 /* the register to read/clear irqstatus differs between v1 and v2 of the IP */
 157 static inline u32 tilcdc_irqstatus_reg(struct drm_device *dev)
 158 {
 159         struct tilcdc_drm_private *priv = dev->dev_private;
 160         return (priv->rev == 2) ? LCDC_MASKED_STAT_REG : LCDC_STAT_REG;
 161 }
 162
 163 static inline u32 tilcdc_read_irqstatus(struct drm_device *dev)
 164 {
 165         return tilcdc_read(dev, tilcdc_irqstatus_reg(dev));
 166 }
 167
 168 static inline void tilcdc_clear_irqstatus(struct drm_device *dev, u32 mask)
 169 {
 170         tilcdc_write(dev, tilcdc_irqstatus_reg(dev), mask);
 171 }
 172
 173 #endif /* __TILCDC_REGS_H__ */