drivers/gpu/drm/tve200/tve200_display.c

   1 /*
   2  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
   3  * Parts of this file were based on sources as follows:
   4  *
   5  * Copyright (C) 2006-2008 Intel Corporation
   6  * Copyright (C) 2007 Amos Lee <amos_lee@storlinksemi.com>
   7  * Copyright (C) 2007 Dave Airlie <airlied@linux.ie>
   8  * Copyright (C) 2011 Texas Instruments
   9  * Copyright (C) 2017 Eric Anholt
  10  *
  11  * This program is free software and is provided to you under the terms of the
  12  * GNU General Public License version 2 as published by the Free Software
  13  * Foundation, and any use by you of this program is subject to the terms of
  14  * such GNU licence.
  15  */
  16 #include <linux/clk.h>
  17 #include <linux/version.h>
  18 #include <linux/dma-buf.h>
  19 #include <linux/of_graph.h>
  20
  21 #include <drm/drmP.h>
  22 #include <drm/drm_panel.h>
  23 #include <drm/drm_gem_cma_helper.h>
  24 #include <drm/drm_fb_cma_helper.h>
  25
  26 #include "tve200_drm.h"
  27
  28 irqreturn_t tve200_irq(int irq, void *data)
  29 {
  30         struct tve200_drm_dev_private *priv = data;
  31         u32 stat;
  32         u32 val;
  33
  34         stat = readl(priv->regs + TVE200_INT_STAT);
  35
  36         if (!stat)
  37                 return IRQ_NONE;
  38
  39         /*
  40          * Vblank IRQ
  41          *
  42          * The hardware is a bit tilted: the line stays high after clearing
  43          * the vblank IRQ, firing many more interrupts. We counter this
  44          * by toggling the IRQ back and forth from firing at vblank and
  45          * firing at start of active image, which works around the problem
  46          * since those occur strictly in sequence, and we get two IRQs for each
  47          * frame, one at start of Vblank (that we make call into the CRTC) and
  48          * another one at the start of the image (that we discard).
  49          */
  50         if (stat & TVE200_INT_V_STATUS) {
  51                 val = readl(priv->regs + TVE200_CTRL);
  52                 /* We have an actual start of vsync */
  53                 if (!(val & TVE200_VSTSTYPE_BITS)) {
  54                         drm_crtc_handle_vblank(&priv->pipe.crtc);
  55                         /* Toggle trigger to start of active image */
  56                         val |= TVE200_VSTSTYPE_VAI;
  57                 } else {
  58                         /* Toggle trigger back to start of vsync */
  59                         val &= ~TVE200_VSTSTYPE_BITS;
  60                 }
  61                 writel(val, priv->regs + TVE200_CTRL);
  62         } else
  63                 dev_err(priv->drm->dev, "stray IRQ %08x\n", stat);
  64
  65         /* Clear the interrupt once done */
  66         writel(stat, priv->regs + TVE200_INT_CLR);
  67
  68         return IRQ_HANDLED;
  69 }
  70
  71 static int tve200_display_check(struct drm_simple_display_pipe *pipe,
  72                                struct drm_plane_state *pstate,
  73                                struct drm_crtc_state *cstate)
  74 {
  75         const struct drm_display_mode *mode = &cstate->mode;
  76         struct drm_framebuffer *old_fb = pipe->plane.state->fb;
  77         struct drm_framebuffer *fb = pstate->fb;
  78
  79         /*
  80          * We support these specific resolutions and nothing else.
  81          */
  82         if (!(mode->hdisplay == 352 && mode->vdisplay == 240) && /* SIF(525) */
  83             !(mode->hdisplay == 352 && mode->vdisplay == 288) && /* CIF(625) */
  84             !(mode->hdisplay == 640 && mode->vdisplay == 480) && /* VGA */
  85             !(mode->hdisplay == 720 && mode->vdisplay == 480) && /* D1 */
  86             !(mode->hdisplay == 720 && mode->vdisplay == 576)) { /* D1 */
  87                 DRM_DEBUG_KMS("unsupported display mode (%u x %u)\n",
  88                         mode->hdisplay, mode->vdisplay);
  89                 return -EINVAL;
  90         }
  91
  92         if (fb) {
  93                 u32 offset = drm_fb_cma_get_gem_addr(fb, pstate, 0);
  94
  95                 /* FB base address must be dword aligned. */
  96                 if (offset & 3) {
  97                         DRM_DEBUG_KMS("FB not 32-bit aligned\n");
  98                         return -EINVAL;
  99                 }
 100
 101                 /*
 102                  * There's no pitch register, the mode's hdisplay
 103                  * controls this.
 104                  */
 105                 if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) {
 106                         DRM_DEBUG_KMS("can't handle pitches\n");
 107                         return -EINVAL;
 108                 }
 109
 110                 /*
 111                  * We can't change the FB format in a flicker-free
 112                  * manner (and only update it during CRTC enable).
 113                  */
 114                 if (old_fb && old_fb->format != fb->format)
 115                         cstate->mode_changed = true;
 116         }
 117
 118         return 0;
 119 }
 120
 121 static void tve200_display_enable(struct drm_simple_display_pipe *pipe,
 122                                  struct drm_crtc_state *cstate)
 123 {
 124         struct drm_crtc *crtc = &pipe->crtc;
 125         struct drm_plane *plane = &pipe->plane;
 126         struct drm_device *drm = crtc->dev;
 127         struct tve200_drm_dev_private *priv = drm->dev_private;
 128         const struct drm_display_mode *mode = &cstate->mode;
 129         struct drm_framebuffer *fb = plane->state->fb;
 130         struct drm_connector *connector = &priv->connector.connector;
 131         u32 format = fb->format->format;
 132         u32 ctrl1 = 0;
 133
 134         clk_prepare_enable(priv->clk);
 135
 136         /* Function 1 */
 137         ctrl1 |= TVE200_CTRL_CSMODE;
 138         /* Interlace mode for CCIR656: parameterize? */
 139         ctrl1 |= TVE200_CTRL_NONINTERLACE;
 140         /* 32 words per burst */
 141         ctrl1 |= TVE200_CTRL_BURST_32_WORDS;
 142         /* 16 retries */
 143         ctrl1 |= TVE200_CTRL_RETRYCNT_16;
 144         /* NTSC mode: parametrize? */
 145         ctrl1 |= TVE200_CTRL_NTSC;
 146
 147         /* Vsync IRQ at start of Vsync at first */
 148         ctrl1 |= TVE200_VSTSTYPE_VSYNC;
 149
 150         if (connector->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
 151                 ctrl1 |= TVE200_CTRL_TVCLKP;
 152
 153         if ((mode->hdisplay == 352 && mode->vdisplay == 240) || /* SIF(525) */
 154             (mode->hdisplay == 352 && mode->vdisplay == 288)) { /* CIF(625) */
 155                 ctrl1 |= TVE200_CTRL_IPRESOL_CIF;
 156                 dev_info(drm->dev, "CIF mode\n");
 157         } else if (mode->hdisplay == 640 && mode->vdisplay == 480) {
 158                 ctrl1 |= TVE200_CTRL_IPRESOL_VGA;
 159                 dev_info(drm->dev, "VGA mode\n");
 160         } else if ((mode->hdisplay == 720 && mode->vdisplay == 480) ||
 161                    (mode->hdisplay == 720 && mode->vdisplay == 576)) {
 162                 ctrl1 |= TVE200_CTRL_IPRESOL_D1;
 163                 dev_info(drm->dev, "D1 mode\n");
 164         }
 165
 166         if (format & DRM_FORMAT_BIG_ENDIAN) {
 167                 ctrl1 |= TVE200_CTRL_BBBP;
 168                 format &= ~DRM_FORMAT_BIG_ENDIAN;
 169         }
 170
 171         switch (format) {
 172         case DRM_FORMAT_XRGB8888:
 173                 ctrl1 |= TVE200_IPDMOD_RGB888;
 174                 break;
 175         case DRM_FORMAT_RGB565:
 176                 ctrl1 |= TVE200_IPDMOD_RGB565;
 177                 break;
 178         case DRM_FORMAT_XRGB1555:
 179                 ctrl1 |= TVE200_IPDMOD_RGB555;
 180                 break;
 181         case DRM_FORMAT_XBGR8888:
 182                 ctrl1 |= TVE200_IPDMOD_RGB888 | TVE200_BGR;
 183                 break;
 184         case DRM_FORMAT_BGR565:
 185                 ctrl1 |= TVE200_IPDMOD_RGB565 | TVE200_BGR;
 186                 break;
 187         case DRM_FORMAT_XBGR1555:
 188                 ctrl1 |= TVE200_IPDMOD_RGB555 | TVE200_BGR;
 189                 break;
 190         case DRM_FORMAT_YUYV:
 191                 ctrl1 |= TVE200_IPDMOD_YUV422;
 192                 ctrl1 |= TVE200_CTRL_YCBCRODR_CR0Y1CB0Y0;
 193                 break;
 194         case DRM_FORMAT_YVYU:
 195                 ctrl1 |= TVE200_IPDMOD_YUV422;
 196                 ctrl1 |= TVE200_CTRL_YCBCRODR_CB0Y1CR0Y0;
 197                 break;
 198         case DRM_FORMAT_UYVY:
 199                 ctrl1 |= TVE200_IPDMOD_YUV422;
 200                 ctrl1 |= TVE200_CTRL_YCBCRODR_Y1CR0Y0CB0;
 201                 break;
 202         case DRM_FORMAT_VYUY:
 203                 ctrl1 |= TVE200_IPDMOD_YUV422;
 204                 ctrl1 |= TVE200_CTRL_YCBCRODR_Y1CB0Y0CR0;
 205                 break;
 206         case DRM_FORMAT_YUV420:
 207                 ctrl1 |= TVE200_CTRL_YUV420;
 208                 ctrl1 |= TVE200_IPDMOD_YUV420;
 209                 break;
 210         default:
 211                 dev_err(drm->dev, "Unknown FB format 0x%08x\n",
 212                         fb->format->format);
 213                 break;
 214         }
 215
 216         ctrl1 |= TVE200_TVEEN;
 217
 218         drm_panel_prepare(priv->connector.panel);
 219
 220         /* Turn it on */
 221         writel(ctrl1, priv->regs + TVE200_CTRL);
 222
 223         drm_panel_enable(priv->connector.panel);
 224
 225         drm_crtc_vblank_on(crtc);
 226 }
 227
 228 void tve200_display_disable(struct drm_simple_display_pipe *pipe)
 229 {
 230         struct drm_crtc *crtc = &pipe->crtc;
 231         struct drm_device *drm = crtc->dev;
 232         struct tve200_drm_dev_private *priv = drm->dev_private;
 233
 234         drm_crtc_vblank_off(crtc);
 235
 236         drm_panel_disable(priv->connector.panel);
 237
 238         /* Disable and Power Down */
 239         writel(0, priv->regs + TVE200_CTRL);
 240
 241         drm_panel_unprepare(priv->connector.panel);
 242
 243         clk_disable_unprepare(priv->clk);
 244 }
 245
 246 static void tve200_display_update(struct drm_simple_display_pipe *pipe,
 247                                  struct drm_plane_state *old_pstate)
 248 {
 249         struct drm_crtc *crtc = &pipe->crtc;
 250         struct drm_device *drm = crtc->dev;
 251         struct tve200_drm_dev_private *priv = drm->dev_private;
 252         struct drm_pending_vblank_event *event = crtc->state->event;
 253         struct drm_plane *plane = &pipe->plane;
 254         struct drm_plane_state *pstate = plane->state;
 255         struct drm_framebuffer *fb = pstate->fb;
 256
 257         if (fb) {
 258                 /* For RGB, the Y component is used as base address */
 259                 writel(drm_fb_cma_get_gem_addr(fb, pstate, 0),
 260                        priv->regs + TVE200_Y_FRAME_BASE_ADDR);
 261
 262                 /* For three plane YUV we need two more addresses */
 263                 if (fb->format->format == DRM_FORMAT_YUV420) {
 264                         writel(drm_fb_cma_get_gem_addr(fb, pstate, 1),
 265                                priv->regs + TVE200_U_FRAME_BASE_ADDR);
 266                         writel(drm_fb_cma_get_gem_addr(fb, pstate, 2),
 267                                priv->regs + TVE200_V_FRAME_BASE_ADDR);
 268                 }
 269         }
 270
 271         if (event) {
 272                 crtc->state->event = NULL;
 273
 274                 spin_lock_irq(&crtc->dev->event_lock);
 275                 if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0)
 276                         drm_crtc_arm_vblank_event(crtc, event);
 277                 else
 278                         drm_crtc_send_vblank_event(crtc, event);
 279                 spin_unlock_irq(&crtc->dev->event_lock);
 280         }
 281 }
 282
 283 int tve200_enable_vblank(struct drm_device *drm, unsigned int crtc)
 284 {
 285         struct tve200_drm_dev_private *priv = drm->dev_private;
 286
 287         writel(TVE200_INT_V_STATUS, priv->regs + TVE200_INT_EN);
 288         return 0;
 289 }
 290
 291 void tve200_disable_vblank(struct drm_device *drm, unsigned int crtc)
 292 {
 293         struct tve200_drm_dev_private *priv = drm->dev_private;
 294
 295         writel(0, priv->regs + TVE200_INT_EN);
 296 }
 297
 298 static int tve200_display_prepare_fb(struct drm_simple_display_pipe *pipe,
 299                                     struct drm_plane_state *plane_state)
 300 {
 301         return drm_fb_cma_prepare_fb(&pipe->plane, plane_state);
 302 }
 303
 304 const struct drm_simple_display_pipe_funcs tve200_display_funcs = {
 305         .check = tve200_display_check,
 306         .enable = tve200_display_enable,
 307         .disable = tve200_display_disable,
 308         .update = tve200_display_update,
 309         .prepare_fb = tve200_display_prepare_fb,
 310 };
 311
 312 int tve200_display_init(struct drm_device *drm)
 313 {
 314         struct tve200_drm_dev_private *priv = drm->dev_private;
 315         int ret;
 316         static const u32 formats[] = {
 317                 DRM_FORMAT_XRGB8888,
 318                 DRM_FORMAT_XBGR8888,
 319                 DRM_FORMAT_RGB565,
 320                 DRM_FORMAT_BGR565,
 321                 DRM_FORMAT_XRGB1555,
 322                 DRM_FORMAT_XBGR1555,
 323                 /*
 324                  * The controller actually supports any YCbCr ordering,
 325                  * for packed YCbCr. This just lists the orderings that
 326                  * DRM supports.
 327                  */
 328                 DRM_FORMAT_YUYV,
 329                 DRM_FORMAT_YVYU,
 330                 DRM_FORMAT_UYVY,
 331                 DRM_FORMAT_VYUY,
 332                 /* This uses three planes */
 333                 DRM_FORMAT_YUV420,
 334         };
 335
 336         ret = drm_simple_display_pipe_init(drm, &priv->pipe,
 337                                            &tve200_display_funcs,
 338                                            formats, ARRAY_SIZE(formats),
 339                                            NULL,
 340                                            &priv->connector.connector);
 341         if (ret)
 342                 return ret;
 343
 344         return 0;
 345 }