2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * DOC: VC4 CRTC module
12 * In VC4, the Pixel Valve is what most closely corresponds to the
13 * DRM's concept of a CRTC. The PV generates video timings from the
14 * output's clock plus its configuration. It pulls scaled pixels from
15 * the HVS at that timing, and feeds it to the encoder.
17 * However, the DRM CRTC also collects the configuration of all the
18 * DRM planes attached to it. As a result, this file also manages
19 * setup of the VC4 HVS's display elements on the CRTC.
21 * The 2835 has 3 different pixel valves. pv0 in the audio power
22 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
23 * image domain can feed either HDMI or the SDTV controller. The
24 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
25 * SDTV, etc.) according to which output type is chosen in the mux.
27 * For power management, the pixel valve's registers are all clocked
28 * by the AXI clock, while the timings and FIFOs make use of the
29 * output-specific clock. Since the encoders also directly consume
30 * the CPRMAN clocks, and know what timings they need, they are the
31 * ones that set the clock.
34 #include "drm_atomic.h"
35 #include "drm_atomic_helper.h"
36 #include "drm_crtc_helper.h"
37 #include "linux/clk.h"
38 #include "drm_fb_cma_helper.h"
39 #include "linux/component.h"
40 #include "linux/of_device.h"
46 const struct vc4_crtc_data
*data
;
49 /* Which HVS channel we're using for our CRTC. */
52 /* Pointer to the actual hardware display list memory for the
57 u32 dlist_size
; /* in dwords */
59 struct drm_pending_vblank_event
*event
;
62 static inline struct vc4_crtc
*
63 to_vc4_crtc(struct drm_crtc
*crtc
)
65 return (struct vc4_crtc
*)crtc
;
68 struct vc4_crtc_data
{
69 /* Which channel of the HVS this pixelvalve sources from. */
72 enum vc4_encoder_type encoder0_type
;
73 enum vc4_encoder_type encoder1_type
;
76 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
77 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
79 #define CRTC_REG(reg) { reg, #reg }
85 CRTC_REG(PV_V_CONTROL
),
86 CRTC_REG(PV_VSYNCD_EVEN
),
91 CRTC_REG(PV_VERTA_EVEN
),
92 CRTC_REG(PV_VERTB_EVEN
),
96 CRTC_REG(PV_HACT_ACT
),
99 static void vc4_crtc_dump_regs(struct vc4_crtc
*vc4_crtc
)
103 for (i
= 0; i
< ARRAY_SIZE(crtc_regs
); i
++) {
104 DRM_INFO("0x%04x (%s): 0x%08x\n",
105 crtc_regs
[i
].reg
, crtc_regs
[i
].name
,
106 CRTC_READ(crtc_regs
[i
].reg
));
110 #ifdef CONFIG_DEBUG_FS
111 int vc4_crtc_debugfs_regs(struct seq_file
*m
, void *unused
)
113 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
114 struct drm_device
*dev
= node
->minor
->dev
;
115 int crtc_index
= (uintptr_t)node
->info_ent
->data
;
116 struct drm_crtc
*crtc
;
117 struct vc4_crtc
*vc4_crtc
;
121 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
128 vc4_crtc
= to_vc4_crtc(crtc
);
130 for (i
= 0; i
< ARRAY_SIZE(crtc_regs
); i
++) {
131 seq_printf(m
, "%s (0x%04x): 0x%08x\n",
132 crtc_regs
[i
].name
, crtc_regs
[i
].reg
,
133 CRTC_READ(crtc_regs
[i
].reg
));
140 static void vc4_crtc_destroy(struct drm_crtc
*crtc
)
142 drm_crtc_cleanup(crtc
);
145 static u32
vc4_get_fifo_full_level(u32 format
)
147 static const u32 fifo_len_bytes
= 64;
148 static const u32 hvs_latency_pix
= 6;
151 case PV_CONTROL_FORMAT_DSIV_16
:
152 case PV_CONTROL_FORMAT_DSIC_16
:
153 return fifo_len_bytes
- 2 * hvs_latency_pix
;
154 case PV_CONTROL_FORMAT_DSIV_18
:
155 return fifo_len_bytes
- 14;
156 case PV_CONTROL_FORMAT_24
:
157 case PV_CONTROL_FORMAT_DSIV_24
:
159 return fifo_len_bytes
- 3 * hvs_latency_pix
;
164 * Returns the clock select bit for the connector attached to the
167 static int vc4_get_clock_select(struct drm_crtc
*crtc
)
169 struct drm_connector
*connector
;
171 drm_for_each_connector(connector
, crtc
->dev
) {
172 if (connector
->state
->crtc
== crtc
) {
173 struct drm_encoder
*encoder
= connector
->encoder
;
174 struct vc4_encoder
*vc4_encoder
=
175 to_vc4_encoder(encoder
);
177 return vc4_encoder
->clock_select
;
184 static void vc4_crtc_mode_set_nofb(struct drm_crtc
*crtc
)
186 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
187 struct drm_crtc_state
*state
= crtc
->state
;
188 struct drm_display_mode
*mode
= &state
->adjusted_mode
;
189 bool interlace
= mode
->flags
& DRM_MODE_FLAG_INTERLACE
;
190 u32 vactive
= (mode
->vdisplay
>> (interlace
? 1 : 0));
191 u32 format
= PV_CONTROL_FORMAT_24
;
192 bool debug_dump_regs
= false;
193 int clock_select
= vc4_get_clock_select(crtc
);
195 if (debug_dump_regs
) {
196 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc
));
197 vc4_crtc_dump_regs(vc4_crtc
);
200 /* Reset the PV fifo. */
201 CRTC_WRITE(PV_CONTROL
, 0);
202 CRTC_WRITE(PV_CONTROL
, PV_CONTROL_FIFO_CLR
| PV_CONTROL_EN
);
203 CRTC_WRITE(PV_CONTROL
, 0);
206 VC4_SET_FIELD(mode
->htotal
- mode
->hsync_end
,
208 VC4_SET_FIELD(mode
->hsync_end
- mode
->hsync_start
,
211 VC4_SET_FIELD(mode
->hsync_start
- mode
->hdisplay
,
213 VC4_SET_FIELD(mode
->hdisplay
, PV_HORZB_HACTIVE
));
216 VC4_SET_FIELD(mode
->vtotal
- mode
->vsync_end
,
218 VC4_SET_FIELD(mode
->vsync_end
- mode
->vsync_start
,
221 VC4_SET_FIELD(mode
->vsync_start
- mode
->vdisplay
,
223 VC4_SET_FIELD(vactive
, PV_VERTB_VACTIVE
));
226 CRTC_WRITE(PV_VERTA_EVEN
,
227 VC4_SET_FIELD(mode
->vtotal
- mode
->vsync_end
- 1,
229 VC4_SET_FIELD(mode
->vsync_end
- mode
->vsync_start
,
231 CRTC_WRITE(PV_VERTB_EVEN
,
232 VC4_SET_FIELD(mode
->vsync_start
- mode
->vdisplay
,
234 VC4_SET_FIELD(vactive
, PV_VERTB_VACTIVE
));
237 CRTC_WRITE(PV_HACT_ACT
, mode
->hdisplay
);
239 CRTC_WRITE(PV_V_CONTROL
,
240 PV_VCONTROL_CONTINUOUS
|
241 (interlace
? PV_VCONTROL_INTERLACE
: 0));
243 CRTC_WRITE(PV_CONTROL
,
244 VC4_SET_FIELD(format
, PV_CONTROL_FORMAT
) |
245 VC4_SET_FIELD(vc4_get_fifo_full_level(format
),
246 PV_CONTROL_FIFO_LEVEL
) |
247 PV_CONTROL_CLR_AT_START
|
248 PV_CONTROL_TRIGGER_UNDERFLOW
|
249 PV_CONTROL_WAIT_HSTART
|
250 VC4_SET_FIELD(clock_select
, PV_CONTROL_CLK_SELECT
) |
251 PV_CONTROL_FIFO_CLR
|
254 if (debug_dump_regs
) {
255 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc
));
256 vc4_crtc_dump_regs(vc4_crtc
);
260 static void require_hvs_enabled(struct drm_device
*dev
)
262 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
264 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL
) & SCALER_DISPCTRL_ENABLE
) !=
265 SCALER_DISPCTRL_ENABLE
);
268 static void vc4_crtc_disable(struct drm_crtc
*crtc
)
270 struct drm_device
*dev
= crtc
->dev
;
271 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
272 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
273 u32 chan
= vc4_crtc
->channel
;
275 require_hvs_enabled(dev
);
277 CRTC_WRITE(PV_V_CONTROL
,
278 CRTC_READ(PV_V_CONTROL
) & ~PV_VCONTROL_VIDEN
);
279 ret
= wait_for(!(CRTC_READ(PV_V_CONTROL
) & PV_VCONTROL_VIDEN
), 1);
280 WARN_ONCE(ret
, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
282 if (HVS_READ(SCALER_DISPCTRLX(chan
)) &
283 SCALER_DISPCTRLX_ENABLE
) {
284 HVS_WRITE(SCALER_DISPCTRLX(chan
),
285 SCALER_DISPCTRLX_RESET
);
287 /* While the docs say that reset is self-clearing, it
288 * seems it doesn't actually.
290 HVS_WRITE(SCALER_DISPCTRLX(chan
), 0);
293 /* Once we leave, the scaler should be disabled and its fifo empty. */
295 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan
)) & SCALER_DISPCTRLX_RESET
);
297 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan
)),
298 SCALER_DISPSTATX_MODE
) !=
299 SCALER_DISPSTATX_MODE_DISABLED
);
301 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan
)) &
302 (SCALER_DISPSTATX_FULL
| SCALER_DISPSTATX_EMPTY
)) !=
303 SCALER_DISPSTATX_EMPTY
);
306 static void vc4_crtc_enable(struct drm_crtc
*crtc
)
308 struct drm_device
*dev
= crtc
->dev
;
309 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
310 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
311 struct drm_crtc_state
*state
= crtc
->state
;
312 struct drm_display_mode
*mode
= &state
->adjusted_mode
;
314 require_hvs_enabled(dev
);
316 /* Turn on the scaler, which will wait for vstart to start
319 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc
->channel
),
320 VC4_SET_FIELD(mode
->hdisplay
, SCALER_DISPCTRLX_WIDTH
) |
321 VC4_SET_FIELD(mode
->vdisplay
, SCALER_DISPCTRLX_HEIGHT
) |
322 SCALER_DISPCTRLX_ENABLE
);
324 /* Turn on the pixel valve, which will emit the vstart signal. */
325 CRTC_WRITE(PV_V_CONTROL
,
326 CRTC_READ(PV_V_CONTROL
) | PV_VCONTROL_VIDEN
);
329 static int vc4_crtc_atomic_check(struct drm_crtc
*crtc
,
330 struct drm_crtc_state
*state
)
332 struct drm_device
*dev
= crtc
->dev
;
333 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
334 struct drm_plane
*plane
;
335 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
338 /* The pixelvalve can only feed one encoder (and encoders are
339 * 1:1 with connectors.)
341 if (hweight32(state
->connector_mask
) > 1)
344 drm_atomic_crtc_state_for_each_plane(plane
, state
) {
345 struct drm_plane_state
*plane_state
=
346 state
->state
->plane_states
[drm_plane_index(plane
)];
348 /* plane might not have changed, in which case take
352 plane_state
= plane
->state
;
354 dlist_count
+= vc4_plane_dlist_size(plane_state
);
357 dlist_count
++; /* Account for SCALER_CTL0_END. */
359 if (!vc4_crtc
->dlist
|| dlist_count
> vc4_crtc
->dlist_size
) {
360 vc4_crtc
->dlist
= ((u32 __iomem
*)vc4
->hvs
->dlist
+
361 HVS_BOOTLOADER_DLIST_END
);
362 vc4_crtc
->dlist_size
= ((SCALER_DLIST_SIZE
>> 2) -
363 HVS_BOOTLOADER_DLIST_END
);
365 if (dlist_count
> vc4_crtc
->dlist_size
) {
366 DRM_DEBUG_KMS("dlist too large for CRTC (%d > %d).\n",
367 dlist_count
, vc4_crtc
->dlist_size
);
375 static void vc4_crtc_atomic_flush(struct drm_crtc
*crtc
,
376 struct drm_crtc_state
*old_state
)
378 struct drm_device
*dev
= crtc
->dev
;
379 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
380 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
381 struct drm_plane
*plane
;
382 bool debug_dump_regs
= false;
383 u32 __iomem
*dlist_next
= vc4_crtc
->dlist
;
385 if (debug_dump_regs
) {
386 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc
));
387 vc4_hvs_dump_state(dev
);
390 /* Copy all the active planes' dlist contents to the hardware dlist.
392 * XXX: If the new display list was large enough that it
393 * overlapped a currently-read display list, we need to do
394 * something like disable scanout before putting in the new
395 * list. For now, we're safe because we only have the two
398 drm_atomic_crtc_for_each_plane(plane
, crtc
) {
399 dlist_next
+= vc4_plane_write_dlist(plane
, dlist_next
);
402 if (dlist_next
== vc4_crtc
->dlist
) {
403 /* If no planes were enabled, use the SCALER_CTL0_END
404 * at the start of the display list memory (in the
405 * bootloader section). We'll rewrite that
406 * SCALER_CTL0_END, just in case, though.
408 writel(SCALER_CTL0_END
, vc4
->hvs
->dlist
);
409 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc
->channel
), 0);
411 writel(SCALER_CTL0_END
, dlist_next
);
414 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc
->channel
),
415 (u32 __iomem
*)vc4_crtc
->dlist
-
416 (u32 __iomem
*)vc4
->hvs
->dlist
);
418 /* Make the next display list start after ours. */
419 vc4_crtc
->dlist_size
-= (dlist_next
- vc4_crtc
->dlist
);
420 vc4_crtc
->dlist
= dlist_next
;
423 if (debug_dump_regs
) {
424 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc
));
425 vc4_hvs_dump_state(dev
);
428 if (crtc
->state
->event
) {
431 crtc
->state
->event
->pipe
= drm_crtc_index(crtc
);
433 WARN_ON(drm_crtc_vblank_get(crtc
) != 0);
435 spin_lock_irqsave(&dev
->event_lock
, flags
);
436 vc4_crtc
->event
= crtc
->state
->event
;
437 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
438 crtc
->state
->event
= NULL
;
442 int vc4_enable_vblank(struct drm_device
*dev
, unsigned int crtc_id
)
444 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
445 struct vc4_crtc
*vc4_crtc
= vc4
->crtc
[crtc_id
];
447 CRTC_WRITE(PV_INTEN
, PV_INT_VFP_START
);
452 void vc4_disable_vblank(struct drm_device
*dev
, unsigned int crtc_id
)
454 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
455 struct vc4_crtc
*vc4_crtc
= vc4
->crtc
[crtc_id
];
457 CRTC_WRITE(PV_INTEN
, 0);
460 static void vc4_crtc_handle_page_flip(struct vc4_crtc
*vc4_crtc
)
462 struct drm_crtc
*crtc
= &vc4_crtc
->base
;
463 struct drm_device
*dev
= crtc
->dev
;
466 spin_lock_irqsave(&dev
->event_lock
, flags
);
467 if (vc4_crtc
->event
) {
468 drm_crtc_send_vblank_event(crtc
, vc4_crtc
->event
);
469 vc4_crtc
->event
= NULL
;
471 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
474 static irqreturn_t
vc4_crtc_irq_handler(int irq
, void *data
)
476 struct vc4_crtc
*vc4_crtc
= data
;
477 u32 stat
= CRTC_READ(PV_INTSTAT
);
478 irqreturn_t ret
= IRQ_NONE
;
480 if (stat
& PV_INT_VFP_START
) {
481 CRTC_WRITE(PV_INTSTAT
, PV_INT_VFP_START
);
482 drm_crtc_handle_vblank(&vc4_crtc
->base
);
483 vc4_crtc_handle_page_flip(vc4_crtc
);
490 struct vc4_async_flip_state
{
491 struct drm_crtc
*crtc
;
492 struct drm_framebuffer
*fb
;
493 struct drm_pending_vblank_event
*event
;
495 struct vc4_seqno_cb cb
;
498 /* Called when the V3D execution for the BO being flipped to is done, so that
499 * we can actually update the plane's address to point to it.
502 vc4_async_page_flip_complete(struct vc4_seqno_cb
*cb
)
504 struct vc4_async_flip_state
*flip_state
=
505 container_of(cb
, struct vc4_async_flip_state
, cb
);
506 struct drm_crtc
*crtc
= flip_state
->crtc
;
507 struct drm_device
*dev
= crtc
->dev
;
508 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
509 struct drm_plane
*plane
= crtc
->primary
;
511 vc4_plane_async_set_fb(plane
, flip_state
->fb
);
512 if (flip_state
->event
) {
515 spin_lock_irqsave(&dev
->event_lock
, flags
);
516 drm_crtc_send_vblank_event(crtc
, flip_state
->event
);
517 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
520 drm_framebuffer_unreference(flip_state
->fb
);
523 up(&vc4
->async_modeset
);
526 /* Implements async (non-vblank-synced) page flips.
528 * The page flip ioctl needs to return immediately, so we grab the
529 * modeset semaphore on the pipe, and queue the address update for
530 * when V3D is done with the BO being flipped to.
532 static int vc4_async_page_flip(struct drm_crtc
*crtc
,
533 struct drm_framebuffer
*fb
,
534 struct drm_pending_vblank_event
*event
,
537 struct drm_device
*dev
= crtc
->dev
;
538 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
539 struct drm_plane
*plane
= crtc
->primary
;
541 struct vc4_async_flip_state
*flip_state
;
542 struct drm_gem_cma_object
*cma_bo
= drm_fb_cma_get_gem_obj(fb
, 0);
543 struct vc4_bo
*bo
= to_vc4_bo(&cma_bo
->base
);
545 flip_state
= kzalloc(sizeof(*flip_state
), GFP_KERNEL
);
549 drm_framebuffer_reference(fb
);
551 flip_state
->crtc
= crtc
;
552 flip_state
->event
= event
;
554 /* Make sure all other async modesetes have landed. */
555 ret
= down_interruptible(&vc4
->async_modeset
);
557 drm_framebuffer_unreference(fb
);
562 /* Immediately update the plane's legacy fb pointer, so that later
563 * modeset prep sees the state that will be present when the semaphore
566 drm_atomic_set_fb_for_plane(plane
->state
, fb
);
569 vc4_queue_seqno_cb(dev
, &flip_state
->cb
, bo
->seqno
,
570 vc4_async_page_flip_complete
);
572 /* Driver takes ownership of state on successful async commit. */
576 static int vc4_page_flip(struct drm_crtc
*crtc
,
577 struct drm_framebuffer
*fb
,
578 struct drm_pending_vblank_event
*event
,
581 if (flags
& DRM_MODE_PAGE_FLIP_ASYNC
)
582 return vc4_async_page_flip(crtc
, fb
, event
, flags
);
584 return drm_atomic_helper_page_flip(crtc
, fb
, event
, flags
);
587 static const struct drm_crtc_funcs vc4_crtc_funcs
= {
588 .set_config
= drm_atomic_helper_set_config
,
589 .destroy
= vc4_crtc_destroy
,
590 .page_flip
= vc4_page_flip
,
591 .set_property
= NULL
,
592 .cursor_set
= NULL
, /* handled by drm_mode_cursor_universal */
593 .cursor_move
= NULL
, /* handled by drm_mode_cursor_universal */
594 .reset
= drm_atomic_helper_crtc_reset
,
595 .atomic_duplicate_state
= drm_atomic_helper_crtc_duplicate_state
,
596 .atomic_destroy_state
= drm_atomic_helper_crtc_destroy_state
,
599 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs
= {
600 .mode_set_nofb
= vc4_crtc_mode_set_nofb
,
601 .disable
= vc4_crtc_disable
,
602 .enable
= vc4_crtc_enable
,
603 .atomic_check
= vc4_crtc_atomic_check
,
604 .atomic_flush
= vc4_crtc_atomic_flush
,
607 /* Frees the page flip event when the DRM device is closed with the
608 * event still outstanding.
610 void vc4_cancel_page_flip(struct drm_crtc
*crtc
, struct drm_file
*file
)
612 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
613 struct drm_device
*dev
= crtc
->dev
;
616 spin_lock_irqsave(&dev
->event_lock
, flags
);
618 if (vc4_crtc
->event
&& vc4_crtc
->event
->base
.file_priv
== file
) {
619 vc4_crtc
->event
->base
.destroy(&vc4_crtc
->event
->base
);
620 drm_crtc_vblank_put(crtc
);
621 vc4_crtc
->event
= NULL
;
624 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
627 static const struct vc4_crtc_data pv0_data
= {
629 .encoder0_type
= VC4_ENCODER_TYPE_DSI0
,
630 .encoder1_type
= VC4_ENCODER_TYPE_DPI
,
633 static const struct vc4_crtc_data pv1_data
= {
635 .encoder0_type
= VC4_ENCODER_TYPE_DSI1
,
636 .encoder1_type
= VC4_ENCODER_TYPE_SMI
,
639 static const struct vc4_crtc_data pv2_data
= {
641 .encoder0_type
= VC4_ENCODER_TYPE_VEC
,
642 .encoder1_type
= VC4_ENCODER_TYPE_HDMI
,
645 static const struct of_device_id vc4_crtc_dt_match
[] = {
646 { .compatible
= "brcm,bcm2835-pixelvalve0", .data
= &pv0_data
},
647 { .compatible
= "brcm,bcm2835-pixelvalve1", .data
= &pv1_data
},
648 { .compatible
= "brcm,bcm2835-pixelvalve2", .data
= &pv2_data
},
652 static void vc4_set_crtc_possible_masks(struct drm_device
*drm
,
653 struct drm_crtc
*crtc
)
655 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
656 struct drm_encoder
*encoder
;
658 drm_for_each_encoder(encoder
, drm
) {
659 struct vc4_encoder
*vc4_encoder
= to_vc4_encoder(encoder
);
661 if (vc4_encoder
->type
== vc4_crtc
->data
->encoder0_type
) {
662 vc4_encoder
->clock_select
= 0;
663 encoder
->possible_crtcs
|= drm_crtc_mask(crtc
);
664 } else if (vc4_encoder
->type
== vc4_crtc
->data
->encoder1_type
) {
665 vc4_encoder
->clock_select
= 1;
666 encoder
->possible_crtcs
|= drm_crtc_mask(crtc
);
671 static int vc4_crtc_bind(struct device
*dev
, struct device
*master
, void *data
)
673 struct platform_device
*pdev
= to_platform_device(dev
);
674 struct drm_device
*drm
= dev_get_drvdata(master
);
675 struct vc4_dev
*vc4
= to_vc4_dev(drm
);
676 struct vc4_crtc
*vc4_crtc
;
677 struct drm_crtc
*crtc
;
678 struct drm_plane
*primary_plane
, *cursor_plane
;
679 const struct of_device_id
*match
;
682 vc4_crtc
= devm_kzalloc(dev
, sizeof(*vc4_crtc
), GFP_KERNEL
);
685 crtc
= &vc4_crtc
->base
;
687 match
= of_match_device(vc4_crtc_dt_match
, dev
);
690 vc4_crtc
->data
= match
->data
;
692 vc4_crtc
->regs
= vc4_ioremap_regs(pdev
, 0);
693 if (IS_ERR(vc4_crtc
->regs
))
694 return PTR_ERR(vc4_crtc
->regs
);
696 /* For now, we create just the primary and the legacy cursor
697 * planes. We should be able to stack more planes on easily,
698 * but to do that we would need to compute the bandwidth
699 * requirement of the plane configuration, and reject ones
700 * that will take too much.
702 primary_plane
= vc4_plane_init(drm
, DRM_PLANE_TYPE_PRIMARY
);
703 if (IS_ERR(primary_plane
)) {
704 dev_err(dev
, "failed to construct primary plane\n");
705 ret
= PTR_ERR(primary_plane
);
709 cursor_plane
= vc4_plane_init(drm
, DRM_PLANE_TYPE_CURSOR
);
710 if (IS_ERR(cursor_plane
)) {
711 dev_err(dev
, "failed to construct cursor plane\n");
712 ret
= PTR_ERR(cursor_plane
);
716 drm_crtc_init_with_planes(drm
, crtc
, primary_plane
, cursor_plane
,
717 &vc4_crtc_funcs
, NULL
);
718 drm_crtc_helper_add(crtc
, &vc4_crtc_helper_funcs
);
719 primary_plane
->crtc
= crtc
;
720 cursor_plane
->crtc
= crtc
;
721 vc4
->crtc
[drm_crtc_index(crtc
)] = vc4_crtc
;
722 vc4_crtc
->channel
= vc4_crtc
->data
->hvs_channel
;
724 CRTC_WRITE(PV_INTEN
, 0);
725 CRTC_WRITE(PV_INTSTAT
, PV_INT_VFP_START
);
726 ret
= devm_request_irq(dev
, platform_get_irq(pdev
, 0),
727 vc4_crtc_irq_handler
, 0, "vc4 crtc", vc4_crtc
);
731 vc4_set_crtc_possible_masks(drm
, crtc
);
733 platform_set_drvdata(pdev
, vc4_crtc
);
738 cursor_plane
->funcs
->destroy(cursor_plane
);
740 primary_plane
->funcs
->destroy(primary_plane
);
745 static void vc4_crtc_unbind(struct device
*dev
, struct device
*master
,
748 struct platform_device
*pdev
= to_platform_device(dev
);
749 struct vc4_crtc
*vc4_crtc
= dev_get_drvdata(dev
);
751 vc4_crtc_destroy(&vc4_crtc
->base
);
753 CRTC_WRITE(PV_INTEN
, 0);
755 platform_set_drvdata(pdev
, NULL
);
758 static const struct component_ops vc4_crtc_ops
= {
759 .bind
= vc4_crtc_bind
,
760 .unbind
= vc4_crtc_unbind
,
763 static int vc4_crtc_dev_probe(struct platform_device
*pdev
)
765 return component_add(&pdev
->dev
, &vc4_crtc_ops
);
768 static int vc4_crtc_dev_remove(struct platform_device
*pdev
)
770 component_del(&pdev
->dev
, &vc4_crtc_ops
);
774 struct platform_driver vc4_crtc_driver
= {
775 .probe
= vc4_crtc_dev_probe
,
776 .remove
= vc4_crtc_dev_remove
,
779 .of_match_table
= vc4_crtc_dt_match
,