2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * DOC: VC4 CRTC module
12 * In VC4, the Pixel Valve is what most closely corresponds to the
13 * DRM's concept of a CRTC. The PV generates video timings from the
14 * output's clock plus its configuration. It pulls scaled pixels from
15 * the HVS at that timing, and feeds it to the encoder.
17 * However, the DRM CRTC also collects the configuration of all the
18 * DRM planes attached to it. As a result, this file also manages
19 * setup of the VC4 HVS's display elements on the CRTC.
21 * The 2835 has 3 different pixel valves. pv0 in the audio power
22 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
23 * image domain can feed either HDMI or the SDTV controller. The
24 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
25 * SDTV, etc.) according to which output type is chosen in the mux.
27 * For power management, the pixel valve's registers are all clocked
28 * by the AXI clock, while the timings and FIFOs make use of the
29 * output-specific clock. Since the encoders also directly consume
30 * the CPRMAN clocks, and know what timings they need, they are the
31 * ones that set the clock.
34 #include "drm_atomic.h"
35 #include "drm_atomic_helper.h"
36 #include "drm_crtc_helper.h"
37 #include "linux/clk.h"
38 #include "drm_fb_cma_helper.h"
39 #include "linux/component.h"
40 #include "linux/of_device.h"
46 const struct vc4_crtc_data
*data
;
49 /* Timestamp at start of vblank irq - unaffected by lock delays. */
52 /* Which HVS channel we're using for our CRTC. */
58 /* Size in pixels of the COB memory allocated to this CRTC. */
61 struct drm_pending_vblank_event
*event
;
64 struct vc4_crtc_state
{
65 struct drm_crtc_state base
;
66 /* Dlist area for this CRTC configuration. */
67 struct drm_mm_node mm
;
70 static inline struct vc4_crtc
*
71 to_vc4_crtc(struct drm_crtc
*crtc
)
73 return (struct vc4_crtc
*)crtc
;
76 static inline struct vc4_crtc_state
*
77 to_vc4_crtc_state(struct drm_crtc_state
*crtc_state
)
79 return (struct vc4_crtc_state
*)crtc_state
;
82 struct vc4_crtc_data
{
83 /* Which channel of the HVS this pixelvalve sources from. */
86 enum vc4_encoder_type encoder_types
[4];
89 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
90 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
92 #define CRTC_REG(reg) { reg, #reg }
98 CRTC_REG(PV_V_CONTROL
),
99 CRTC_REG(PV_VSYNCD_EVEN
),
104 CRTC_REG(PV_VERTA_EVEN
),
105 CRTC_REG(PV_VERTB_EVEN
),
107 CRTC_REG(PV_INTSTAT
),
109 CRTC_REG(PV_HACT_ACT
),
112 static void vc4_crtc_dump_regs(struct vc4_crtc
*vc4_crtc
)
116 for (i
= 0; i
< ARRAY_SIZE(crtc_regs
); i
++) {
117 DRM_INFO("0x%04x (%s): 0x%08x\n",
118 crtc_regs
[i
].reg
, crtc_regs
[i
].name
,
119 CRTC_READ(crtc_regs
[i
].reg
));
123 #ifdef CONFIG_DEBUG_FS
124 int vc4_crtc_debugfs_regs(struct seq_file
*m
, void *unused
)
126 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
127 struct drm_device
*dev
= node
->minor
->dev
;
128 int crtc_index
= (uintptr_t)node
->info_ent
->data
;
129 struct drm_crtc
*crtc
;
130 struct vc4_crtc
*vc4_crtc
;
134 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
141 vc4_crtc
= to_vc4_crtc(crtc
);
143 for (i
= 0; i
< ARRAY_SIZE(crtc_regs
); i
++) {
144 seq_printf(m
, "%s (0x%04x): 0x%08x\n",
145 crtc_regs
[i
].name
, crtc_regs
[i
].reg
,
146 CRTC_READ(crtc_regs
[i
].reg
));
153 int vc4_crtc_get_scanoutpos(struct drm_device
*dev
, unsigned int crtc_id
,
154 unsigned int flags
, int *vpos
, int *hpos
,
155 ktime_t
*stime
, ktime_t
*etime
,
156 const struct drm_display_mode
*mode
)
158 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
159 struct vc4_crtc
*vc4_crtc
= vc4
->crtc
[crtc_id
];
165 if (vc4
->firmware_kms
)
168 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
170 /* Get optional system timestamp before query. */
172 *stime
= ktime_get();
175 * Read vertical scanline which is currently composed for our
176 * pixelvalve by the HVS, and also the scaler status.
178 val
= HVS_READ(SCALER_DISPSTATX(vc4_crtc
->channel
));
180 /* Get optional system timestamp after query. */
182 *etime
= ktime_get();
184 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
186 /* Vertical position of hvs composed scanline. */
187 *vpos
= VC4_GET_FIELD(val
, SCALER_DISPSTATX_LINE
);
190 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
193 /* Use hpos to correct for field offset in interlaced mode. */
194 if (VC4_GET_FIELD(val
, SCALER_DISPSTATX_FRAME_COUNT
) % 2)
195 *hpos
+= mode
->crtc_htotal
/ 2;
198 /* This is the offset we need for translating hvs -> pv scanout pos. */
199 fifo_lines
= vc4_crtc
->cob_size
/ mode
->crtc_hdisplay
;
202 ret
|= DRM_SCANOUTPOS_VALID
;
204 /* HVS more than fifo_lines into frame for compositing? */
205 if (*vpos
> fifo_lines
) {
207 * We are in active scanout and can get some meaningful results
208 * from HVS. The actual PV scanout can not trail behind more
209 * than fifo_lines as that is the fifo's capacity. Assume that
210 * in active scanout the HVS and PV work in lockstep wrt. HVS
211 * refilling the fifo and PV consuming from the fifo, ie.
212 * whenever the PV consumes and frees up a scanline in the
213 * fifo, the HVS will immediately refill it, therefore
214 * incrementing vpos. Therefore we choose HVS read position -
215 * fifo size in scanlines as a estimate of the real scanout
216 * position of the PV.
218 *vpos
-= fifo_lines
+ 1;
220 ret
|= DRM_SCANOUTPOS_ACCURATE
;
225 * Less: This happens when we are in vblank and the HVS, after getting
226 * the VSTART restart signal from the PV, just started refilling its
227 * fifo with new lines from the top-most lines of the new framebuffers.
228 * The PV does not scan out in vblank, so does not remove lines from
229 * the fifo, so the fifo will be full quickly and the HVS has to pause.
230 * We can't get meaningful readings wrt. scanline position of the PV
231 * and need to make things up in a approximative but consistent way.
233 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
234 vblank_lines
= mode
->vtotal
- mode
->vdisplay
;
236 if (flags
& DRM_CALLED_FROM_VBLIRQ
) {
238 * Assume the irq handler got called close to first
239 * line of vblank, so PV has about a full vblank
240 * scanlines to go, and as a base timestamp use the
241 * one taken at entry into vblank irq handler, so it
242 * is not affected by random delays due to lock
243 * contention on event_lock or vblank_time lock in
246 *vpos
= -vblank_lines
;
249 *stime
= vc4_crtc
->t_vblank
;
251 *etime
= vc4_crtc
->t_vblank
;
254 * If the HVS fifo is not yet full then we know for certain
255 * we are at the very beginning of vblank, as the hvs just
256 * started refilling, and the stime and etime timestamps
257 * truly correspond to start of vblank.
259 if ((val
& SCALER_DISPSTATX_FULL
) != SCALER_DISPSTATX_FULL
)
260 ret
|= DRM_SCANOUTPOS_ACCURATE
;
263 * No clue where we are inside vblank. Return a vpos of zero,
264 * which will cause calling code to just return the etime
265 * timestamp uncorrected. At least this is no worse than the
274 int vc4_crtc_get_vblank_timestamp(struct drm_device
*dev
, unsigned int crtc_id
,
275 int *max_error
, struct timeval
*vblank_time
,
278 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
279 struct vc4_crtc
*vc4_crtc
= vc4
->crtc
[crtc_id
];
280 struct drm_crtc
*crtc
= &vc4_crtc
->base
;
281 struct drm_crtc_state
*state
= crtc
->state
;
283 /* Helper routine in DRM core does all the work: */
284 return drm_calc_vbltimestamp_from_scanoutpos(dev
, crtc_id
, max_error
,
286 &state
->adjusted_mode
);
289 static void vc4_crtc_destroy(struct drm_crtc
*crtc
)
291 drm_crtc_cleanup(crtc
);
295 vc4_crtc_lut_load(struct drm_crtc
*crtc
)
297 struct drm_device
*dev
= crtc
->dev
;
298 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
299 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
302 /* The LUT memory is laid out with each HVS channel in order,
303 * each of which takes 256 writes for R, 256 for G, then 256
306 HVS_WRITE(SCALER_GAMADDR
,
307 SCALER_GAMADDR_AUTOINC
|
308 (vc4_crtc
->channel
* 3 * crtc
->gamma_size
));
310 for (i
= 0; i
< crtc
->gamma_size
; i
++)
311 HVS_WRITE(SCALER_GAMDATA
, vc4_crtc
->lut_r
[i
]);
312 for (i
= 0; i
< crtc
->gamma_size
; i
++)
313 HVS_WRITE(SCALER_GAMDATA
, vc4_crtc
->lut_g
[i
]);
314 for (i
= 0; i
< crtc
->gamma_size
; i
++)
315 HVS_WRITE(SCALER_GAMDATA
, vc4_crtc
->lut_b
[i
]);
319 vc4_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*r
, u16
*g
, u16
*b
,
322 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
325 for (i
= 0; i
< size
; i
++) {
326 vc4_crtc
->lut_r
[i
] = r
[i
] >> 8;
327 vc4_crtc
->lut_g
[i
] = g
[i
] >> 8;
328 vc4_crtc
->lut_b
[i
] = b
[i
] >> 8;
331 vc4_crtc_lut_load(crtc
);
336 static u32
vc4_get_fifo_full_level(u32 format
)
338 static const u32 fifo_len_bytes
= 64;
339 static const u32 hvs_latency_pix
= 6;
342 case PV_CONTROL_FORMAT_DSIV_16
:
343 case PV_CONTROL_FORMAT_DSIC_16
:
344 return fifo_len_bytes
- 2 * hvs_latency_pix
;
345 case PV_CONTROL_FORMAT_DSIV_18
:
346 return fifo_len_bytes
- 14;
347 case PV_CONTROL_FORMAT_24
:
348 case PV_CONTROL_FORMAT_DSIV_24
:
350 return fifo_len_bytes
- 3 * hvs_latency_pix
;
355 * Returns the clock select bit for the connector attached to the
358 static int vc4_get_clock_select(struct drm_crtc
*crtc
)
360 struct drm_connector
*connector
;
362 drm_for_each_connector(connector
, crtc
->dev
) {
363 if (connector
->state
->crtc
== crtc
) {
364 struct drm_encoder
*encoder
= connector
->encoder
;
365 struct vc4_encoder
*vc4_encoder
=
366 to_vc4_encoder(encoder
);
368 return vc4_encoder
->clock_select
;
375 static void vc4_crtc_mode_set_nofb(struct drm_crtc
*crtc
)
377 struct drm_device
*dev
= crtc
->dev
;
378 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
379 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
380 struct drm_crtc_state
*state
= crtc
->state
;
381 struct drm_display_mode
*mode
= &state
->adjusted_mode
;
382 bool interlace
= mode
->flags
& DRM_MODE_FLAG_INTERLACE
;
383 u32 pixel_rep
= (mode
->flags
& DRM_MODE_FLAG_DBLCLK
) ? 2 : 1;
384 u32 format
= PV_CONTROL_FORMAT_24
;
385 bool debug_dump_regs
= false;
386 int clock_select
= vc4_get_clock_select(crtc
);
388 if (debug_dump_regs
) {
389 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc
));
390 vc4_crtc_dump_regs(vc4_crtc
);
393 /* Reset the PV fifo. */
394 CRTC_WRITE(PV_CONTROL
, 0);
395 CRTC_WRITE(PV_CONTROL
, PV_CONTROL_FIFO_CLR
| PV_CONTROL_EN
);
396 CRTC_WRITE(PV_CONTROL
, 0);
399 VC4_SET_FIELD((mode
->htotal
-
400 mode
->hsync_end
) * pixel_rep
,
402 VC4_SET_FIELD((mode
->hsync_end
-
403 mode
->hsync_start
) * pixel_rep
,
406 VC4_SET_FIELD((mode
->hsync_start
-
407 mode
->hdisplay
) * pixel_rep
,
409 VC4_SET_FIELD(mode
->hdisplay
* pixel_rep
, PV_HORZB_HACTIVE
));
412 VC4_SET_FIELD(mode
->crtc_vtotal
- mode
->crtc_vsync_end
,
414 VC4_SET_FIELD(mode
->crtc_vsync_end
- mode
->crtc_vsync_start
,
417 VC4_SET_FIELD(mode
->crtc_vsync_start
- mode
->crtc_vdisplay
,
419 VC4_SET_FIELD(mode
->crtc_vdisplay
, PV_VERTB_VACTIVE
));
422 CRTC_WRITE(PV_VERTA_EVEN
,
423 VC4_SET_FIELD(mode
->crtc_vtotal
-
424 mode
->crtc_vsync_end
- 1,
426 VC4_SET_FIELD(mode
->crtc_vsync_end
-
427 mode
->crtc_vsync_start
,
429 CRTC_WRITE(PV_VERTB_EVEN
,
430 VC4_SET_FIELD(mode
->crtc_vsync_start
-
433 VC4_SET_FIELD(mode
->crtc_vdisplay
, PV_VERTB_VACTIVE
));
435 /* We set up first field even mode for HDMI. VEC's
436 * NTSC mode would want first field odd instead, once
437 * we support it (to do so, set ODD_FIRST and put the
438 * delay in VSYNCD_EVEN instead).
440 CRTC_WRITE(PV_V_CONTROL
,
441 PV_VCONTROL_CONTINUOUS
|
442 PV_VCONTROL_INTERLACE
|
443 VC4_SET_FIELD(mode
->htotal
* pixel_rep
/ 2,
444 PV_VCONTROL_ODD_DELAY
));
445 CRTC_WRITE(PV_VSYNCD_EVEN
, 0);
447 CRTC_WRITE(PV_V_CONTROL
, PV_VCONTROL_CONTINUOUS
);
450 CRTC_WRITE(PV_HACT_ACT
, mode
->hdisplay
* pixel_rep
);
453 CRTC_WRITE(PV_CONTROL
,
454 VC4_SET_FIELD(format
, PV_CONTROL_FORMAT
) |
455 VC4_SET_FIELD(vc4_get_fifo_full_level(format
),
456 PV_CONTROL_FIFO_LEVEL
) |
457 VC4_SET_FIELD(pixel_rep
- 1, PV_CONTROL_PIXEL_REP
) |
458 PV_CONTROL_CLR_AT_START
|
459 PV_CONTROL_TRIGGER_UNDERFLOW
|
460 PV_CONTROL_WAIT_HSTART
|
461 VC4_SET_FIELD(clock_select
, PV_CONTROL_CLK_SELECT
) |
462 PV_CONTROL_FIFO_CLR
|
465 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc
->channel
),
466 SCALER_DISPBKGND_AUTOHS
|
467 SCALER_DISPBKGND_GAMMA
|
468 (interlace
? SCALER_DISPBKGND_INTERLACE
: 0));
470 /* Reload the LUT, since the SRAMs would have been disabled if
471 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
473 vc4_crtc_lut_load(crtc
);
475 if (debug_dump_regs
) {
476 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc
));
477 vc4_crtc_dump_regs(vc4_crtc
);
481 static void require_hvs_enabled(struct drm_device
*dev
)
483 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
485 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL
) & SCALER_DISPCTRL_ENABLE
) !=
486 SCALER_DISPCTRL_ENABLE
);
489 static void vc4_crtc_disable(struct drm_crtc
*crtc
)
491 struct drm_device
*dev
= crtc
->dev
;
492 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
493 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
494 u32 chan
= vc4_crtc
->channel
;
496 require_hvs_enabled(dev
);
498 /* Disable vblank irq handling before crtc is disabled. */
499 drm_crtc_vblank_off(crtc
);
501 CRTC_WRITE(PV_V_CONTROL
,
502 CRTC_READ(PV_V_CONTROL
) & ~PV_VCONTROL_VIDEN
);
503 ret
= wait_for(!(CRTC_READ(PV_V_CONTROL
) & PV_VCONTROL_VIDEN
), 1);
504 WARN_ONCE(ret
, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
506 if (HVS_READ(SCALER_DISPCTRLX(chan
)) &
507 SCALER_DISPCTRLX_ENABLE
) {
508 HVS_WRITE(SCALER_DISPCTRLX(chan
),
509 SCALER_DISPCTRLX_RESET
);
511 /* While the docs say that reset is self-clearing, it
512 * seems it doesn't actually.
514 HVS_WRITE(SCALER_DISPCTRLX(chan
), 0);
517 /* Once we leave, the scaler should be disabled and its fifo empty. */
519 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan
)) & SCALER_DISPCTRLX_RESET
);
521 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan
)),
522 SCALER_DISPSTATX_MODE
) !=
523 SCALER_DISPSTATX_MODE_DISABLED
);
525 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan
)) &
526 (SCALER_DISPSTATX_FULL
| SCALER_DISPSTATX_EMPTY
)) !=
527 SCALER_DISPSTATX_EMPTY
);
530 static void vc4_crtc_enable(struct drm_crtc
*crtc
)
532 struct drm_device
*dev
= crtc
->dev
;
533 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
534 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
535 struct drm_crtc_state
*state
= crtc
->state
;
536 struct drm_display_mode
*mode
= &state
->adjusted_mode
;
538 require_hvs_enabled(dev
);
540 /* Turn on the scaler, which will wait for vstart to start
543 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc
->channel
),
544 VC4_SET_FIELD(mode
->hdisplay
, SCALER_DISPCTRLX_WIDTH
) |
545 VC4_SET_FIELD(mode
->vdisplay
, SCALER_DISPCTRLX_HEIGHT
) |
546 SCALER_DISPCTRLX_ENABLE
);
548 /* Turn on the pixel valve, which will emit the vstart signal. */
549 CRTC_WRITE(PV_V_CONTROL
,
550 CRTC_READ(PV_V_CONTROL
) | PV_VCONTROL_VIDEN
);
552 /* Enable vblank irq handling after crtc is started. */
553 drm_crtc_vblank_on(crtc
);
556 static bool vc4_crtc_mode_fixup(struct drm_crtc
*crtc
,
557 const struct drm_display_mode
*mode
,
558 struct drm_display_mode
*adjusted_mode
)
560 /* Do not allow doublescan modes from user space */
561 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
) {
562 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
570 static int vc4_crtc_atomic_check(struct drm_crtc
*crtc
,
571 struct drm_crtc_state
*state
)
573 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(state
);
574 struct drm_device
*dev
= crtc
->dev
;
575 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
576 struct drm_plane
*plane
;
578 const struct drm_plane_state
*plane_state
;
582 /* The pixelvalve can only feed one encoder (and encoders are
583 * 1:1 with connectors.)
585 if (hweight32(state
->connector_mask
) > 1)
588 drm_atomic_crtc_state_for_each_plane_state(plane
, plane_state
, state
)
589 dlist_count
+= vc4_plane_dlist_size(plane_state
);
591 dlist_count
++; /* Account for SCALER_CTL0_END. */
593 spin_lock_irqsave(&vc4
->hvs
->mm_lock
, flags
);
594 ret
= drm_mm_insert_node(&vc4
->hvs
->dlist_mm
, &vc4_state
->mm
,
596 spin_unlock_irqrestore(&vc4
->hvs
->mm_lock
, flags
);
603 static void vc4_crtc_atomic_flush(struct drm_crtc
*crtc
,
604 struct drm_crtc_state
*old_state
)
606 struct drm_device
*dev
= crtc
->dev
;
607 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
608 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
609 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(crtc
->state
);
610 struct drm_plane
*plane
;
611 bool debug_dump_regs
= false;
612 u32 __iomem
*dlist_start
= vc4
->hvs
->dlist
+ vc4_state
->mm
.start
;
613 u32 __iomem
*dlist_next
= dlist_start
;
615 if (debug_dump_regs
) {
616 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc
));
617 vc4_hvs_dump_state(dev
);
620 /* Copy all the active planes' dlist contents to the hardware dlist. */
621 drm_atomic_crtc_for_each_plane(plane
, crtc
) {
622 dlist_next
+= vc4_plane_write_dlist(plane
, dlist_next
);
625 writel(SCALER_CTL0_END
, dlist_next
);
628 WARN_ON_ONCE(dlist_next
- dlist_start
!= vc4_state
->mm
.size
);
630 if (crtc
->state
->event
) {
633 crtc
->state
->event
->pipe
= drm_crtc_index(crtc
);
635 WARN_ON(drm_crtc_vblank_get(crtc
) != 0);
637 spin_lock_irqsave(&dev
->event_lock
, flags
);
638 vc4_crtc
->event
= crtc
->state
->event
;
639 crtc
->state
->event
= NULL
;
641 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc
->channel
),
642 vc4_state
->mm
.start
);
644 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
646 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc
->channel
),
647 vc4_state
->mm
.start
);
650 if (debug_dump_regs
) {
651 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc
));
652 vc4_hvs_dump_state(dev
);
656 int vc4_enable_vblank(struct drm_device
*dev
, unsigned int crtc_id
)
658 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
659 struct vc4_crtc
*vc4_crtc
= vc4
->crtc
[crtc_id
];
661 if (vc4
->firmware_kms
) {
662 /* XXX: Can we mask the SMI interrupt? */
666 CRTC_WRITE(PV_INTEN
, PV_INT_VFP_START
);
671 void vc4_disable_vblank(struct drm_device
*dev
, unsigned int crtc_id
)
673 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
674 struct vc4_crtc
*vc4_crtc
= vc4
->crtc
[crtc_id
];
676 if (vc4
->firmware_kms
) {
677 /* XXX: Can we mask the SMI interrupt? */
681 CRTC_WRITE(PV_INTEN
, 0);
684 /* Must be called with the event lock held */
685 bool vc4_event_pending(struct drm_crtc
*crtc
)
687 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
689 return !!vc4_crtc
->event
;
692 static void vc4_crtc_handle_page_flip(struct vc4_crtc
*vc4_crtc
)
694 struct drm_crtc
*crtc
= &vc4_crtc
->base
;
695 struct drm_device
*dev
= crtc
->dev
;
696 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
697 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(crtc
->state
);
698 u32 chan
= vc4_crtc
->channel
;
701 spin_lock_irqsave(&dev
->event_lock
, flags
);
702 if (vc4_crtc
->event
&&
703 (vc4_state
->mm
.start
== HVS_READ(SCALER_DISPLACTX(chan
)))) {
704 drm_crtc_send_vblank_event(crtc
, vc4_crtc
->event
);
705 vc4_crtc
->event
= NULL
;
706 drm_crtc_vblank_put(crtc
);
708 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
711 static irqreturn_t
vc4_crtc_irq_handler(int irq
, void *data
)
713 struct vc4_crtc
*vc4_crtc
= data
;
714 u32 stat
= CRTC_READ(PV_INTSTAT
);
715 irqreturn_t ret
= IRQ_NONE
;
717 if (stat
& PV_INT_VFP_START
) {
718 vc4_crtc
->t_vblank
= ktime_get();
719 CRTC_WRITE(PV_INTSTAT
, PV_INT_VFP_START
);
720 drm_crtc_handle_vblank(&vc4_crtc
->base
);
721 vc4_crtc_handle_page_flip(vc4_crtc
);
728 struct vc4_async_flip_state
{
729 struct drm_crtc
*crtc
;
730 struct drm_framebuffer
*fb
;
731 struct drm_pending_vblank_event
*event
;
733 struct vc4_seqno_cb cb
;
736 /* Called when the V3D execution for the BO being flipped to is done, so that
737 * we can actually update the plane's address to point to it.
740 vc4_async_page_flip_complete(struct vc4_seqno_cb
*cb
)
742 struct vc4_async_flip_state
*flip_state
=
743 container_of(cb
, struct vc4_async_flip_state
, cb
);
744 struct drm_crtc
*crtc
= flip_state
->crtc
;
745 struct drm_device
*dev
= crtc
->dev
;
746 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
747 struct drm_plane
*plane
= crtc
->primary
;
749 vc4_plane_async_set_fb(plane
, flip_state
->fb
);
750 if (flip_state
->event
) {
753 spin_lock_irqsave(&dev
->event_lock
, flags
);
754 drm_crtc_send_vblank_event(crtc
, flip_state
->event
);
755 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
758 drm_crtc_vblank_put(crtc
);
759 drm_framebuffer_unreference(flip_state
->fb
);
762 up(&vc4
->async_modeset
);
765 /* Implements async (non-vblank-synced) page flips.
767 * The page flip ioctl needs to return immediately, so we grab the
768 * modeset semaphore on the pipe, and queue the address update for
769 * when V3D is done with the BO being flipped to.
771 static int vc4_async_page_flip(struct drm_crtc
*crtc
,
772 struct drm_framebuffer
*fb
,
773 struct drm_pending_vblank_event
*event
,
776 struct drm_device
*dev
= crtc
->dev
;
777 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
778 struct drm_plane
*plane
= crtc
->primary
;
780 struct vc4_async_flip_state
*flip_state
;
781 struct drm_gem_cma_object
*cma_bo
= drm_fb_cma_get_gem_obj(fb
, 0);
782 struct vc4_bo
*bo
= to_vc4_bo(&cma_bo
->base
);
784 flip_state
= kzalloc(sizeof(*flip_state
), GFP_KERNEL
);
788 drm_framebuffer_reference(fb
);
790 flip_state
->crtc
= crtc
;
791 flip_state
->event
= event
;
793 /* Make sure all other async modesetes have landed. */
794 ret
= down_interruptible(&vc4
->async_modeset
);
796 drm_framebuffer_unreference(fb
);
801 WARN_ON(drm_crtc_vblank_get(crtc
) != 0);
803 /* Immediately update the plane's legacy fb pointer, so that later
804 * modeset prep sees the state that will be present when the semaphore
807 drm_atomic_set_fb_for_plane(plane
->state
, fb
);
810 vc4_queue_seqno_cb(dev
, &flip_state
->cb
, bo
->seqno
,
811 vc4_async_page_flip_complete
);
813 /* Driver takes ownership of state on successful async commit. */
817 static int vc4_page_flip(struct drm_crtc
*crtc
,
818 struct drm_framebuffer
*fb
,
819 struct drm_pending_vblank_event
*event
,
822 if (flags
& DRM_MODE_PAGE_FLIP_ASYNC
)
823 return vc4_async_page_flip(crtc
, fb
, event
, flags
);
825 return drm_atomic_helper_page_flip(crtc
, fb
, event
, flags
);
828 static struct drm_crtc_state
*vc4_crtc_duplicate_state(struct drm_crtc
*crtc
)
830 struct vc4_crtc_state
*vc4_state
;
832 vc4_state
= kzalloc(sizeof(*vc4_state
), GFP_KERNEL
);
836 __drm_atomic_helper_crtc_duplicate_state(crtc
, &vc4_state
->base
);
837 return &vc4_state
->base
;
840 static void vc4_crtc_destroy_state(struct drm_crtc
*crtc
,
841 struct drm_crtc_state
*state
)
843 struct vc4_dev
*vc4
= to_vc4_dev(crtc
->dev
);
844 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(state
);
846 if (vc4_state
->mm
.allocated
) {
849 spin_lock_irqsave(&vc4
->hvs
->mm_lock
, flags
);
850 drm_mm_remove_node(&vc4_state
->mm
);
851 spin_unlock_irqrestore(&vc4
->hvs
->mm_lock
, flags
);
855 drm_atomic_helper_crtc_destroy_state(crtc
, state
);
859 vc4_crtc_reset(struct drm_crtc
*crtc
)
862 __drm_atomic_helper_crtc_destroy_state(crtc
->state
);
864 crtc
->state
= kzalloc(sizeof(struct vc4_crtc_state
), GFP_KERNEL
);
866 crtc
->state
->crtc
= crtc
;
869 static const struct drm_crtc_funcs vc4_crtc_funcs
= {
870 .set_config
= drm_atomic_helper_set_config
,
871 .destroy
= vc4_crtc_destroy
,
872 .page_flip
= vc4_page_flip
,
873 .set_property
= NULL
,
874 .cursor_set
= NULL
, /* handled by drm_mode_cursor_universal */
875 .cursor_move
= NULL
, /* handled by drm_mode_cursor_universal */
876 .reset
= vc4_crtc_reset
,
877 .atomic_duplicate_state
= vc4_crtc_duplicate_state
,
878 .atomic_destroy_state
= vc4_crtc_destroy_state
,
879 .gamma_set
= vc4_crtc_gamma_set
,
882 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs
= {
883 .mode_set_nofb
= vc4_crtc_mode_set_nofb
,
884 .disable
= vc4_crtc_disable
,
885 .enable
= vc4_crtc_enable
,
886 .mode_fixup
= vc4_crtc_mode_fixup
,
887 .atomic_check
= vc4_crtc_atomic_check
,
888 .atomic_flush
= vc4_crtc_atomic_flush
,
891 static const struct vc4_crtc_data pv0_data
= {
894 [PV_CONTROL_CLK_SELECT_DSI
] = VC4_ENCODER_TYPE_DSI0
,
895 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI
] = VC4_ENCODER_TYPE_DPI
,
899 static const struct vc4_crtc_data pv1_data
= {
902 [PV_CONTROL_CLK_SELECT_DSI
] = VC4_ENCODER_TYPE_DSI1
,
903 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI
] = VC4_ENCODER_TYPE_SMI
,
907 static const struct vc4_crtc_data pv2_data
= {
910 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI
] = VC4_ENCODER_TYPE_HDMI
,
911 [PV_CONTROL_CLK_SELECT_VEC
] = VC4_ENCODER_TYPE_VEC
,
915 static const struct of_device_id vc4_crtc_dt_match
[] = {
916 { .compatible
= "brcm,bcm2835-pixelvalve0", .data
= &pv0_data
},
917 { .compatible
= "brcm,bcm2835-pixelvalve1", .data
= &pv1_data
},
918 { .compatible
= "brcm,bcm2835-pixelvalve2", .data
= &pv2_data
},
922 static void vc4_set_crtc_possible_masks(struct drm_device
*drm
,
923 struct drm_crtc
*crtc
)
925 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
926 const struct vc4_crtc_data
*crtc_data
= vc4_crtc
->data
;
927 const enum vc4_encoder_type
*encoder_types
= crtc_data
->encoder_types
;
928 struct drm_encoder
*encoder
;
930 drm_for_each_encoder(encoder
, drm
) {
931 struct vc4_encoder
*vc4_encoder
= to_vc4_encoder(encoder
);
934 for (i
= 0; i
< ARRAY_SIZE(crtc_data
->encoder_types
); i
++) {
935 if (vc4_encoder
->type
== encoder_types
[i
]) {
936 vc4_encoder
->clock_select
= i
;
937 encoder
->possible_crtcs
|= drm_crtc_mask(crtc
);
945 vc4_crtc_get_cob_allocation(struct vc4_crtc
*vc4_crtc
)
947 struct drm_device
*drm
= vc4_crtc
->base
.dev
;
948 struct vc4_dev
*vc4
= to_vc4_dev(drm
);
949 u32 dispbase
= HVS_READ(SCALER_DISPBASEX(vc4_crtc
->channel
));
950 /* Top/base are supposed to be 4-pixel aligned, but the
951 * Raspberry Pi firmware fills the low bits (which are
952 * presumably ignored).
954 u32 top
= VC4_GET_FIELD(dispbase
, SCALER_DISPBASEX_TOP
) & ~3;
955 u32 base
= VC4_GET_FIELD(dispbase
, SCALER_DISPBASEX_BASE
) & ~3;
957 vc4_crtc
->cob_size
= top
- base
+ 4;
960 static int vc4_crtc_bind(struct device
*dev
, struct device
*master
, void *data
)
962 struct platform_device
*pdev
= to_platform_device(dev
);
963 struct drm_device
*drm
= dev_get_drvdata(master
);
964 struct vc4_dev
*vc4
= to_vc4_dev(drm
);
965 struct vc4_crtc
*vc4_crtc
;
966 struct drm_crtc
*crtc
;
967 struct drm_plane
*primary_plane
, *cursor_plane
, *destroy_plane
, *temp
;
968 const struct of_device_id
*match
;
971 vc4_crtc
= devm_kzalloc(dev
, sizeof(*vc4_crtc
), GFP_KERNEL
);
974 crtc
= &vc4_crtc
->base
;
976 match
= of_match_device(vc4_crtc_dt_match
, dev
);
979 vc4_crtc
->data
= match
->data
;
981 vc4_crtc
->regs
= vc4_ioremap_regs(pdev
, 0);
982 if (IS_ERR(vc4_crtc
->regs
))
983 return PTR_ERR(vc4_crtc
->regs
);
985 /* For now, we create just the primary and the legacy cursor
986 * planes. We should be able to stack more planes on easily,
987 * but to do that we would need to compute the bandwidth
988 * requirement of the plane configuration, and reject ones
989 * that will take too much.
991 primary_plane
= vc4_plane_init(drm
, DRM_PLANE_TYPE_PRIMARY
);
992 if (IS_ERR(primary_plane
)) {
993 dev_err(dev
, "failed to construct primary plane\n");
994 ret
= PTR_ERR(primary_plane
);
998 drm_crtc_init_with_planes(drm
, crtc
, primary_plane
, NULL
,
999 &vc4_crtc_funcs
, NULL
);
1000 drm_crtc_helper_add(crtc
, &vc4_crtc_helper_funcs
);
1001 primary_plane
->crtc
= crtc
;
1002 vc4
->crtc
[drm_crtc_index(crtc
)] = vc4_crtc
;
1003 vc4_crtc
->channel
= vc4_crtc
->data
->hvs_channel
;
1004 drm_mode_crtc_set_gamma_size(crtc
, ARRAY_SIZE(vc4_crtc
->lut_r
));
1006 /* Set up some arbitrary number of planes. We're not limited
1007 * by a set number of physical registers, just the space in
1008 * the HVS (16k) and how small an plane can be (28 bytes).
1009 * However, each plane we set up takes up some memory, and
1010 * increases the cost of looping over planes, which atomic
1011 * modesetting does quite a bit. As a result, we pick a
1012 * modest number of planes to expose, that should hopefully
1013 * still cover any sane usecase.
1015 for (i
= 0; i
< 8; i
++) {
1016 struct drm_plane
*plane
=
1017 vc4_plane_init(drm
, DRM_PLANE_TYPE_OVERLAY
);
1022 plane
->possible_crtcs
= 1 << drm_crtc_index(crtc
);
1025 /* Set up the legacy cursor after overlay initialization,
1026 * since we overlay planes on the CRTC in the order they were
1029 cursor_plane
= vc4_plane_init(drm
, DRM_PLANE_TYPE_CURSOR
);
1030 if (!IS_ERR(cursor_plane
)) {
1031 cursor_plane
->possible_crtcs
= 1 << drm_crtc_index(crtc
);
1032 cursor_plane
->crtc
= crtc
;
1033 crtc
->cursor
= cursor_plane
;
1036 vc4_crtc_get_cob_allocation(vc4_crtc
);
1038 CRTC_WRITE(PV_INTEN
, 0);
1039 CRTC_WRITE(PV_INTSTAT
, PV_INT_VFP_START
);
1040 ret
= devm_request_irq(dev
, platform_get_irq(pdev
, 0),
1041 vc4_crtc_irq_handler
, 0, "vc4 crtc", vc4_crtc
);
1043 goto err_destroy_planes
;
1045 vc4_set_crtc_possible_masks(drm
, crtc
);
1047 for (i
= 0; i
< crtc
->gamma_size
; i
++) {
1048 vc4_crtc
->lut_r
[i
] = i
;
1049 vc4_crtc
->lut_g
[i
] = i
;
1050 vc4_crtc
->lut_b
[i
] = i
;
1053 platform_set_drvdata(pdev
, vc4_crtc
);
1058 list_for_each_entry_safe(destroy_plane
, temp
,
1059 &drm
->mode_config
.plane_list
, head
) {
1060 if (destroy_plane
->possible_crtcs
== 1 << drm_crtc_index(crtc
))
1061 destroy_plane
->funcs
->destroy(destroy_plane
);
1067 static void vc4_crtc_unbind(struct device
*dev
, struct device
*master
,
1070 struct platform_device
*pdev
= to_platform_device(dev
);
1071 struct vc4_crtc
*vc4_crtc
= dev_get_drvdata(dev
);
1073 vc4_crtc_destroy(&vc4_crtc
->base
);
1075 CRTC_WRITE(PV_INTEN
, 0);
1077 platform_set_drvdata(pdev
, NULL
);
1080 static const struct component_ops vc4_crtc_ops
= {
1081 .bind
= vc4_crtc_bind
,
1082 .unbind
= vc4_crtc_unbind
,
1085 static int vc4_crtc_dev_probe(struct platform_device
*pdev
)
1087 return component_add(&pdev
->dev
, &vc4_crtc_ops
);
1090 static int vc4_crtc_dev_remove(struct platform_device
*pdev
)
1092 component_del(&pdev
->dev
, &vc4_crtc_ops
);
1096 struct platform_driver vc4_crtc_driver
= {
1097 .probe
= vc4_crtc_dev_probe
,
1098 .remove
= vc4_crtc_dev_remove
,
1101 .of_match_table
= vc4_crtc_dt_match
,