2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * DOC: VC4 CRTC module
12 * In VC4, the Pixel Valve is what most closely corresponds to the
13 * DRM's concept of a CRTC. The PV generates video timings from the
14 * encoder's clock plus its configuration. It pulls scaled pixels from
15 * the HVS at that timing, and feeds it to the encoder.
17 * However, the DRM CRTC also collects the configuration of all the
18 * DRM planes attached to it. As a result, the CRTC is also
19 * responsible for writing the display list for the HVS channel that
22 * The 2835 has 3 different pixel valves. pv0 in the audio power
23 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
24 * image domain can feed either HDMI or the SDTV controller. The
25 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
26 * SDTV, etc.) according to which output type is chosen in the mux.
28 * For power management, the pixel valve's registers are all clocked
29 * by the AXI clock, while the timings and FIFOs make use of the
30 * output-specific clock. Since the encoders also directly consume
31 * the CPRMAN clocks, and know what timings they need, they are the
32 * ones that set the clock.
35 #include <drm/drm_atomic.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc_helper.h>
38 #include <linux/clk.h>
39 #include <drm/drm_fb_cma_helper.h>
40 #include <linux/component.h>
41 #include <linux/of_device.h>
47 const struct vc4_crtc_data
*data
;
50 /* Timestamp at start of vblank irq - unaffected by lock delays. */
53 /* Which HVS channel we're using for our CRTC. */
59 /* Size in pixels of the COB memory allocated to this CRTC. */
62 struct drm_pending_vblank_event
*event
;
65 struct vc4_crtc_state
{
66 struct drm_crtc_state base
;
67 /* Dlist area for this CRTC configuration. */
68 struct drm_mm_node mm
;
71 static inline struct vc4_crtc
*
72 to_vc4_crtc(struct drm_crtc
*crtc
)
74 return (struct vc4_crtc
*)crtc
;
77 static inline struct vc4_crtc_state
*
78 to_vc4_crtc_state(struct drm_crtc_state
*crtc_state
)
80 return (struct vc4_crtc_state
*)crtc_state
;
83 struct vc4_crtc_data
{
84 /* Which channel of the HVS this pixelvalve sources from. */
87 enum vc4_encoder_type encoder_types
[4];
90 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
91 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
93 #define CRTC_REG(reg) { reg, #reg }
99 CRTC_REG(PV_V_CONTROL
),
100 CRTC_REG(PV_VSYNCD_EVEN
),
105 CRTC_REG(PV_VERTA_EVEN
),
106 CRTC_REG(PV_VERTB_EVEN
),
108 CRTC_REG(PV_INTSTAT
),
110 CRTC_REG(PV_HACT_ACT
),
113 static void vc4_crtc_dump_regs(struct vc4_crtc
*vc4_crtc
)
117 for (i
= 0; i
< ARRAY_SIZE(crtc_regs
); i
++) {
118 DRM_INFO("0x%04x (%s): 0x%08x\n",
119 crtc_regs
[i
].reg
, crtc_regs
[i
].name
,
120 CRTC_READ(crtc_regs
[i
].reg
));
124 #ifdef CONFIG_DEBUG_FS
125 int vc4_crtc_debugfs_regs(struct seq_file
*m
, void *unused
)
127 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
128 struct drm_device
*dev
= node
->minor
->dev
;
129 int crtc_index
= (uintptr_t)node
->info_ent
->data
;
130 struct drm_crtc
*crtc
;
131 struct vc4_crtc
*vc4_crtc
;
135 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
142 vc4_crtc
= to_vc4_crtc(crtc
);
144 for (i
= 0; i
< ARRAY_SIZE(crtc_regs
); i
++) {
145 seq_printf(m
, "%s (0x%04x): 0x%08x\n",
146 crtc_regs
[i
].name
, crtc_regs
[i
].reg
,
147 CRTC_READ(crtc_regs
[i
].reg
));
154 bool vc4_crtc_get_scanoutpos(struct drm_device
*dev
, unsigned int crtc_id
,
155 bool in_vblank_irq
, int *vpos
, int *hpos
,
156 ktime_t
*stime
, ktime_t
*etime
,
157 const struct drm_display_mode
*mode
)
159 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
160 struct drm_crtc
*crtc
= drm_crtc_from_index(dev
, crtc_id
);
161 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
167 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
169 /* Get optional system timestamp before query. */
171 *stime
= ktime_get();
174 * Read vertical scanline which is currently composed for our
175 * pixelvalve by the HVS, and also the scaler status.
177 val
= HVS_READ(SCALER_DISPSTATX(vc4_crtc
->channel
));
179 /* Get optional system timestamp after query. */
181 *etime
= ktime_get();
183 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
185 /* Vertical position of hvs composed scanline. */
186 *vpos
= VC4_GET_FIELD(val
, SCALER_DISPSTATX_LINE
);
189 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
192 /* Use hpos to correct for field offset in interlaced mode. */
193 if (VC4_GET_FIELD(val
, SCALER_DISPSTATX_FRAME_COUNT
) % 2)
194 *hpos
+= mode
->crtc_htotal
/ 2;
197 /* This is the offset we need for translating hvs -> pv scanout pos. */
198 fifo_lines
= vc4_crtc
->cob_size
/ mode
->crtc_hdisplay
;
203 /* HVS more than fifo_lines into frame for compositing? */
204 if (*vpos
> fifo_lines
) {
206 * We are in active scanout and can get some meaningful results
207 * from HVS. The actual PV scanout can not trail behind more
208 * than fifo_lines as that is the fifo's capacity. Assume that
209 * in active scanout the HVS and PV work in lockstep wrt. HVS
210 * refilling the fifo and PV consuming from the fifo, ie.
211 * whenever the PV consumes and frees up a scanline in the
212 * fifo, the HVS will immediately refill it, therefore
213 * incrementing vpos. Therefore we choose HVS read position -
214 * fifo size in scanlines as a estimate of the real scanout
215 * position of the PV.
217 *vpos
-= fifo_lines
+ 1;
223 * Less: This happens when we are in vblank and the HVS, after getting
224 * the VSTART restart signal from the PV, just started refilling its
225 * fifo with new lines from the top-most lines of the new framebuffers.
226 * The PV does not scan out in vblank, so does not remove lines from
227 * the fifo, so the fifo will be full quickly and the HVS has to pause.
228 * We can't get meaningful readings wrt. scanline position of the PV
229 * and need to make things up in a approximative but consistent way.
231 vblank_lines
= mode
->vtotal
- mode
->vdisplay
;
235 * Assume the irq handler got called close to first
236 * line of vblank, so PV has about a full vblank
237 * scanlines to go, and as a base timestamp use the
238 * one taken at entry into vblank irq handler, so it
239 * is not affected by random delays due to lock
240 * contention on event_lock or vblank_time lock in
243 *vpos
= -vblank_lines
;
246 *stime
= vc4_crtc
->t_vblank
;
248 *etime
= vc4_crtc
->t_vblank
;
251 * If the HVS fifo is not yet full then we know for certain
252 * we are at the very beginning of vblank, as the hvs just
253 * started refilling, and the stime and etime timestamps
254 * truly correspond to start of vblank.
256 * Unfortunately there's no way to report this to upper levels
257 * and make it more useful.
261 * No clue where we are inside vblank. Return a vpos of zero,
262 * which will cause calling code to just return the etime
263 * timestamp uncorrected. At least this is no worse than the
272 static void vc4_crtc_destroy(struct drm_crtc
*crtc
)
274 drm_crtc_cleanup(crtc
);
278 vc4_crtc_lut_load(struct drm_crtc
*crtc
)
280 struct drm_device
*dev
= crtc
->dev
;
281 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
282 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
285 /* The LUT memory is laid out with each HVS channel in order,
286 * each of which takes 256 writes for R, 256 for G, then 256
289 HVS_WRITE(SCALER_GAMADDR
,
290 SCALER_GAMADDR_AUTOINC
|
291 (vc4_crtc
->channel
* 3 * crtc
->gamma_size
));
293 for (i
= 0; i
< crtc
->gamma_size
; i
++)
294 HVS_WRITE(SCALER_GAMDATA
, vc4_crtc
->lut_r
[i
]);
295 for (i
= 0; i
< crtc
->gamma_size
; i
++)
296 HVS_WRITE(SCALER_GAMDATA
, vc4_crtc
->lut_g
[i
]);
297 for (i
= 0; i
< crtc
->gamma_size
; i
++)
298 HVS_WRITE(SCALER_GAMDATA
, vc4_crtc
->lut_b
[i
]);
302 vc4_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*r
, u16
*g
, u16
*b
,
304 struct drm_modeset_acquire_ctx
*ctx
)
306 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
309 for (i
= 0; i
< size
; i
++) {
310 vc4_crtc
->lut_r
[i
] = r
[i
] >> 8;
311 vc4_crtc
->lut_g
[i
] = g
[i
] >> 8;
312 vc4_crtc
->lut_b
[i
] = b
[i
] >> 8;
315 vc4_crtc_lut_load(crtc
);
320 static u32
vc4_get_fifo_full_level(u32 format
)
322 static const u32 fifo_len_bytes
= 64;
323 static const u32 hvs_latency_pix
= 6;
326 case PV_CONTROL_FORMAT_DSIV_16
:
327 case PV_CONTROL_FORMAT_DSIC_16
:
328 return fifo_len_bytes
- 2 * hvs_latency_pix
;
329 case PV_CONTROL_FORMAT_DSIV_18
:
330 return fifo_len_bytes
- 14;
331 case PV_CONTROL_FORMAT_24
:
332 case PV_CONTROL_FORMAT_DSIV_24
:
334 return fifo_len_bytes
- 3 * hvs_latency_pix
;
339 * Returns the encoder attached to the CRTC.
341 * VC4 can only scan out to one encoder at a time, while the DRM core
342 * allows drivers to push pixels to more than one encoder from the
345 static struct drm_encoder
*vc4_get_crtc_encoder(struct drm_crtc
*crtc
)
347 struct drm_connector
*connector
;
348 struct drm_connector_list_iter conn_iter
;
350 drm_connector_list_iter_begin(crtc
->dev
, &conn_iter
);
351 drm_for_each_connector_iter(connector
, &conn_iter
) {
352 if (connector
->state
->crtc
== crtc
) {
353 drm_connector_list_iter_end(&conn_iter
);
354 return connector
->encoder
;
357 drm_connector_list_iter_end(&conn_iter
);
362 static void vc4_crtc_mode_set_nofb(struct drm_crtc
*crtc
)
364 struct drm_device
*dev
= crtc
->dev
;
365 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
366 struct drm_encoder
*encoder
= vc4_get_crtc_encoder(crtc
);
367 struct vc4_encoder
*vc4_encoder
= to_vc4_encoder(encoder
);
368 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
369 struct drm_crtc_state
*state
= crtc
->state
;
370 struct drm_display_mode
*mode
= &state
->adjusted_mode
;
371 bool interlace
= mode
->flags
& DRM_MODE_FLAG_INTERLACE
;
372 u32 pixel_rep
= (mode
->flags
& DRM_MODE_FLAG_DBLCLK
) ? 2 : 1;
373 bool is_dsi
= (vc4_encoder
->type
== VC4_ENCODER_TYPE_DSI0
||
374 vc4_encoder
->type
== VC4_ENCODER_TYPE_DSI1
);
375 u32 format
= is_dsi
? PV_CONTROL_FORMAT_DSIV_24
: PV_CONTROL_FORMAT_24
;
376 bool debug_dump_regs
= false;
378 if (debug_dump_regs
) {
379 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc
));
380 vc4_crtc_dump_regs(vc4_crtc
);
383 /* Reset the PV fifo. */
384 CRTC_WRITE(PV_CONTROL
, 0);
385 CRTC_WRITE(PV_CONTROL
, PV_CONTROL_FIFO_CLR
| PV_CONTROL_EN
);
386 CRTC_WRITE(PV_CONTROL
, 0);
389 VC4_SET_FIELD((mode
->htotal
-
390 mode
->hsync_end
) * pixel_rep
,
392 VC4_SET_FIELD((mode
->hsync_end
-
393 mode
->hsync_start
) * pixel_rep
,
396 VC4_SET_FIELD((mode
->hsync_start
-
397 mode
->hdisplay
) * pixel_rep
,
399 VC4_SET_FIELD(mode
->hdisplay
* pixel_rep
, PV_HORZB_HACTIVE
));
402 VC4_SET_FIELD(mode
->crtc_vtotal
- mode
->crtc_vsync_end
,
404 VC4_SET_FIELD(mode
->crtc_vsync_end
- mode
->crtc_vsync_start
,
407 VC4_SET_FIELD(mode
->crtc_vsync_start
- mode
->crtc_vdisplay
,
409 VC4_SET_FIELD(mode
->crtc_vdisplay
, PV_VERTB_VACTIVE
));
412 CRTC_WRITE(PV_VERTA_EVEN
,
413 VC4_SET_FIELD(mode
->crtc_vtotal
-
414 mode
->crtc_vsync_end
- 1,
416 VC4_SET_FIELD(mode
->crtc_vsync_end
-
417 mode
->crtc_vsync_start
,
419 CRTC_WRITE(PV_VERTB_EVEN
,
420 VC4_SET_FIELD(mode
->crtc_vsync_start
-
423 VC4_SET_FIELD(mode
->crtc_vdisplay
, PV_VERTB_VACTIVE
));
425 /* We set up first field even mode for HDMI. VEC's
426 * NTSC mode would want first field odd instead, once
427 * we support it (to do so, set ODD_FIRST and put the
428 * delay in VSYNCD_EVEN instead).
430 CRTC_WRITE(PV_V_CONTROL
,
431 PV_VCONTROL_CONTINUOUS
|
432 (is_dsi
? PV_VCONTROL_DSI
: 0) |
433 PV_VCONTROL_INTERLACE
|
434 VC4_SET_FIELD(mode
->htotal
* pixel_rep
/ 2,
435 PV_VCONTROL_ODD_DELAY
));
436 CRTC_WRITE(PV_VSYNCD_EVEN
, 0);
438 CRTC_WRITE(PV_V_CONTROL
,
439 PV_VCONTROL_CONTINUOUS
|
440 (is_dsi
? PV_VCONTROL_DSI
: 0));
443 CRTC_WRITE(PV_HACT_ACT
, mode
->hdisplay
* pixel_rep
);
445 CRTC_WRITE(PV_CONTROL
,
446 VC4_SET_FIELD(format
, PV_CONTROL_FORMAT
) |
447 VC4_SET_FIELD(vc4_get_fifo_full_level(format
),
448 PV_CONTROL_FIFO_LEVEL
) |
449 VC4_SET_FIELD(pixel_rep
- 1, PV_CONTROL_PIXEL_REP
) |
450 PV_CONTROL_CLR_AT_START
|
451 PV_CONTROL_TRIGGER_UNDERFLOW
|
452 PV_CONTROL_WAIT_HSTART
|
453 VC4_SET_FIELD(vc4_encoder
->clock_select
,
454 PV_CONTROL_CLK_SELECT
) |
455 PV_CONTROL_FIFO_CLR
|
458 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc
->channel
),
459 SCALER_DISPBKGND_AUTOHS
|
460 SCALER_DISPBKGND_GAMMA
|
461 (interlace
? SCALER_DISPBKGND_INTERLACE
: 0));
463 /* Reload the LUT, since the SRAMs would have been disabled if
464 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
466 vc4_crtc_lut_load(crtc
);
468 if (debug_dump_regs
) {
469 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc
));
470 vc4_crtc_dump_regs(vc4_crtc
);
474 static void require_hvs_enabled(struct drm_device
*dev
)
476 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
478 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL
) & SCALER_DISPCTRL_ENABLE
) !=
479 SCALER_DISPCTRL_ENABLE
);
482 static void vc4_crtc_atomic_disable(struct drm_crtc
*crtc
,
483 struct drm_crtc_state
*old_state
)
485 struct drm_device
*dev
= crtc
->dev
;
486 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
487 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
488 u32 chan
= vc4_crtc
->channel
;
490 require_hvs_enabled(dev
);
492 /* Disable vblank irq handling before crtc is disabled. */
493 drm_crtc_vblank_off(crtc
);
495 CRTC_WRITE(PV_V_CONTROL
,
496 CRTC_READ(PV_V_CONTROL
) & ~PV_VCONTROL_VIDEN
);
497 ret
= wait_for(!(CRTC_READ(PV_V_CONTROL
) & PV_VCONTROL_VIDEN
), 1);
498 WARN_ONCE(ret
, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
500 if (HVS_READ(SCALER_DISPCTRLX(chan
)) &
501 SCALER_DISPCTRLX_ENABLE
) {
502 HVS_WRITE(SCALER_DISPCTRLX(chan
),
503 SCALER_DISPCTRLX_RESET
);
505 /* While the docs say that reset is self-clearing, it
506 * seems it doesn't actually.
508 HVS_WRITE(SCALER_DISPCTRLX(chan
), 0);
511 /* Once we leave, the scaler should be disabled and its fifo empty. */
513 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan
)) & SCALER_DISPCTRLX_RESET
);
515 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan
)),
516 SCALER_DISPSTATX_MODE
) !=
517 SCALER_DISPSTATX_MODE_DISABLED
);
519 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan
)) &
520 (SCALER_DISPSTATX_FULL
| SCALER_DISPSTATX_EMPTY
)) !=
521 SCALER_DISPSTATX_EMPTY
);
524 * Make sure we issue a vblank event after disabling the CRTC if
525 * someone was waiting it.
527 if (crtc
->state
->event
) {
530 spin_lock_irqsave(&dev
->event_lock
, flags
);
531 drm_crtc_send_vblank_event(crtc
, crtc
->state
->event
);
532 crtc
->state
->event
= NULL
;
533 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
537 static void vc4_crtc_update_dlist(struct drm_crtc
*crtc
)
539 struct drm_device
*dev
= crtc
->dev
;
540 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
541 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
542 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(crtc
->state
);
544 if (crtc
->state
->event
) {
547 crtc
->state
->event
->pipe
= drm_crtc_index(crtc
);
549 WARN_ON(drm_crtc_vblank_get(crtc
) != 0);
551 spin_lock_irqsave(&dev
->event_lock
, flags
);
552 vc4_crtc
->event
= crtc
->state
->event
;
553 crtc
->state
->event
= NULL
;
555 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc
->channel
),
556 vc4_state
->mm
.start
);
558 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
560 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc
->channel
),
561 vc4_state
->mm
.start
);
565 static void vc4_crtc_atomic_enable(struct drm_crtc
*crtc
,
566 struct drm_crtc_state
*old_state
)
568 struct drm_device
*dev
= crtc
->dev
;
569 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
570 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
571 struct drm_crtc_state
*state
= crtc
->state
;
572 struct drm_display_mode
*mode
= &state
->adjusted_mode
;
574 require_hvs_enabled(dev
);
576 /* Enable vblank irq handling before crtc is started otherwise
577 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
579 drm_crtc_vblank_on(crtc
);
580 vc4_crtc_update_dlist(crtc
);
582 /* Turn on the scaler, which will wait for vstart to start
585 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc
->channel
),
586 VC4_SET_FIELD(mode
->hdisplay
, SCALER_DISPCTRLX_WIDTH
) |
587 VC4_SET_FIELD(mode
->vdisplay
, SCALER_DISPCTRLX_HEIGHT
) |
588 SCALER_DISPCTRLX_ENABLE
);
590 /* Turn on the pixel valve, which will emit the vstart signal. */
591 CRTC_WRITE(PV_V_CONTROL
,
592 CRTC_READ(PV_V_CONTROL
) | PV_VCONTROL_VIDEN
);
595 static enum drm_mode_status
vc4_crtc_mode_valid(struct drm_crtc
*crtc
,
596 const struct drm_display_mode
*mode
)
598 /* Do not allow doublescan modes from user space */
599 if (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
) {
600 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
602 return MODE_NO_DBLESCAN
;
608 static int vc4_crtc_atomic_check(struct drm_crtc
*crtc
,
609 struct drm_crtc_state
*state
)
611 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(state
);
612 struct drm_device
*dev
= crtc
->dev
;
613 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
614 struct drm_plane
*plane
;
616 const struct drm_plane_state
*plane_state
;
620 /* The pixelvalve can only feed one encoder (and encoders are
621 * 1:1 with connectors.)
623 if (hweight32(state
->connector_mask
) > 1)
626 drm_atomic_crtc_state_for_each_plane_state(plane
, plane_state
, state
)
627 dlist_count
+= vc4_plane_dlist_size(plane_state
);
629 dlist_count
++; /* Account for SCALER_CTL0_END. */
631 spin_lock_irqsave(&vc4
->hvs
->mm_lock
, flags
);
632 ret
= drm_mm_insert_node(&vc4
->hvs
->dlist_mm
, &vc4_state
->mm
,
634 spin_unlock_irqrestore(&vc4
->hvs
->mm_lock
, flags
);
641 static void vc4_crtc_atomic_flush(struct drm_crtc
*crtc
,
642 struct drm_crtc_state
*old_state
)
644 struct drm_device
*dev
= crtc
->dev
;
645 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
646 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
647 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(crtc
->state
);
648 struct drm_plane
*plane
;
649 struct vc4_plane_state
*vc4_plane_state
;
650 bool debug_dump_regs
= false;
651 bool enable_bg_fill
= false;
652 u32 __iomem
*dlist_start
= vc4
->hvs
->dlist
+ vc4_state
->mm
.start
;
653 u32 __iomem
*dlist_next
= dlist_start
;
655 if (debug_dump_regs
) {
656 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc
));
657 vc4_hvs_dump_state(dev
);
660 /* Copy all the active planes' dlist contents to the hardware dlist. */
661 drm_atomic_crtc_for_each_plane(plane
, crtc
) {
662 /* Is this the first active plane? */
663 if (dlist_next
== dlist_start
) {
664 /* We need to enable background fill when a plane
665 * could be alpha blending from the background, i.e.
666 * where no other plane is underneath. It suffices to
667 * consider the first active plane here since we set
668 * needs_bg_fill such that either the first plane
669 * already needs it or all planes on top blend from
670 * the first or a lower plane.
672 vc4_plane_state
= to_vc4_plane_state(plane
->state
);
673 enable_bg_fill
= vc4_plane_state
->needs_bg_fill
;
676 dlist_next
+= vc4_plane_write_dlist(plane
, dlist_next
);
679 writel(SCALER_CTL0_END
, dlist_next
);
682 WARN_ON_ONCE(dlist_next
- dlist_start
!= vc4_state
->mm
.size
);
685 /* This sets a black background color fill, as is the case
686 * with other DRM drivers.
688 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc
->channel
),
689 HVS_READ(SCALER_DISPBKGNDX(vc4_crtc
->channel
)) |
690 SCALER_DISPBKGND_FILL
);
692 /* Only update DISPLIST if the CRTC was already running and is not
694 * vc4_crtc_enable() takes care of updating the dlist just after
695 * re-enabling VBLANK interrupts and before enabling the engine.
696 * If the CRTC is being disabled, there's no point in updating this
699 if (crtc
->state
->active
&& old_state
->active
)
700 vc4_crtc_update_dlist(crtc
);
702 if (debug_dump_regs
) {
703 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc
));
704 vc4_hvs_dump_state(dev
);
708 static int vc4_enable_vblank(struct drm_crtc
*crtc
)
710 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
712 CRTC_WRITE(PV_INTEN
, PV_INT_VFP_START
);
717 static void vc4_disable_vblank(struct drm_crtc
*crtc
)
719 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
721 CRTC_WRITE(PV_INTEN
, 0);
724 static void vc4_crtc_handle_page_flip(struct vc4_crtc
*vc4_crtc
)
726 struct drm_crtc
*crtc
= &vc4_crtc
->base
;
727 struct drm_device
*dev
= crtc
->dev
;
728 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
729 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(crtc
->state
);
730 u32 chan
= vc4_crtc
->channel
;
733 spin_lock_irqsave(&dev
->event_lock
, flags
);
734 if (vc4_crtc
->event
&&
735 (vc4_state
->mm
.start
== HVS_READ(SCALER_DISPLACTX(chan
)))) {
736 drm_crtc_send_vblank_event(crtc
, vc4_crtc
->event
);
737 vc4_crtc
->event
= NULL
;
738 drm_crtc_vblank_put(crtc
);
740 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
743 static irqreturn_t
vc4_crtc_irq_handler(int irq
, void *data
)
745 struct vc4_crtc
*vc4_crtc
= data
;
746 u32 stat
= CRTC_READ(PV_INTSTAT
);
747 irqreturn_t ret
= IRQ_NONE
;
749 if (stat
& PV_INT_VFP_START
) {
750 vc4_crtc
->t_vblank
= ktime_get();
751 CRTC_WRITE(PV_INTSTAT
, PV_INT_VFP_START
);
752 drm_crtc_handle_vblank(&vc4_crtc
->base
);
753 vc4_crtc_handle_page_flip(vc4_crtc
);
760 struct vc4_async_flip_state
{
761 struct drm_crtc
*crtc
;
762 struct drm_framebuffer
*fb
;
763 struct drm_framebuffer
*old_fb
;
764 struct drm_pending_vblank_event
*event
;
766 struct vc4_seqno_cb cb
;
769 /* Called when the V3D execution for the BO being flipped to is done, so that
770 * we can actually update the plane's address to point to it.
773 vc4_async_page_flip_complete(struct vc4_seqno_cb
*cb
)
775 struct vc4_async_flip_state
*flip_state
=
776 container_of(cb
, struct vc4_async_flip_state
, cb
);
777 struct drm_crtc
*crtc
= flip_state
->crtc
;
778 struct drm_device
*dev
= crtc
->dev
;
779 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
780 struct drm_plane
*plane
= crtc
->primary
;
782 vc4_plane_async_set_fb(plane
, flip_state
->fb
);
783 if (flip_state
->event
) {
786 spin_lock_irqsave(&dev
->event_lock
, flags
);
787 drm_crtc_send_vblank_event(crtc
, flip_state
->event
);
788 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
791 drm_crtc_vblank_put(crtc
);
792 drm_framebuffer_put(flip_state
->fb
);
794 /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
795 * when the planes are updated through the async update path.
796 * FIXME: we should move to generic async-page-flip when it's
797 * available, so that we can get rid of this hand-made cleanup_fb()
800 if (flip_state
->old_fb
) {
801 struct drm_gem_cma_object
*cma_bo
;
804 cma_bo
= drm_fb_cma_get_gem_obj(flip_state
->old_fb
, 0);
805 bo
= to_vc4_bo(&cma_bo
->base
);
806 vc4_bo_dec_usecnt(bo
);
807 drm_framebuffer_put(flip_state
->old_fb
);
812 up(&vc4
->async_modeset
);
815 /* Implements async (non-vblank-synced) page flips.
817 * The page flip ioctl needs to return immediately, so we grab the
818 * modeset semaphore on the pipe, and queue the address update for
819 * when V3D is done with the BO being flipped to.
821 static int vc4_async_page_flip(struct drm_crtc
*crtc
,
822 struct drm_framebuffer
*fb
,
823 struct drm_pending_vblank_event
*event
,
826 struct drm_device
*dev
= crtc
->dev
;
827 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
828 struct drm_plane
*plane
= crtc
->primary
;
830 struct vc4_async_flip_state
*flip_state
;
831 struct drm_gem_cma_object
*cma_bo
= drm_fb_cma_get_gem_obj(fb
, 0);
832 struct vc4_bo
*bo
= to_vc4_bo(&cma_bo
->base
);
834 /* Increment the BO usecnt here, so that we never end up with an
835 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
836 * plane is later updated through the non-async path.
837 * FIXME: we should move to generic async-page-flip when it's
838 * available, so that we can get rid of this hand-made prepare_fb()
841 ret
= vc4_bo_inc_usecnt(bo
);
845 flip_state
= kzalloc(sizeof(*flip_state
), GFP_KERNEL
);
847 vc4_bo_dec_usecnt(bo
);
851 drm_framebuffer_get(fb
);
853 flip_state
->crtc
= crtc
;
854 flip_state
->event
= event
;
856 /* Make sure all other async modesetes have landed. */
857 ret
= down_interruptible(&vc4
->async_modeset
);
859 drm_framebuffer_put(fb
);
860 vc4_bo_dec_usecnt(bo
);
865 /* Save the current FB before it's replaced by the new one in
866 * drm_atomic_set_fb_for_plane(). We'll need the old FB in
867 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
869 * FIXME: we should move to generic async-page-flip when it's
870 * available, so that we can get rid of this hand-made cleanup_fb()
873 flip_state
->old_fb
= plane
->state
->fb
;
874 if (flip_state
->old_fb
)
875 drm_framebuffer_get(flip_state
->old_fb
);
877 WARN_ON(drm_crtc_vblank_get(crtc
) != 0);
879 /* Immediately update the plane's legacy fb pointer, so that later
880 * modeset prep sees the state that will be present when the semaphore
883 drm_atomic_set_fb_for_plane(plane
->state
, fb
);
886 vc4_queue_seqno_cb(dev
, &flip_state
->cb
, bo
->seqno
,
887 vc4_async_page_flip_complete
);
889 /* Driver takes ownership of state on successful async commit. */
893 static int vc4_page_flip(struct drm_crtc
*crtc
,
894 struct drm_framebuffer
*fb
,
895 struct drm_pending_vblank_event
*event
,
897 struct drm_modeset_acquire_ctx
*ctx
)
899 if (flags
& DRM_MODE_PAGE_FLIP_ASYNC
)
900 return vc4_async_page_flip(crtc
, fb
, event
, flags
);
902 return drm_atomic_helper_page_flip(crtc
, fb
, event
, flags
, ctx
);
905 static struct drm_crtc_state
*vc4_crtc_duplicate_state(struct drm_crtc
*crtc
)
907 struct vc4_crtc_state
*vc4_state
;
909 vc4_state
= kzalloc(sizeof(*vc4_state
), GFP_KERNEL
);
913 __drm_atomic_helper_crtc_duplicate_state(crtc
, &vc4_state
->base
);
914 return &vc4_state
->base
;
917 static void vc4_crtc_destroy_state(struct drm_crtc
*crtc
,
918 struct drm_crtc_state
*state
)
920 struct vc4_dev
*vc4
= to_vc4_dev(crtc
->dev
);
921 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(state
);
923 if (vc4_state
->mm
.allocated
) {
926 spin_lock_irqsave(&vc4
->hvs
->mm_lock
, flags
);
927 drm_mm_remove_node(&vc4_state
->mm
);
928 spin_unlock_irqrestore(&vc4
->hvs
->mm_lock
, flags
);
932 drm_atomic_helper_crtc_destroy_state(crtc
, state
);
936 vc4_crtc_reset(struct drm_crtc
*crtc
)
939 __drm_atomic_helper_crtc_destroy_state(crtc
->state
);
941 crtc
->state
= kzalloc(sizeof(struct vc4_crtc_state
), GFP_KERNEL
);
943 crtc
->state
->crtc
= crtc
;
946 static const struct drm_crtc_funcs vc4_crtc_funcs
= {
947 .set_config
= drm_atomic_helper_set_config
,
948 .destroy
= vc4_crtc_destroy
,
949 .page_flip
= vc4_page_flip
,
950 .set_property
= NULL
,
951 .cursor_set
= NULL
, /* handled by drm_mode_cursor_universal */
952 .cursor_move
= NULL
, /* handled by drm_mode_cursor_universal */
953 .reset
= vc4_crtc_reset
,
954 .atomic_duplicate_state
= vc4_crtc_duplicate_state
,
955 .atomic_destroy_state
= vc4_crtc_destroy_state
,
956 .gamma_set
= vc4_crtc_gamma_set
,
957 .enable_vblank
= vc4_enable_vblank
,
958 .disable_vblank
= vc4_disable_vblank
,
961 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs
= {
962 .mode_set_nofb
= vc4_crtc_mode_set_nofb
,
963 .mode_valid
= vc4_crtc_mode_valid
,
964 .atomic_check
= vc4_crtc_atomic_check
,
965 .atomic_flush
= vc4_crtc_atomic_flush
,
966 .atomic_enable
= vc4_crtc_atomic_enable
,
967 .atomic_disable
= vc4_crtc_atomic_disable
,
970 static const struct vc4_crtc_data pv0_data
= {
973 [PV_CONTROL_CLK_SELECT_DSI
] = VC4_ENCODER_TYPE_DSI0
,
974 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI
] = VC4_ENCODER_TYPE_DPI
,
978 static const struct vc4_crtc_data pv1_data
= {
981 [PV_CONTROL_CLK_SELECT_DSI
] = VC4_ENCODER_TYPE_DSI1
,
982 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI
] = VC4_ENCODER_TYPE_SMI
,
986 static const struct vc4_crtc_data pv2_data
= {
989 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI
] = VC4_ENCODER_TYPE_HDMI
,
990 [PV_CONTROL_CLK_SELECT_VEC
] = VC4_ENCODER_TYPE_VEC
,
994 static const struct of_device_id vc4_crtc_dt_match
[] = {
995 { .compatible
= "brcm,bcm2835-pixelvalve0", .data
= &pv0_data
},
996 { .compatible
= "brcm,bcm2835-pixelvalve1", .data
= &pv1_data
},
997 { .compatible
= "brcm,bcm2835-pixelvalve2", .data
= &pv2_data
},
1001 static void vc4_set_crtc_possible_masks(struct drm_device
*drm
,
1002 struct drm_crtc
*crtc
)
1004 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
1005 const struct vc4_crtc_data
*crtc_data
= vc4_crtc
->data
;
1006 const enum vc4_encoder_type
*encoder_types
= crtc_data
->encoder_types
;
1007 struct drm_encoder
*encoder
;
1009 drm_for_each_encoder(encoder
, drm
) {
1010 struct vc4_encoder
*vc4_encoder
= to_vc4_encoder(encoder
);
1013 for (i
= 0; i
< ARRAY_SIZE(crtc_data
->encoder_types
); i
++) {
1014 if (vc4_encoder
->type
== encoder_types
[i
]) {
1015 vc4_encoder
->clock_select
= i
;
1016 encoder
->possible_crtcs
|= drm_crtc_mask(crtc
);
1024 vc4_crtc_get_cob_allocation(struct vc4_crtc
*vc4_crtc
)
1026 struct drm_device
*drm
= vc4_crtc
->base
.dev
;
1027 struct vc4_dev
*vc4
= to_vc4_dev(drm
);
1028 u32 dispbase
= HVS_READ(SCALER_DISPBASEX(vc4_crtc
->channel
));
1029 /* Top/base are supposed to be 4-pixel aligned, but the
1030 * Raspberry Pi firmware fills the low bits (which are
1031 * presumably ignored).
1033 u32 top
= VC4_GET_FIELD(dispbase
, SCALER_DISPBASEX_TOP
) & ~3;
1034 u32 base
= VC4_GET_FIELD(dispbase
, SCALER_DISPBASEX_BASE
) & ~3;
1036 vc4_crtc
->cob_size
= top
- base
+ 4;
1039 static int vc4_crtc_bind(struct device
*dev
, struct device
*master
, void *data
)
1041 struct platform_device
*pdev
= to_platform_device(dev
);
1042 struct drm_device
*drm
= dev_get_drvdata(master
);
1043 struct vc4_crtc
*vc4_crtc
;
1044 struct drm_crtc
*crtc
;
1045 struct drm_plane
*primary_plane
, *cursor_plane
, *destroy_plane
, *temp
;
1046 const struct of_device_id
*match
;
1049 vc4_crtc
= devm_kzalloc(dev
, sizeof(*vc4_crtc
), GFP_KERNEL
);
1052 crtc
= &vc4_crtc
->base
;
1054 match
= of_match_device(vc4_crtc_dt_match
, dev
);
1057 vc4_crtc
->data
= match
->data
;
1059 vc4_crtc
->regs
= vc4_ioremap_regs(pdev
, 0);
1060 if (IS_ERR(vc4_crtc
->regs
))
1061 return PTR_ERR(vc4_crtc
->regs
);
1063 /* For now, we create just the primary and the legacy cursor
1064 * planes. We should be able to stack more planes on easily,
1065 * but to do that we would need to compute the bandwidth
1066 * requirement of the plane configuration, and reject ones
1067 * that will take too much.
1069 primary_plane
= vc4_plane_init(drm
, DRM_PLANE_TYPE_PRIMARY
);
1070 if (IS_ERR(primary_plane
)) {
1071 dev_err(dev
, "failed to construct primary plane\n");
1072 ret
= PTR_ERR(primary_plane
);
1076 drm_crtc_init_with_planes(drm
, crtc
, primary_plane
, NULL
,
1077 &vc4_crtc_funcs
, NULL
);
1078 drm_crtc_helper_add(crtc
, &vc4_crtc_helper_funcs
);
1079 primary_plane
->crtc
= crtc
;
1080 vc4_crtc
->channel
= vc4_crtc
->data
->hvs_channel
;
1081 drm_mode_crtc_set_gamma_size(crtc
, ARRAY_SIZE(vc4_crtc
->lut_r
));
1083 /* Set up some arbitrary number of planes. We're not limited
1084 * by a set number of physical registers, just the space in
1085 * the HVS (16k) and how small an plane can be (28 bytes).
1086 * However, each plane we set up takes up some memory, and
1087 * increases the cost of looping over planes, which atomic
1088 * modesetting does quite a bit. As a result, we pick a
1089 * modest number of planes to expose, that should hopefully
1090 * still cover any sane usecase.
1092 for (i
= 0; i
< 8; i
++) {
1093 struct drm_plane
*plane
=
1094 vc4_plane_init(drm
, DRM_PLANE_TYPE_OVERLAY
);
1099 plane
->possible_crtcs
= 1 << drm_crtc_index(crtc
);
1102 /* Set up the legacy cursor after overlay initialization,
1103 * since we overlay planes on the CRTC in the order they were
1106 cursor_plane
= vc4_plane_init(drm
, DRM_PLANE_TYPE_CURSOR
);
1107 if (!IS_ERR(cursor_plane
)) {
1108 cursor_plane
->possible_crtcs
= 1 << drm_crtc_index(crtc
);
1109 cursor_plane
->crtc
= crtc
;
1110 crtc
->cursor
= cursor_plane
;
1113 vc4_crtc_get_cob_allocation(vc4_crtc
);
1115 CRTC_WRITE(PV_INTEN
, 0);
1116 CRTC_WRITE(PV_INTSTAT
, PV_INT_VFP_START
);
1117 ret
= devm_request_irq(dev
, platform_get_irq(pdev
, 0),
1118 vc4_crtc_irq_handler
, 0, "vc4 crtc", vc4_crtc
);
1120 goto err_destroy_planes
;
1122 vc4_set_crtc_possible_masks(drm
, crtc
);
1124 for (i
= 0; i
< crtc
->gamma_size
; i
++) {
1125 vc4_crtc
->lut_r
[i
] = i
;
1126 vc4_crtc
->lut_g
[i
] = i
;
1127 vc4_crtc
->lut_b
[i
] = i
;
1130 platform_set_drvdata(pdev
, vc4_crtc
);
1135 list_for_each_entry_safe(destroy_plane
, temp
,
1136 &drm
->mode_config
.plane_list
, head
) {
1137 if (destroy_plane
->possible_crtcs
== 1 << drm_crtc_index(crtc
))
1138 destroy_plane
->funcs
->destroy(destroy_plane
);
1144 static void vc4_crtc_unbind(struct device
*dev
, struct device
*master
,
1147 struct platform_device
*pdev
= to_platform_device(dev
);
1148 struct vc4_crtc
*vc4_crtc
= dev_get_drvdata(dev
);
1150 vc4_crtc_destroy(&vc4_crtc
->base
);
1152 CRTC_WRITE(PV_INTEN
, 0);
1154 platform_set_drvdata(pdev
, NULL
);
1157 static const struct component_ops vc4_crtc_ops
= {
1158 .bind
= vc4_crtc_bind
,
1159 .unbind
= vc4_crtc_unbind
,
1162 static int vc4_crtc_dev_probe(struct platform_device
*pdev
)
1164 return component_add(&pdev
->dev
, &vc4_crtc_ops
);
1167 static int vc4_crtc_dev_remove(struct platform_device
*pdev
)
1169 component_del(&pdev
->dev
, &vc4_crtc_ops
);
1173 struct platform_driver vc4_crtc_driver
= {
1174 .probe
= vc4_crtc_dev_probe
,
1175 .remove
= vc4_crtc_dev_remove
,
1178 .of_match_table
= vc4_crtc_dt_match
,