2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * DOC: VC4 CRTC module
12 * In VC4, the Pixel Valve is what most closely corresponds to the
13 * DRM's concept of a CRTC. The PV generates video timings from the
14 * encoder's clock plus its configuration. It pulls scaled pixels from
15 * the HVS at that timing, and feeds it to the encoder.
17 * However, the DRM CRTC also collects the configuration of all the
18 * DRM planes attached to it. As a result, the CRTC is also
19 * responsible for writing the display list for the HVS channel that
22 * The 2835 has 3 different pixel valves. pv0 in the audio power
23 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
24 * image domain can feed either HDMI or the SDTV controller. The
25 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
26 * SDTV, etc.) according to which output type is chosen in the mux.
28 * For power management, the pixel valve's registers are all clocked
29 * by the AXI clock, while the timings and FIFOs make use of the
30 * output-specific clock. Since the encoders also directly consume
31 * the CPRMAN clocks, and know what timings they need, they are the
32 * ones that set the clock.
35 #include "drm_atomic.h"
36 #include "drm_atomic_helper.h"
37 #include "drm_crtc_helper.h"
38 #include "linux/clk.h"
39 #include "drm_fb_cma_helper.h"
40 #include "linux/component.h"
41 #include "linux/of_device.h"
47 const struct vc4_crtc_data
*data
;
50 /* Timestamp at start of vblank irq - unaffected by lock delays. */
53 /* Which HVS channel we're using for our CRTC. */
59 /* Size in pixels of the COB memory allocated to this CRTC. */
62 struct drm_pending_vblank_event
*event
;
65 struct vc4_crtc_state
{
66 struct drm_crtc_state base
;
67 /* Dlist area for this CRTC configuration. */
68 struct drm_mm_node mm
;
71 static inline struct vc4_crtc
*
72 to_vc4_crtc(struct drm_crtc
*crtc
)
74 return (struct vc4_crtc
*)crtc
;
77 static inline struct vc4_crtc_state
*
78 to_vc4_crtc_state(struct drm_crtc_state
*crtc_state
)
80 return (struct vc4_crtc_state
*)crtc_state
;
83 struct vc4_crtc_data
{
84 /* Which channel of the HVS this pixelvalve sources from. */
87 enum vc4_encoder_type encoder_types
[4];
90 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
91 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
93 #define CRTC_REG(reg) { reg, #reg }
99 CRTC_REG(PV_V_CONTROL
),
100 CRTC_REG(PV_VSYNCD_EVEN
),
105 CRTC_REG(PV_VERTA_EVEN
),
106 CRTC_REG(PV_VERTB_EVEN
),
108 CRTC_REG(PV_INTSTAT
),
110 CRTC_REG(PV_HACT_ACT
),
113 static void vc4_crtc_dump_regs(struct vc4_crtc
*vc4_crtc
)
117 for (i
= 0; i
< ARRAY_SIZE(crtc_regs
); i
++) {
118 DRM_INFO("0x%04x (%s): 0x%08x\n",
119 crtc_regs
[i
].reg
, crtc_regs
[i
].name
,
120 CRTC_READ(crtc_regs
[i
].reg
));
124 #ifdef CONFIG_DEBUG_FS
125 int vc4_crtc_debugfs_regs(struct seq_file
*m
, void *unused
)
127 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
128 struct drm_device
*dev
= node
->minor
->dev
;
129 int crtc_index
= (uintptr_t)node
->info_ent
->data
;
130 struct drm_crtc
*crtc
;
131 struct vc4_crtc
*vc4_crtc
;
135 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
142 vc4_crtc
= to_vc4_crtc(crtc
);
144 for (i
= 0; i
< ARRAY_SIZE(crtc_regs
); i
++) {
145 seq_printf(m
, "%s (0x%04x): 0x%08x\n",
146 crtc_regs
[i
].name
, crtc_regs
[i
].reg
,
147 CRTC_READ(crtc_regs
[i
].reg
));
154 int vc4_crtc_get_scanoutpos(struct drm_device
*dev
, unsigned int crtc_id
,
155 unsigned int flags
, int *vpos
, int *hpos
,
156 ktime_t
*stime
, ktime_t
*etime
,
157 const struct drm_display_mode
*mode
)
159 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
160 struct drm_crtc
*crtc
= drm_crtc_from_index(dev
, crtc_id
);
161 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
167 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
169 /* Get optional system timestamp before query. */
171 *stime
= ktime_get();
174 * Read vertical scanline which is currently composed for our
175 * pixelvalve by the HVS, and also the scaler status.
177 val
= HVS_READ(SCALER_DISPSTATX(vc4_crtc
->channel
));
179 /* Get optional system timestamp after query. */
181 *etime
= ktime_get();
183 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
185 /* Vertical position of hvs composed scanline. */
186 *vpos
= VC4_GET_FIELD(val
, SCALER_DISPSTATX_LINE
);
189 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
192 /* Use hpos to correct for field offset in interlaced mode. */
193 if (VC4_GET_FIELD(val
, SCALER_DISPSTATX_FRAME_COUNT
) % 2)
194 *hpos
+= mode
->crtc_htotal
/ 2;
197 /* This is the offset we need for translating hvs -> pv scanout pos. */
198 fifo_lines
= vc4_crtc
->cob_size
/ mode
->crtc_hdisplay
;
201 ret
|= DRM_SCANOUTPOS_VALID
;
203 /* HVS more than fifo_lines into frame for compositing? */
204 if (*vpos
> fifo_lines
) {
206 * We are in active scanout and can get some meaningful results
207 * from HVS. The actual PV scanout can not trail behind more
208 * than fifo_lines as that is the fifo's capacity. Assume that
209 * in active scanout the HVS and PV work in lockstep wrt. HVS
210 * refilling the fifo and PV consuming from the fifo, ie.
211 * whenever the PV consumes and frees up a scanline in the
212 * fifo, the HVS will immediately refill it, therefore
213 * incrementing vpos. Therefore we choose HVS read position -
214 * fifo size in scanlines as a estimate of the real scanout
215 * position of the PV.
217 *vpos
-= fifo_lines
+ 1;
219 ret
|= DRM_SCANOUTPOS_ACCURATE
;
224 * Less: This happens when we are in vblank and the HVS, after getting
225 * the VSTART restart signal from the PV, just started refilling its
226 * fifo with new lines from the top-most lines of the new framebuffers.
227 * The PV does not scan out in vblank, so does not remove lines from
228 * the fifo, so the fifo will be full quickly and the HVS has to pause.
229 * We can't get meaningful readings wrt. scanline position of the PV
230 * and need to make things up in a approximative but consistent way.
232 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
233 vblank_lines
= mode
->vtotal
- mode
->vdisplay
;
235 if (flags
& DRM_CALLED_FROM_VBLIRQ
) {
237 * Assume the irq handler got called close to first
238 * line of vblank, so PV has about a full vblank
239 * scanlines to go, and as a base timestamp use the
240 * one taken at entry into vblank irq handler, so it
241 * is not affected by random delays due to lock
242 * contention on event_lock or vblank_time lock in
245 *vpos
= -vblank_lines
;
248 *stime
= vc4_crtc
->t_vblank
;
250 *etime
= vc4_crtc
->t_vblank
;
253 * If the HVS fifo is not yet full then we know for certain
254 * we are at the very beginning of vblank, as the hvs just
255 * started refilling, and the stime and etime timestamps
256 * truly correspond to start of vblank.
258 if ((val
& SCALER_DISPSTATX_FULL
) != SCALER_DISPSTATX_FULL
)
259 ret
|= DRM_SCANOUTPOS_ACCURATE
;
262 * No clue where we are inside vblank. Return a vpos of zero,
263 * which will cause calling code to just return the etime
264 * timestamp uncorrected. At least this is no worse than the
273 int vc4_crtc_get_vblank_timestamp(struct drm_device
*dev
, unsigned int crtc_id
,
274 int *max_error
, struct timeval
*vblank_time
,
277 struct drm_crtc
*crtc
= drm_crtc_from_index(dev
, crtc_id
);
278 struct drm_crtc_state
*state
= crtc
->state
;
280 /* Helper routine in DRM core does all the work: */
281 return drm_calc_vbltimestamp_from_scanoutpos(dev
, crtc_id
, max_error
,
283 &state
->adjusted_mode
);
286 static void vc4_crtc_destroy(struct drm_crtc
*crtc
)
288 drm_crtc_cleanup(crtc
);
292 vc4_crtc_lut_load(struct drm_crtc
*crtc
)
294 struct drm_device
*dev
= crtc
->dev
;
295 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
296 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
299 /* The LUT memory is laid out with each HVS channel in order,
300 * each of which takes 256 writes for R, 256 for G, then 256
303 HVS_WRITE(SCALER_GAMADDR
,
304 SCALER_GAMADDR_AUTOINC
|
305 (vc4_crtc
->channel
* 3 * crtc
->gamma_size
));
307 for (i
= 0; i
< crtc
->gamma_size
; i
++)
308 HVS_WRITE(SCALER_GAMDATA
, vc4_crtc
->lut_r
[i
]);
309 for (i
= 0; i
< crtc
->gamma_size
; i
++)
310 HVS_WRITE(SCALER_GAMDATA
, vc4_crtc
->lut_g
[i
]);
311 for (i
= 0; i
< crtc
->gamma_size
; i
++)
312 HVS_WRITE(SCALER_GAMDATA
, vc4_crtc
->lut_b
[i
]);
316 vc4_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*r
, u16
*g
, u16
*b
,
318 struct drm_modeset_acquire_ctx
*ctx
)
320 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
323 for (i
= 0; i
< size
; i
++) {
324 vc4_crtc
->lut_r
[i
] = r
[i
] >> 8;
325 vc4_crtc
->lut_g
[i
] = g
[i
] >> 8;
326 vc4_crtc
->lut_b
[i
] = b
[i
] >> 8;
329 vc4_crtc_lut_load(crtc
);
334 static u32
vc4_get_fifo_full_level(u32 format
)
336 static const u32 fifo_len_bytes
= 64;
337 static const u32 hvs_latency_pix
= 6;
340 case PV_CONTROL_FORMAT_DSIV_16
:
341 case PV_CONTROL_FORMAT_DSIC_16
:
342 return fifo_len_bytes
- 2 * hvs_latency_pix
;
343 case PV_CONTROL_FORMAT_DSIV_18
:
344 return fifo_len_bytes
- 14;
345 case PV_CONTROL_FORMAT_24
:
346 case PV_CONTROL_FORMAT_DSIV_24
:
348 return fifo_len_bytes
- 3 * hvs_latency_pix
;
353 * Returns the encoder attached to the CRTC.
355 * VC4 can only scan out to one encoder at a time, while the DRM core
356 * allows drivers to push pixels to more than one encoder from the
359 static struct drm_encoder
*vc4_get_crtc_encoder(struct drm_crtc
*crtc
)
361 struct drm_connector
*connector
;
363 drm_for_each_connector(connector
, crtc
->dev
) {
364 if (connector
->state
->crtc
== crtc
) {
365 return connector
->encoder
;
372 static void vc4_crtc_mode_set_nofb(struct drm_crtc
*crtc
)
374 struct drm_device
*dev
= crtc
->dev
;
375 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
376 struct drm_encoder
*encoder
= vc4_get_crtc_encoder(crtc
);
377 struct vc4_encoder
*vc4_encoder
= to_vc4_encoder(encoder
);
378 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
379 struct drm_crtc_state
*state
= crtc
->state
;
380 struct drm_display_mode
*mode
= &state
->adjusted_mode
;
381 bool interlace
= mode
->flags
& DRM_MODE_FLAG_INTERLACE
;
382 u32 pixel_rep
= (mode
->flags
& DRM_MODE_FLAG_DBLCLK
) ? 2 : 1;
383 bool is_dsi
= (vc4_encoder
->type
== VC4_ENCODER_TYPE_DSI0
||
384 vc4_encoder
->type
== VC4_ENCODER_TYPE_DSI1
);
385 u32 format
= is_dsi
? PV_CONTROL_FORMAT_DSIV_24
: PV_CONTROL_FORMAT_24
;
386 bool debug_dump_regs
= false;
388 if (debug_dump_regs
) {
389 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc
));
390 vc4_crtc_dump_regs(vc4_crtc
);
393 /* Reset the PV fifo. */
394 CRTC_WRITE(PV_CONTROL
, 0);
395 CRTC_WRITE(PV_CONTROL
, PV_CONTROL_FIFO_CLR
| PV_CONTROL_EN
);
396 CRTC_WRITE(PV_CONTROL
, 0);
399 VC4_SET_FIELD((mode
->htotal
-
400 mode
->hsync_end
) * pixel_rep
,
402 VC4_SET_FIELD((mode
->hsync_end
-
403 mode
->hsync_start
) * pixel_rep
,
406 VC4_SET_FIELD((mode
->hsync_start
-
407 mode
->hdisplay
) * pixel_rep
,
409 VC4_SET_FIELD(mode
->hdisplay
* pixel_rep
, PV_HORZB_HACTIVE
));
412 VC4_SET_FIELD(mode
->crtc_vtotal
- mode
->crtc_vsync_end
,
414 VC4_SET_FIELD(mode
->crtc_vsync_end
- mode
->crtc_vsync_start
,
417 VC4_SET_FIELD(mode
->crtc_vsync_start
- mode
->crtc_vdisplay
,
419 VC4_SET_FIELD(mode
->crtc_vdisplay
, PV_VERTB_VACTIVE
));
422 CRTC_WRITE(PV_VERTA_EVEN
,
423 VC4_SET_FIELD(mode
->crtc_vtotal
-
424 mode
->crtc_vsync_end
- 1,
426 VC4_SET_FIELD(mode
->crtc_vsync_end
-
427 mode
->crtc_vsync_start
,
429 CRTC_WRITE(PV_VERTB_EVEN
,
430 VC4_SET_FIELD(mode
->crtc_vsync_start
-
433 VC4_SET_FIELD(mode
->crtc_vdisplay
, PV_VERTB_VACTIVE
));
435 /* We set up first field even mode for HDMI. VEC's
436 * NTSC mode would want first field odd instead, once
437 * we support it (to do so, set ODD_FIRST and put the
438 * delay in VSYNCD_EVEN instead).
440 CRTC_WRITE(PV_V_CONTROL
,
441 PV_VCONTROL_CONTINUOUS
|
442 (is_dsi
? PV_VCONTROL_DSI
: 0) |
443 PV_VCONTROL_INTERLACE
|
444 VC4_SET_FIELD(mode
->htotal
* pixel_rep
/ 2,
445 PV_VCONTROL_ODD_DELAY
));
446 CRTC_WRITE(PV_VSYNCD_EVEN
, 0);
448 CRTC_WRITE(PV_V_CONTROL
,
449 PV_VCONTROL_CONTINUOUS
|
450 (is_dsi
? PV_VCONTROL_DSI
: 0));
453 CRTC_WRITE(PV_HACT_ACT
, mode
->hdisplay
* pixel_rep
);
455 CRTC_WRITE(PV_CONTROL
,
456 VC4_SET_FIELD(format
, PV_CONTROL_FORMAT
) |
457 VC4_SET_FIELD(vc4_get_fifo_full_level(format
),
458 PV_CONTROL_FIFO_LEVEL
) |
459 VC4_SET_FIELD(pixel_rep
- 1, PV_CONTROL_PIXEL_REP
) |
460 PV_CONTROL_CLR_AT_START
|
461 PV_CONTROL_TRIGGER_UNDERFLOW
|
462 PV_CONTROL_WAIT_HSTART
|
463 VC4_SET_FIELD(vc4_encoder
->clock_select
,
464 PV_CONTROL_CLK_SELECT
) |
465 PV_CONTROL_FIFO_CLR
|
468 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc
->channel
),
469 SCALER_DISPBKGND_AUTOHS
|
470 SCALER_DISPBKGND_GAMMA
|
471 (interlace
? SCALER_DISPBKGND_INTERLACE
: 0));
473 /* Reload the LUT, since the SRAMs would have been disabled if
474 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
476 vc4_crtc_lut_load(crtc
);
478 if (debug_dump_regs
) {
479 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc
));
480 vc4_crtc_dump_regs(vc4_crtc
);
484 static void require_hvs_enabled(struct drm_device
*dev
)
486 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
488 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL
) & SCALER_DISPCTRL_ENABLE
) !=
489 SCALER_DISPCTRL_ENABLE
);
492 static void vc4_crtc_disable(struct drm_crtc
*crtc
)
494 struct drm_device
*dev
= crtc
->dev
;
495 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
496 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
497 u32 chan
= vc4_crtc
->channel
;
499 require_hvs_enabled(dev
);
501 /* Disable vblank irq handling before crtc is disabled. */
502 drm_crtc_vblank_off(crtc
);
504 CRTC_WRITE(PV_V_CONTROL
,
505 CRTC_READ(PV_V_CONTROL
) & ~PV_VCONTROL_VIDEN
);
506 ret
= wait_for(!(CRTC_READ(PV_V_CONTROL
) & PV_VCONTROL_VIDEN
), 1);
507 WARN_ONCE(ret
, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
509 if (HVS_READ(SCALER_DISPCTRLX(chan
)) &
510 SCALER_DISPCTRLX_ENABLE
) {
511 HVS_WRITE(SCALER_DISPCTRLX(chan
),
512 SCALER_DISPCTRLX_RESET
);
514 /* While the docs say that reset is self-clearing, it
515 * seems it doesn't actually.
517 HVS_WRITE(SCALER_DISPCTRLX(chan
), 0);
520 /* Once we leave, the scaler should be disabled and its fifo empty. */
522 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan
)) & SCALER_DISPCTRLX_RESET
);
524 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan
)),
525 SCALER_DISPSTATX_MODE
) !=
526 SCALER_DISPSTATX_MODE_DISABLED
);
528 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan
)) &
529 (SCALER_DISPSTATX_FULL
| SCALER_DISPSTATX_EMPTY
)) !=
530 SCALER_DISPSTATX_EMPTY
);
533 static void vc4_crtc_enable(struct drm_crtc
*crtc
)
535 struct drm_device
*dev
= crtc
->dev
;
536 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
537 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
538 struct drm_crtc_state
*state
= crtc
->state
;
539 struct drm_display_mode
*mode
= &state
->adjusted_mode
;
541 require_hvs_enabled(dev
);
543 /* Turn on the scaler, which will wait for vstart to start
546 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc
->channel
),
547 VC4_SET_FIELD(mode
->hdisplay
, SCALER_DISPCTRLX_WIDTH
) |
548 VC4_SET_FIELD(mode
->vdisplay
, SCALER_DISPCTRLX_HEIGHT
) |
549 SCALER_DISPCTRLX_ENABLE
);
551 /* Turn on the pixel valve, which will emit the vstart signal. */
552 CRTC_WRITE(PV_V_CONTROL
,
553 CRTC_READ(PV_V_CONTROL
) | PV_VCONTROL_VIDEN
);
555 /* Enable vblank irq handling after crtc is started. */
556 drm_crtc_vblank_on(crtc
);
559 static bool vc4_crtc_mode_fixup(struct drm_crtc
*crtc
,
560 const struct drm_display_mode
*mode
,
561 struct drm_display_mode
*adjusted_mode
)
563 /* Do not allow doublescan modes from user space */
564 if (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
) {
565 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
573 static int vc4_crtc_atomic_check(struct drm_crtc
*crtc
,
574 struct drm_crtc_state
*state
)
576 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(state
);
577 struct drm_device
*dev
= crtc
->dev
;
578 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
579 struct drm_plane
*plane
;
581 const struct drm_plane_state
*plane_state
;
585 /* The pixelvalve can only feed one encoder (and encoders are
586 * 1:1 with connectors.)
588 if (hweight32(state
->connector_mask
) > 1)
591 drm_atomic_crtc_state_for_each_plane_state(plane
, plane_state
, state
)
592 dlist_count
+= vc4_plane_dlist_size(plane_state
);
594 dlist_count
++; /* Account for SCALER_CTL0_END. */
596 spin_lock_irqsave(&vc4
->hvs
->mm_lock
, flags
);
597 ret
= drm_mm_insert_node(&vc4
->hvs
->dlist_mm
, &vc4_state
->mm
,
599 spin_unlock_irqrestore(&vc4
->hvs
->mm_lock
, flags
);
606 static void vc4_crtc_atomic_flush(struct drm_crtc
*crtc
,
607 struct drm_crtc_state
*old_state
)
609 struct drm_device
*dev
= crtc
->dev
;
610 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
611 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
612 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(crtc
->state
);
613 struct drm_plane
*plane
;
614 bool debug_dump_regs
= false;
615 u32 __iomem
*dlist_start
= vc4
->hvs
->dlist
+ vc4_state
->mm
.start
;
616 u32 __iomem
*dlist_next
= dlist_start
;
618 if (debug_dump_regs
) {
619 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc
));
620 vc4_hvs_dump_state(dev
);
623 /* Copy all the active planes' dlist contents to the hardware dlist. */
624 drm_atomic_crtc_for_each_plane(plane
, crtc
) {
625 dlist_next
+= vc4_plane_write_dlist(plane
, dlist_next
);
628 writel(SCALER_CTL0_END
, dlist_next
);
631 WARN_ON_ONCE(dlist_next
- dlist_start
!= vc4_state
->mm
.size
);
633 if (crtc
->state
->event
) {
636 crtc
->state
->event
->pipe
= drm_crtc_index(crtc
);
638 WARN_ON(drm_crtc_vblank_get(crtc
) != 0);
640 spin_lock_irqsave(&dev
->event_lock
, flags
);
641 vc4_crtc
->event
= crtc
->state
->event
;
642 crtc
->state
->event
= NULL
;
644 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc
->channel
),
645 vc4_state
->mm
.start
);
647 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
649 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc
->channel
),
650 vc4_state
->mm
.start
);
653 if (debug_dump_regs
) {
654 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc
));
655 vc4_hvs_dump_state(dev
);
659 static int vc4_enable_vblank(struct drm_crtc
*crtc
)
661 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
663 CRTC_WRITE(PV_INTEN
, PV_INT_VFP_START
);
668 static void vc4_disable_vblank(struct drm_crtc
*crtc
)
670 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
672 CRTC_WRITE(PV_INTEN
, 0);
675 /* Must be called with the event lock held */
676 bool vc4_event_pending(struct drm_crtc
*crtc
)
678 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
680 return !!vc4_crtc
->event
;
683 static void vc4_crtc_handle_page_flip(struct vc4_crtc
*vc4_crtc
)
685 struct drm_crtc
*crtc
= &vc4_crtc
->base
;
686 struct drm_device
*dev
= crtc
->dev
;
687 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
688 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(crtc
->state
);
689 u32 chan
= vc4_crtc
->channel
;
692 spin_lock_irqsave(&dev
->event_lock
, flags
);
693 if (vc4_crtc
->event
&&
694 (vc4_state
->mm
.start
== HVS_READ(SCALER_DISPLACTX(chan
)))) {
695 drm_crtc_send_vblank_event(crtc
, vc4_crtc
->event
);
696 vc4_crtc
->event
= NULL
;
697 drm_crtc_vblank_put(crtc
);
699 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
702 static irqreturn_t
vc4_crtc_irq_handler(int irq
, void *data
)
704 struct vc4_crtc
*vc4_crtc
= data
;
705 u32 stat
= CRTC_READ(PV_INTSTAT
);
706 irqreturn_t ret
= IRQ_NONE
;
708 if (stat
& PV_INT_VFP_START
) {
709 vc4_crtc
->t_vblank
= ktime_get();
710 CRTC_WRITE(PV_INTSTAT
, PV_INT_VFP_START
);
711 drm_crtc_handle_vblank(&vc4_crtc
->base
);
712 vc4_crtc_handle_page_flip(vc4_crtc
);
719 struct vc4_async_flip_state
{
720 struct drm_crtc
*crtc
;
721 struct drm_framebuffer
*fb
;
722 struct drm_pending_vblank_event
*event
;
724 struct vc4_seqno_cb cb
;
727 /* Called when the V3D execution for the BO being flipped to is done, so that
728 * we can actually update the plane's address to point to it.
731 vc4_async_page_flip_complete(struct vc4_seqno_cb
*cb
)
733 struct vc4_async_flip_state
*flip_state
=
734 container_of(cb
, struct vc4_async_flip_state
, cb
);
735 struct drm_crtc
*crtc
= flip_state
->crtc
;
736 struct drm_device
*dev
= crtc
->dev
;
737 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
738 struct drm_plane
*plane
= crtc
->primary
;
740 vc4_plane_async_set_fb(plane
, flip_state
->fb
);
741 if (flip_state
->event
) {
744 spin_lock_irqsave(&dev
->event_lock
, flags
);
745 drm_crtc_send_vblank_event(crtc
, flip_state
->event
);
746 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
749 drm_crtc_vblank_put(crtc
);
750 drm_framebuffer_unreference(flip_state
->fb
);
753 up(&vc4
->async_modeset
);
756 /* Implements async (non-vblank-synced) page flips.
758 * The page flip ioctl needs to return immediately, so we grab the
759 * modeset semaphore on the pipe, and queue the address update for
760 * when V3D is done with the BO being flipped to.
762 static int vc4_async_page_flip(struct drm_crtc
*crtc
,
763 struct drm_framebuffer
*fb
,
764 struct drm_pending_vblank_event
*event
,
767 struct drm_device
*dev
= crtc
->dev
;
768 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
769 struct drm_plane
*plane
= crtc
->primary
;
771 struct vc4_async_flip_state
*flip_state
;
772 struct drm_gem_cma_object
*cma_bo
= drm_fb_cma_get_gem_obj(fb
, 0);
773 struct vc4_bo
*bo
= to_vc4_bo(&cma_bo
->base
);
775 flip_state
= kzalloc(sizeof(*flip_state
), GFP_KERNEL
);
779 drm_framebuffer_reference(fb
);
781 flip_state
->crtc
= crtc
;
782 flip_state
->event
= event
;
784 /* Make sure all other async modesetes have landed. */
785 ret
= down_interruptible(&vc4
->async_modeset
);
787 drm_framebuffer_unreference(fb
);
792 WARN_ON(drm_crtc_vblank_get(crtc
) != 0);
794 /* Immediately update the plane's legacy fb pointer, so that later
795 * modeset prep sees the state that will be present when the semaphore
798 drm_atomic_set_fb_for_plane(plane
->state
, fb
);
801 vc4_queue_seqno_cb(dev
, &flip_state
->cb
, bo
->seqno
,
802 vc4_async_page_flip_complete
);
804 /* Driver takes ownership of state on successful async commit. */
808 static int vc4_page_flip(struct drm_crtc
*crtc
,
809 struct drm_framebuffer
*fb
,
810 struct drm_pending_vblank_event
*event
,
812 struct drm_modeset_acquire_ctx
*ctx
)
814 if (flags
& DRM_MODE_PAGE_FLIP_ASYNC
)
815 return vc4_async_page_flip(crtc
, fb
, event
, flags
);
817 return drm_atomic_helper_page_flip(crtc
, fb
, event
, flags
, ctx
);
820 static struct drm_crtc_state
*vc4_crtc_duplicate_state(struct drm_crtc
*crtc
)
822 struct vc4_crtc_state
*vc4_state
;
824 vc4_state
= kzalloc(sizeof(*vc4_state
), GFP_KERNEL
);
828 __drm_atomic_helper_crtc_duplicate_state(crtc
, &vc4_state
->base
);
829 return &vc4_state
->base
;
832 static void vc4_crtc_destroy_state(struct drm_crtc
*crtc
,
833 struct drm_crtc_state
*state
)
835 struct vc4_dev
*vc4
= to_vc4_dev(crtc
->dev
);
836 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(state
);
838 if (vc4_state
->mm
.allocated
) {
841 spin_lock_irqsave(&vc4
->hvs
->mm_lock
, flags
);
842 drm_mm_remove_node(&vc4_state
->mm
);
843 spin_unlock_irqrestore(&vc4
->hvs
->mm_lock
, flags
);
847 drm_atomic_helper_crtc_destroy_state(crtc
, state
);
851 vc4_crtc_reset(struct drm_crtc
*crtc
)
854 __drm_atomic_helper_crtc_destroy_state(crtc
->state
);
856 crtc
->state
= kzalloc(sizeof(struct vc4_crtc_state
), GFP_KERNEL
);
858 crtc
->state
->crtc
= crtc
;
861 static const struct drm_crtc_funcs vc4_crtc_funcs
= {
862 .set_config
= drm_atomic_helper_set_config
,
863 .destroy
= vc4_crtc_destroy
,
864 .page_flip
= vc4_page_flip
,
865 .set_property
= NULL
,
866 .cursor_set
= NULL
, /* handled by drm_mode_cursor_universal */
867 .cursor_move
= NULL
, /* handled by drm_mode_cursor_universal */
868 .reset
= vc4_crtc_reset
,
869 .atomic_duplicate_state
= vc4_crtc_duplicate_state
,
870 .atomic_destroy_state
= vc4_crtc_destroy_state
,
871 .gamma_set
= vc4_crtc_gamma_set
,
872 .enable_vblank
= vc4_enable_vblank
,
873 .disable_vblank
= vc4_disable_vblank
,
876 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs
= {
877 .mode_set_nofb
= vc4_crtc_mode_set_nofb
,
878 .disable
= vc4_crtc_disable
,
879 .enable
= vc4_crtc_enable
,
880 .mode_fixup
= vc4_crtc_mode_fixup
,
881 .atomic_check
= vc4_crtc_atomic_check
,
882 .atomic_flush
= vc4_crtc_atomic_flush
,
885 static const struct vc4_crtc_data pv0_data
= {
888 [PV_CONTROL_CLK_SELECT_DSI
] = VC4_ENCODER_TYPE_DSI0
,
889 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI
] = VC4_ENCODER_TYPE_DPI
,
893 static const struct vc4_crtc_data pv1_data
= {
896 [PV_CONTROL_CLK_SELECT_DSI
] = VC4_ENCODER_TYPE_DSI1
,
897 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI
] = VC4_ENCODER_TYPE_SMI
,
901 static const struct vc4_crtc_data pv2_data
= {
904 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI
] = VC4_ENCODER_TYPE_HDMI
,
905 [PV_CONTROL_CLK_SELECT_VEC
] = VC4_ENCODER_TYPE_VEC
,
909 static const struct of_device_id vc4_crtc_dt_match
[] = {
910 { .compatible
= "brcm,bcm2835-pixelvalve0", .data
= &pv0_data
},
911 { .compatible
= "brcm,bcm2835-pixelvalve1", .data
= &pv1_data
},
912 { .compatible
= "brcm,bcm2835-pixelvalve2", .data
= &pv2_data
},
916 static void vc4_set_crtc_possible_masks(struct drm_device
*drm
,
917 struct drm_crtc
*crtc
)
919 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
920 const struct vc4_crtc_data
*crtc_data
= vc4_crtc
->data
;
921 const enum vc4_encoder_type
*encoder_types
= crtc_data
->encoder_types
;
922 struct drm_encoder
*encoder
;
924 drm_for_each_encoder(encoder
, drm
) {
925 struct vc4_encoder
*vc4_encoder
= to_vc4_encoder(encoder
);
928 for (i
= 0; i
< ARRAY_SIZE(crtc_data
->encoder_types
); i
++) {
929 if (vc4_encoder
->type
== encoder_types
[i
]) {
930 vc4_encoder
->clock_select
= i
;
931 encoder
->possible_crtcs
|= drm_crtc_mask(crtc
);
939 vc4_crtc_get_cob_allocation(struct vc4_crtc
*vc4_crtc
)
941 struct drm_device
*drm
= vc4_crtc
->base
.dev
;
942 struct vc4_dev
*vc4
= to_vc4_dev(drm
);
943 u32 dispbase
= HVS_READ(SCALER_DISPBASEX(vc4_crtc
->channel
));
944 /* Top/base are supposed to be 4-pixel aligned, but the
945 * Raspberry Pi firmware fills the low bits (which are
946 * presumably ignored).
948 u32 top
= VC4_GET_FIELD(dispbase
, SCALER_DISPBASEX_TOP
) & ~3;
949 u32 base
= VC4_GET_FIELD(dispbase
, SCALER_DISPBASEX_BASE
) & ~3;
951 vc4_crtc
->cob_size
= top
- base
+ 4;
954 static int vc4_crtc_bind(struct device
*dev
, struct device
*master
, void *data
)
956 struct platform_device
*pdev
= to_platform_device(dev
);
957 struct drm_device
*drm
= dev_get_drvdata(master
);
958 struct vc4_crtc
*vc4_crtc
;
959 struct drm_crtc
*crtc
;
960 struct drm_plane
*primary_plane
, *cursor_plane
, *destroy_plane
, *temp
;
961 const struct of_device_id
*match
;
964 vc4_crtc
= devm_kzalloc(dev
, sizeof(*vc4_crtc
), GFP_KERNEL
);
967 crtc
= &vc4_crtc
->base
;
969 match
= of_match_device(vc4_crtc_dt_match
, dev
);
972 vc4_crtc
->data
= match
->data
;
974 vc4_crtc
->regs
= vc4_ioremap_regs(pdev
, 0);
975 if (IS_ERR(vc4_crtc
->regs
))
976 return PTR_ERR(vc4_crtc
->regs
);
978 /* For now, we create just the primary and the legacy cursor
979 * planes. We should be able to stack more planes on easily,
980 * but to do that we would need to compute the bandwidth
981 * requirement of the plane configuration, and reject ones
982 * that will take too much.
984 primary_plane
= vc4_plane_init(drm
, DRM_PLANE_TYPE_PRIMARY
);
985 if (IS_ERR(primary_plane
)) {
986 dev_err(dev
, "failed to construct primary plane\n");
987 ret
= PTR_ERR(primary_plane
);
991 drm_crtc_init_with_planes(drm
, crtc
, primary_plane
, NULL
,
992 &vc4_crtc_funcs
, NULL
);
993 drm_crtc_helper_add(crtc
, &vc4_crtc_helper_funcs
);
994 primary_plane
->crtc
= crtc
;
995 vc4_crtc
->channel
= vc4_crtc
->data
->hvs_channel
;
996 drm_mode_crtc_set_gamma_size(crtc
, ARRAY_SIZE(vc4_crtc
->lut_r
));
998 /* Set up some arbitrary number of planes. We're not limited
999 * by a set number of physical registers, just the space in
1000 * the HVS (16k) and how small an plane can be (28 bytes).
1001 * However, each plane we set up takes up some memory, and
1002 * increases the cost of looping over planes, which atomic
1003 * modesetting does quite a bit. As a result, we pick a
1004 * modest number of planes to expose, that should hopefully
1005 * still cover any sane usecase.
1007 for (i
= 0; i
< 8; i
++) {
1008 struct drm_plane
*plane
=
1009 vc4_plane_init(drm
, DRM_PLANE_TYPE_OVERLAY
);
1014 plane
->possible_crtcs
= 1 << drm_crtc_index(crtc
);
1017 /* Set up the legacy cursor after overlay initialization,
1018 * since we overlay planes on the CRTC in the order they were
1021 cursor_plane
= vc4_plane_init(drm
, DRM_PLANE_TYPE_CURSOR
);
1022 if (!IS_ERR(cursor_plane
)) {
1023 cursor_plane
->possible_crtcs
= 1 << drm_crtc_index(crtc
);
1024 cursor_plane
->crtc
= crtc
;
1025 crtc
->cursor
= cursor_plane
;
1028 vc4_crtc_get_cob_allocation(vc4_crtc
);
1030 CRTC_WRITE(PV_INTEN
, 0);
1031 CRTC_WRITE(PV_INTSTAT
, PV_INT_VFP_START
);
1032 ret
= devm_request_irq(dev
, platform_get_irq(pdev
, 0),
1033 vc4_crtc_irq_handler
, 0, "vc4 crtc", vc4_crtc
);
1035 goto err_destroy_planes
;
1037 vc4_set_crtc_possible_masks(drm
, crtc
);
1039 for (i
= 0; i
< crtc
->gamma_size
; i
++) {
1040 vc4_crtc
->lut_r
[i
] = i
;
1041 vc4_crtc
->lut_g
[i
] = i
;
1042 vc4_crtc
->lut_b
[i
] = i
;
1045 platform_set_drvdata(pdev
, vc4_crtc
);
1050 list_for_each_entry_safe(destroy_plane
, temp
,
1051 &drm
->mode_config
.plane_list
, head
) {
1052 if (destroy_plane
->possible_crtcs
== 1 << drm_crtc_index(crtc
))
1053 destroy_plane
->funcs
->destroy(destroy_plane
);
1059 static void vc4_crtc_unbind(struct device
*dev
, struct device
*master
,
1062 struct platform_device
*pdev
= to_platform_device(dev
);
1063 struct vc4_crtc
*vc4_crtc
= dev_get_drvdata(dev
);
1065 vc4_crtc_destroy(&vc4_crtc
->base
);
1067 CRTC_WRITE(PV_INTEN
, 0);
1069 platform_set_drvdata(pdev
, NULL
);
1072 static const struct component_ops vc4_crtc_ops
= {
1073 .bind
= vc4_crtc_bind
,
1074 .unbind
= vc4_crtc_unbind
,
1077 static int vc4_crtc_dev_probe(struct platform_device
*pdev
)
1079 return component_add(&pdev
->dev
, &vc4_crtc_ops
);
1082 static int vc4_crtc_dev_remove(struct platform_device
*pdev
)
1084 component_del(&pdev
->dev
, &vc4_crtc_ops
);
1088 struct platform_driver vc4_crtc_driver
= {
1089 .probe
= vc4_crtc_dev_probe
,
1090 .remove
= vc4_crtc_dev_remove
,
1093 .of_match_table
= vc4_crtc_dt_match
,