drivers/gpu/drm/vc4/vc4_drv.h

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include "drmP.h"
  10 #include "drm_gem_cma_helper.h"
  11
  12 struct vc4_dev {
  13         struct drm_device *dev;
  14
  15         bool firmware_kms;
  16         struct rpi_firmware *firmware;
  17
  18         struct vc4_hdmi *hdmi;
  19         struct vc4_hvs *hvs;
  20         struct vc4_crtc *crtc[3];
  21         struct vc4_v3d *v3d;
  22         struct vc4_dpi *dpi;
  23         struct vc4_vec *vec;
  24
  25         struct drm_fbdev_cma *fbdev;
  26
  27         struct vc4_hang_state *hang_state;
  28
  29         /* The kernel-space BO cache.  Tracks buffers that have been
  30          * unreferenced by all other users (refcounts of 0!) but not
  31          * yet freed, so we can do cheap allocations.
  32          */
  33         struct vc4_bo_cache {
  34                 /* Array of list heads for entries in the BO cache,
  35                  * based on number of pages, so we can do O(1) lookups
  36                  * in the cache when allocating.
  37                  */
  38                 struct list_head *size_list;
  39                 uint32_t size_list_size;
  40
  41                 /* List of all BOs in the cache, ordered by age, so we
  42                  * can do O(1) lookups when trying to free old
  43                  * buffers.
  44                  */
  45                 struct list_head time_list;
  46                 struct work_struct time_work;
  47                 struct timer_list time_timer;
  48         } bo_cache;
  49
  50         struct vc4_bo_stats {
  51                 u32 num_allocated;
  52                 u32 size_allocated;
  53                 u32 num_cached;
  54                 u32 size_cached;
  55         } bo_stats;
  56
  57         /* Protects bo_cache and the BO stats. */
  58         struct mutex bo_lock;
  59
  60         /* Sequence number for the last job queued in bin_job_list.
  61          * Starts at 0 (no jobs emitted).
  62          */
  63         uint64_t emit_seqno;
  64
  65         /* Sequence number for the last completed job on the GPU.
  66          * Starts at 0 (no jobs completed).
  67          */
  68         uint64_t finished_seqno;
  69
  70         /* List of all struct vc4_exec_info for jobs to be executed in
  71          * the binner.  The first job in the list is the one currently
  72          * programmed into ct0ca for execution.
  73          */
  74         struct list_head bin_job_list;
  75
  76         /* List of all struct vc4_exec_info for jobs that have
  77          * completed binning and are ready for rendering.  The first
  78          * job in the list is the one currently programmed into ct1ca
  79          * for execution.
  80          */
  81         struct list_head render_job_list;
  82
  83         /* List of the finished vc4_exec_infos waiting to be freed by
  84          * job_done_work.
  85          */
  86         struct list_head job_done_list;
  87         /* Spinlock used to synchronize the job_list and seqno
  88          * accesses between the IRQ handler and GEM ioctls.
  89          */
  90         spinlock_t job_lock;
  91         wait_queue_head_t job_wait_queue;
  92         struct work_struct job_done_work;
  93
  94         /* List of struct vc4_seqno_cb for callbacks to be made from a
  95          * workqueue when the given seqno is passed.
  96          */
  97         struct list_head seqno_cb_list;
  98
  99         /* The binner overflow memory that's currently set up in
 100          * BPOA/BPOS registers.  When overflow occurs and a new one is
 101          * allocated, the previous one will be moved to
 102          * vc4->current_exec's free list.
 103          */
 104         struct vc4_bo *overflow_mem;
 105         struct work_struct overflow_mem_work;
 106
 107         int power_refcount;
 108
 109         /* Mutex controlling the power refcount. */
 110         struct mutex power_lock;
 111
 112         struct {
 113                 struct timer_list timer;
 114                 struct work_struct reset_work;
 115         } hangcheck;
 116
 117         struct semaphore async_modeset;
 118 };
 119
 120 static inline struct vc4_dev *
 121 to_vc4_dev(struct drm_device *dev)
 122 {
 123         return (struct vc4_dev *)dev->dev_private;
 124 }
 125
 126 struct vc4_bo {
 127         struct drm_gem_cma_object base;
 128
 129         /* seqno of the last job to render using this BO. */
 130         uint64_t seqno;
 131
 132         /* seqno of the last job to use the RCL to write to this BO.
 133          *
 134          * Note that this doesn't include binner overflow memory
 135          * writes.
 136          */
 137         uint64_t write_seqno;
 138
 139         /* List entry for the BO's position in either
 140          * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
 141          */
 142         struct list_head unref_head;
 143
 144         /* Time in jiffies when the BO was put in vc4->bo_cache. */
 145         unsigned long free_time;
 146
 147         /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
 148         struct list_head size_head;
 149
 150         /* Struct for shader validation state, if created by
 151          * DRM_IOCTL_VC4_CREATE_SHADER_BO.
 152          */
 153         struct vc4_validated_shader_info *validated_shader;
 154 };
 155
 156 static inline struct vc4_bo *
 157 to_vc4_bo(struct drm_gem_object *bo)
 158 {
 159         return (struct vc4_bo *)bo;
 160 }
 161
 162 struct vc4_seqno_cb {
 163         struct work_struct work;
 164         uint64_t seqno;
 165         void (*func)(struct vc4_seqno_cb *cb);
 166 };
 167
 168 struct vc4_v3d {
 169         struct vc4_dev *vc4;
 170         struct platform_device *pdev;
 171         void __iomem *regs;
 172 };
 173
 174 struct vc4_hvs {
 175         struct platform_device *pdev;
 176         void __iomem *regs;
 177         u32 __iomem *dlist;
 178
 179         /* Memory manager for CRTCs to allocate space in the display
 180          * list.  Units are dwords.
 181          */
 182         struct drm_mm dlist_mm;
 183         /* Memory manager for the LBM memory used by HVS scaling. */
 184         struct drm_mm lbm_mm;
 185         spinlock_t mm_lock;
 186
 187         struct drm_mm_node mitchell_netravali_filter;
 188 };
 189
 190 struct vc4_plane {
 191         struct drm_plane base;
 192 };
 193
 194 static inline struct vc4_plane *
 195 to_vc4_plane(struct drm_plane *plane)
 196 {
 197         return (struct vc4_plane *)plane;
 198 }
 199
 200 enum vc4_encoder_type {
 201         VC4_ENCODER_TYPE_NONE,
 202         VC4_ENCODER_TYPE_HDMI,
 203         VC4_ENCODER_TYPE_VEC,
 204         VC4_ENCODER_TYPE_DSI0,
 205         VC4_ENCODER_TYPE_DSI1,
 206         VC4_ENCODER_TYPE_SMI,
 207         VC4_ENCODER_TYPE_DPI,
 208 };
 209
 210 struct vc4_encoder {
 211         struct drm_encoder base;
 212         enum vc4_encoder_type type;
 213         u32 clock_select;
 214 };
 215
 216 static inline struct vc4_encoder *
 217 to_vc4_encoder(struct drm_encoder *encoder)
 218 {
 219         return container_of(encoder, struct vc4_encoder, base);
 220 }
 221
 222 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
 223 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
 224 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
 225 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
 226
 227 struct vc4_exec_info {
 228         /* Sequence number for this bin/render job. */
 229         uint64_t seqno;
 230
 231         /* Latest write_seqno of any BO that binning depends on. */
 232         uint64_t bin_dep_seqno;
 233
 234         /* Last current addresses the hardware was processing when the
 235          * hangcheck timer checked on us.
 236          */
 237         uint32_t last_ct0ca, last_ct1ca;
 238
 239         /* Kernel-space copy of the ioctl arguments */
 240         struct drm_vc4_submit_cl *args;
 241
 242         /* This is the array of BOs that were looked up at the start of exec.
 243          * Command validation will use indices into this array.
 244          */
 245         struct drm_gem_cma_object **bo;
 246         uint32_t bo_count;
 247
 248         /* List of BOs that are being written by the RCL.  Other than
 249          * the binner temporary storage, this is all the BOs written
 250          * by the job.
 251          */
 252         struct drm_gem_cma_object *rcl_write_bo[4];
 253         uint32_t rcl_write_bo_count;
 254
 255         /* Pointers for our position in vc4->job_list */
 256         struct list_head head;
 257
 258         /* List of other BOs used in the job that need to be released
 259          * once the job is complete.
 260          */
 261         struct list_head unref_list;
 262
 263         /* Current unvalidated indices into @bo loaded by the non-hardware
 264          * VC4_PACKET_GEM_HANDLES.
 265          */
 266         uint32_t bo_index[2];
 267
 268         /* This is the BO where we store the validated command lists, shader
 269          * records, and uniforms.
 270          */
 271         struct drm_gem_cma_object *exec_bo;
 272
 273         /**
 274          * This tracks the per-shader-record state (packet 64) that
 275          * determines the length of the shader record and the offset
 276          * it's expected to be found at.  It gets read in from the
 277          * command lists.
 278          */
 279         struct vc4_shader_state {
 280                 uint32_t addr;
 281                 /* Maximum vertex index referenced by any primitive using this
 282                  * shader state.
 283                  */
 284                 uint32_t max_index;
 285         } *shader_state;
 286
 287         /** How many shader states the user declared they were using. */
 288         uint32_t shader_state_size;
 289         /** How many shader state records the validator has seen. */
 290         uint32_t shader_state_count;
 291
 292         bool found_tile_binning_mode_config_packet;
 293         bool found_start_tile_binning_packet;
 294         bool found_increment_semaphore_packet;
 295         bool found_flush;
 296         uint8_t bin_tiles_x, bin_tiles_y;
 297         struct drm_gem_cma_object *tile_bo;
 298         uint32_t tile_alloc_offset;
 299
 300         /**
 301          * Computed addresses pointing into exec_bo where we start the
 302          * bin thread (ct0) and render thread (ct1).
 303          */
 304         uint32_t ct0ca, ct0ea;
 305         uint32_t ct1ca, ct1ea;
 306
 307         /* Pointer to the unvalidated bin CL (if present). */
 308         void *bin_u;
 309
 310         /* Pointers to the shader recs.  These paddr gets incremented as CL
 311          * packets are relocated in validate_gl_shader_state, and the vaddrs
 312          * (u and v) get incremented and size decremented as the shader recs
 313          * themselves are validated.
 314          */
 315         void *shader_rec_u;
 316         void *shader_rec_v;
 317         uint32_t shader_rec_p;
 318         uint32_t shader_rec_size;
 319
 320         /* Pointers to the uniform data.  These pointers are incremented, and
 321          * size decremented, as each batch of uniforms is uploaded.
 322          */
 323         void *uniforms_u;
 324         void *uniforms_v;
 325         uint32_t uniforms_p;
 326         uint32_t uniforms_size;
 327 };
 328
 329 static inline struct vc4_exec_info *
 330 vc4_first_bin_job(struct vc4_dev *vc4)
 331 {
 332         return list_first_entry_or_null(&vc4->bin_job_list,
 333                                         struct vc4_exec_info, head);
 334 }
 335
 336 static inline struct vc4_exec_info *
 337 vc4_first_render_job(struct vc4_dev *vc4)
 338 {
 339         return list_first_entry_or_null(&vc4->render_job_list,
 340                                         struct vc4_exec_info, head);
 341 }
 342
 343 static inline struct vc4_exec_info *
 344 vc4_last_render_job(struct vc4_dev *vc4)
 345 {
 346         if (list_empty(&vc4->render_job_list))
 347                 return NULL;
 348         return list_last_entry(&vc4->render_job_list,
 349                                struct vc4_exec_info, head);
 350 }
 351
 352 /**
 353  * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
 354  * setup parameters.
 355  *
 356  * This will be used at draw time to relocate the reference to the texture
 357  * contents in p0, and validate that the offset combined with
 358  * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
 359  * Note that the hardware treats unprovided config parameters as 0, so not all
 360  * of them need to be set up for every texure sample, and we'll store ~0 as
 361  * the offset to mark the unused ones.
 362  *
 363  * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
 364  * Setup") for definitions of the texture parameters.
 365  */
 366 struct vc4_texture_sample_info {
 367         bool is_direct;
 368         uint32_t p_offset[4];
 369 };
 370
 371 /**
 372  * struct vc4_validated_shader_info - information about validated shaders that
 373  * needs to be used from command list validation.
 374  *
 375  * For a given shader, each time a shader state record references it, we need
 376  * to verify that the shader doesn't read more uniforms than the shader state
 377  * record's uniform BO pointer can provide, and we need to apply relocations
 378  * and validate the shader state record's uniforms that define the texture
 379  * samples.
 380  */
 381 struct vc4_validated_shader_info {
 382         uint32_t uniforms_size;
 383         uint32_t uniforms_src_size;
 384         uint32_t num_texture_samples;
 385         struct vc4_texture_sample_info *texture_samples;
 386
 387         uint32_t num_uniform_addr_offsets;
 388         uint32_t *uniform_addr_offsets;
 389
 390         bool is_threaded;
 391 };
 392
 393 /**
 394  * _wait_for - magic (register) wait macro
 395  *
 396  * Does the right thing for modeset paths when run under kdgb or similar atomic
 397  * contexts. Note that it's important that we check the condition again after
 398  * having timed out, since the timeout could be due to preemption or similar and
 399  * we've never had a chance to check the condition before the timeout.
 400  */
 401 #define _wait_for(COND, MS, W) ({ \
 402         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
 403         int ret__ = 0;                                                  \
 404         while (!(COND)) {                                               \
 405                 if (time_after(jiffies, timeout__)) {                   \
 406                         if (!(COND))                                    \
 407                                 ret__ = -ETIMEDOUT;                     \
 408                         break;                                          \
 409                 }                                                       \
 410                 if (W && drm_can_sleep())  {                            \
 411                         msleep(W);                                      \
 412                 } else {                                                \
 413                         cpu_relax();                                    \
 414                 }                                                       \
 415         }                                                               \
 416         ret__;                                                          \
 417 })
 418
 419 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
 420
 421 /* vc4_bo.c */
 422 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
 423 void vc4_free_object(struct drm_gem_object *gem_obj);
 424 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
 425                              bool from_cache);
 426 int vc4_dumb_create(struct drm_file *file_priv,
 427                     struct drm_device *dev,
 428                     struct drm_mode_create_dumb *args);
 429 struct dma_buf *vc4_prime_export(struct drm_device *dev,
 430                                  struct drm_gem_object *obj, int flags);
 431 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
 432                         struct drm_file *file_priv);
 433 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
 434                                struct drm_file *file_priv);
 435 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
 436                       struct drm_file *file_priv);
 437 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
 438                              struct drm_file *file_priv);
 439 int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
 440 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
 441 void *vc4_prime_vmap(struct drm_gem_object *obj);
 442 void vc4_bo_cache_init(struct drm_device *dev);
 443 void vc4_bo_cache_destroy(struct drm_device *dev);
 444 int vc4_bo_stats_debugfs(struct seq_file *m, void *arg);
 445
 446 /* vc4_crtc.c */
 447 extern struct platform_driver vc4_crtc_driver;
 448 int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id);
 449 void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id);
 450 bool vc4_event_pending(struct drm_crtc *crtc);
 451 int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg);
 452 int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
 453                             unsigned int flags, int *vpos, int *hpos,
 454                             ktime_t *stime, ktime_t *etime,
 455                             const struct drm_display_mode *mode);
 456 int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id,
 457                                   int *max_error, struct timeval *vblank_time,
 458                                   unsigned flags);
 459
 460 /* vc4_debugfs.c */
 461 int vc4_debugfs_init(struct drm_minor *minor);
 462 void vc4_debugfs_cleanup(struct drm_minor *minor);
 463
 464 /* vc4_drv.c */
 465 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
 466
 467 /* vc4_dpi.c */
 468 extern struct platform_driver vc4_dpi_driver;
 469 int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused);
 470
 471 /* vc4_firmware_kms.c */
 472 extern struct platform_driver vc4_firmware_kms_driver;
 473 void vc4_fkms_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file);
 474
 475 /* vc4_gem.c */
 476 void vc4_gem_init(struct drm_device *dev);
 477 void vc4_gem_destroy(struct drm_device *dev);
 478 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
 479                         struct drm_file *file_priv);
 480 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
 481                          struct drm_file *file_priv);
 482 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
 483                       struct drm_file *file_priv);
 484 void vc4_submit_next_bin_job(struct drm_device *dev);
 485 void vc4_submit_next_render_job(struct drm_device *dev);
 486 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
 487 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
 488                        uint64_t timeout_ns, bool interruptible);
 489 void vc4_job_handle_completed(struct vc4_dev *vc4);
 490 int vc4_queue_seqno_cb(struct drm_device *dev,
 491                        struct vc4_seqno_cb *cb, uint64_t seqno,
 492                        void (*func)(struct vc4_seqno_cb *cb));
 493
 494 /* vc4_hdmi.c */
 495 extern struct platform_driver vc4_hdmi_driver;
 496 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused);
 497
 498 /* vc4_hdmi.c */
 499 extern struct platform_driver vc4_vec_driver;
 500 int vc4_vec_debugfs_regs(struct seq_file *m, void *unused);
 501
 502 /* vc4_irq.c */
 503 irqreturn_t vc4_irq(int irq, void *arg);
 504 void vc4_irq_preinstall(struct drm_device *dev);
 505 int vc4_irq_postinstall(struct drm_device *dev);
 506 void vc4_irq_uninstall(struct drm_device *dev);
 507 void vc4_irq_reset(struct drm_device *dev);
 508
 509 /* vc4_hvs.c */
 510 extern struct platform_driver vc4_hvs_driver;
 511 void vc4_hvs_dump_state(struct drm_device *dev);
 512 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused);
 513
 514 /* vc4_kms.c */
 515 int vc4_kms_load(struct drm_device *dev);
 516
 517 /* vc4_plane.c */
 518 struct drm_plane *vc4_plane_init(struct drm_device *dev,
 519                                  enum drm_plane_type type);
 520 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
 521 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
 522 void vc4_plane_async_set_fb(struct drm_plane *plane,
 523                             struct drm_framebuffer *fb);
 524
 525 /* vc4_v3d.c */
 526 extern struct platform_driver vc4_v3d_driver;
 527 int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused);
 528 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused);
 529
 530 /* vc4_validate.c */
 531 int
 532 vc4_validate_bin_cl(struct drm_device *dev,
 533                     void *validated,
 534                     void *unvalidated,
 535                     struct vc4_exec_info *exec);
 536
 537 int
 538 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
 539
 540 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
 541                                       uint32_t hindex);
 542
 543 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
 544
 545 bool vc4_check_tex_size(struct vc4_exec_info *exec,
 546                         struct drm_gem_cma_object *fbo,
 547                         uint32_t offset, uint8_t tiling_format,
 548                         uint32_t width, uint32_t height, uint8_t cpp);
 549
 550 /* vc4_validate_shader.c */
 551 struct vc4_validated_shader_info *
 552 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);