drivers/gpu/drm/vc4/vc4_drv.h

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include "drmP.h"
  10 #include "drm_gem_cma_helper.h"
  11
  12 struct vc4_dev {
  13         struct drm_device *dev;
  14
  15         struct vc4_hdmi *hdmi;
  16         struct vc4_hvs *hvs;
  17         struct vc4_crtc *crtc[3];
  18         struct vc4_v3d *v3d;
  19
  20         struct drm_fbdev_cma *fbdev;
  21
  22         struct vc4_hang_state *hang_state;
  23
  24         /* The kernel-space BO cache.  Tracks buffers that have been
  25          * unreferenced by all other users (refcounts of 0!) but not
  26          * yet freed, so we can do cheap allocations.
  27          */
  28         struct vc4_bo_cache {
  29                 /* Array of list heads for entries in the BO cache,
  30                  * based on number of pages, so we can do O(1) lookups
  31                  * in the cache when allocating.
  32                  */
  33                 struct list_head *size_list;
  34                 uint32_t size_list_size;
  35
  36                 /* List of all BOs in the cache, ordered by age, so we
  37                  * can do O(1) lookups when trying to free old
  38                  * buffers.
  39                  */
  40                 struct list_head time_list;
  41                 struct work_struct time_work;
  42                 struct timer_list time_timer;
  43         } bo_cache;
  44
  45         struct vc4_bo_stats {
  46                 u32 num_allocated;
  47                 u32 size_allocated;
  48                 u32 num_cached;
  49                 u32 size_cached;
  50         } bo_stats;
  51
  52         /* Protects bo_cache and the BO stats. */
  53         struct mutex bo_lock;
  54
  55         /* Sequence number for the last job queued in job_list.
  56          * Starts at 0 (no jobs emitted).
  57          */
  58         uint64_t emit_seqno;
  59
  60         /* Sequence number for the last completed job on the GPU.
  61          * Starts at 0 (no jobs completed).
  62          */
  63         uint64_t finished_seqno;
  64
  65         /* List of all struct vc4_exec_info for jobs to be executed.
  66          * The first job in the list is the one currently programmed
  67          * into ct0ca/ct1ca for execution.
  68          */
  69         struct list_head job_list;
  70         /* List of the finished vc4_exec_infos waiting to be freed by
  71          * job_done_work.
  72          */
  73         struct list_head job_done_list;
  74         /* Spinlock used to synchronize the job_list and seqno
  75          * accesses between the IRQ handler and GEM ioctls.
  76          */
  77         spinlock_t job_lock;
  78         wait_queue_head_t job_wait_queue;
  79         struct work_struct job_done_work;
  80
  81         /* List of struct vc4_seqno_cb for callbacks to be made from a
  82          * workqueue when the given seqno is passed.
  83          */
  84         struct list_head seqno_cb_list;
  85
  86         /* The binner overflow memory that's currently set up in
  87          * BPOA/BPOS registers.  When overflow occurs and a new one is
  88          * allocated, the previous one will be moved to
  89          * vc4->current_exec's free list.
  90          */
  91         struct vc4_bo *overflow_mem;
  92         struct work_struct overflow_mem_work;
  93
  94         struct {
  95                 struct timer_list timer;
  96                 struct work_struct reset_work;
  97         } hangcheck;
  98
  99         struct semaphore async_modeset;
 100 };
 101
 102 static inline struct vc4_dev *
 103 to_vc4_dev(struct drm_device *dev)
 104 {
 105         return (struct vc4_dev *)dev->dev_private;
 106 }
 107
 108 struct vc4_bo {
 109         struct drm_gem_cma_object base;
 110
 111         /* seqno of the last job to render to this BO. */
 112         uint64_t seqno;
 113
 114         /* List entry for the BO's position in either
 115          * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
 116          */
 117         struct list_head unref_head;
 118
 119         /* Time in jiffies when the BO was put in vc4->bo_cache. */
 120         unsigned long free_time;
 121
 122         /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
 123         struct list_head size_head;
 124
 125         /* Struct for shader validation state, if created by
 126          * DRM_IOCTL_VC4_CREATE_SHADER_BO.
 127          */
 128         struct vc4_validated_shader_info *validated_shader;
 129 };
 130
 131 static inline struct vc4_bo *
 132 to_vc4_bo(struct drm_gem_object *bo)
 133 {
 134         return (struct vc4_bo *)bo;
 135 }
 136
 137 struct vc4_seqno_cb {
 138         struct work_struct work;
 139         uint64_t seqno;
 140         void (*func)(struct vc4_seqno_cb *cb);
 141 };
 142
 143 struct vc4_v3d {
 144         struct platform_device *pdev;
 145         void __iomem *regs;
 146 };
 147
 148 struct vc4_hvs {
 149         struct platform_device *pdev;
 150         void __iomem *regs;
 151         void __iomem *dlist;
 152 };
 153
 154 struct vc4_plane {
 155         struct drm_plane base;
 156 };
 157
 158 static inline struct vc4_plane *
 159 to_vc4_plane(struct drm_plane *plane)
 160 {
 161         return (struct vc4_plane *)plane;
 162 }
 163
 164 enum vc4_encoder_type {
 165         VC4_ENCODER_TYPE_HDMI,
 166         VC4_ENCODER_TYPE_VEC,
 167         VC4_ENCODER_TYPE_DSI0,
 168         VC4_ENCODER_TYPE_DSI1,
 169         VC4_ENCODER_TYPE_SMI,
 170         VC4_ENCODER_TYPE_DPI,
 171 };
 172
 173 struct vc4_encoder {
 174         struct drm_encoder base;
 175         enum vc4_encoder_type type;
 176         u32 clock_select;
 177 };
 178
 179 static inline struct vc4_encoder *
 180 to_vc4_encoder(struct drm_encoder *encoder)
 181 {
 182         return container_of(encoder, struct vc4_encoder, base);
 183 }
 184
 185 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
 186 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
 187 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
 188 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
 189
 190 struct vc4_exec_info {
 191         /* Sequence number for this bin/render job. */
 192         uint64_t seqno;
 193
 194         /* Last current addresses the hardware was processing when the
 195          * hangcheck timer checked on us.
 196          */
 197         uint32_t last_ct0ca, last_ct1ca;
 198
 199         /* Kernel-space copy of the ioctl arguments */
 200         struct drm_vc4_submit_cl *args;
 201
 202         /* This is the array of BOs that were looked up at the start of exec.
 203          * Command validation will use indices into this array.
 204          */
 205         struct drm_gem_cma_object **bo;
 206         uint32_t bo_count;
 207
 208         /* Pointers for our position in vc4->job_list */
 209         struct list_head head;
 210
 211         /* List of other BOs used in the job that need to be released
 212          * once the job is complete.
 213          */
 214         struct list_head unref_list;
 215
 216         /* Current unvalidated indices into @bo loaded by the non-hardware
 217          * VC4_PACKET_GEM_HANDLES.
 218          */
 219         uint32_t bo_index[2];
 220
 221         /* This is the BO where we store the validated command lists, shader
 222          * records, and uniforms.
 223          */
 224         struct drm_gem_cma_object *exec_bo;
 225
 226         /**
 227          * This tracks the per-shader-record state (packet 64) that
 228          * determines the length of the shader record and the offset
 229          * it's expected to be found at.  It gets read in from the
 230          * command lists.
 231          */
 232         struct vc4_shader_state {
 233                 uint32_t addr;
 234                 /* Maximum vertex index referenced by any primitive using this
 235                  * shader state.
 236                  */
 237                 uint32_t max_index;
 238         } *shader_state;
 239
 240         /** How many shader states the user declared they were using. */
 241         uint32_t shader_state_size;
 242         /** How many shader state records the validator has seen. */
 243         uint32_t shader_state_count;
 244
 245         bool found_tile_binning_mode_config_packet;
 246         bool found_start_tile_binning_packet;
 247         bool found_increment_semaphore_packet;
 248         bool found_flush;
 249         uint8_t bin_tiles_x, bin_tiles_y;
 250         struct drm_gem_cma_object *tile_bo;
 251         uint32_t tile_alloc_offset;
 252
 253         /**
 254          * Computed addresses pointing into exec_bo where we start the
 255          * bin thread (ct0) and render thread (ct1).
 256          */
 257         uint32_t ct0ca, ct0ea;
 258         uint32_t ct1ca, ct1ea;
 259
 260         /* Pointer to the unvalidated bin CL (if present). */
 261         void *bin_u;
 262
 263         /* Pointers to the shader recs.  These paddr gets incremented as CL
 264          * packets are relocated in validate_gl_shader_state, and the vaddrs
 265          * (u and v) get incremented and size decremented as the shader recs
 266          * themselves are validated.
 267          */
 268         void *shader_rec_u;
 269         void *shader_rec_v;
 270         uint32_t shader_rec_p;
 271         uint32_t shader_rec_size;
 272
 273         /* Pointers to the uniform data.  These pointers are incremented, and
 274          * size decremented, as each batch of uniforms is uploaded.
 275          */
 276         void *uniforms_u;
 277         void *uniforms_v;
 278         uint32_t uniforms_p;
 279         uint32_t uniforms_size;
 280 };
 281
 282 static inline struct vc4_exec_info *
 283 vc4_first_job(struct vc4_dev *vc4)
 284 {
 285         if (list_empty(&vc4->job_list))
 286                 return NULL;
 287         return list_first_entry(&vc4->job_list, struct vc4_exec_info, head);
 288 }
 289
 290 /**
 291  * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
 292  * setup parameters.
 293  *
 294  * This will be used at draw time to relocate the reference to the texture
 295  * contents in p0, and validate that the offset combined with
 296  * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
 297  * Note that the hardware treats unprovided config parameters as 0, so not all
 298  * of them need to be set up for every texure sample, and we'll store ~0 as
 299  * the offset to mark the unused ones.
 300  *
 301  * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
 302  * Setup") for definitions of the texture parameters.
 303  */
 304 struct vc4_texture_sample_info {
 305         bool is_direct;
 306         uint32_t p_offset[4];
 307 };
 308
 309 /**
 310  * struct vc4_validated_shader_info - information about validated shaders that
 311  * needs to be used from command list validation.
 312  *
 313  * For a given shader, each time a shader state record references it, we need
 314  * to verify that the shader doesn't read more uniforms than the shader state
 315  * record's uniform BO pointer can provide, and we need to apply relocations
 316  * and validate the shader state record's uniforms that define the texture
 317  * samples.
 318  */
 319 struct vc4_validated_shader_info {
 320         uint32_t uniforms_size;
 321         uint32_t uniforms_src_size;
 322         uint32_t num_texture_samples;
 323         struct vc4_texture_sample_info *texture_samples;
 324 };
 325
 326 /**
 327  * _wait_for - magic (register) wait macro
 328  *
 329  * Does the right thing for modeset paths when run under kdgb or similar atomic
 330  * contexts. Note that it's important that we check the condition again after
 331  * having timed out, since the timeout could be due to preemption or similar and
 332  * we've never had a chance to check the condition before the timeout.
 333  */
 334 #define _wait_for(COND, MS, W) ({ \
 335         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
 336         int ret__ = 0;                                                  \
 337         while (!(COND)) {                                               \
 338                 if (time_after(jiffies, timeout__)) {                   \
 339                         if (!(COND))                                    \
 340                                 ret__ = -ETIMEDOUT;                     \
 341                         break;                                          \
 342                 }                                                       \
 343                 if (W && drm_can_sleep())  {                            \
 344                         msleep(W);                                      \
 345                 } else {                                                \
 346                         cpu_relax();                                    \
 347                 }                                                       \
 348         }                                                               \
 349         ret__;                                                          \
 350 })
 351
 352 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
 353
 354 /* vc4_bo.c */
 355 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
 356 void vc4_free_object(struct drm_gem_object *gem_obj);
 357 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
 358                              bool from_cache);
 359 int vc4_dumb_create(struct drm_file *file_priv,
 360                     struct drm_device *dev,
 361                     struct drm_mode_create_dumb *args);
 362 struct dma_buf *vc4_prime_export(struct drm_device *dev,
 363                                  struct drm_gem_object *obj, int flags);
 364 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
 365                         struct drm_file *file_priv);
 366 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
 367                                struct drm_file *file_priv);
 368 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
 369                       struct drm_file *file_priv);
 370 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
 371                              struct drm_file *file_priv);
 372 int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
 373 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
 374 void *vc4_prime_vmap(struct drm_gem_object *obj);
 375 void vc4_bo_cache_init(struct drm_device *dev);
 376 void vc4_bo_cache_destroy(struct drm_device *dev);
 377 int vc4_bo_stats_debugfs(struct seq_file *m, void *arg);
 378
 379 /* vc4_crtc.c */
 380 extern struct platform_driver vc4_crtc_driver;
 381 int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id);
 382 void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id);
 383 void vc4_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file);
 384 int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg);
 385
 386 /* vc4_debugfs.c */
 387 int vc4_debugfs_init(struct drm_minor *minor);
 388 void vc4_debugfs_cleanup(struct drm_minor *minor);
 389
 390 /* vc4_drv.c */
 391 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
 392
 393 /* vc4_gem.c */
 394 void vc4_gem_init(struct drm_device *dev);
 395 void vc4_gem_destroy(struct drm_device *dev);
 396 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
 397                         struct drm_file *file_priv);
 398 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
 399                          struct drm_file *file_priv);
 400 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
 401                       struct drm_file *file_priv);
 402 void vc4_submit_next_job(struct drm_device *dev);
 403 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
 404                        uint64_t timeout_ns, bool interruptible);
 405 void vc4_job_handle_completed(struct vc4_dev *vc4);
 406 int vc4_queue_seqno_cb(struct drm_device *dev,
 407                        struct vc4_seqno_cb *cb, uint64_t seqno,
 408                        void (*func)(struct vc4_seqno_cb *cb));
 409
 410 /* vc4_hdmi.c */
 411 extern struct platform_driver vc4_hdmi_driver;
 412 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused);
 413
 414 /* vc4_irq.c */
 415 irqreturn_t vc4_irq(int irq, void *arg);
 416 void vc4_irq_preinstall(struct drm_device *dev);
 417 int vc4_irq_postinstall(struct drm_device *dev);
 418 void vc4_irq_uninstall(struct drm_device *dev);
 419 void vc4_irq_reset(struct drm_device *dev);
 420
 421 /* vc4_hvs.c */
 422 extern struct platform_driver vc4_hvs_driver;
 423 void vc4_hvs_dump_state(struct drm_device *dev);
 424 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused);
 425
 426 /* vc4_kms.c */
 427 int vc4_kms_load(struct drm_device *dev);
 428
 429 /* vc4_plane.c */
 430 struct drm_plane *vc4_plane_init(struct drm_device *dev,
 431                                  enum drm_plane_type type);
 432 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
 433 u32 vc4_plane_dlist_size(struct drm_plane_state *state);
 434 void vc4_plane_async_set_fb(struct drm_plane *plane,
 435                             struct drm_framebuffer *fb);
 436
 437 /* vc4_v3d.c */
 438 extern struct platform_driver vc4_v3d_driver;
 439 int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused);
 440 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused);
 441 int vc4_v3d_set_power(struct vc4_dev *vc4, bool on);
 442
 443 /* vc4_validate.c */
 444 int
 445 vc4_validate_bin_cl(struct drm_device *dev,
 446                     void *validated,
 447                     void *unvalidated,
 448                     struct vc4_exec_info *exec);
 449
 450 int
 451 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
 452
 453 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
 454                                       uint32_t hindex);
 455
 456 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
 457
 458 bool vc4_check_tex_size(struct vc4_exec_info *exec,
 459                         struct drm_gem_cma_object *fbo,
 460                         uint32_t offset, uint8_t tiling_format,
 461                         uint32_t width, uint32_t height, uint8_t cpp);
 462
 463 /* vc4_validate_shader.c */
 464 struct vc4_validated_shader_info *
 465 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);