1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2015 Broadcom
6 #include <linux/mm_types.h>
8 #include <drm/drm_util.h>
9 #include <drm/drm_encoder.h>
10 #include <drm/drm_gem_cma_helper.h>
11 #include <drm/drm_atomic.h>
12 #include <drm/drm_syncobj.h>
14 #include "uapi/drm/vc4_drm.h"
16 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to
19 enum vc4_kernel_bo_type
{
20 /* Any kernel allocation (gem_create_object hook) before it
21 * gets another type set.
25 VC4_BO_TYPE_V3D_SHADER
,
30 VC4_BO_TYPE_KERNEL_CACHE
,
34 /* Performance monitor object. The perform lifetime is controlled by userspace
35 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
36 * request, and when this is the case, HW perf counters will be activated just
37 * before the submit_cl is submitted to the GPU and disabled when the job is
38 * done. This way, only events related to a specific job will be counted.
41 /* Tracks the number of users of the perfmon, when this counter reaches
42 * zero the perfmon is destroyed.
46 /* Number of counters activated in this perfmon instance
47 * (should be less than DRM_VC4_MAX_PERF_COUNTERS).
51 /* Events counted by the HW perf counters. */
52 u8 events
[DRM_VC4_MAX_PERF_COUNTERS
];
54 /* Storage for counter values. Counters are incremented by the HW
55 * perf counter values every time the perfmon is attached to a GPU job.
56 * This way, perfmon users don't have to retrieve the results after
57 * each job if they want to track events covering several submissions.
58 * Note that counter values can't be reset, but you can fake a reset by
59 * destroying the perfmon and creating a new one.
65 struct drm_device
*dev
;
67 struct vc4_hdmi
*hdmi
;
75 struct vc4_hang_state
*hang_state
;
77 /* The kernel-space BO cache. Tracks buffers that have been
78 * unreferenced by all other users (refcounts of 0!) but not
79 * yet freed, so we can do cheap allocations.
82 /* Array of list heads for entries in the BO cache,
83 * based on number of pages, so we can do O(1) lookups
84 * in the cache when allocating.
86 struct list_head
*size_list
;
87 uint32_t size_list_size
;
89 /* List of all BOs in the cache, ordered by age, so we
90 * can do O(1) lookups when trying to free old
93 struct list_head time_list
;
94 struct work_struct time_work
;
95 struct timer_list time_timer
;
105 /* Protects bo_cache and bo_labels. */
106 struct mutex bo_lock
;
108 /* Purgeable BO pool. All BOs in this pool can have their memory
109 * reclaimed if the driver is unable to allocate new BOs. We also
110 * keep stats related to the purge mechanism here.
113 struct list_head list
;
116 unsigned int purged_num
;
121 uint64_t dma_fence_context
;
123 /* Sequence number for the last job queued in bin_job_list.
124 * Starts at 0 (no jobs emitted).
128 /* Sequence number for the last completed job on the GPU.
129 * Starts at 0 (no jobs completed).
131 uint64_t finished_seqno
;
133 /* List of all struct vc4_exec_info for jobs to be executed in
134 * the binner. The first job in the list is the one currently
135 * programmed into ct0ca for execution.
137 struct list_head bin_job_list
;
139 /* List of all struct vc4_exec_info for jobs that have
140 * completed binning and are ready for rendering. The first
141 * job in the list is the one currently programmed into ct1ca
144 struct list_head render_job_list
;
146 /* List of the finished vc4_exec_infos waiting to be freed by
149 struct list_head job_done_list
;
150 /* Spinlock used to synchronize the job_list and seqno
151 * accesses between the IRQ handler and GEM ioctls.
154 wait_queue_head_t job_wait_queue
;
155 struct work_struct job_done_work
;
157 /* Used to track the active perfmon if any. Access to this field is
158 * protected by job_lock.
160 struct vc4_perfmon
*active_perfmon
;
162 /* List of struct vc4_seqno_cb for callbacks to be made from a
163 * workqueue when the given seqno is passed.
165 struct list_head seqno_cb_list
;
167 /* The memory used for storing binner tile alloc, tile state,
168 * and overflow memory allocations. This is freed when V3D
171 struct vc4_bo
*bin_bo
;
173 /* Size of blocks allocated within bin_bo. */
174 uint32_t bin_alloc_size
;
176 /* Bitmask of the bin_alloc_size chunks in bin_bo that are
179 uint32_t bin_alloc_used
;
181 /* Bitmask of the current bin_alloc used for overflow memory. */
182 uint32_t bin_alloc_overflow
;
184 /* Incremented when an underrun error happened after an atomic commit.
185 * This is particularly useful to detect when a specific modeset is too
186 * demanding in term of memory or HVS bandwidth which is hard to guess
187 * at atomic check time.
191 struct work_struct overflow_mem_work
;
195 /* Set to true when the load tracker is active. */
196 bool load_tracker_enabled
;
198 /* Mutex controlling the power refcount. */
199 struct mutex power_lock
;
202 struct timer_list timer
;
203 struct work_struct reset_work
;
206 struct semaphore async_modeset
;
208 struct drm_modeset_lock ctm_state_lock
;
209 struct drm_private_obj ctm_manager
;
210 struct drm_private_obj load_tracker
;
212 /* List of vc4_debugfs_info_entry for adding to debugfs once
213 * the minor is available (after drm_dev_register()).
215 struct list_head debugfs_list
;
218 static inline struct vc4_dev
*
219 to_vc4_dev(struct drm_device
*dev
)
221 return (struct vc4_dev
*)dev
->dev_private
;
225 struct drm_gem_cma_object base
;
227 /* seqno of the last job to render using this BO. */
230 /* seqno of the last job to use the RCL to write to this BO.
232 * Note that this doesn't include binner overflow memory
235 uint64_t write_seqno
;
239 /* List entry for the BO's position in either
240 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
242 struct list_head unref_head
;
244 /* Time in jiffies when the BO was put in vc4->bo_cache. */
245 unsigned long free_time
;
247 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
248 struct list_head size_head
;
250 /* Struct for shader validation state, if created by
251 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
253 struct vc4_validated_shader_info
*validated_shader
;
255 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i
256 * for user-allocated labels.
260 /* Count the number of active users. This is needed to determine
261 * whether we can move the BO to the purgeable list or not (when the BO
262 * is used by the GPU or the display engine we can't purge it).
266 /* Store purgeable/purged state here */
268 struct mutex madv_lock
;
271 static inline struct vc4_bo
*
272 to_vc4_bo(struct drm_gem_object
*bo
)
274 return (struct vc4_bo
*)bo
;
278 struct dma_fence base
;
279 struct drm_device
*dev
;
280 /* vc4 seqno for signaled() test */
284 static inline struct vc4_fence
*
285 to_vc4_fence(struct dma_fence
*fence
)
287 return (struct vc4_fence
*)fence
;
290 struct vc4_seqno_cb
{
291 struct work_struct work
;
293 void (*func
)(struct vc4_seqno_cb
*cb
);
298 struct platform_device
*pdev
;
301 struct debugfs_regset32 regset
;
305 struct platform_device
*pdev
;
309 /* Memory manager for CRTCs to allocate space in the display
310 * list. Units are dwords.
312 struct drm_mm dlist_mm
;
313 /* Memory manager for the LBM memory used by HVS scaling. */
314 struct drm_mm lbm_mm
;
317 struct drm_mm_node mitchell_netravali_filter
;
318 struct debugfs_regset32 regset
;
322 struct drm_plane base
;
325 static inline struct vc4_plane
*
326 to_vc4_plane(struct drm_plane
*plane
)
328 return (struct vc4_plane
*)plane
;
331 enum vc4_scaling_mode
{
337 struct vc4_plane_state
{
338 struct drm_plane_state base
;
339 /* System memory copy of the display list for this element, computed
340 * at atomic_check time.
343 u32 dlist_size
; /* Number of dwords allocated for the display list */
344 u32 dlist_count
; /* Number of used dwords in the display list. */
346 /* Offset in the dlist to various words, for pageflip or
354 /* Offset where the plane's dlist was last stored in the
355 * hardware at vc4_crtc_atomic_flush() time.
357 u32 __iomem
*hw_dlist
;
359 /* Clipped coordinates of the plane on the display. */
360 int crtc_x
, crtc_y
, crtc_w
, crtc_h
;
361 /* Clipped area being scanned from in the FB. */
364 u32 src_w
[2], src_h
[2];
366 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
367 enum vc4_scaling_mode x_scaling
[2], y_scaling
[2];
371 /* Offset to start scanning out from the start of the plane's
376 /* Our allocation in LBM for temporary storage during scaling. */
377 struct drm_mm_node lbm
;
379 /* Set when the plane has per-pixel alpha content or does not cover
380 * the entire screen. This is a hint to the CRTC that it might need
381 * to enable background color fill.
385 /* Mark the dlist as initialized. Useful to avoid initializing it twice
386 * when async update is not possible.
388 bool dlist_initialized
;
390 /* Load of this plane on the HVS block. The load is expressed in HVS
395 /* Memory bandwidth needed for this plane. This is expressed in
401 static inline struct vc4_plane_state
*
402 to_vc4_plane_state(struct drm_plane_state
*state
)
404 return (struct vc4_plane_state
*)state
;
407 enum vc4_encoder_type
{
408 VC4_ENCODER_TYPE_NONE
,
409 VC4_ENCODER_TYPE_HDMI
,
410 VC4_ENCODER_TYPE_VEC
,
411 VC4_ENCODER_TYPE_DSI0
,
412 VC4_ENCODER_TYPE_DSI1
,
413 VC4_ENCODER_TYPE_SMI
,
414 VC4_ENCODER_TYPE_DPI
,
418 struct drm_encoder base
;
419 enum vc4_encoder_type type
;
423 static inline struct vc4_encoder
*
424 to_vc4_encoder(struct drm_encoder
*encoder
)
426 return container_of(encoder
, struct vc4_encoder
, base
);
429 struct vc4_crtc_data
{
430 /* Which channel of the HVS this pixelvalve sources from. */
433 enum vc4_encoder_type encoder_types
[4];
434 const char *debugfs_name
;
438 struct drm_crtc base
;
439 struct platform_device
*pdev
;
440 const struct vc4_crtc_data
*data
;
443 /* Timestamp at start of vblank irq - unaffected by lock delays. */
446 /* Which HVS channel we're using for our CRTC. */
452 /* Size in pixels of the COB memory allocated to this CRTC. */
455 struct drm_pending_vblank_event
*event
;
457 struct debugfs_regset32 regset
;
460 static inline struct vc4_crtc
*
461 to_vc4_crtc(struct drm_crtc
*crtc
)
463 return (struct vc4_crtc
*)crtc
;
466 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
467 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
468 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
469 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
471 #define VC4_REG32(reg) { .name = #reg, .offset = reg }
473 struct vc4_exec_info
{
474 /* Sequence number for this bin/render job. */
477 /* Latest write_seqno of any BO that binning depends on. */
478 uint64_t bin_dep_seqno
;
480 struct dma_fence
*fence
;
482 /* Last current addresses the hardware was processing when the
483 * hangcheck timer checked on us.
485 uint32_t last_ct0ca
, last_ct1ca
;
487 /* Kernel-space copy of the ioctl arguments */
488 struct drm_vc4_submit_cl
*args
;
490 /* This is the array of BOs that were looked up at the start of exec.
491 * Command validation will use indices into this array.
493 struct drm_gem_cma_object
**bo
;
496 /* List of BOs that are being written by the RCL. Other than
497 * the binner temporary storage, this is all the BOs written
500 struct drm_gem_cma_object
*rcl_write_bo
[4];
501 uint32_t rcl_write_bo_count
;
503 /* Pointers for our position in vc4->job_list */
504 struct list_head head
;
506 /* List of other BOs used in the job that need to be released
507 * once the job is complete.
509 struct list_head unref_list
;
511 /* Current unvalidated indices into @bo loaded by the non-hardware
512 * VC4_PACKET_GEM_HANDLES.
514 uint32_t bo_index
[2];
516 /* This is the BO where we store the validated command lists, shader
517 * records, and uniforms.
519 struct drm_gem_cma_object
*exec_bo
;
522 * This tracks the per-shader-record state (packet 64) that
523 * determines the length of the shader record and the offset
524 * it's expected to be found at. It gets read in from the
527 struct vc4_shader_state
{
529 /* Maximum vertex index referenced by any primitive using this
535 /** How many shader states the user declared they were using. */
536 uint32_t shader_state_size
;
537 /** How many shader state records the validator has seen. */
538 uint32_t shader_state_count
;
540 bool found_tile_binning_mode_config_packet
;
541 bool found_start_tile_binning_packet
;
542 bool found_increment_semaphore_packet
;
544 uint8_t bin_tiles_x
, bin_tiles_y
;
545 /* Physical address of the start of the tile alloc array
546 * (where each tile's binned CL will start)
548 uint32_t tile_alloc_offset
;
549 /* Bitmask of which binner slots are freed when this job completes. */
553 * Computed addresses pointing into exec_bo where we start the
554 * bin thread (ct0) and render thread (ct1).
556 uint32_t ct0ca
, ct0ea
;
557 uint32_t ct1ca
, ct1ea
;
559 /* Pointer to the unvalidated bin CL (if present). */
562 /* Pointers to the shader recs. These paddr gets incremented as CL
563 * packets are relocated in validate_gl_shader_state, and the vaddrs
564 * (u and v) get incremented and size decremented as the shader recs
565 * themselves are validated.
569 uint32_t shader_rec_p
;
570 uint32_t shader_rec_size
;
572 /* Pointers to the uniform data. These pointers are incremented, and
573 * size decremented, as each batch of uniforms is uploaded.
578 uint32_t uniforms_size
;
580 /* Pointer to a performance monitor object if the user requested it,
583 struct vc4_perfmon
*perfmon
;
586 /* Per-open file private data. Any driver-specific resource that has to be
587 * released when the DRM file is closed should be placed here.
596 static inline struct vc4_exec_info
*
597 vc4_first_bin_job(struct vc4_dev
*vc4
)
599 return list_first_entry_or_null(&vc4
->bin_job_list
,
600 struct vc4_exec_info
, head
);
603 static inline struct vc4_exec_info
*
604 vc4_first_render_job(struct vc4_dev
*vc4
)
606 return list_first_entry_or_null(&vc4
->render_job_list
,
607 struct vc4_exec_info
, head
);
610 static inline struct vc4_exec_info
*
611 vc4_last_render_job(struct vc4_dev
*vc4
)
613 if (list_empty(&vc4
->render_job_list
))
615 return list_last_entry(&vc4
->render_job_list
,
616 struct vc4_exec_info
, head
);
620 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
623 * This will be used at draw time to relocate the reference to the texture
624 * contents in p0, and validate that the offset combined with
625 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
626 * Note that the hardware treats unprovided config parameters as 0, so not all
627 * of them need to be set up for every texure sample, and we'll store ~0 as
628 * the offset to mark the unused ones.
630 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
631 * Setup") for definitions of the texture parameters.
633 struct vc4_texture_sample_info
{
635 uint32_t p_offset
[4];
639 * struct vc4_validated_shader_info - information about validated shaders that
640 * needs to be used from command list validation.
642 * For a given shader, each time a shader state record references it, we need
643 * to verify that the shader doesn't read more uniforms than the shader state
644 * record's uniform BO pointer can provide, and we need to apply relocations
645 * and validate the shader state record's uniforms that define the texture
648 struct vc4_validated_shader_info
{
649 uint32_t uniforms_size
;
650 uint32_t uniforms_src_size
;
651 uint32_t num_texture_samples
;
652 struct vc4_texture_sample_info
*texture_samples
;
654 uint32_t num_uniform_addr_offsets
;
655 uint32_t *uniform_addr_offsets
;
661 * _wait_for - magic (register) wait macro
663 * Does the right thing for modeset paths when run under kdgb or similar atomic
664 * contexts. Note that it's important that we check the condition again after
665 * having timed out, since the timeout could be due to preemption or similar and
666 * we've never had a chance to check the condition before the timeout.
668 #define _wait_for(COND, MS, W) ({ \
669 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
672 if (time_after(jiffies, timeout__)) { \
674 ret__ = -ETIMEDOUT; \
677 if (W && drm_can_sleep()) { \
686 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
689 struct drm_gem_object
*vc4_create_object(struct drm_device
*dev
, size_t size
);
690 void vc4_free_object(struct drm_gem_object
*gem_obj
);
691 struct vc4_bo
*vc4_bo_create(struct drm_device
*dev
, size_t size
,
692 bool from_cache
, enum vc4_kernel_bo_type type
);
693 int vc4_dumb_create(struct drm_file
*file_priv
,
694 struct drm_device
*dev
,
695 struct drm_mode_create_dumb
*args
);
696 struct dma_buf
*vc4_prime_export(struct drm_device
*dev
,
697 struct drm_gem_object
*obj
, int flags
);
698 int vc4_create_bo_ioctl(struct drm_device
*dev
, void *data
,
699 struct drm_file
*file_priv
);
700 int vc4_create_shader_bo_ioctl(struct drm_device
*dev
, void *data
,
701 struct drm_file
*file_priv
);
702 int vc4_mmap_bo_ioctl(struct drm_device
*dev
, void *data
,
703 struct drm_file
*file_priv
);
704 int vc4_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
705 struct drm_file
*file_priv
);
706 int vc4_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
707 struct drm_file
*file_priv
);
708 int vc4_get_hang_state_ioctl(struct drm_device
*dev
, void *data
,
709 struct drm_file
*file_priv
);
710 int vc4_label_bo_ioctl(struct drm_device
*dev
, void *data
,
711 struct drm_file
*file_priv
);
712 vm_fault_t
vc4_fault(struct vm_fault
*vmf
);
713 int vc4_mmap(struct file
*filp
, struct vm_area_struct
*vma
);
714 int vc4_prime_mmap(struct drm_gem_object
*obj
, struct vm_area_struct
*vma
);
715 struct drm_gem_object
*vc4_prime_import_sg_table(struct drm_device
*dev
,
716 struct dma_buf_attachment
*attach
,
717 struct sg_table
*sgt
);
718 void *vc4_prime_vmap(struct drm_gem_object
*obj
);
719 int vc4_bo_cache_init(struct drm_device
*dev
);
720 void vc4_bo_cache_destroy(struct drm_device
*dev
);
721 int vc4_bo_inc_usecnt(struct vc4_bo
*bo
);
722 void vc4_bo_dec_usecnt(struct vc4_bo
*bo
);
723 void vc4_bo_add_to_purgeable_pool(struct vc4_bo
*bo
);
724 void vc4_bo_remove_from_purgeable_pool(struct vc4_bo
*bo
);
727 extern struct platform_driver vc4_crtc_driver
;
728 bool vc4_crtc_get_scanoutpos(struct drm_device
*dev
, unsigned int crtc_id
,
729 bool in_vblank_irq
, int *vpos
, int *hpos
,
730 ktime_t
*stime
, ktime_t
*etime
,
731 const struct drm_display_mode
*mode
);
732 void vc4_crtc_handle_vblank(struct vc4_crtc
*crtc
);
733 void vc4_crtc_txp_armed(struct drm_crtc_state
*state
);
734 void vc4_crtc_get_margins(struct drm_crtc_state
*state
,
735 unsigned int *right
, unsigned int *left
,
736 unsigned int *top
, unsigned int *bottom
);
739 int vc4_debugfs_init(struct drm_minor
*minor
);
740 #ifdef CONFIG_DEBUG_FS
741 void vc4_debugfs_add_file(struct drm_device
*drm
,
742 const char *filename
,
743 int (*show
)(struct seq_file
*, void*),
745 void vc4_debugfs_add_regset32(struct drm_device
*drm
,
746 const char *filename
,
747 struct debugfs_regset32
*regset
);
749 static inline void vc4_debugfs_add_file(struct drm_device
*drm
,
750 const char *filename
,
751 int (*show
)(struct seq_file
*, void*),
756 static inline void vc4_debugfs_add_regset32(struct drm_device
*drm
,
757 const char *filename
,
758 struct debugfs_regset32
*regset
)
764 void __iomem
*vc4_ioremap_regs(struct platform_device
*dev
, int index
);
767 extern struct platform_driver vc4_dpi_driver
;
770 extern struct platform_driver vc4_dsi_driver
;
773 extern const struct dma_fence_ops vc4_fence_ops
;
776 void vc4_gem_init(struct drm_device
*dev
);
777 void vc4_gem_destroy(struct drm_device
*dev
);
778 int vc4_submit_cl_ioctl(struct drm_device
*dev
, void *data
,
779 struct drm_file
*file_priv
);
780 int vc4_wait_seqno_ioctl(struct drm_device
*dev
, void *data
,
781 struct drm_file
*file_priv
);
782 int vc4_wait_bo_ioctl(struct drm_device
*dev
, void *data
,
783 struct drm_file
*file_priv
);
784 void vc4_submit_next_bin_job(struct drm_device
*dev
);
785 void vc4_submit_next_render_job(struct drm_device
*dev
);
786 void vc4_move_job_to_render(struct drm_device
*dev
, struct vc4_exec_info
*exec
);
787 int vc4_wait_for_seqno(struct drm_device
*dev
, uint64_t seqno
,
788 uint64_t timeout_ns
, bool interruptible
);
789 void vc4_job_handle_completed(struct vc4_dev
*vc4
);
790 int vc4_queue_seqno_cb(struct drm_device
*dev
,
791 struct vc4_seqno_cb
*cb
, uint64_t seqno
,
792 void (*func
)(struct vc4_seqno_cb
*cb
));
793 int vc4_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
794 struct drm_file
*file_priv
);
797 extern struct platform_driver vc4_hdmi_driver
;
800 extern struct platform_driver vc4_vec_driver
;
803 extern struct platform_driver vc4_txp_driver
;
806 irqreturn_t
vc4_irq(int irq
, void *arg
);
807 void vc4_irq_preinstall(struct drm_device
*dev
);
808 int vc4_irq_postinstall(struct drm_device
*dev
);
809 void vc4_irq_uninstall(struct drm_device
*dev
);
810 void vc4_irq_reset(struct drm_device
*dev
);
813 extern struct platform_driver vc4_hvs_driver
;
814 void vc4_hvs_dump_state(struct drm_device
*dev
);
815 void vc4_hvs_unmask_underrun(struct drm_device
*dev
, int channel
);
816 void vc4_hvs_mask_underrun(struct drm_device
*dev
, int channel
);
819 int vc4_kms_load(struct drm_device
*dev
);
822 struct drm_plane
*vc4_plane_init(struct drm_device
*dev
,
823 enum drm_plane_type type
);
824 u32
vc4_plane_write_dlist(struct drm_plane
*plane
, u32 __iomem
*dlist
);
825 u32
vc4_plane_dlist_size(const struct drm_plane_state
*state
);
826 void vc4_plane_async_set_fb(struct drm_plane
*plane
,
827 struct drm_framebuffer
*fb
);
830 extern struct platform_driver vc4_v3d_driver
;
831 extern const struct of_device_id vc4_v3d_dt_match
[];
832 int vc4_v3d_get_bin_slot(struct vc4_dev
*vc4
);
833 int vc4_v3d_pm_get(struct vc4_dev
*vc4
);
834 void vc4_v3d_pm_put(struct vc4_dev
*vc4
);
838 vc4_validate_bin_cl(struct drm_device
*dev
,
841 struct vc4_exec_info
*exec
);
844 vc4_validate_shader_recs(struct drm_device
*dev
, struct vc4_exec_info
*exec
);
846 struct drm_gem_cma_object
*vc4_use_bo(struct vc4_exec_info
*exec
,
849 int vc4_get_rcl(struct drm_device
*dev
, struct vc4_exec_info
*exec
);
851 bool vc4_check_tex_size(struct vc4_exec_info
*exec
,
852 struct drm_gem_cma_object
*fbo
,
853 uint32_t offset
, uint8_t tiling_format
,
854 uint32_t width
, uint32_t height
, uint8_t cpp
);
856 /* vc4_validate_shader.c */
857 struct vc4_validated_shader_info
*
858 vc4_validate_shader(struct drm_gem_cma_object
*shader_obj
);
861 void vc4_perfmon_get(struct vc4_perfmon
*perfmon
);
862 void vc4_perfmon_put(struct vc4_perfmon
*perfmon
);
863 void vc4_perfmon_start(struct vc4_dev
*vc4
, struct vc4_perfmon
*perfmon
);
864 void vc4_perfmon_stop(struct vc4_dev
*vc4
, struct vc4_perfmon
*perfmon
,
866 struct vc4_perfmon
*vc4_perfmon_find(struct vc4_file
*vc4file
, int id
);
867 void vc4_perfmon_open_file(struct vc4_file
*vc4file
);
868 void vc4_perfmon_close_file(struct vc4_file
*vc4file
);
869 int vc4_perfmon_create_ioctl(struct drm_device
*dev
, void *data
,
870 struct drm_file
*file_priv
);
871 int vc4_perfmon_destroy_ioctl(struct drm_device
*dev
, void *data
,
872 struct drm_file
*file_priv
);
873 int vc4_perfmon_get_values_ioctl(struct drm_device
*dev
, void *data
,
874 struct drm_file
*file_priv
);