2 * Copyright (C) 2016 Broadcom
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * DOC: VC4 DSI0/DSI1 module
20 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
21 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
24 * Most Raspberry Pi boards expose DSI1 as their "DISPLAY" connector,
25 * while the compute module brings both DSI0 and DSI1 out.
27 * This driver has been tested for DSI1 video-mode display only
28 * currently, with most of the information necessary for DSI0
32 #include <linux/clk-provider.h>
33 #include <linux/clk.h>
34 #include <linux/completion.h>
35 #include <linux/component.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/dmaengine.h>
38 #include <linux/i2c.h>
40 #include <linux/of_address.h>
41 #include <linux/of_platform.h>
42 #include <linux/pm_runtime.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_edid.h>
46 #include <drm/drm_mipi_dsi.h>
47 #include <drm/drm_of.h>
48 #include <drm/drm_panel.h>
49 #include <drm/drm_probe_helper.h>
54 #define DSI_CMD_FIFO_DEPTH 16
55 #define DSI_PIX_FIFO_DEPTH 256
56 #define DSI_PIX_FIFO_WIDTH 4
58 #define DSI0_CTRL 0x00
60 /* Command packet control. */
61 #define DSI0_TXPKT1C 0x04 /* AKA PKTC */
62 #define DSI1_TXPKT1C 0x04
63 # define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24)
64 # define DSI_TXPKT1C_TRIG_CMD_SHIFT 24
65 # define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10)
66 # define DSI_TXPKT1C_CMD_REPEAT_SHIFT 10
68 # define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8)
69 # define DSI_TXPKT1C_DISPLAY_NO_SHIFT 8
70 /* Short, trigger, BTA, or a long packet that fits all in CMDFIFO. */
71 # define DSI_TXPKT1C_DISPLAY_NO_SHORT 0
72 /* Primary display where cmdfifo provides part of the payload and
73 * pixelvalve the rest.
75 # define DSI_TXPKT1C_DISPLAY_NO_PRIMARY 1
76 /* Secondary display where cmdfifo provides part of the payload and
79 # define DSI_TXPKT1C_DISPLAY_NO_SECONDARY 2
81 # define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6)
82 # define DSI_TXPKT1C_CMD_TX_TIME_SHIFT 6
84 # define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4)
85 # define DSI_TXPKT1C_CMD_CTRL_SHIFT 4
86 /* Command only. Uses TXPKT1H and DISPLAY_NO */
87 # define DSI_TXPKT1C_CMD_CTRL_TX 0
88 /* Command with BTA for either ack or read data. */
89 # define DSI_TXPKT1C_CMD_CTRL_RX 1
90 /* Trigger according to TRIG_CMD */
91 # define DSI_TXPKT1C_CMD_CTRL_TRIG 2
92 /* BTA alone for getting error status after a command, or a TE trigger
93 * without a previous command.
95 # define DSI_TXPKT1C_CMD_CTRL_BTA 3
97 # define DSI_TXPKT1C_CMD_MODE_LP BIT(3)
98 # define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2)
99 # define DSI_TXPKT1C_CMD_TE_EN BIT(1)
100 # define DSI_TXPKT1C_CMD_EN BIT(0)
102 /* Command packet header. */
103 #define DSI0_TXPKT1H 0x08 /* AKA PKTH */
104 #define DSI1_TXPKT1H 0x08
105 # define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24)
106 # define DSI_TXPKT1H_BC_CMDFIFO_SHIFT 24
107 # define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
108 # define DSI_TXPKT1H_BC_PARAM_SHIFT 8
109 # define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0)
110 # define DSI_TXPKT1H_BC_DT_SHIFT 0
112 #define DSI0_RXPKT1H 0x0c /* AKA RX1_PKTH */
113 #define DSI1_RXPKT1H 0x14
114 # define DSI_RXPKT1H_CRC_ERR BIT(31)
115 # define DSI_RXPKT1H_DET_ERR BIT(30)
116 # define DSI_RXPKT1H_ECC_ERR BIT(29)
117 # define DSI_RXPKT1H_COR_ERR BIT(28)
118 # define DSI_RXPKT1H_INCOMP_PKT BIT(25)
119 # define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24)
120 /* Byte count if DSI_RXPKT1H_PKT_TYPE_LONG */
121 # define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
122 # define DSI_RXPKT1H_BC_PARAM_SHIFT 8
123 /* Short return bytes if !DSI_RXPKT1H_PKT_TYPE_LONG */
124 # define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(23, 16)
125 # define DSI_RXPKT1H_SHORT_1_SHIFT 16
126 # define DSI_RXPKT1H_SHORT_0_MASK VC4_MASK(15, 8)
127 # define DSI_RXPKT1H_SHORT_0_SHIFT 8
128 # define DSI_RXPKT1H_DT_LP_CMD_MASK VC4_MASK(7, 0)
129 # define DSI_RXPKT1H_DT_LP_CMD_SHIFT 0
131 #define DSI0_RXPKT2H 0x10 /* AKA RX2_PKTH */
132 #define DSI1_RXPKT2H 0x18
133 # define DSI_RXPKT1H_DET_ERR BIT(30)
134 # define DSI_RXPKT1H_ECC_ERR BIT(29)
135 # define DSI_RXPKT1H_COR_ERR BIT(28)
136 # define DSI_RXPKT1H_INCOMP_PKT BIT(25)
137 # define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
138 # define DSI_RXPKT1H_BC_PARAM_SHIFT 8
139 # define DSI_RXPKT1H_DT_MASK VC4_MASK(7, 0)
140 # define DSI_RXPKT1H_DT_SHIFT 0
142 #define DSI0_TXPKT_CMD_FIFO 0x14 /* AKA CMD_DATAF */
143 #define DSI1_TXPKT_CMD_FIFO 0x1c
145 #define DSI0_DISP0_CTRL 0x18
146 # define DSI_DISP0_PIX_CLK_DIV_MASK VC4_MASK(21, 13)
147 # define DSI_DISP0_PIX_CLK_DIV_SHIFT 13
148 # define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11)
149 # define DSI_DISP0_LP_STOP_CTRL_SHIFT 11
150 # define DSI_DISP0_LP_STOP_DISABLE 0
151 # define DSI_DISP0_LP_STOP_PERLINE 1
152 # define DSI_DISP0_LP_STOP_PERFRAME 2
154 /* Transmit RGB pixels and null packets only during HACTIVE, instead
155 * of going to LP-STOP.
157 # define DSI_DISP_HACTIVE_NULL BIT(10)
158 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
159 # define DSI_DISP_VBLP_CTRL BIT(9)
160 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
161 # define DSI_DISP_HFP_CTRL BIT(8)
162 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
163 # define DSI_DISP_HBP_CTRL BIT(7)
164 # define DSI_DISP0_CHANNEL_MASK VC4_MASK(6, 5)
165 # define DSI_DISP0_CHANNEL_SHIFT 5
166 /* Enables end events for HSYNC/VSYNC, not just start events. */
167 # define DSI_DISP0_ST_END BIT(4)
168 # define DSI_DISP0_PFORMAT_MASK VC4_MASK(3, 2)
169 # define DSI_DISP0_PFORMAT_SHIFT 2
170 # define DSI_PFORMAT_RGB565 0
171 # define DSI_PFORMAT_RGB666_PACKED 1
172 # define DSI_PFORMAT_RGB666 2
173 # define DSI_PFORMAT_RGB888 3
174 /* Default is VIDEO mode. */
175 # define DSI_DISP0_COMMAND_MODE BIT(1)
176 # define DSI_DISP0_ENABLE BIT(0)
178 #define DSI0_DISP1_CTRL 0x1c
179 #define DSI1_DISP1_CTRL 0x2c
180 /* Format of the data written to TXPKT_PIX_FIFO. */
181 # define DSI_DISP1_PFORMAT_MASK VC4_MASK(2, 1)
182 # define DSI_DISP1_PFORMAT_SHIFT 1
183 # define DSI_DISP1_PFORMAT_16BIT 0
184 # define DSI_DISP1_PFORMAT_24BIT 1
185 # define DSI_DISP1_PFORMAT_32BIT_LE 2
186 # define DSI_DISP1_PFORMAT_32BIT_BE 3
188 /* DISP1 is always command mode. */
189 # define DSI_DISP1_ENABLE BIT(0)
191 #define DSI0_TXPKT_PIX_FIFO 0x20 /* AKA PIX_FIFO */
193 #define DSI0_INT_STAT 0x24
194 #define DSI0_INT_EN 0x28
195 # define DSI1_INT_PHY_D3_ULPS BIT(30)
196 # define DSI1_INT_PHY_D3_STOP BIT(29)
197 # define DSI1_INT_PHY_D2_ULPS BIT(28)
198 # define DSI1_INT_PHY_D2_STOP BIT(27)
199 # define DSI1_INT_PHY_D1_ULPS BIT(26)
200 # define DSI1_INT_PHY_D1_STOP BIT(25)
201 # define DSI1_INT_PHY_D0_ULPS BIT(24)
202 # define DSI1_INT_PHY_D0_STOP BIT(23)
203 # define DSI1_INT_FIFO_ERR BIT(22)
204 # define DSI1_INT_PHY_DIR_RTF BIT(21)
205 # define DSI1_INT_PHY_RXLPDT BIT(20)
206 # define DSI1_INT_PHY_RXTRIG BIT(19)
207 # define DSI1_INT_PHY_D0_LPDT BIT(18)
208 # define DSI1_INT_PHY_DIR_FTR BIT(17)
210 /* Signaled when the clock lane enters the given state. */
211 # define DSI1_INT_PHY_CLOCK_ULPS BIT(16)
212 # define DSI1_INT_PHY_CLOCK_HS BIT(15)
213 # define DSI1_INT_PHY_CLOCK_STOP BIT(14)
215 /* Signaled on timeouts */
216 # define DSI1_INT_PR_TO BIT(13)
217 # define DSI1_INT_TA_TO BIT(12)
218 # define DSI1_INT_LPRX_TO BIT(11)
219 # define DSI1_INT_HSTX_TO BIT(10)
221 /* Contention on a line when trying to drive the line low */
222 # define DSI1_INT_ERR_CONT_LP1 BIT(9)
223 # define DSI1_INT_ERR_CONT_LP0 BIT(8)
225 /* Control error: incorrect line state sequence on data lane 0. */
226 # define DSI1_INT_ERR_CONTROL BIT(7)
227 /* LPDT synchronization error (bits received not a multiple of 8. */
229 # define DSI1_INT_ERR_SYNC_ESC BIT(6)
230 /* Signaled after receiving an error packet from the display in
231 * response to a read.
233 # define DSI1_INT_RXPKT2 BIT(5)
234 /* Signaled after receiving a packet. The header and optional short
235 * response will be in RXPKT1H, and a long response will be in the
238 # define DSI1_INT_RXPKT1 BIT(4)
239 # define DSI1_INT_TXPKT2_DONE BIT(3)
240 # define DSI1_INT_TXPKT2_END BIT(2)
241 /* Signaled after all repeats of TXPKT1 are transferred. */
242 # define DSI1_INT_TXPKT1_DONE BIT(1)
243 /* Signaled after each TXPKT1 repeat is scheduled. */
244 # define DSI1_INT_TXPKT1_END BIT(0)
246 #define DSI1_INTERRUPTS_ALWAYS_ENABLED (DSI1_INT_ERR_SYNC_ESC | \
247 DSI1_INT_ERR_CONTROL | \
248 DSI1_INT_ERR_CONT_LP0 | \
249 DSI1_INT_ERR_CONT_LP1 | \
255 #define DSI0_STAT 0x2c
256 #define DSI0_HSTX_TO_CNT 0x30
257 #define DSI0_LPRX_TO_CNT 0x34
258 #define DSI0_TA_TO_CNT 0x38
259 #define DSI0_PR_TO_CNT 0x3c
260 #define DSI0_PHYC 0x40
261 # define DSI1_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(25, 20)
262 # define DSI1_PHYC_ESC_CLK_LPDT_SHIFT 20
263 # define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18)
264 # define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12)
265 # define DSI0_PHYC_ESC_CLK_LPDT_SHIFT 12
266 # define DSI1_PHYC_CLANE_ULPS BIT(17)
267 # define DSI1_PHYC_CLANE_ENABLE BIT(16)
268 # define DSI_PHYC_DLANE3_ULPS BIT(13)
269 # define DSI_PHYC_DLANE3_ENABLE BIT(12)
270 # define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10)
271 # define DSI0_PHYC_CLANE_ULPS BIT(9)
272 # define DSI_PHYC_DLANE2_ULPS BIT(9)
273 # define DSI0_PHYC_CLANE_ENABLE BIT(8)
274 # define DSI_PHYC_DLANE2_ENABLE BIT(8)
275 # define DSI_PHYC_DLANE1_ULPS BIT(5)
276 # define DSI_PHYC_DLANE1_ENABLE BIT(4)
277 # define DSI_PHYC_DLANE0_FORCE_STOP BIT(2)
278 # define DSI_PHYC_DLANE0_ULPS BIT(1)
279 # define DSI_PHYC_DLANE0_ENABLE BIT(0)
281 #define DSI0_HS_CLT0 0x44
282 #define DSI0_HS_CLT1 0x48
283 #define DSI0_HS_CLT2 0x4c
284 #define DSI0_HS_DLT3 0x50
285 #define DSI0_HS_DLT4 0x54
286 #define DSI0_HS_DLT5 0x58
287 #define DSI0_HS_DLT6 0x5c
288 #define DSI0_HS_DLT7 0x60
290 #define DSI0_PHY_AFEC0 0x64
291 # define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26)
292 # define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25)
293 # define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24)
294 # define DSI1_PHY_AFEC0_IDR_DLANE3_MASK VC4_MASK(31, 29)
295 # define DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT 29
296 # define DSI1_PHY_AFEC0_IDR_DLANE2_MASK VC4_MASK(28, 26)
297 # define DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT 26
298 # define DSI1_PHY_AFEC0_IDR_DLANE1_MASK VC4_MASK(27, 23)
299 # define DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT 23
300 # define DSI1_PHY_AFEC0_IDR_DLANE0_MASK VC4_MASK(22, 20)
301 # define DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT 20
302 # define DSI1_PHY_AFEC0_IDR_CLANE_MASK VC4_MASK(19, 17)
303 # define DSI1_PHY_AFEC0_IDR_CLANE_SHIFT 17
304 # define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK VC4_MASK(23, 20)
305 # define DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT 20
306 # define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK VC4_MASK(19, 16)
307 # define DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT 16
308 # define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12)
309 # define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT 12
310 # define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16)
311 # define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15)
312 # define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14)
313 # define DSI1_PHY_AFEC0_RESET BIT(13)
314 # define DSI1_PHY_AFEC0_PD BIT(12)
315 # define DSI0_PHY_AFEC0_RESET BIT(11)
316 # define DSI1_PHY_AFEC0_PD_BG BIT(11)
317 # define DSI0_PHY_AFEC0_PD BIT(10)
318 # define DSI1_PHY_AFEC0_PD_DLANE3 BIT(10)
319 # define DSI0_PHY_AFEC0_PD_BG BIT(9)
320 # define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9)
321 # define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8)
322 # define DSI1_PHY_AFEC0_PD_DLANE1 BIT(8)
323 # define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4)
324 # define DSI_PHY_AFEC0_PTATADJ_SHIFT 4
325 # define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0)
326 # define DSI_PHY_AFEC0_CTATADJ_SHIFT 0
328 #define DSI0_PHY_AFEC1 0x68
329 # define DSI0_PHY_AFEC1_IDR_DLANE1_MASK VC4_MASK(10, 8)
330 # define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT 8
331 # define DSI0_PHY_AFEC1_IDR_DLANE0_MASK VC4_MASK(6, 4)
332 # define DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT 4
333 # define DSI0_PHY_AFEC1_IDR_CLANE_MASK VC4_MASK(2, 0)
334 # define DSI0_PHY_AFEC1_IDR_CLANE_SHIFT 0
336 #define DSI0_TST_SEL 0x6c
337 #define DSI0_TST_MON 0x70
339 # define DSI_ID_VALUE 0x00647369
341 #define DSI1_CTRL 0x00
342 # define DSI_CTRL_HS_CLKC_MASK VC4_MASK(15, 14)
343 # define DSI_CTRL_HS_CLKC_SHIFT 14
344 # define DSI_CTRL_HS_CLKC_BYTE 0
345 # define DSI_CTRL_HS_CLKC_DDR2 1
346 # define DSI_CTRL_HS_CLKC_DDR 2
348 # define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13)
349 # define DSI_CTRL_LPDT_EOT_DISABLE BIT(12)
350 # define DSI_CTRL_HSDT_EOT_DISABLE BIT(11)
351 # define DSI_CTRL_SOFT_RESET_CFG BIT(10)
352 # define DSI_CTRL_CAL_BYTE BIT(9)
353 # define DSI_CTRL_INV_BYTE BIT(8)
354 # define DSI_CTRL_CLR_LDF BIT(7)
355 # define DSI0_CTRL_CLR_PBCF BIT(6)
356 # define DSI1_CTRL_CLR_RXF BIT(6)
357 # define DSI0_CTRL_CLR_CPBCF BIT(5)
358 # define DSI1_CTRL_CLR_PDF BIT(5)
359 # define DSI0_CTRL_CLR_PDF BIT(4)
360 # define DSI1_CTRL_CLR_CDF BIT(4)
361 # define DSI0_CTRL_CLR_CDF BIT(3)
362 # define DSI0_CTRL_CTRL2 BIT(2)
363 # define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2)
364 # define DSI0_CTRL_CTRL1 BIT(1)
365 # define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1)
366 # define DSI0_CTRL_CTRL0 BIT(0)
367 # define DSI1_CTRL_EN BIT(0)
368 # define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
369 DSI0_CTRL_CLR_PBCF | \
370 DSI0_CTRL_CLR_CPBCF | \
371 DSI0_CTRL_CLR_PDF | \
373 # define DSI1_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
374 DSI1_CTRL_CLR_RXF | \
375 DSI1_CTRL_CLR_PDF | \
378 #define DSI1_TXPKT2C 0x0c
379 #define DSI1_TXPKT2H 0x10
380 #define DSI1_TXPKT_PIX_FIFO 0x20
381 #define DSI1_RXPKT_FIFO 0x24
382 #define DSI1_DISP0_CTRL 0x28
383 #define DSI1_INT_STAT 0x30
384 #define DSI1_INT_EN 0x34
385 /* State reporting bits. These mostly behave like INT_STAT, where
386 * writing a 1 clears the bit.
388 #define DSI1_STAT 0x38
389 # define DSI1_STAT_PHY_D3_ULPS BIT(31)
390 # define DSI1_STAT_PHY_D3_STOP BIT(30)
391 # define DSI1_STAT_PHY_D2_ULPS BIT(29)
392 # define DSI1_STAT_PHY_D2_STOP BIT(28)
393 # define DSI1_STAT_PHY_D1_ULPS BIT(27)
394 # define DSI1_STAT_PHY_D1_STOP BIT(26)
395 # define DSI1_STAT_PHY_D0_ULPS BIT(25)
396 # define DSI1_STAT_PHY_D0_STOP BIT(24)
397 # define DSI1_STAT_FIFO_ERR BIT(23)
398 # define DSI1_STAT_PHY_RXLPDT BIT(22)
399 # define DSI1_STAT_PHY_RXTRIG BIT(21)
400 # define DSI1_STAT_PHY_D0_LPDT BIT(20)
401 /* Set when in forward direction */
402 # define DSI1_STAT_PHY_DIR BIT(19)
403 # define DSI1_STAT_PHY_CLOCK_ULPS BIT(18)
404 # define DSI1_STAT_PHY_CLOCK_HS BIT(17)
405 # define DSI1_STAT_PHY_CLOCK_STOP BIT(16)
406 # define DSI1_STAT_PR_TO BIT(15)
407 # define DSI1_STAT_TA_TO BIT(14)
408 # define DSI1_STAT_LPRX_TO BIT(13)
409 # define DSI1_STAT_HSTX_TO BIT(12)
410 # define DSI1_STAT_ERR_CONT_LP1 BIT(11)
411 # define DSI1_STAT_ERR_CONT_LP0 BIT(10)
412 # define DSI1_STAT_ERR_CONTROL BIT(9)
413 # define DSI1_STAT_ERR_SYNC_ESC BIT(8)
414 # define DSI1_STAT_RXPKT2 BIT(7)
415 # define DSI1_STAT_RXPKT1 BIT(6)
416 # define DSI1_STAT_TXPKT2_BUSY BIT(5)
417 # define DSI1_STAT_TXPKT2_DONE BIT(4)
418 # define DSI1_STAT_TXPKT2_END BIT(3)
419 # define DSI1_STAT_TXPKT1_BUSY BIT(2)
420 # define DSI1_STAT_TXPKT1_DONE BIT(1)
421 # define DSI1_STAT_TXPKT1_END BIT(0)
423 #define DSI1_HSTX_TO_CNT 0x3c
424 #define DSI1_LPRX_TO_CNT 0x40
425 #define DSI1_TA_TO_CNT 0x44
426 #define DSI1_PR_TO_CNT 0x48
427 #define DSI1_PHYC 0x4c
429 #define DSI1_HS_CLT0 0x50
430 # define DSI_HS_CLT0_CZERO_MASK VC4_MASK(26, 18)
431 # define DSI_HS_CLT0_CZERO_SHIFT 18
432 # define DSI_HS_CLT0_CPRE_MASK VC4_MASK(17, 9)
433 # define DSI_HS_CLT0_CPRE_SHIFT 9
434 # define DSI_HS_CLT0_CPREP_MASK VC4_MASK(8, 0)
435 # define DSI_HS_CLT0_CPREP_SHIFT 0
437 #define DSI1_HS_CLT1 0x54
438 # define DSI_HS_CLT1_CTRAIL_MASK VC4_MASK(17, 9)
439 # define DSI_HS_CLT1_CTRAIL_SHIFT 9
440 # define DSI_HS_CLT1_CPOST_MASK VC4_MASK(8, 0)
441 # define DSI_HS_CLT1_CPOST_SHIFT 0
443 #define DSI1_HS_CLT2 0x58
444 # define DSI_HS_CLT2_WUP_MASK VC4_MASK(23, 0)
445 # define DSI_HS_CLT2_WUP_SHIFT 0
447 #define DSI1_HS_DLT3 0x5c
448 # define DSI_HS_DLT3_EXIT_MASK VC4_MASK(26, 18)
449 # define DSI_HS_DLT3_EXIT_SHIFT 18
450 # define DSI_HS_DLT3_ZERO_MASK VC4_MASK(17, 9)
451 # define DSI_HS_DLT3_ZERO_SHIFT 9
452 # define DSI_HS_DLT3_PRE_MASK VC4_MASK(8, 0)
453 # define DSI_HS_DLT3_PRE_SHIFT 0
455 #define DSI1_HS_DLT4 0x60
456 # define DSI_HS_DLT4_ANLAT_MASK VC4_MASK(22, 18)
457 # define DSI_HS_DLT4_ANLAT_SHIFT 18
458 # define DSI_HS_DLT4_TRAIL_MASK VC4_MASK(17, 9)
459 # define DSI_HS_DLT4_TRAIL_SHIFT 9
460 # define DSI_HS_DLT4_LPX_MASK VC4_MASK(8, 0)
461 # define DSI_HS_DLT4_LPX_SHIFT 0
463 #define DSI1_HS_DLT5 0x64
464 # define DSI_HS_DLT5_INIT_MASK VC4_MASK(23, 0)
465 # define DSI_HS_DLT5_INIT_SHIFT 0
467 #define DSI1_HS_DLT6 0x68
468 # define DSI_HS_DLT6_TA_GET_MASK VC4_MASK(31, 24)
469 # define DSI_HS_DLT6_TA_GET_SHIFT 24
470 # define DSI_HS_DLT6_TA_SURE_MASK VC4_MASK(23, 16)
471 # define DSI_HS_DLT6_TA_SURE_SHIFT 16
472 # define DSI_HS_DLT6_TA_GO_MASK VC4_MASK(15, 8)
473 # define DSI_HS_DLT6_TA_GO_SHIFT 8
474 # define DSI_HS_DLT6_LP_LPX_MASK VC4_MASK(7, 0)
475 # define DSI_HS_DLT6_LP_LPX_SHIFT 0
477 #define DSI1_HS_DLT7 0x6c
478 # define DSI_HS_DLT7_LP_WUP_MASK VC4_MASK(23, 0)
479 # define DSI_HS_DLT7_LP_WUP_SHIFT 0
481 #define DSI1_PHY_AFEC0 0x70
483 #define DSI1_PHY_AFEC1 0x74
484 # define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK VC4_MASK(19, 16)
485 # define DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT 16
486 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12)
487 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT 12
488 # define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK VC4_MASK(11, 8)
489 # define DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT 8
490 # define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK VC4_MASK(7, 4)
491 # define DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT 4
492 # define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK VC4_MASK(3, 0)
493 # define DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT 0
495 #define DSI1_TST_SEL 0x78
496 #define DSI1_TST_MON 0x7c
497 #define DSI1_PHY_TST1 0x80
498 #define DSI1_PHY_TST2 0x84
499 #define DSI1_PHY_FIFO_STAT 0x88
500 /* Actually, all registers in the range that aren't otherwise claimed
501 * will return the ID.
505 /* General DSI hardware state. */
507 struct platform_device
*pdev
;
509 struct mipi_dsi_host dsi_host
;
510 struct drm_encoder
*encoder
;
511 struct drm_bridge
*bridge
;
515 struct dma_chan
*reg_dma_chan
;
516 dma_addr_t reg_dma_paddr
;
518 dma_addr_t reg_paddr
;
520 /* Whether we're on bcm2835's DSI0 or DSI1. */
523 /* DSI channel for the panel we're connected to. */
530 /* Input clock from CPRMAN to the digital PHY, for the DSI
533 struct clk
*escape_clock
;
535 /* Input clock to the analog PHY, used to generate the DSI bit
538 struct clk
*pll_phy_clock
;
540 /* HS Clocks generated within the DSI analog PHY. */
541 struct clk_fixed_factor phy_clocks
[3];
543 struct clk_hw_onecell_data
*clk_onecell
;
545 /* Pixel clock output to the pixelvalve, generated from the HS
548 struct clk
*pixel_clock
;
550 struct completion xfer_completion
;
553 struct debugfs_regset32 regset
;
556 #define host_to_dsi(host) container_of(host, struct vc4_dsi, dsi_host)
559 dsi_dma_workaround_write(struct vc4_dsi
*dsi
, u32 offset
, u32 val
)
561 struct dma_chan
*chan
= dsi
->reg_dma_chan
;
562 struct dma_async_tx_descriptor
*tx
;
566 /* DSI0 should be able to write normally. */
568 writel(val
, dsi
->regs
+ offset
);
572 *dsi
->reg_dma_mem
= val
;
574 tx
= chan
->device
->device_prep_dma_memcpy(chan
,
575 dsi
->reg_paddr
+ offset
,
579 DRM_ERROR("Failed to set up DMA register write\n");
583 cookie
= tx
->tx_submit(tx
);
584 ret
= dma_submit_error(cookie
);
586 DRM_ERROR("Failed to submit DMA: %d\n", ret
);
589 ret
= dma_sync_wait(chan
, cookie
);
591 DRM_ERROR("Failed to wait for DMA: %d\n", ret
);
594 #define DSI_READ(offset) readl(dsi->regs + (offset))
595 #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
596 #define DSI_PORT_READ(offset) \
597 DSI_READ(dsi->port ? DSI1_##offset : DSI0_##offset)
598 #define DSI_PORT_WRITE(offset, val) \
599 DSI_WRITE(dsi->port ? DSI1_##offset : DSI0_##offset, val)
600 #define DSI_PORT_BIT(bit) (dsi->port ? DSI1_##bit : DSI0_##bit)
602 /* VC4 DSI encoder KMS struct */
603 struct vc4_dsi_encoder
{
604 struct vc4_encoder base
;
608 static inline struct vc4_dsi_encoder
*
609 to_vc4_dsi_encoder(struct drm_encoder
*encoder
)
611 return container_of(encoder
, struct vc4_dsi_encoder
, base
.base
);
614 static const struct debugfs_reg32 dsi0_regs
[] = {
615 VC4_REG32(DSI0_CTRL
),
616 VC4_REG32(DSI0_STAT
),
617 VC4_REG32(DSI0_HSTX_TO_CNT
),
618 VC4_REG32(DSI0_LPRX_TO_CNT
),
619 VC4_REG32(DSI0_TA_TO_CNT
),
620 VC4_REG32(DSI0_PR_TO_CNT
),
621 VC4_REG32(DSI0_DISP0_CTRL
),
622 VC4_REG32(DSI0_DISP1_CTRL
),
623 VC4_REG32(DSI0_INT_STAT
),
624 VC4_REG32(DSI0_INT_EN
),
625 VC4_REG32(DSI0_PHYC
),
626 VC4_REG32(DSI0_HS_CLT0
),
627 VC4_REG32(DSI0_HS_CLT1
),
628 VC4_REG32(DSI0_HS_CLT2
),
629 VC4_REG32(DSI0_HS_DLT3
),
630 VC4_REG32(DSI0_HS_DLT4
),
631 VC4_REG32(DSI0_HS_DLT5
),
632 VC4_REG32(DSI0_HS_DLT6
),
633 VC4_REG32(DSI0_HS_DLT7
),
634 VC4_REG32(DSI0_PHY_AFEC0
),
635 VC4_REG32(DSI0_PHY_AFEC1
),
639 static const struct debugfs_reg32 dsi1_regs
[] = {
640 VC4_REG32(DSI1_CTRL
),
641 VC4_REG32(DSI1_STAT
),
642 VC4_REG32(DSI1_HSTX_TO_CNT
),
643 VC4_REG32(DSI1_LPRX_TO_CNT
),
644 VC4_REG32(DSI1_TA_TO_CNT
),
645 VC4_REG32(DSI1_PR_TO_CNT
),
646 VC4_REG32(DSI1_DISP0_CTRL
),
647 VC4_REG32(DSI1_DISP1_CTRL
),
648 VC4_REG32(DSI1_INT_STAT
),
649 VC4_REG32(DSI1_INT_EN
),
650 VC4_REG32(DSI1_PHYC
),
651 VC4_REG32(DSI1_HS_CLT0
),
652 VC4_REG32(DSI1_HS_CLT1
),
653 VC4_REG32(DSI1_HS_CLT2
),
654 VC4_REG32(DSI1_HS_DLT3
),
655 VC4_REG32(DSI1_HS_DLT4
),
656 VC4_REG32(DSI1_HS_DLT5
),
657 VC4_REG32(DSI1_HS_DLT6
),
658 VC4_REG32(DSI1_HS_DLT7
),
659 VC4_REG32(DSI1_PHY_AFEC0
),
660 VC4_REG32(DSI1_PHY_AFEC1
),
664 static void vc4_dsi_encoder_destroy(struct drm_encoder
*encoder
)
666 drm_encoder_cleanup(encoder
);
669 static const struct drm_encoder_funcs vc4_dsi_encoder_funcs
= {
670 .destroy
= vc4_dsi_encoder_destroy
,
673 static void vc4_dsi_latch_ulps(struct vc4_dsi
*dsi
, bool latch
)
675 u32 afec0
= DSI_PORT_READ(PHY_AFEC0
);
678 afec0
|= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS
);
680 afec0
&= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS
);
682 DSI_PORT_WRITE(PHY_AFEC0
, afec0
);
685 /* Enters or exits Ultra Low Power State. */
686 static void vc4_dsi_ulps(struct vc4_dsi
*dsi
, bool ulps
)
688 bool non_continuous
= dsi
->mode_flags
& MIPI_DSI_CLOCK_NON_CONTINUOUS
;
689 u32 phyc_ulps
= ((non_continuous
? DSI_PORT_BIT(PHYC_CLANE_ULPS
) : 0) |
690 DSI_PHYC_DLANE0_ULPS
|
691 (dsi
->lanes
> 1 ? DSI_PHYC_DLANE1_ULPS
: 0) |
692 (dsi
->lanes
> 2 ? DSI_PHYC_DLANE2_ULPS
: 0) |
693 (dsi
->lanes
> 3 ? DSI_PHYC_DLANE3_ULPS
: 0));
694 u32 stat_ulps
= ((non_continuous
? DSI1_STAT_PHY_CLOCK_ULPS
: 0) |
695 DSI1_STAT_PHY_D0_ULPS
|
696 (dsi
->lanes
> 1 ? DSI1_STAT_PHY_D1_ULPS
: 0) |
697 (dsi
->lanes
> 2 ? DSI1_STAT_PHY_D2_ULPS
: 0) |
698 (dsi
->lanes
> 3 ? DSI1_STAT_PHY_D3_ULPS
: 0));
699 u32 stat_stop
= ((non_continuous
? DSI1_STAT_PHY_CLOCK_STOP
: 0) |
700 DSI1_STAT_PHY_D0_STOP
|
701 (dsi
->lanes
> 1 ? DSI1_STAT_PHY_D1_STOP
: 0) |
702 (dsi
->lanes
> 2 ? DSI1_STAT_PHY_D2_STOP
: 0) |
703 (dsi
->lanes
> 3 ? DSI1_STAT_PHY_D3_STOP
: 0));
705 bool ulps_currently_enabled
= (DSI_PORT_READ(PHY_AFEC0
) &
706 DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS
));
708 if (ulps
== ulps_currently_enabled
)
711 DSI_PORT_WRITE(STAT
, stat_ulps
);
712 DSI_PORT_WRITE(PHYC
, DSI_PORT_READ(PHYC
) | phyc_ulps
);
713 ret
= wait_for((DSI_PORT_READ(STAT
) & stat_ulps
) == stat_ulps
, 200);
715 dev_warn(&dsi
->pdev
->dev
,
716 "Timeout waiting for DSI ULPS entry: STAT 0x%08x",
717 DSI_PORT_READ(STAT
));
718 DSI_PORT_WRITE(PHYC
, DSI_PORT_READ(PHYC
) & ~phyc_ulps
);
719 vc4_dsi_latch_ulps(dsi
, false);
723 /* The DSI module can't be disabled while the module is
724 * generating ULPS state. So, to be able to disable the
725 * module, we have the AFE latch the ULPS state and continue
726 * on to having the module enter STOP.
728 vc4_dsi_latch_ulps(dsi
, ulps
);
730 DSI_PORT_WRITE(STAT
, stat_stop
);
731 DSI_PORT_WRITE(PHYC
, DSI_PORT_READ(PHYC
) & ~phyc_ulps
);
732 ret
= wait_for((DSI_PORT_READ(STAT
) & stat_stop
) == stat_stop
, 200);
734 dev_warn(&dsi
->pdev
->dev
,
735 "Timeout waiting for DSI STOP entry: STAT 0x%08x",
736 DSI_PORT_READ(STAT
));
737 DSI_PORT_WRITE(PHYC
, DSI_PORT_READ(PHYC
) & ~phyc_ulps
);
743 dsi_hs_timing(u32 ui_ns
, u32 ns
, u32 ui
)
745 /* The HS timings have to be rounded up to a multiple of 8
746 * because we're using the byte clock.
748 return roundup(ui
+ DIV_ROUND_UP(ns
, ui_ns
), 8);
751 /* ESC always runs at 100Mhz. */
752 #define ESC_TIME_NS 10
755 dsi_esc_timing(u32 ns
)
757 return DIV_ROUND_UP(ns
, ESC_TIME_NS
);
760 static void vc4_dsi_encoder_disable(struct drm_encoder
*encoder
)
762 struct vc4_dsi_encoder
*vc4_encoder
= to_vc4_dsi_encoder(encoder
);
763 struct vc4_dsi
*dsi
= vc4_encoder
->dsi
;
764 struct device
*dev
= &dsi
->pdev
->dev
;
766 drm_bridge_disable(dsi
->bridge
);
767 vc4_dsi_ulps(dsi
, true);
768 drm_bridge_post_disable(dsi
->bridge
);
770 clk_disable_unprepare(dsi
->pll_phy_clock
);
771 clk_disable_unprepare(dsi
->escape_clock
);
772 clk_disable_unprepare(dsi
->pixel_clock
);
777 /* Extends the mode's blank intervals to handle BCM2835's integer-only
780 * On 2835, PLLD is set to 2Ghz, and may not be changed by the display
781 * driver since most peripherals are hanging off of the PLLD_PER
782 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore
783 * the pixel clock), only has an integer divider off of DSI.
785 * To get our panel mode to refresh at the expected 60Hz, we need to
786 * extend the horizontal blank time. This means we drive a
787 * higher-than-expected clock rate to the panel, but that's what the
790 static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder
*encoder
,
791 const struct drm_display_mode
*mode
,
792 struct drm_display_mode
*adjusted_mode
)
794 struct vc4_dsi_encoder
*vc4_encoder
= to_vc4_dsi_encoder(encoder
);
795 struct vc4_dsi
*dsi
= vc4_encoder
->dsi
;
796 struct clk
*phy_parent
= clk_get_parent(dsi
->pll_phy_clock
);
797 unsigned long parent_rate
= clk_get_rate(phy_parent
);
798 unsigned long pixel_clock_hz
= mode
->clock
* 1000;
799 unsigned long pll_clock
= pixel_clock_hz
* dsi
->divider
;
802 /* Find what divider gets us a faster clock than the requested
805 for (divider
= 1; divider
< 8; divider
++) {
806 if (parent_rate
/ divider
< pll_clock
) {
812 /* Now that we've picked a PLL divider, calculate back to its
815 pll_clock
= parent_rate
/ divider
;
816 pixel_clock_hz
= pll_clock
/ dsi
->divider
;
818 adjusted_mode
->clock
= pixel_clock_hz
/ 1000;
820 /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
821 adjusted_mode
->htotal
= adjusted_mode
->clock
* mode
->htotal
/
823 adjusted_mode
->hsync_end
+= adjusted_mode
->htotal
- mode
->htotal
;
824 adjusted_mode
->hsync_start
+= adjusted_mode
->htotal
- mode
->htotal
;
829 static void vc4_dsi_encoder_enable(struct drm_encoder
*encoder
)
831 struct drm_display_mode
*mode
= &encoder
->crtc
->state
->adjusted_mode
;
832 struct vc4_dsi_encoder
*vc4_encoder
= to_vc4_dsi_encoder(encoder
);
833 struct vc4_dsi
*dsi
= vc4_encoder
->dsi
;
834 struct device
*dev
= &dsi
->pdev
->dev
;
835 bool debug_dump_regs
= false;
836 unsigned long hs_clock
;
838 /* Minimum LP state duration in escape clock cycles. */
839 u32 lpx
= dsi_esc_timing(60);
840 unsigned long pixel_clock_hz
= mode
->clock
* 1000;
841 unsigned long dsip_clock
;
842 unsigned long phy_clock
;
845 ret
= pm_runtime_get_sync(dev
);
847 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi
->port
);
851 if (debug_dump_regs
) {
852 struct drm_printer p
= drm_info_printer(&dsi
->pdev
->dev
);
853 dev_info(&dsi
->pdev
->dev
, "DSI regs before:\n");
854 drm_print_regset32(&p
, &dsi
->regset
);
857 /* Round up the clk_set_rate() request slightly, since
858 * PLLD_DSI1 is an integer divider and its rate selection will
861 phy_clock
= (pixel_clock_hz
+ 1000) * dsi
->divider
;
862 ret
= clk_set_rate(dsi
->pll_phy_clock
, phy_clock
);
864 dev_err(&dsi
->pdev
->dev
,
865 "Failed to set phy clock to %ld: %d\n", phy_clock
, ret
);
868 /* Reset the DSI and all its fifos. */
870 DSI_CTRL_SOFT_RESET_CFG
|
871 DSI_PORT_BIT(CTRL_RESET_FIFOS
));
874 DSI_CTRL_HSDT_EOT_DISABLE
|
875 DSI_CTRL_RX_LPDT_EOT_DISABLE
);
877 /* Clear all stat bits so we see what has happened during enable. */
878 DSI_PORT_WRITE(STAT
, DSI_PORT_READ(STAT
));
880 /* Set AFE CTR00/CTR1 to release powerdown of analog. */
881 if (dsi
->port
== 0) {
882 u32 afec0
= (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ
) |
883 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ
));
886 afec0
|= DSI0_PHY_AFEC0_PD_DLANE1
;
888 if (!(dsi
->mode_flags
& MIPI_DSI_MODE_VIDEO
))
889 afec0
|= DSI0_PHY_AFEC0_RESET
;
891 DSI_PORT_WRITE(PHY_AFEC0
, afec0
);
893 DSI_PORT_WRITE(PHY_AFEC1
,
894 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1
) |
895 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0
) |
896 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE
));
898 u32 afec0
= (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ
) |
899 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ
) |
900 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE
) |
901 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0
) |
902 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1
) |
903 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2
) |
904 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3
));
907 afec0
|= DSI1_PHY_AFEC0_PD_DLANE3
;
909 afec0
|= DSI1_PHY_AFEC0_PD_DLANE2
;
911 afec0
|= DSI1_PHY_AFEC0_PD_DLANE1
;
913 afec0
|= DSI1_PHY_AFEC0_RESET
;
915 DSI_PORT_WRITE(PHY_AFEC0
, afec0
);
917 DSI_PORT_WRITE(PHY_AFEC1
, 0);
919 /* AFEC reset hold time */
923 ret
= clk_prepare_enable(dsi
->escape_clock
);
925 DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret
);
929 ret
= clk_prepare_enable(dsi
->pll_phy_clock
);
931 DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret
);
935 hs_clock
= clk_get_rate(dsi
->pll_phy_clock
);
937 /* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate,
938 * not the pixel clock rate. DSIxP take from the APHY's byte,
939 * DDR2, or DDR4 clock (we use byte) and feed into the PV at
940 * that rate. Separately, a value derived from PIX_CLK_DIV
941 * and HS_CLKC is fed into the PV to divide down to the actual
942 * pixel clock for pushing pixels into DSI.
944 dsip_clock
= phy_clock
/ 8;
945 ret
= clk_set_rate(dsi
->pixel_clock
, dsip_clock
);
947 dev_err(dev
, "Failed to set pixel clock to %ldHz: %d\n",
951 ret
= clk_prepare_enable(dsi
->pixel_clock
);
953 DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret
);
957 /* How many ns one DSI unit interval is. Note that the clock
958 * is DDR, so there's an extra divide by 2.
960 ui_ns
= DIV_ROUND_UP(500000000, hs_clock
);
962 DSI_PORT_WRITE(HS_CLT0
,
963 VC4_SET_FIELD(dsi_hs_timing(ui_ns
, 262, 0),
965 VC4_SET_FIELD(dsi_hs_timing(ui_ns
, 0, 8),
967 VC4_SET_FIELD(dsi_hs_timing(ui_ns
, 38, 0),
970 DSI_PORT_WRITE(HS_CLT1
,
971 VC4_SET_FIELD(dsi_hs_timing(ui_ns
, 60, 0),
972 DSI_HS_CLT1_CTRAIL
) |
973 VC4_SET_FIELD(dsi_hs_timing(ui_ns
, 60, 52),
976 DSI_PORT_WRITE(HS_CLT2
,
977 VC4_SET_FIELD(dsi_hs_timing(ui_ns
, 1000000, 0),
980 DSI_PORT_WRITE(HS_DLT3
,
981 VC4_SET_FIELD(dsi_hs_timing(ui_ns
, 100, 0),
983 VC4_SET_FIELD(dsi_hs_timing(ui_ns
, 105, 6),
985 VC4_SET_FIELD(dsi_hs_timing(ui_ns
, 40, 4),
988 DSI_PORT_WRITE(HS_DLT4
,
989 VC4_SET_FIELD(dsi_hs_timing(ui_ns
, lpx
* ESC_TIME_NS
, 0),
991 VC4_SET_FIELD(max(dsi_hs_timing(ui_ns
, 0, 8),
992 dsi_hs_timing(ui_ns
, 60, 4)),
994 VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT
));
996 /* T_INIT is how long STOP is driven after power-up to
997 * indicate to the slave (also coming out of power-up) that
998 * master init is complete, and should be greater than the
999 * maximum of two value: T_INIT,MASTER and T_INIT,SLAVE. The
1000 * D-PHY spec gives a minimum 100us for T_INIT,MASTER and
1001 * T_INIT,SLAVE, while allowing protocols on top of it to give
1002 * greater minimums. The vc4 firmware uses an extremely
1003 * conservative 5ms, and we maintain that here.
1005 DSI_PORT_WRITE(HS_DLT5
, VC4_SET_FIELD(dsi_hs_timing(ui_ns
,
1006 5 * 1000 * 1000, 0),
1009 DSI_PORT_WRITE(HS_DLT6
,
1010 VC4_SET_FIELD(lpx
* 5, DSI_HS_DLT6_TA_GET
) |
1011 VC4_SET_FIELD(lpx
, DSI_HS_DLT6_TA_SURE
) |
1012 VC4_SET_FIELD(lpx
* 4, DSI_HS_DLT6_TA_GO
) |
1013 VC4_SET_FIELD(lpx
, DSI_HS_DLT6_LP_LPX
));
1015 DSI_PORT_WRITE(HS_DLT7
,
1016 VC4_SET_FIELD(dsi_esc_timing(1000000),
1017 DSI_HS_DLT7_LP_WUP
));
1019 DSI_PORT_WRITE(PHYC
,
1020 DSI_PHYC_DLANE0_ENABLE
|
1021 (dsi
->lanes
>= 2 ? DSI_PHYC_DLANE1_ENABLE
: 0) |
1022 (dsi
->lanes
>= 3 ? DSI_PHYC_DLANE2_ENABLE
: 0) |
1023 (dsi
->lanes
>= 4 ? DSI_PHYC_DLANE3_ENABLE
: 0) |
1024 DSI_PORT_BIT(PHYC_CLANE_ENABLE
) |
1025 ((dsi
->mode_flags
& MIPI_DSI_CLOCK_NON_CONTINUOUS
) ?
1026 0 : DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS
)) |
1028 VC4_SET_FIELD(lpx
- 1, DSI0_PHYC_ESC_CLK_LPDT
) :
1029 VC4_SET_FIELD(lpx
- 1, DSI1_PHYC_ESC_CLK_LPDT
)));
1031 DSI_PORT_WRITE(CTRL
,
1032 DSI_PORT_READ(CTRL
) |
1035 /* HS timeout in HS clock cycles: disabled. */
1036 DSI_PORT_WRITE(HSTX_TO_CNT
, 0);
1037 /* LP receive timeout in HS clocks. */
1038 DSI_PORT_WRITE(LPRX_TO_CNT
, 0xffffff);
1039 /* Bus turnaround timeout */
1040 DSI_PORT_WRITE(TA_TO_CNT
, 100000);
1041 /* Display reset sequence timeout */
1042 DSI_PORT_WRITE(PR_TO_CNT
, 100000);
1044 /* Set up DISP1 for transferring long command payloads through
1047 DSI_PORT_WRITE(DISP1_CTRL
,
1048 VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE
,
1049 DSI_DISP1_PFORMAT
) |
1052 /* Ungate the block. */
1054 DSI_PORT_WRITE(CTRL
, DSI_PORT_READ(CTRL
) | DSI0_CTRL_CTRL0
);
1056 DSI_PORT_WRITE(CTRL
, DSI_PORT_READ(CTRL
) | DSI1_CTRL_EN
);
1058 /* Bring AFE out of reset. */
1059 if (dsi
->port
== 0) {
1061 DSI_PORT_WRITE(PHY_AFEC0
,
1062 DSI_PORT_READ(PHY_AFEC0
) &
1063 ~DSI1_PHY_AFEC0_RESET
);
1066 vc4_dsi_ulps(dsi
, false);
1068 drm_bridge_pre_enable(dsi
->bridge
);
1070 if (dsi
->mode_flags
& MIPI_DSI_MODE_VIDEO
) {
1071 DSI_PORT_WRITE(DISP0_CTRL
,
1072 VC4_SET_FIELD(dsi
->divider
,
1073 DSI_DISP0_PIX_CLK_DIV
) |
1074 VC4_SET_FIELD(dsi
->format
, DSI_DISP0_PFORMAT
) |
1075 VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME
,
1076 DSI_DISP0_LP_STOP_CTRL
) |
1080 DSI_PORT_WRITE(DISP0_CTRL
,
1081 DSI_DISP0_COMMAND_MODE
|
1085 drm_bridge_enable(dsi
->bridge
);
1087 if (debug_dump_regs
) {
1088 struct drm_printer p
= drm_info_printer(&dsi
->pdev
->dev
);
1089 dev_info(&dsi
->pdev
->dev
, "DSI regs after:\n");
1090 drm_print_regset32(&p
, &dsi
->regset
);
1094 static ssize_t
vc4_dsi_host_transfer(struct mipi_dsi_host
*host
,
1095 const struct mipi_dsi_msg
*msg
)
1097 struct vc4_dsi
*dsi
= host_to_dsi(host
);
1098 struct mipi_dsi_packet packet
;
1099 u32 pkth
= 0, pktc
= 0;
1101 bool is_long
= mipi_dsi_packet_format_is_long(msg
->type
);
1102 u32 cmd_fifo_len
= 0, pix_fifo_len
= 0;
1104 mipi_dsi_create_packet(&packet
, msg
);
1106 pkth
|= VC4_SET_FIELD(packet
.header
[0], DSI_TXPKT1H_BC_DT
);
1107 pkth
|= VC4_SET_FIELD(packet
.header
[1] |
1108 (packet
.header
[2] << 8),
1109 DSI_TXPKT1H_BC_PARAM
);
1111 /* Divide data across the various FIFOs we have available.
1112 * The command FIFO takes byte-oriented data, but is of
1113 * limited size. The pixel FIFO (never actually used for
1114 * pixel data in reality) is word oriented, and substantially
1115 * larger. So, we use the pixel FIFO for most of the data,
1116 * sending the residual bytes in the command FIFO at the start.
1118 * With this arrangement, the command FIFO will never get full.
1120 if (packet
.payload_length
<= 16) {
1121 cmd_fifo_len
= packet
.payload_length
;
1124 cmd_fifo_len
= (packet
.payload_length
%
1125 DSI_PIX_FIFO_WIDTH
);
1126 pix_fifo_len
= ((packet
.payload_length
- cmd_fifo_len
) /
1127 DSI_PIX_FIFO_WIDTH
);
1130 WARN_ON_ONCE(pix_fifo_len
>= DSI_PIX_FIFO_DEPTH
);
1132 pkth
|= VC4_SET_FIELD(cmd_fifo_len
, DSI_TXPKT1H_BC_CMDFIFO
);
1136 pktc
|= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX
,
1137 DSI_TXPKT1C_CMD_CTRL
);
1139 pktc
|= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX
,
1140 DSI_TXPKT1C_CMD_CTRL
);
1143 for (i
= 0; i
< cmd_fifo_len
; i
++)
1144 DSI_PORT_WRITE(TXPKT_CMD_FIFO
, packet
.payload
[i
]);
1145 for (i
= 0; i
< pix_fifo_len
; i
++) {
1146 const u8
*pix
= packet
.payload
+ cmd_fifo_len
+ i
* 4;
1148 DSI_PORT_WRITE(TXPKT_PIX_FIFO
,
1155 if (msg
->flags
& MIPI_DSI_MSG_USE_LPM
)
1156 pktc
|= DSI_TXPKT1C_CMD_MODE_LP
;
1158 pktc
|= DSI_TXPKT1C_CMD_TYPE_LONG
;
1160 /* Send one copy of the packet. Larger repeats are used for pixel
1161 * data in command mode.
1163 pktc
|= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT
);
1165 pktc
|= DSI_TXPKT1C_CMD_EN
;
1167 pktc
|= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY
,
1168 DSI_TXPKT1C_DISPLAY_NO
);
1170 pktc
|= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT
,
1171 DSI_TXPKT1C_DISPLAY_NO
);
1174 /* Enable the appropriate interrupt for the transfer completion. */
1175 dsi
->xfer_result
= 0;
1176 reinit_completion(&dsi
->xfer_completion
);
1177 DSI_PORT_WRITE(INT_STAT
, DSI1_INT_TXPKT1_DONE
| DSI1_INT_PHY_DIR_RTF
);
1179 DSI_PORT_WRITE(INT_EN
, (DSI1_INTERRUPTS_ALWAYS_ENABLED
|
1180 DSI1_INT_PHY_DIR_RTF
));
1182 DSI_PORT_WRITE(INT_EN
, (DSI1_INTERRUPTS_ALWAYS_ENABLED
|
1183 DSI1_INT_TXPKT1_DONE
));
1186 /* Send the packet. */
1187 DSI_PORT_WRITE(TXPKT1H
, pkth
);
1188 DSI_PORT_WRITE(TXPKT1C
, pktc
);
1190 if (!wait_for_completion_timeout(&dsi
->xfer_completion
,
1191 msecs_to_jiffies(1000))) {
1192 dev_err(&dsi
->pdev
->dev
, "transfer interrupt wait timeout");
1193 dev_err(&dsi
->pdev
->dev
, "instat: 0x%08x\n",
1194 DSI_PORT_READ(INT_STAT
));
1197 ret
= dsi
->xfer_result
;
1200 DSI_PORT_WRITE(INT_EN
, DSI1_INTERRUPTS_ALWAYS_ENABLED
);
1203 goto reset_fifo_and_return
;
1205 if (ret
== 0 && msg
->rx_len
) {
1206 u32 rxpkt1h
= DSI_PORT_READ(RXPKT1H
);
1207 u8
*msg_rx
= msg
->rx_buf
;
1209 if (rxpkt1h
& DSI_RXPKT1H_PKT_TYPE_LONG
) {
1210 u32 rxlen
= VC4_GET_FIELD(rxpkt1h
,
1211 DSI_RXPKT1H_BC_PARAM
);
1213 if (rxlen
!= msg
->rx_len
) {
1214 DRM_ERROR("DSI returned %db, expecting %db\n",
1215 rxlen
, (int)msg
->rx_len
);
1217 goto reset_fifo_and_return
;
1220 for (i
= 0; i
< msg
->rx_len
; i
++)
1221 msg_rx
[i
] = DSI_READ(DSI1_RXPKT_FIFO
);
1223 /* FINISHME: Handle AWER */
1225 msg_rx
[0] = VC4_GET_FIELD(rxpkt1h
,
1226 DSI_RXPKT1H_SHORT_0
);
1227 if (msg
->rx_len
> 1) {
1228 msg_rx
[1] = VC4_GET_FIELD(rxpkt1h
,
1229 DSI_RXPKT1H_SHORT_1
);
1236 reset_fifo_and_return
:
1237 DRM_ERROR("DSI transfer failed, resetting: %d\n", ret
);
1239 DSI_PORT_WRITE(TXPKT1C
, DSI_PORT_READ(TXPKT1C
) & ~DSI_TXPKT1C_CMD_EN
);
1241 DSI_PORT_WRITE(CTRL
,
1242 DSI_PORT_READ(CTRL
) |
1243 DSI_PORT_BIT(CTRL_RESET_FIFOS
));
1245 DSI_PORT_WRITE(TXPKT1C
, 0);
1246 DSI_PORT_WRITE(INT_EN
, DSI1_INTERRUPTS_ALWAYS_ENABLED
);
1250 static int vc4_dsi_host_attach(struct mipi_dsi_host
*host
,
1251 struct mipi_dsi_device
*device
)
1253 struct vc4_dsi
*dsi
= host_to_dsi(host
);
1255 dsi
->lanes
= device
->lanes
;
1256 dsi
->channel
= device
->channel
;
1257 dsi
->mode_flags
= device
->mode_flags
;
1259 switch (device
->format
) {
1260 case MIPI_DSI_FMT_RGB888
:
1261 dsi
->format
= DSI_PFORMAT_RGB888
;
1262 dsi
->divider
= 24 / dsi
->lanes
;
1264 case MIPI_DSI_FMT_RGB666
:
1265 dsi
->format
= DSI_PFORMAT_RGB666
;
1266 dsi
->divider
= 24 / dsi
->lanes
;
1268 case MIPI_DSI_FMT_RGB666_PACKED
:
1269 dsi
->format
= DSI_PFORMAT_RGB666_PACKED
;
1270 dsi
->divider
= 18 / dsi
->lanes
;
1272 case MIPI_DSI_FMT_RGB565
:
1273 dsi
->format
= DSI_PFORMAT_RGB565
;
1274 dsi
->divider
= 16 / dsi
->lanes
;
1277 dev_err(&dsi
->pdev
->dev
, "Unknown DSI format: %d.\n",
1282 if (!(dsi
->mode_flags
& MIPI_DSI_MODE_VIDEO
)) {
1283 dev_err(&dsi
->pdev
->dev
,
1284 "Only VIDEO mode panels supported currently.\n");
1291 static int vc4_dsi_host_detach(struct mipi_dsi_host
*host
,
1292 struct mipi_dsi_device
*device
)
1297 static const struct mipi_dsi_host_ops vc4_dsi_host_ops
= {
1298 .attach
= vc4_dsi_host_attach
,
1299 .detach
= vc4_dsi_host_detach
,
1300 .transfer
= vc4_dsi_host_transfer
,
1303 static const struct drm_encoder_helper_funcs vc4_dsi_encoder_helper_funcs
= {
1304 .disable
= vc4_dsi_encoder_disable
,
1305 .enable
= vc4_dsi_encoder_enable
,
1306 .mode_fixup
= vc4_dsi_encoder_mode_fixup
,
1309 static const struct of_device_id vc4_dsi_dt_match
[] = {
1310 { .compatible
= "brcm,bcm2835-dsi1", (void *)(uintptr_t)1 },
1314 static void dsi_handle_error(struct vc4_dsi
*dsi
,
1315 irqreturn_t
*ret
, u32 stat
, u32 bit
,
1321 DRM_ERROR("DSI%d: %s error\n", dsi
->port
, type
);
1326 * Initial handler for port 1 where we need the reg_dma workaround.
1327 * The register DMA writes sleep, so we can't do it in the top half.
1328 * Instead we use IRQF_ONESHOT so that the IRQ gets disabled in the
1329 * parent interrupt contrller until our interrupt thread is done.
1331 static irqreturn_t
vc4_dsi_irq_defer_to_thread_handler(int irq
, void *data
)
1333 struct vc4_dsi
*dsi
= data
;
1334 u32 stat
= DSI_PORT_READ(INT_STAT
);
1339 return IRQ_WAKE_THREAD
;
1343 * Normal IRQ handler for port 0, or the threaded IRQ handler for port
1344 * 1 where we need the reg_dma workaround.
1346 static irqreturn_t
vc4_dsi_irq_handler(int irq
, void *data
)
1348 struct vc4_dsi
*dsi
= data
;
1349 u32 stat
= DSI_PORT_READ(INT_STAT
);
1350 irqreturn_t ret
= IRQ_NONE
;
1352 DSI_PORT_WRITE(INT_STAT
, stat
);
1354 dsi_handle_error(dsi
, &ret
, stat
,
1355 DSI1_INT_ERR_SYNC_ESC
, "LPDT sync");
1356 dsi_handle_error(dsi
, &ret
, stat
,
1357 DSI1_INT_ERR_CONTROL
, "data lane 0 sequence");
1358 dsi_handle_error(dsi
, &ret
, stat
,
1359 DSI1_INT_ERR_CONT_LP0
, "LP0 contention");
1360 dsi_handle_error(dsi
, &ret
, stat
,
1361 DSI1_INT_ERR_CONT_LP1
, "LP1 contention");
1362 dsi_handle_error(dsi
, &ret
, stat
,
1363 DSI1_INT_HSTX_TO
, "HSTX timeout");
1364 dsi_handle_error(dsi
, &ret
, stat
,
1365 DSI1_INT_LPRX_TO
, "LPRX timeout");
1366 dsi_handle_error(dsi
, &ret
, stat
,
1367 DSI1_INT_TA_TO
, "turnaround timeout");
1368 dsi_handle_error(dsi
, &ret
, stat
,
1369 DSI1_INT_PR_TO
, "peripheral reset timeout");
1371 if (stat
& (DSI1_INT_TXPKT1_DONE
| DSI1_INT_PHY_DIR_RTF
)) {
1372 complete(&dsi
->xfer_completion
);
1374 } else if (stat
& DSI1_INT_HSTX_TO
) {
1375 complete(&dsi
->xfer_completion
);
1376 dsi
->xfer_result
= -ETIMEDOUT
;
1384 * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog
1385 * PHY that are consumed by CPRMAN (clk-bcm2835.c).
1389 vc4_dsi_init_phy_clocks(struct vc4_dsi
*dsi
)
1391 struct device
*dev
= &dsi
->pdev
->dev
;
1392 const char *parent_name
= __clk_get_name(dsi
->pll_phy_clock
);
1393 static const struct {
1394 const char *dsi0_name
, *dsi1_name
;
1397 { "dsi0_byte", "dsi1_byte", 8 },
1398 { "dsi0_ddr2", "dsi1_ddr2", 4 },
1399 { "dsi0_ddr", "dsi1_ddr", 2 },
1403 dsi
->clk_onecell
= devm_kzalloc(dev
,
1404 sizeof(*dsi
->clk_onecell
) +
1405 ARRAY_SIZE(phy_clocks
) *
1406 sizeof(struct clk_hw
*),
1408 if (!dsi
->clk_onecell
)
1410 dsi
->clk_onecell
->num
= ARRAY_SIZE(phy_clocks
);
1412 for (i
= 0; i
< ARRAY_SIZE(phy_clocks
); i
++) {
1413 struct clk_fixed_factor
*fix
= &dsi
->phy_clocks
[i
];
1414 struct clk_init_data init
;
1417 /* We just use core fixed factor clock ops for the PHY
1418 * clocks. The clocks are actually gated by the
1419 * PHY_AFEC0_DDRCLK_EN bits, which we should be
1420 * setting if we use the DDR/DDR2 clocks. However,
1421 * vc4_dsi_encoder_enable() is setting up both AFEC0,
1422 * setting both our parent DSI PLL's rate and this
1423 * clock's rate, so it knows if DDR/DDR2 are going to
1424 * be used and could enable the gates itself.
1427 fix
->div
= phy_clocks
[i
].div
;
1428 fix
->hw
.init
= &init
;
1430 memset(&init
, 0, sizeof(init
));
1431 init
.parent_names
= &parent_name
;
1432 init
.num_parents
= 1;
1434 init
.name
= phy_clocks
[i
].dsi1_name
;
1436 init
.name
= phy_clocks
[i
].dsi0_name
;
1437 init
.ops
= &clk_fixed_factor_ops
;
1439 ret
= devm_clk_hw_register(dev
, &fix
->hw
);
1443 dsi
->clk_onecell
->hws
[i
] = &fix
->hw
;
1446 return of_clk_add_hw_provider(dev
->of_node
,
1447 of_clk_hw_onecell_get
,
1451 static int vc4_dsi_bind(struct device
*dev
, struct device
*master
, void *data
)
1453 struct platform_device
*pdev
= to_platform_device(dev
);
1454 struct drm_device
*drm
= dev_get_drvdata(master
);
1455 struct vc4_dev
*vc4
= to_vc4_dev(drm
);
1456 struct vc4_dsi
*dsi
= dev_get_drvdata(dev
);
1457 struct vc4_dsi_encoder
*vc4_dsi_encoder
;
1458 struct drm_panel
*panel
;
1459 const struct of_device_id
*match
;
1460 dma_cap_mask_t dma_mask
;
1463 match
= of_match_device(vc4_dsi_dt_match
, dev
);
1467 dsi
->port
= (uintptr_t)match
->data
;
1469 vc4_dsi_encoder
= devm_kzalloc(dev
, sizeof(*vc4_dsi_encoder
),
1471 if (!vc4_dsi_encoder
)
1473 vc4_dsi_encoder
->base
.type
= VC4_ENCODER_TYPE_DSI1
;
1474 vc4_dsi_encoder
->dsi
= dsi
;
1475 dsi
->encoder
= &vc4_dsi_encoder
->base
.base
;
1477 dsi
->regs
= vc4_ioremap_regs(pdev
, 0);
1478 if (IS_ERR(dsi
->regs
))
1479 return PTR_ERR(dsi
->regs
);
1481 dsi
->regset
.base
= dsi
->regs
;
1482 if (dsi
->port
== 0) {
1483 dsi
->regset
.regs
= dsi0_regs
;
1484 dsi
->regset
.nregs
= ARRAY_SIZE(dsi0_regs
);
1486 dsi
->regset
.regs
= dsi1_regs
;
1487 dsi
->regset
.nregs
= ARRAY_SIZE(dsi1_regs
);
1490 if (DSI_PORT_READ(ID
) != DSI_ID_VALUE
) {
1491 dev_err(dev
, "Port returned 0x%08x for ID instead of 0x%08x\n",
1492 DSI_PORT_READ(ID
), DSI_ID_VALUE
);
1496 /* DSI1 has a broken AXI slave that doesn't respond to writes
1497 * from the ARM. It does handle writes from the DMA engine,
1498 * so set up a channel for talking to it.
1500 if (dsi
->port
== 1) {
1501 dsi
->reg_dma_mem
= dma_alloc_coherent(dev
, 4,
1502 &dsi
->reg_dma_paddr
,
1504 if (!dsi
->reg_dma_mem
) {
1505 DRM_ERROR("Failed to get DMA memory\n");
1509 dma_cap_zero(dma_mask
);
1510 dma_cap_set(DMA_MEMCPY
, dma_mask
);
1511 dsi
->reg_dma_chan
= dma_request_chan_by_mask(&dma_mask
);
1512 if (IS_ERR(dsi
->reg_dma_chan
)) {
1513 ret
= PTR_ERR(dsi
->reg_dma_chan
);
1514 if (ret
!= -EPROBE_DEFER
)
1515 DRM_ERROR("Failed to get DMA channel: %d\n",
1520 /* Get the physical address of the device's registers. The
1521 * struct resource for the regs gives us the bus address
1524 dsi
->reg_paddr
= be32_to_cpup(of_get_address(dev
->of_node
,
1528 init_completion(&dsi
->xfer_completion
);
1529 /* At startup enable error-reporting interrupts and nothing else. */
1530 DSI_PORT_WRITE(INT_EN
, DSI1_INTERRUPTS_ALWAYS_ENABLED
);
1531 /* Clear any existing interrupt state. */
1532 DSI_PORT_WRITE(INT_STAT
, DSI_PORT_READ(INT_STAT
));
1534 if (dsi
->reg_dma_mem
)
1535 ret
= devm_request_threaded_irq(dev
, platform_get_irq(pdev
, 0),
1536 vc4_dsi_irq_defer_to_thread_handler
,
1537 vc4_dsi_irq_handler
,
1541 ret
= devm_request_irq(dev
, platform_get_irq(pdev
, 0),
1542 vc4_dsi_irq_handler
, 0, "vc4 dsi", dsi
);
1544 if (ret
!= -EPROBE_DEFER
)
1545 dev_err(dev
, "Failed to get interrupt: %d\n", ret
);
1549 dsi
->escape_clock
= devm_clk_get(dev
, "escape");
1550 if (IS_ERR(dsi
->escape_clock
)) {
1551 ret
= PTR_ERR(dsi
->escape_clock
);
1552 if (ret
!= -EPROBE_DEFER
)
1553 dev_err(dev
, "Failed to get escape clock: %d\n", ret
);
1557 dsi
->pll_phy_clock
= devm_clk_get(dev
, "phy");
1558 if (IS_ERR(dsi
->pll_phy_clock
)) {
1559 ret
= PTR_ERR(dsi
->pll_phy_clock
);
1560 if (ret
!= -EPROBE_DEFER
)
1561 dev_err(dev
, "Failed to get phy clock: %d\n", ret
);
1565 dsi
->pixel_clock
= devm_clk_get(dev
, "pixel");
1566 if (IS_ERR(dsi
->pixel_clock
)) {
1567 ret
= PTR_ERR(dsi
->pixel_clock
);
1568 if (ret
!= -EPROBE_DEFER
)
1569 dev_err(dev
, "Failed to get pixel clock: %d\n", ret
);
1573 ret
= drm_of_find_panel_or_bridge(dev
->of_node
, 0, 0,
1574 &panel
, &dsi
->bridge
);
1576 /* If the bridge or panel pointed by dev->of_node is not
1577 * enabled, just return 0 here so that we don't prevent the DRM
1578 * dev from being registered. Of course that means the DSI
1579 * encoder won't be exposed, but that's not a problem since
1580 * nothing is connected to it.
1589 dsi
->bridge
= devm_drm_panel_bridge_add(dev
, panel
,
1590 DRM_MODE_CONNECTOR_DSI
);
1591 if (IS_ERR(dsi
->bridge
))
1592 return PTR_ERR(dsi
->bridge
);
1595 /* The esc clock rate is supposed to always be 100Mhz. */
1596 ret
= clk_set_rate(dsi
->escape_clock
, 100 * 1000000);
1598 dev_err(dev
, "Failed to set esc clock: %d\n", ret
);
1602 ret
= vc4_dsi_init_phy_clocks(dsi
);
1609 drm_encoder_init(drm
, dsi
->encoder
, &vc4_dsi_encoder_funcs
,
1610 DRM_MODE_ENCODER_DSI
, NULL
);
1611 drm_encoder_helper_add(dsi
->encoder
, &vc4_dsi_encoder_helper_funcs
);
1613 ret
= drm_bridge_attach(dsi
->encoder
, dsi
->bridge
, NULL
);
1615 dev_err(dev
, "bridge attach failed: %d\n", ret
);
1618 /* Disable the atomic helper calls into the bridge. We
1619 * manually call the bridge pre_enable / enable / etc. calls
1620 * from our driver, since we need to sequence them within the
1621 * encoder's enable/disable paths.
1623 dsi
->encoder
->bridge
= NULL
;
1626 vc4_debugfs_add_regset32(drm
, "dsi0_regs", &dsi
->regset
);
1628 vc4_debugfs_add_regset32(drm
, "dsi1_regs", &dsi
->regset
);
1630 pm_runtime_enable(dev
);
1635 static void vc4_dsi_unbind(struct device
*dev
, struct device
*master
,
1638 struct drm_device
*drm
= dev_get_drvdata(master
);
1639 struct vc4_dev
*vc4
= to_vc4_dev(drm
);
1640 struct vc4_dsi
*dsi
= dev_get_drvdata(dev
);
1643 pm_runtime_disable(dev
);
1645 vc4_dsi_encoder_destroy(dsi
->encoder
);
1651 static const struct component_ops vc4_dsi_ops
= {
1652 .bind
= vc4_dsi_bind
,
1653 .unbind
= vc4_dsi_unbind
,
1656 static int vc4_dsi_dev_probe(struct platform_device
*pdev
)
1658 struct device
*dev
= &pdev
->dev
;
1659 struct vc4_dsi
*dsi
;
1662 dsi
= devm_kzalloc(dev
, sizeof(*dsi
), GFP_KERNEL
);
1665 dev_set_drvdata(dev
, dsi
);
1669 /* Note, the initialization sequence for DSI and panels is
1670 * tricky. The component bind above won't get past its
1671 * -EPROBE_DEFER until the panel/bridge probes. The
1672 * panel/bridge will return -EPROBE_DEFER until it has a
1673 * mipi_dsi_host to register its device to. So, we register
1674 * the host during pdev probe time, so vc4 as a whole can then
1675 * -EPROBE_DEFER its component bind process until the panel
1676 * successfully attaches.
1678 dsi
->dsi_host
.ops
= &vc4_dsi_host_ops
;
1679 dsi
->dsi_host
.dev
= dev
;
1680 mipi_dsi_host_register(&dsi
->dsi_host
);
1682 ret
= component_add(&pdev
->dev
, &vc4_dsi_ops
);
1684 mipi_dsi_host_unregister(&dsi
->dsi_host
);
1691 static int vc4_dsi_dev_remove(struct platform_device
*pdev
)
1693 struct device
*dev
= &pdev
->dev
;
1694 struct vc4_dsi
*dsi
= dev_get_drvdata(dev
);
1696 component_del(&pdev
->dev
, &vc4_dsi_ops
);
1697 mipi_dsi_host_unregister(&dsi
->dsi_host
);
1702 struct platform_driver vc4_dsi_driver
= {
1703 .probe
= vc4_dsi_dev_probe
,
1704 .remove
= vc4_dsi_dev_remove
,
1707 .of_match_table
= vc4_dsi_dt_match
,