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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / vc4 / vc4_hdmi.c
1 /*
2 * Copyright (C) 2015 Broadcom
3 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 /**
21 * DOC: VC4 Falcon HDMI module
22 *
23 * The HDMI core has a state machine and a PHY. On BCM2835, most of
24 * the unit operates off of the HSM clock from CPRMAN. It also
25 * internally uses the PLLH_PIX clock for the PHY.
26 *
27 * HDMI infoframes are kept within a small packet ram, where each
28 * packet can be individually enabled for including in a frame.
29 *
30 * HDMI audio is implemented entirely within the HDMI IP block. A
31 * register in the HDMI encoder takes SPDIF frames from the DMA engine
32 * and transfers them over an internal MAI (multi-channel audio
33 * interconnect) bus to the encoder side for insertion into the video
34 * blank regions.
35 *
36 * The driver's HDMI encoder does not yet support power management.
37 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
38 * continuously running, and only the HDMI logic and packet ram are
39 * powered off/on at disable/enable time.
40 *
41 * The driver does not yet support CEC control, though the HDMI
42 * encoder block has CEC support.
43 */
44
45 #include <drm/drm_atomic_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_edid.h>
48 #include <linux/clk.h>
49 #include <linux/component.h>
50 #include <linux/i2c.h>
51 #include <linux/of_address.h>
52 #include <linux/of_gpio.h>
53 #include <linux/of_platform.h>
54 #include <linux/pm_runtime.h>
55 #include <linux/rational.h>
56 #include <sound/dmaengine_pcm.h>
57 #include <sound/pcm_drm_eld.h>
58 #include <sound/pcm_params.h>
59 #include <sound/soc.h>
60 #include "media/cec.h"
61 #include "vc4_drv.h"
62 #include "vc4_regs.h"
63
64 #define HSM_CLOCK_FREQ 163682864
65 #define CEC_CLOCK_FREQ 40000
66 #define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ)
67
68 /* HDMI audio information */
69 struct vc4_hdmi_audio {
70 struct snd_soc_card card;
71 struct snd_soc_dai_link link;
72 int samplerate;
73 int channels;
74 struct snd_dmaengine_dai_dma_data dma_data;
75 struct snd_pcm_substream *substream;
76 };
77
78 /* General HDMI hardware state. */
79 struct vc4_hdmi {
80 struct platform_device *pdev;
81
82 struct drm_encoder *encoder;
83 struct drm_connector *connector;
84
85 struct vc4_hdmi_audio audio;
86
87 struct i2c_adapter *ddc;
88 void __iomem *hdmicore_regs;
89 void __iomem *hd_regs;
90 int hpd_gpio;
91 bool hpd_active_low;
92
93 struct cec_adapter *cec_adap;
94 struct cec_msg cec_rx_msg;
95 bool cec_tx_ok;
96 bool cec_irq_was_rx;
97
98 struct clk *pixel_clock;
99 struct clk *hsm_clock;
100 };
101
102 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
103 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
104 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
105 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
106
107 /* VC4 HDMI encoder KMS struct */
108 struct vc4_hdmi_encoder {
109 struct vc4_encoder base;
110 bool hdmi_monitor;
111 bool limited_rgb_range;
112 bool rgb_range_selectable;
113 };
114
115 static inline struct vc4_hdmi_encoder *
116 to_vc4_hdmi_encoder(struct drm_encoder *encoder)
117 {
118 return container_of(encoder, struct vc4_hdmi_encoder, base.base);
119 }
120
121 /* VC4 HDMI connector KMS struct */
122 struct vc4_hdmi_connector {
123 struct drm_connector base;
124
125 /* Since the connector is attached to just the one encoder,
126 * this is the reference to it so we can do the best_encoder()
127 * hook.
128 */
129 struct drm_encoder *encoder;
130 };
131
132 static inline struct vc4_hdmi_connector *
133 to_vc4_hdmi_connector(struct drm_connector *connector)
134 {
135 return container_of(connector, struct vc4_hdmi_connector, base);
136 }
137
138 #define HDMI_REG(reg) { reg, #reg }
139 static const struct {
140 u32 reg;
141 const char *name;
142 } hdmi_regs[] = {
143 HDMI_REG(VC4_HDMI_CORE_REV),
144 HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),
145 HDMI_REG(VC4_HDMI_HOTPLUG_INT),
146 HDMI_REG(VC4_HDMI_HOTPLUG),
147 HDMI_REG(VC4_HDMI_MAI_CHANNEL_MAP),
148 HDMI_REG(VC4_HDMI_MAI_CONFIG),
149 HDMI_REG(VC4_HDMI_MAI_FORMAT),
150 HDMI_REG(VC4_HDMI_AUDIO_PACKET_CONFIG),
151 HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),
152 HDMI_REG(VC4_HDMI_HORZA),
153 HDMI_REG(VC4_HDMI_HORZB),
154 HDMI_REG(VC4_HDMI_FIFO_CTL),
155 HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL),
156 HDMI_REG(VC4_HDMI_VERTA0),
157 HDMI_REG(VC4_HDMI_VERTA1),
158 HDMI_REG(VC4_HDMI_VERTB0),
159 HDMI_REG(VC4_HDMI_VERTB1),
160 HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),
161 HDMI_REG(VC4_HDMI_TX_PHY_CTL0),
162
163 HDMI_REG(VC4_HDMI_CEC_CNTRL_1),
164 HDMI_REG(VC4_HDMI_CEC_CNTRL_2),
165 HDMI_REG(VC4_HDMI_CEC_CNTRL_3),
166 HDMI_REG(VC4_HDMI_CEC_CNTRL_4),
167 HDMI_REG(VC4_HDMI_CEC_CNTRL_5),
168 HDMI_REG(VC4_HDMI_CPU_STATUS),
169 HDMI_REG(VC4_HDMI_CPU_MASK_STATUS),
170
171 HDMI_REG(VC4_HDMI_CEC_RX_DATA_1),
172 HDMI_REG(VC4_HDMI_CEC_RX_DATA_2),
173 HDMI_REG(VC4_HDMI_CEC_RX_DATA_3),
174 HDMI_REG(VC4_HDMI_CEC_RX_DATA_4),
175 HDMI_REG(VC4_HDMI_CEC_TX_DATA_1),
176 HDMI_REG(VC4_HDMI_CEC_TX_DATA_2),
177 HDMI_REG(VC4_HDMI_CEC_TX_DATA_3),
178 HDMI_REG(VC4_HDMI_CEC_TX_DATA_4),
179 };
180
181 static const struct {
182 u32 reg;
183 const char *name;
184 } hd_regs[] = {
185 HDMI_REG(VC4_HD_M_CTL),
186 HDMI_REG(VC4_HD_MAI_CTL),
187 HDMI_REG(VC4_HD_MAI_THR),
188 HDMI_REG(VC4_HD_MAI_FMT),
189 HDMI_REG(VC4_HD_MAI_SMP),
190 HDMI_REG(VC4_HD_VID_CTL),
191 HDMI_REG(VC4_HD_CSC_CTL),
192 HDMI_REG(VC4_HD_FRAME_COUNT),
193 };
194
195 #ifdef CONFIG_DEBUG_FS
196 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
197 {
198 struct drm_info_node *node = (struct drm_info_node *)m->private;
199 struct drm_device *dev = node->minor->dev;
200 struct vc4_dev *vc4 = to_vc4_dev(dev);
201 int i;
202
203 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
204 seq_printf(m, "%s (0x%04x): 0x%08x\n",
205 hdmi_regs[i].name, hdmi_regs[i].reg,
206 HDMI_READ(hdmi_regs[i].reg));
207 }
208
209 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
210 seq_printf(m, "%s (0x%04x): 0x%08x\n",
211 hd_regs[i].name, hd_regs[i].reg,
212 HD_READ(hd_regs[i].reg));
213 }
214
215 return 0;
216 }
217 #endif /* CONFIG_DEBUG_FS */
218
219 static void vc4_hdmi_dump_regs(struct drm_device *dev)
220 {
221 struct vc4_dev *vc4 = to_vc4_dev(dev);
222 int i;
223
224 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
225 DRM_INFO("0x%04x (%s): 0x%08x\n",
226 hdmi_regs[i].reg, hdmi_regs[i].name,
227 HDMI_READ(hdmi_regs[i].reg));
228 }
229 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
230 DRM_INFO("0x%04x (%s): 0x%08x\n",
231 hd_regs[i].reg, hd_regs[i].name,
232 HD_READ(hd_regs[i].reg));
233 }
234 }
235
236 static enum drm_connector_status
237 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
238 {
239 struct drm_device *dev = connector->dev;
240 struct vc4_dev *vc4 = to_vc4_dev(dev);
241
242 if (vc4->hdmi->hpd_gpio) {
243 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
244 vc4->hdmi->hpd_active_low)
245 return connector_status_connected;
246 cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
247 return connector_status_disconnected;
248 }
249
250 if (drm_probe_ddc(vc4->hdmi->ddc))
251 return connector_status_connected;
252
253 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
254 return connector_status_connected;
255 cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
256 return connector_status_disconnected;
257 }
258
259 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
260 {
261 drm_connector_unregister(connector);
262 drm_connector_cleanup(connector);
263 }
264
265 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
266 {
267 struct vc4_hdmi_connector *vc4_connector =
268 to_vc4_hdmi_connector(connector);
269 struct drm_encoder *encoder = vc4_connector->encoder;
270 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
271 struct drm_device *dev = connector->dev;
272 struct vc4_dev *vc4 = to_vc4_dev(dev);
273 int ret = 0;
274 struct edid *edid;
275
276 edid = drm_get_edid(connector, vc4->hdmi->ddc);
277 cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid);
278 if (!edid)
279 return -ENODEV;
280
281 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
282
283 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
284 vc4_encoder->rgb_range_selectable =
285 drm_rgb_quant_range_selectable(edid);
286 }
287
288 drm_mode_connector_update_edid_property(connector, edid);
289 ret = drm_add_edid_modes(connector, edid);
290 drm_edid_to_eld(connector, edid);
291 kfree(edid);
292
293 return ret;
294 }
295
296 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
297 .detect = vc4_hdmi_connector_detect,
298 .fill_modes = drm_helper_probe_single_connector_modes,
299 .destroy = vc4_hdmi_connector_destroy,
300 .reset = drm_atomic_helper_connector_reset,
301 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
302 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
303 };
304
305 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
306 .get_modes = vc4_hdmi_connector_get_modes,
307 };
308
309 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
310 struct drm_encoder *encoder)
311 {
312 struct drm_connector *connector = NULL;
313 struct vc4_hdmi_connector *hdmi_connector;
314 int ret = 0;
315
316 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
317 GFP_KERNEL);
318 if (!hdmi_connector) {
319 ret = -ENOMEM;
320 goto fail;
321 }
322 connector = &hdmi_connector->base;
323
324 hdmi_connector->encoder = encoder;
325
326 drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
327 DRM_MODE_CONNECTOR_HDMIA);
328 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
329
330 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
331 DRM_CONNECTOR_POLL_DISCONNECT);
332
333 connector->interlace_allowed = 1;
334 connector->doublescan_allowed = 0;
335
336 drm_mode_connector_attach_encoder(connector, encoder);
337
338 return connector;
339
340 fail:
341 if (connector)
342 vc4_hdmi_connector_destroy(connector);
343
344 return ERR_PTR(ret);
345 }
346
347 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
348 {
349 drm_encoder_cleanup(encoder);
350 }
351
352 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
353 .destroy = vc4_hdmi_encoder_destroy,
354 };
355
356 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
357 enum hdmi_infoframe_type type)
358 {
359 struct drm_device *dev = encoder->dev;
360 struct vc4_dev *vc4 = to_vc4_dev(dev);
361 u32 packet_id = type - 0x80;
362
363 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
364 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
365
366 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
367 BIT(packet_id)), 100);
368 }
369
370 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
371 union hdmi_infoframe *frame)
372 {
373 struct drm_device *dev = encoder->dev;
374 struct vc4_dev *vc4 = to_vc4_dev(dev);
375 u32 packet_id = frame->any.type - 0x80;
376 u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id);
377 uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
378 ssize_t len, i;
379 int ret;
380
381 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
382 VC4_HDMI_RAM_PACKET_ENABLE),
383 "Packet RAM has to be on to store the packet.");
384
385 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
386 if (len < 0)
387 return;
388
389 ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
390 if (ret) {
391 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
392 return;
393 }
394
395 for (i = 0; i < len; i += 7) {
396 HDMI_WRITE(packet_reg,
397 buffer[i + 0] << 0 |
398 buffer[i + 1] << 8 |
399 buffer[i + 2] << 16);
400 packet_reg += 4;
401
402 HDMI_WRITE(packet_reg,
403 buffer[i + 3] << 0 |
404 buffer[i + 4] << 8 |
405 buffer[i + 5] << 16 |
406 buffer[i + 6] << 24);
407 packet_reg += 4;
408 }
409
410 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
411 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
412 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
413 BIT(packet_id)), 100);
414 if (ret)
415 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
416 }
417
418 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
419 {
420 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
421 struct drm_crtc *crtc = encoder->crtc;
422 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
423 union hdmi_infoframe frame;
424 int ret;
425
426 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false);
427 if (ret < 0) {
428 DRM_ERROR("couldn't fill AVI infoframe\n");
429 return;
430 }
431
432 drm_hdmi_avi_infoframe_quant_range(&frame.avi, mode,
433 vc4_encoder->limited_rgb_range ?
434 HDMI_QUANTIZATION_RANGE_LIMITED :
435 HDMI_QUANTIZATION_RANGE_FULL,
436 vc4_encoder->rgb_range_selectable,
437 false);
438
439 vc4_hdmi_write_infoframe(encoder, &frame);
440 }
441
442 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
443 {
444 union hdmi_infoframe frame;
445 int ret;
446
447 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
448 if (ret < 0) {
449 DRM_ERROR("couldn't fill SPD infoframe\n");
450 return;
451 }
452
453 frame.spd.sdi = HDMI_SPD_SDI_PC;
454
455 vc4_hdmi_write_infoframe(encoder, &frame);
456 }
457
458 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
459 {
460 struct drm_device *drm = encoder->dev;
461 struct vc4_dev *vc4 = drm->dev_private;
462 struct vc4_hdmi *hdmi = vc4->hdmi;
463 union hdmi_infoframe frame;
464 int ret;
465
466 ret = hdmi_audio_infoframe_init(&frame.audio);
467
468 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
469 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
470 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
471 frame.audio.channels = hdmi->audio.channels;
472
473 vc4_hdmi_write_infoframe(encoder, &frame);
474 }
475
476 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
477 {
478 vc4_hdmi_set_avi_infoframe(encoder);
479 vc4_hdmi_set_spd_infoframe(encoder);
480 }
481
482 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
483 {
484 struct drm_device *dev = encoder->dev;
485 struct vc4_dev *vc4 = to_vc4_dev(dev);
486 struct vc4_hdmi *hdmi = vc4->hdmi;
487 int ret;
488
489 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0);
490
491 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
492 HD_WRITE(VC4_HD_VID_CTL,
493 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
494
495 clk_disable_unprepare(hdmi->pixel_clock);
496
497 ret = pm_runtime_put(&hdmi->pdev->dev);
498 if (ret < 0)
499 DRM_ERROR("Failed to release power domain: %d\n", ret);
500 }
501
502 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
503 {
504 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
505 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
506 struct drm_device *dev = encoder->dev;
507 struct vc4_dev *vc4 = to_vc4_dev(dev);
508 struct vc4_hdmi *hdmi = vc4->hdmi;
509 bool debug_dump_regs = false;
510 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
511 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
512 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
513 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
514 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
515 VC4_HDMI_VERTA_VSP) |
516 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
517 VC4_HDMI_VERTA_VFP) |
518 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
519 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
520 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
521 VC4_HDMI_VERTB_VBP));
522 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
523 VC4_SET_FIELD(mode->crtc_vtotal -
524 mode->crtc_vsync_end -
525 interlaced,
526 VC4_HDMI_VERTB_VBP));
527 u32 csc_ctl;
528 int ret;
529
530 ret = pm_runtime_get_sync(&hdmi->pdev->dev);
531 if (ret < 0) {
532 DRM_ERROR("Failed to retain power domain: %d\n", ret);
533 return;
534 }
535
536 ret = clk_set_rate(hdmi->pixel_clock,
537 mode->clock * 1000 *
538 ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1));
539 if (ret) {
540 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
541 return;
542 }
543
544 ret = clk_prepare_enable(hdmi->pixel_clock);
545 if (ret) {
546 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
547 return;
548 }
549
550 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
551 VC4_HDMI_SW_RESET_HDMI |
552 VC4_HDMI_SW_RESET_FORMAT_DETECT);
553
554 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
555
556 /* PHY should be in reset, like
557 * vc4_hdmi_encoder_disable() does.
558 */
559 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
560
561 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);
562
563 if (debug_dump_regs) {
564 DRM_INFO("HDMI regs before:\n");
565 vc4_hdmi_dump_regs(dev);
566 }
567
568 HD_WRITE(VC4_HD_VID_CTL, 0);
569
570 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
571 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
572 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
573 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
574
575 HDMI_WRITE(VC4_HDMI_HORZA,
576 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
577 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
578 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
579 VC4_HDMI_HORZA_HAP));
580
581 HDMI_WRITE(VC4_HDMI_HORZB,
582 VC4_SET_FIELD((mode->htotal -
583 mode->hsync_end) * pixel_rep,
584 VC4_HDMI_HORZB_HBP) |
585 VC4_SET_FIELD((mode->hsync_end -
586 mode->hsync_start) * pixel_rep,
587 VC4_HDMI_HORZB_HSP) |
588 VC4_SET_FIELD((mode->hsync_start -
589 mode->hdisplay) * pixel_rep,
590 VC4_HDMI_HORZB_HFP));
591
592 HDMI_WRITE(VC4_HDMI_VERTA0, verta);
593 HDMI_WRITE(VC4_HDMI_VERTA1, verta);
594
595 HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even);
596 HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
597
598 HD_WRITE(VC4_HD_VID_CTL,
599 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
600 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
601
602 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
603 VC4_HD_CSC_CTL_ORDER);
604
605 if (vc4_encoder->hdmi_monitor &&
606 drm_default_rgb_quant_range(mode) ==
607 HDMI_QUANTIZATION_RANGE_LIMITED) {
608 /* CEA VICs other than #1 requre limited range RGB
609 * output unless overridden by an AVI infoframe.
610 * Apply a colorspace conversion to squash 0-255 down
611 * to 16-235. The matrix here is:
612 *
613 * [ 0 0 0.8594 16]
614 * [ 0 0.8594 0 16]
615 * [ 0.8594 0 0 16]
616 * [ 0 0 0 1]
617 */
618 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
619 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
620 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
621 VC4_HD_CSC_CTL_MODE);
622
623 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000);
624 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0);
625 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000);
626 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
627 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
628 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
629 vc4_encoder->limited_rgb_range = true;
630 } else {
631 vc4_encoder->limited_rgb_range = false;
632 }
633
634 /* The RGB order applies even when CSC is disabled. */
635 HD_WRITE(VC4_HD_CSC_CTL, csc_ctl);
636
637 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
638
639 if (debug_dump_regs) {
640 DRM_INFO("HDMI regs after:\n");
641 vc4_hdmi_dump_regs(dev);
642 }
643
644 HD_WRITE(VC4_HD_VID_CTL,
645 HD_READ(VC4_HD_VID_CTL) |
646 VC4_HD_VID_CTL_ENABLE |
647 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
648 VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
649
650 if (vc4_encoder->hdmi_monitor) {
651 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
652 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
653 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
654
655 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
656 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
657 WARN_ONCE(ret, "Timeout waiting for "
658 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
659 } else {
660 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
661 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
662 ~(VC4_HDMI_RAM_PACKET_ENABLE));
663 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
664 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
665 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
666
667 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
668 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
669 WARN_ONCE(ret, "Timeout waiting for "
670 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
671 }
672
673 if (vc4_encoder->hdmi_monitor) {
674 u32 drift;
675
676 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
677 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
678 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
679 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
680 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
681
682 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
683 VC4_HDMI_RAM_PACKET_ENABLE);
684
685 vc4_hdmi_set_infoframes(encoder);
686
687 drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
688 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
689
690 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
691 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
692 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
693 drift | VC4_HDMI_FIFO_CTL_RECENTER);
694 udelay(1000);
695 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
696 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
697 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
698 drift | VC4_HDMI_FIFO_CTL_RECENTER);
699
700 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
701 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
702 WARN_ONCE(ret, "Timeout waiting for "
703 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
704 }
705 }
706
707 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
708 .disable = vc4_hdmi_encoder_disable,
709 .enable = vc4_hdmi_encoder_enable,
710 };
711
712 /* HDMI audio codec callbacks */
713 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi)
714 {
715 struct drm_device *drm = hdmi->encoder->dev;
716 struct vc4_dev *vc4 = to_vc4_dev(drm);
717 u32 hsm_clock = clk_get_rate(hdmi->hsm_clock);
718 unsigned long n, m;
719
720 rational_best_approximation(hsm_clock, hdmi->audio.samplerate,
721 VC4_HD_MAI_SMP_N_MASK >>
722 VC4_HD_MAI_SMP_N_SHIFT,
723 (VC4_HD_MAI_SMP_M_MASK >>
724 VC4_HD_MAI_SMP_M_SHIFT) + 1,
725 &n, &m);
726
727 HD_WRITE(VC4_HD_MAI_SMP,
728 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
729 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
730 }
731
732 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi)
733 {
734 struct drm_encoder *encoder = hdmi->encoder;
735 struct drm_crtc *crtc = encoder->crtc;
736 struct drm_device *drm = encoder->dev;
737 struct vc4_dev *vc4 = to_vc4_dev(drm);
738 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
739 u32 samplerate = hdmi->audio.samplerate;
740 u32 n, cts;
741 u64 tmp;
742
743 n = 128 * samplerate / 1000;
744 tmp = (u64)(mode->clock * 1000) * n;
745 do_div(tmp, 128 * samplerate);
746 cts = tmp;
747
748 HDMI_WRITE(VC4_HDMI_CRP_CFG,
749 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
750 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
751
752 /*
753 * We could get slightly more accurate clocks in some cases by
754 * providing a CTS_1 value. The two CTS values are alternated
755 * between based on the period fields
756 */
757 HDMI_WRITE(VC4_HDMI_CTS_0, cts);
758 HDMI_WRITE(VC4_HDMI_CTS_1, cts);
759 }
760
761 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
762 {
763 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
764
765 return snd_soc_card_get_drvdata(card);
766 }
767
768 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
769 struct snd_soc_dai *dai)
770 {
771 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
772 struct drm_encoder *encoder = hdmi->encoder;
773 struct vc4_dev *vc4 = to_vc4_dev(encoder->dev);
774 int ret;
775
776 if (hdmi->audio.substream && hdmi->audio.substream != substream)
777 return -EINVAL;
778
779 hdmi->audio.substream = substream;
780
781 /*
782 * If the HDMI encoder hasn't probed, or the encoder is
783 * currently in DVI mode, treat the codec dai as missing.
784 */
785 if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
786 VC4_HDMI_RAM_PACKET_ENABLE))
787 return -ENODEV;
788
789 ret = snd_pcm_hw_constraint_eld(substream->runtime,
790 hdmi->connector->eld);
791 if (ret)
792 return ret;
793
794 return 0;
795 }
796
797 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
798 {
799 return 0;
800 }
801
802 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi)
803 {
804 struct drm_encoder *encoder = hdmi->encoder;
805 struct drm_device *drm = encoder->dev;
806 struct device *dev = &hdmi->pdev->dev;
807 struct vc4_dev *vc4 = to_vc4_dev(drm);
808 int ret;
809
810 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
811 if (ret)
812 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
813
814 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET);
815 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
816 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
817 }
818
819 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
820 struct snd_soc_dai *dai)
821 {
822 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
823
824 if (substream != hdmi->audio.substream)
825 return;
826
827 vc4_hdmi_audio_reset(hdmi);
828
829 hdmi->audio.substream = NULL;
830 }
831
832 /* HDMI audio codec callbacks */
833 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
834 struct snd_pcm_hw_params *params,
835 struct snd_soc_dai *dai)
836 {
837 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
838 struct drm_encoder *encoder = hdmi->encoder;
839 struct drm_device *drm = encoder->dev;
840 struct device *dev = &hdmi->pdev->dev;
841 struct vc4_dev *vc4 = to_vc4_dev(drm);
842 u32 audio_packet_config, channel_mask;
843 u32 channel_map, i;
844
845 if (substream != hdmi->audio.substream)
846 return -EINVAL;
847
848 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
849 params_rate(params), params_width(params),
850 params_channels(params));
851
852 hdmi->audio.channels = params_channels(params);
853 hdmi->audio.samplerate = params_rate(params);
854
855 HD_WRITE(VC4_HD_MAI_CTL,
856 VC4_HD_MAI_CTL_RESET |
857 VC4_HD_MAI_CTL_FLUSH |
858 VC4_HD_MAI_CTL_DLATE |
859 VC4_HD_MAI_CTL_ERRORE |
860 VC4_HD_MAI_CTL_ERRORF);
861
862 vc4_hdmi_audio_set_mai_clock(hdmi);
863
864 audio_packet_config =
865 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
866 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
867 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
868
869 channel_mask = GENMASK(hdmi->audio.channels - 1, 0);
870 audio_packet_config |= VC4_SET_FIELD(channel_mask,
871 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
872
873 /* Set the MAI threshold. This logic mimics the firmware's. */
874 if (hdmi->audio.samplerate > 96000) {
875 HD_WRITE(VC4_HD_MAI_THR,
876 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
877 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
878 } else if (hdmi->audio.samplerate > 48000) {
879 HD_WRITE(VC4_HD_MAI_THR,
880 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
881 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
882 } else {
883 HD_WRITE(VC4_HD_MAI_THR,
884 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
885 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
886 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
887 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
888 }
889
890 HDMI_WRITE(VC4_HDMI_MAI_CONFIG,
891 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
892 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
893
894 channel_map = 0;
895 for (i = 0; i < 8; i++) {
896 if (channel_mask & BIT(i))
897 channel_map |= i << (3 * i);
898 }
899
900 HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map);
901 HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
902 vc4_hdmi_set_n_cts(hdmi);
903
904 return 0;
905 }
906
907 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
908 struct snd_soc_dai *dai)
909 {
910 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
911 struct drm_encoder *encoder = hdmi->encoder;
912 struct drm_device *drm = encoder->dev;
913 struct vc4_dev *vc4 = to_vc4_dev(drm);
914
915 switch (cmd) {
916 case SNDRV_PCM_TRIGGER_START:
917 vc4_hdmi_set_audio_infoframe(encoder);
918 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
919 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) &
920 ~VC4_HDMI_TX_PHY_RNG_PWRDN);
921 HD_WRITE(VC4_HD_MAI_CTL,
922 VC4_SET_FIELD(hdmi->audio.channels,
923 VC4_HD_MAI_CTL_CHNUM) |
924 VC4_HD_MAI_CTL_ENABLE);
925 break;
926 case SNDRV_PCM_TRIGGER_STOP:
927 HD_WRITE(VC4_HD_MAI_CTL,
928 VC4_HD_MAI_CTL_DLATE |
929 VC4_HD_MAI_CTL_ERRORE |
930 VC4_HD_MAI_CTL_ERRORF);
931 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
932 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) |
933 VC4_HDMI_TX_PHY_RNG_PWRDN);
934 break;
935 default:
936 break;
937 }
938
939 return 0;
940 }
941
942 static inline struct vc4_hdmi *
943 snd_component_to_hdmi(struct snd_soc_component *component)
944 {
945 struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
946
947 return snd_soc_card_get_drvdata(card);
948 }
949
950 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
951 struct snd_ctl_elem_info *uinfo)
952 {
953 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
954 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
955
956 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
957 uinfo->count = sizeof(hdmi->connector->eld);
958
959 return 0;
960 }
961
962 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
963 struct snd_ctl_elem_value *ucontrol)
964 {
965 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
966 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
967
968 memcpy(ucontrol->value.bytes.data, hdmi->connector->eld,
969 sizeof(hdmi->connector->eld));
970
971 return 0;
972 }
973
974 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
975 {
976 .access = SNDRV_CTL_ELEM_ACCESS_READ |
977 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
978 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
979 .name = "ELD",
980 .info = vc4_hdmi_audio_eld_ctl_info,
981 .get = vc4_hdmi_audio_eld_ctl_get,
982 },
983 };
984
985 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
986 SND_SOC_DAPM_OUTPUT("TX"),
987 };
988
989 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
990 { "TX", NULL, "Playback" },
991 };
992
993 static const struct snd_soc_codec_driver vc4_hdmi_audio_codec_drv = {
994 .component_driver = {
995 .controls = vc4_hdmi_audio_controls,
996 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls),
997 .dapm_widgets = vc4_hdmi_audio_widgets,
998 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets),
999 .dapm_routes = vc4_hdmi_audio_routes,
1000 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes),
1001 },
1002 };
1003
1004 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
1005 .startup = vc4_hdmi_audio_startup,
1006 .shutdown = vc4_hdmi_audio_shutdown,
1007 .hw_params = vc4_hdmi_audio_hw_params,
1008 .set_fmt = vc4_hdmi_audio_set_fmt,
1009 .trigger = vc4_hdmi_audio_trigger,
1010 };
1011
1012 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1013 .name = "vc4-hdmi-hifi",
1014 .playback = {
1015 .stream_name = "Playback",
1016 .channels_min = 2,
1017 .channels_max = 8,
1018 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1019 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1020 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1021 SNDRV_PCM_RATE_192000,
1022 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1023 },
1024 };
1025
1026 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1027 .name = "vc4-hdmi-cpu-dai-component",
1028 };
1029
1030 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1031 {
1032 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
1033
1034 snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL);
1035
1036 return 0;
1037 }
1038
1039 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1040 .name = "vc4-hdmi-cpu-dai",
1041 .probe = vc4_hdmi_audio_cpu_dai_probe,
1042 .playback = {
1043 .stream_name = "Playback",
1044 .channels_min = 1,
1045 .channels_max = 8,
1046 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1047 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1048 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1049 SNDRV_PCM_RATE_192000,
1050 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1051 },
1052 .ops = &vc4_hdmi_audio_dai_ops,
1053 };
1054
1055 static const struct snd_dmaengine_pcm_config pcm_conf = {
1056 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1057 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1058 };
1059
1060 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi)
1061 {
1062 struct snd_soc_dai_link *dai_link = &hdmi->audio.link;
1063 struct snd_soc_card *card = &hdmi->audio.card;
1064 struct device *dev = &hdmi->pdev->dev;
1065 const __be32 *addr;
1066 int ret;
1067
1068 if (!of_find_property(dev->of_node, "dmas", NULL)) {
1069 dev_warn(dev,
1070 "'dmas' DT property is missing, no HDMI audio\n");
1071 return 0;
1072 }
1073
1074 /*
1075 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1076 * the bus address specified in the DT, because the physical address
1077 * (the one returned by platform_get_resource()) is not appropriate
1078 * for DMA transfers.
1079 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1080 */
1081 addr = of_get_address(dev->of_node, 1, NULL, NULL);
1082 hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA;
1083 hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1084 hdmi->audio.dma_data.maxburst = 2;
1085
1086 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1087 if (ret) {
1088 dev_err(dev, "Could not register PCM component: %d\n", ret);
1089 return ret;
1090 }
1091
1092 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1093 &vc4_hdmi_audio_cpu_dai_drv, 1);
1094 if (ret) {
1095 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1096 return ret;
1097 }
1098
1099 /* register codec and codec dai */
1100 ret = snd_soc_register_codec(dev, &vc4_hdmi_audio_codec_drv,
1101 &vc4_hdmi_audio_codec_dai_drv, 1);
1102 if (ret) {
1103 dev_err(dev, "Could not register codec: %d\n", ret);
1104 return ret;
1105 }
1106
1107 dai_link->name = "MAI";
1108 dai_link->stream_name = "MAI PCM";
1109 dai_link->codec_dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1110 dai_link->cpu_dai_name = dev_name(dev);
1111 dai_link->codec_name = dev_name(dev);
1112 dai_link->platform_name = dev_name(dev);
1113
1114 card->dai_link = dai_link;
1115 card->num_links = 1;
1116 card->name = "vc4-hdmi";
1117 card->dev = dev;
1118
1119 /*
1120 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1121 * stores a pointer to the snd card object in dev->driver_data. This
1122 * means we cannot use it for something else. The hdmi back-pointer is
1123 * now stored in card->drvdata and should be retrieved with
1124 * snd_soc_card_get_drvdata() if needed.
1125 */
1126 snd_soc_card_set_drvdata(card, hdmi);
1127 ret = devm_snd_soc_register_card(dev, card);
1128 if (ret) {
1129 dev_err(dev, "Could not register sound card: %d\n", ret);
1130 goto unregister_codec;
1131 }
1132
1133 return 0;
1134
1135 unregister_codec:
1136 snd_soc_unregister_codec(dev);
1137
1138 return ret;
1139 }
1140
1141 static void vc4_hdmi_audio_cleanup(struct vc4_hdmi *hdmi)
1142 {
1143 struct device *dev = &hdmi->pdev->dev;
1144
1145 /*
1146 * If drvdata is not set this means the audio card was not
1147 * registered, just skip codec unregistration in this case.
1148 */
1149 if (dev_get_drvdata(dev))
1150 snd_soc_unregister_codec(dev);
1151 }
1152
1153 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1154 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1155 {
1156 struct vc4_dev *vc4 = priv;
1157 struct vc4_hdmi *hdmi = vc4->hdmi;
1158
1159 if (hdmi->cec_irq_was_rx) {
1160 if (hdmi->cec_rx_msg.len)
1161 cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg);
1162 } else if (hdmi->cec_tx_ok) {
1163 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK,
1164 0, 0, 0, 0);
1165 } else {
1166 /*
1167 * This CEC implementation makes 1 retry, so if we
1168 * get a NACK, then that means it made 2 attempts.
1169 */
1170 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK,
1171 0, 2, 0, 0);
1172 }
1173 return IRQ_HANDLED;
1174 }
1175
1176 static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1)
1177 {
1178 struct cec_msg *msg = &vc4->hdmi->cec_rx_msg;
1179 unsigned int i;
1180
1181 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1182 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1183 for (i = 0; i < msg->len; i += 4) {
1184 u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i);
1185
1186 msg->msg[i] = val & 0xff;
1187 msg->msg[i + 1] = (val >> 8) & 0xff;
1188 msg->msg[i + 2] = (val >> 16) & 0xff;
1189 msg->msg[i + 3] = (val >> 24) & 0xff;
1190 }
1191 }
1192
1193 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1194 {
1195 struct vc4_dev *vc4 = priv;
1196 struct vc4_hdmi *hdmi = vc4->hdmi;
1197 u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS);
1198 u32 cntrl1, cntrl5;
1199
1200 if (!(stat & VC4_HDMI_CPU_CEC))
1201 return IRQ_NONE;
1202 hdmi->cec_rx_msg.len = 0;
1203 cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1204 cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1205 hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1206 if (hdmi->cec_irq_was_rx) {
1207 vc4_cec_read_msg(vc4, cntrl1);
1208 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1209 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1210 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1211 } else {
1212 hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1213 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1214 }
1215 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1216 HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1217
1218 return IRQ_WAKE_THREAD;
1219 }
1220
1221 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1222 {
1223 struct vc4_dev *vc4 = cec_get_drvdata(adap);
1224 /* clock period in microseconds */
1225 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1226 u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1227
1228 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1229 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1230 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1231 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1232 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1233
1234 if (enable) {
1235 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1236 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1237 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val);
1238 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2,
1239 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1240 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1241 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1242 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1243 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1244 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3,
1245 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1246 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1247 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1248 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1249 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4,
1250 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1251 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1252 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1253 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1254
1255 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1256 } else {
1257 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1258 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1259 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1260 }
1261 return 0;
1262 }
1263
1264 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1265 {
1266 struct vc4_dev *vc4 = cec_get_drvdata(adap);
1267
1268 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1,
1269 (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1270 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1271 return 0;
1272 }
1273
1274 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1275 u32 signal_free_time, struct cec_msg *msg)
1276 {
1277 struct vc4_dev *vc4 = cec_get_drvdata(adap);
1278 u32 val;
1279 unsigned int i;
1280
1281 for (i = 0; i < msg->len; i += 4)
1282 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i,
1283 (msg->msg[i]) |
1284 (msg->msg[i + 1] << 8) |
1285 (msg->msg[i + 2] << 16) |
1286 (msg->msg[i + 3] << 24));
1287
1288 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1289 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1290 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1291 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1292 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1293 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1294
1295 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1296 return 0;
1297 }
1298
1299 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1300 .adap_enable = vc4_hdmi_cec_adap_enable,
1301 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1302 .adap_transmit = vc4_hdmi_cec_adap_transmit,
1303 };
1304 #endif
1305
1306 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1307 {
1308 struct platform_device *pdev = to_platform_device(dev);
1309 struct drm_device *drm = dev_get_drvdata(master);
1310 struct vc4_dev *vc4 = drm->dev_private;
1311 struct vc4_hdmi *hdmi;
1312 struct vc4_hdmi_encoder *vc4_hdmi_encoder;
1313 struct device_node *ddc_node;
1314 u32 value;
1315 int ret;
1316
1317 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1318 if (!hdmi)
1319 return -ENOMEM;
1320
1321 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
1322 GFP_KERNEL);
1323 if (!vc4_hdmi_encoder)
1324 return -ENOMEM;
1325 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
1326 hdmi->encoder = &vc4_hdmi_encoder->base.base;
1327
1328 hdmi->pdev = pdev;
1329 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1330 if (IS_ERR(hdmi->hdmicore_regs))
1331 return PTR_ERR(hdmi->hdmicore_regs);
1332
1333 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1334 if (IS_ERR(hdmi->hd_regs))
1335 return PTR_ERR(hdmi->hd_regs);
1336
1337 hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1338 if (IS_ERR(hdmi->pixel_clock)) {
1339 DRM_ERROR("Failed to get pixel clock\n");
1340 return PTR_ERR(hdmi->pixel_clock);
1341 }
1342 hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1343 if (IS_ERR(hdmi->hsm_clock)) {
1344 DRM_ERROR("Failed to get HDMI state machine clock\n");
1345 return PTR_ERR(hdmi->hsm_clock);
1346 }
1347
1348 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1349 if (!ddc_node) {
1350 DRM_ERROR("Failed to find ddc node in device tree\n");
1351 return -ENODEV;
1352 }
1353
1354 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1355 of_node_put(ddc_node);
1356 if (!hdmi->ddc) {
1357 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1358 return -EPROBE_DEFER;
1359 }
1360
1361 /* This is the rate that is set by the firmware. The number
1362 * needs to be a bit higher than the pixel clock rate
1363 * (generally 148.5Mhz).
1364 */
1365 ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ);
1366 if (ret) {
1367 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1368 goto err_put_i2c;
1369 }
1370
1371 ret = clk_prepare_enable(hdmi->hsm_clock);
1372 if (ret) {
1373 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
1374 ret);
1375 goto err_put_i2c;
1376 }
1377
1378 /* Only use the GPIO HPD pin if present in the DT, otherwise
1379 * we'll use the HDMI core's register.
1380 */
1381 if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1382 enum of_gpio_flags hpd_gpio_flags;
1383
1384 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1385 "hpd-gpios", 0,
1386 &hpd_gpio_flags);
1387 if (hdmi->hpd_gpio < 0) {
1388 ret = hdmi->hpd_gpio;
1389 goto err_unprepare_hsm;
1390 }
1391
1392 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1393 }
1394
1395 vc4->hdmi = hdmi;
1396
1397 /* HDMI core must be enabled. */
1398 if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
1399 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
1400 udelay(1);
1401 HD_WRITE(VC4_HD_M_CTL, 0);
1402
1403 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
1404 }
1405 pm_runtime_enable(dev);
1406
1407 drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
1408 DRM_MODE_ENCODER_TMDS, NULL);
1409 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
1410
1411 hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
1412 if (IS_ERR(hdmi->connector)) {
1413 ret = PTR_ERR(hdmi->connector);
1414 goto err_destroy_encoder;
1415 }
1416 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1417 hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1418 vc4, "vc4",
1419 CEC_CAP_TRANSMIT |
1420 CEC_CAP_LOG_ADDRS |
1421 CEC_CAP_PASSTHROUGH |
1422 CEC_CAP_RC, 1);
1423 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
1424 if (ret < 0)
1425 goto err_destroy_conn;
1426 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff);
1427 value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1428 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
1429 /*
1430 * Set the logical address to Unregistered and set the clock
1431 * divider: the hsm_clock rate and this divider setting will
1432 * give a 40 kHz CEC clock.
1433 */
1434 value |= VC4_HDMI_CEC_ADDR_MASK |
1435 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
1436 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value);
1437 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1438 vc4_cec_irq_handler,
1439 vc4_cec_irq_handler_thread, 0,
1440 "vc4 hdmi cec", vc4);
1441 if (ret)
1442 goto err_delete_cec_adap;
1443 ret = cec_register_adapter(hdmi->cec_adap, dev);
1444 if (ret < 0)
1445 goto err_delete_cec_adap;
1446 #endif
1447
1448 ret = vc4_hdmi_audio_init(hdmi);
1449 if (ret)
1450 goto err_destroy_encoder;
1451
1452 return 0;
1453
1454 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1455 err_delete_cec_adap:
1456 cec_delete_adapter(hdmi->cec_adap);
1457 err_destroy_conn:
1458 vc4_hdmi_connector_destroy(hdmi->connector);
1459 #endif
1460 err_destroy_encoder:
1461 vc4_hdmi_encoder_destroy(hdmi->encoder);
1462 err_unprepare_hsm:
1463 clk_disable_unprepare(hdmi->hsm_clock);
1464 pm_runtime_disable(dev);
1465 err_put_i2c:
1466 put_device(&hdmi->ddc->dev);
1467
1468 return ret;
1469 }
1470
1471 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1472 void *data)
1473 {
1474 struct drm_device *drm = dev_get_drvdata(master);
1475 struct vc4_dev *vc4 = drm->dev_private;
1476 struct vc4_hdmi *hdmi = vc4->hdmi;
1477
1478 vc4_hdmi_audio_cleanup(hdmi);
1479 cec_unregister_adapter(hdmi->cec_adap);
1480 vc4_hdmi_connector_destroy(hdmi->connector);
1481 vc4_hdmi_encoder_destroy(hdmi->encoder);
1482
1483 clk_disable_unprepare(hdmi->hsm_clock);
1484 pm_runtime_disable(dev);
1485
1486 put_device(&hdmi->ddc->dev);
1487
1488 vc4->hdmi = NULL;
1489 }
1490
1491 static const struct component_ops vc4_hdmi_ops = {
1492 .bind = vc4_hdmi_bind,
1493 .unbind = vc4_hdmi_unbind,
1494 };
1495
1496 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1497 {
1498 return component_add(&pdev->dev, &vc4_hdmi_ops);
1499 }
1500
1501 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1502 {
1503 component_del(&pdev->dev, &vc4_hdmi_ops);
1504 return 0;
1505 }
1506
1507 static const struct of_device_id vc4_hdmi_dt_match[] = {
1508 { .compatible = "brcm,bcm2835-hdmi" },
1509 {}
1510 };
1511
1512 struct platform_driver vc4_hdmi_driver = {
1513 .probe = vc4_hdmi_dev_probe,
1514 .remove = vc4_hdmi_dev_remove,
1515 .driver = {
1516 .name = "vc4_hdmi",
1517 .of_match_table = vc4_hdmi_dt_match,
1518 },
1519 };
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