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drm: Nuke drm_atomic_helper_connector_dpms
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / vc4 / vc4_hdmi.c
1 /*
2 * Copyright (C) 2015 Broadcom
3 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 /**
21 * DOC: VC4 Falcon HDMI module
22 *
23 * The HDMI core has a state machine and a PHY. On BCM2835, most of
24 * the unit operates off of the HSM clock from CPRMAN. It also
25 * internally uses the PLLH_PIX clock for the PHY.
26 *
27 * HDMI infoframes are kept within a small packet ram, where each
28 * packet can be individually enabled for including in a frame.
29 *
30 * HDMI audio is implemented entirely within the HDMI IP block. A
31 * register in the HDMI encoder takes SPDIF frames from the DMA engine
32 * and transfers them over an internal MAI (multi-channel audio
33 * interconnect) bus to the encoder side for insertion into the video
34 * blank regions.
35 *
36 * The driver's HDMI encoder does not yet support power management.
37 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
38 * continuously running, and only the HDMI logic and packet ram are
39 * powered off/on at disable/enable time.
40 *
41 * The driver does not yet support CEC control, though the HDMI
42 * encoder block has CEC support.
43 */
44
45 #include <drm/drm_atomic_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_edid.h>
48 #include <linux/clk.h>
49 #include <linux/component.h>
50 #include <linux/i2c.h>
51 #include <linux/of_address.h>
52 #include <linux/of_gpio.h>
53 #include <linux/of_platform.h>
54 #include <linux/pm_runtime.h>
55 #include <linux/rational.h>
56 #include <sound/dmaengine_pcm.h>
57 #include <sound/pcm_drm_eld.h>
58 #include <sound/pcm_params.h>
59 #include <sound/soc.h>
60 #include "media/cec.h"
61 #include "vc4_drv.h"
62 #include "vc4_regs.h"
63
64 #define HSM_CLOCK_FREQ 163682864
65 #define CEC_CLOCK_FREQ 40000
66 #define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ)
67
68 /* HDMI audio information */
69 struct vc4_hdmi_audio {
70 struct snd_soc_card card;
71 struct snd_soc_dai_link link;
72 int samplerate;
73 int channels;
74 struct snd_dmaengine_dai_dma_data dma_data;
75 struct snd_pcm_substream *substream;
76 };
77
78 /* General HDMI hardware state. */
79 struct vc4_hdmi {
80 struct platform_device *pdev;
81
82 struct drm_encoder *encoder;
83 struct drm_connector *connector;
84
85 struct vc4_hdmi_audio audio;
86
87 struct i2c_adapter *ddc;
88 void __iomem *hdmicore_regs;
89 void __iomem *hd_regs;
90 int hpd_gpio;
91 bool hpd_active_low;
92
93 struct cec_adapter *cec_adap;
94 struct cec_msg cec_rx_msg;
95 bool cec_tx_ok;
96 bool cec_irq_was_rx;
97
98 struct clk *pixel_clock;
99 struct clk *hsm_clock;
100 };
101
102 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
103 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
104 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
105 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
106
107 /* VC4 HDMI encoder KMS struct */
108 struct vc4_hdmi_encoder {
109 struct vc4_encoder base;
110 bool hdmi_monitor;
111 bool limited_rgb_range;
112 bool rgb_range_selectable;
113 };
114
115 static inline struct vc4_hdmi_encoder *
116 to_vc4_hdmi_encoder(struct drm_encoder *encoder)
117 {
118 return container_of(encoder, struct vc4_hdmi_encoder, base.base);
119 }
120
121 /* VC4 HDMI connector KMS struct */
122 struct vc4_hdmi_connector {
123 struct drm_connector base;
124
125 /* Since the connector is attached to just the one encoder,
126 * this is the reference to it so we can do the best_encoder()
127 * hook.
128 */
129 struct drm_encoder *encoder;
130 };
131
132 static inline struct vc4_hdmi_connector *
133 to_vc4_hdmi_connector(struct drm_connector *connector)
134 {
135 return container_of(connector, struct vc4_hdmi_connector, base);
136 }
137
138 #define HDMI_REG(reg) { reg, #reg }
139 static const struct {
140 u32 reg;
141 const char *name;
142 } hdmi_regs[] = {
143 HDMI_REG(VC4_HDMI_CORE_REV),
144 HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),
145 HDMI_REG(VC4_HDMI_HOTPLUG_INT),
146 HDMI_REG(VC4_HDMI_HOTPLUG),
147 HDMI_REG(VC4_HDMI_MAI_CHANNEL_MAP),
148 HDMI_REG(VC4_HDMI_MAI_CONFIG),
149 HDMI_REG(VC4_HDMI_MAI_FORMAT),
150 HDMI_REG(VC4_HDMI_AUDIO_PACKET_CONFIG),
151 HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),
152 HDMI_REG(VC4_HDMI_HORZA),
153 HDMI_REG(VC4_HDMI_HORZB),
154 HDMI_REG(VC4_HDMI_FIFO_CTL),
155 HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL),
156 HDMI_REG(VC4_HDMI_VERTA0),
157 HDMI_REG(VC4_HDMI_VERTA1),
158 HDMI_REG(VC4_HDMI_VERTB0),
159 HDMI_REG(VC4_HDMI_VERTB1),
160 HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),
161 HDMI_REG(VC4_HDMI_TX_PHY_CTL0),
162
163 HDMI_REG(VC4_HDMI_CEC_CNTRL_1),
164 HDMI_REG(VC4_HDMI_CEC_CNTRL_2),
165 HDMI_REG(VC4_HDMI_CEC_CNTRL_3),
166 HDMI_REG(VC4_HDMI_CEC_CNTRL_4),
167 HDMI_REG(VC4_HDMI_CEC_CNTRL_5),
168 HDMI_REG(VC4_HDMI_CPU_STATUS),
169 HDMI_REG(VC4_HDMI_CPU_MASK_STATUS),
170
171 HDMI_REG(VC4_HDMI_CEC_RX_DATA_1),
172 HDMI_REG(VC4_HDMI_CEC_RX_DATA_2),
173 HDMI_REG(VC4_HDMI_CEC_RX_DATA_3),
174 HDMI_REG(VC4_HDMI_CEC_RX_DATA_4),
175 HDMI_REG(VC4_HDMI_CEC_TX_DATA_1),
176 HDMI_REG(VC4_HDMI_CEC_TX_DATA_2),
177 HDMI_REG(VC4_HDMI_CEC_TX_DATA_3),
178 HDMI_REG(VC4_HDMI_CEC_TX_DATA_4),
179 };
180
181 static const struct {
182 u32 reg;
183 const char *name;
184 } hd_regs[] = {
185 HDMI_REG(VC4_HD_M_CTL),
186 HDMI_REG(VC4_HD_MAI_CTL),
187 HDMI_REG(VC4_HD_MAI_THR),
188 HDMI_REG(VC4_HD_MAI_FMT),
189 HDMI_REG(VC4_HD_MAI_SMP),
190 HDMI_REG(VC4_HD_VID_CTL),
191 HDMI_REG(VC4_HD_CSC_CTL),
192 HDMI_REG(VC4_HD_FRAME_COUNT),
193 };
194
195 #ifdef CONFIG_DEBUG_FS
196 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
197 {
198 struct drm_info_node *node = (struct drm_info_node *)m->private;
199 struct drm_device *dev = node->minor->dev;
200 struct vc4_dev *vc4 = to_vc4_dev(dev);
201 int i;
202
203 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
204 seq_printf(m, "%s (0x%04x): 0x%08x\n",
205 hdmi_regs[i].name, hdmi_regs[i].reg,
206 HDMI_READ(hdmi_regs[i].reg));
207 }
208
209 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
210 seq_printf(m, "%s (0x%04x): 0x%08x\n",
211 hd_regs[i].name, hd_regs[i].reg,
212 HD_READ(hd_regs[i].reg));
213 }
214
215 return 0;
216 }
217 #endif /* CONFIG_DEBUG_FS */
218
219 static void vc4_hdmi_dump_regs(struct drm_device *dev)
220 {
221 struct vc4_dev *vc4 = to_vc4_dev(dev);
222 int i;
223
224 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
225 DRM_INFO("0x%04x (%s): 0x%08x\n",
226 hdmi_regs[i].reg, hdmi_regs[i].name,
227 HDMI_READ(hdmi_regs[i].reg));
228 }
229 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
230 DRM_INFO("0x%04x (%s): 0x%08x\n",
231 hd_regs[i].reg, hd_regs[i].name,
232 HD_READ(hd_regs[i].reg));
233 }
234 }
235
236 static enum drm_connector_status
237 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
238 {
239 struct drm_device *dev = connector->dev;
240 struct vc4_dev *vc4 = to_vc4_dev(dev);
241
242 if (vc4->hdmi->hpd_gpio) {
243 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
244 vc4->hdmi->hpd_active_low)
245 return connector_status_connected;
246 cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
247 return connector_status_disconnected;
248 }
249
250 if (drm_probe_ddc(vc4->hdmi->ddc))
251 return connector_status_connected;
252
253 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
254 return connector_status_connected;
255 cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
256 return connector_status_disconnected;
257 }
258
259 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
260 {
261 drm_connector_unregister(connector);
262 drm_connector_cleanup(connector);
263 }
264
265 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
266 {
267 struct vc4_hdmi_connector *vc4_connector =
268 to_vc4_hdmi_connector(connector);
269 struct drm_encoder *encoder = vc4_connector->encoder;
270 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
271 struct drm_device *dev = connector->dev;
272 struct vc4_dev *vc4 = to_vc4_dev(dev);
273 int ret = 0;
274 struct edid *edid;
275
276 edid = drm_get_edid(connector, vc4->hdmi->ddc);
277 cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid);
278 if (!edid)
279 return -ENODEV;
280
281 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
282
283 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
284 vc4_encoder->rgb_range_selectable =
285 drm_rgb_quant_range_selectable(edid);
286 }
287
288 drm_mode_connector_update_edid_property(connector, edid);
289 ret = drm_add_edid_modes(connector, edid);
290 drm_edid_to_eld(connector, edid);
291
292 return ret;
293 }
294
295 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
296 .detect = vc4_hdmi_connector_detect,
297 .fill_modes = drm_helper_probe_single_connector_modes,
298 .destroy = vc4_hdmi_connector_destroy,
299 .reset = drm_atomic_helper_connector_reset,
300 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
301 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
302 };
303
304 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
305 .get_modes = vc4_hdmi_connector_get_modes,
306 };
307
308 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
309 struct drm_encoder *encoder)
310 {
311 struct drm_connector *connector = NULL;
312 struct vc4_hdmi_connector *hdmi_connector;
313 int ret = 0;
314
315 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
316 GFP_KERNEL);
317 if (!hdmi_connector) {
318 ret = -ENOMEM;
319 goto fail;
320 }
321 connector = &hdmi_connector->base;
322
323 hdmi_connector->encoder = encoder;
324
325 drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
326 DRM_MODE_CONNECTOR_HDMIA);
327 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
328
329 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
330 DRM_CONNECTOR_POLL_DISCONNECT);
331
332 connector->interlace_allowed = 1;
333 connector->doublescan_allowed = 0;
334
335 drm_mode_connector_attach_encoder(connector, encoder);
336
337 return connector;
338
339 fail:
340 if (connector)
341 vc4_hdmi_connector_destroy(connector);
342
343 return ERR_PTR(ret);
344 }
345
346 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
347 {
348 drm_encoder_cleanup(encoder);
349 }
350
351 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
352 .destroy = vc4_hdmi_encoder_destroy,
353 };
354
355 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
356 enum hdmi_infoframe_type type)
357 {
358 struct drm_device *dev = encoder->dev;
359 struct vc4_dev *vc4 = to_vc4_dev(dev);
360 u32 packet_id = type - 0x80;
361
362 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
363 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
364
365 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
366 BIT(packet_id)), 100);
367 }
368
369 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
370 union hdmi_infoframe *frame)
371 {
372 struct drm_device *dev = encoder->dev;
373 struct vc4_dev *vc4 = to_vc4_dev(dev);
374 u32 packet_id = frame->any.type - 0x80;
375 u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id);
376 uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
377 ssize_t len, i;
378 int ret;
379
380 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
381 VC4_HDMI_RAM_PACKET_ENABLE),
382 "Packet RAM has to be on to store the packet.");
383
384 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
385 if (len < 0)
386 return;
387
388 ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
389 if (ret) {
390 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
391 return;
392 }
393
394 for (i = 0; i < len; i += 7) {
395 HDMI_WRITE(packet_reg,
396 buffer[i + 0] << 0 |
397 buffer[i + 1] << 8 |
398 buffer[i + 2] << 16);
399 packet_reg += 4;
400
401 HDMI_WRITE(packet_reg,
402 buffer[i + 3] << 0 |
403 buffer[i + 4] << 8 |
404 buffer[i + 5] << 16 |
405 buffer[i + 6] << 24);
406 packet_reg += 4;
407 }
408
409 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
410 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
411 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
412 BIT(packet_id)), 100);
413 if (ret)
414 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
415 }
416
417 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
418 {
419 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
420 struct drm_crtc *crtc = encoder->crtc;
421 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
422 union hdmi_infoframe frame;
423 int ret;
424
425 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false);
426 if (ret < 0) {
427 DRM_ERROR("couldn't fill AVI infoframe\n");
428 return;
429 }
430
431 drm_hdmi_avi_infoframe_quant_range(&frame.avi, mode,
432 vc4_encoder->limited_rgb_range ?
433 HDMI_QUANTIZATION_RANGE_LIMITED :
434 HDMI_QUANTIZATION_RANGE_FULL,
435 vc4_encoder->rgb_range_selectable);
436
437 vc4_hdmi_write_infoframe(encoder, &frame);
438 }
439
440 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
441 {
442 union hdmi_infoframe frame;
443 int ret;
444
445 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
446 if (ret < 0) {
447 DRM_ERROR("couldn't fill SPD infoframe\n");
448 return;
449 }
450
451 frame.spd.sdi = HDMI_SPD_SDI_PC;
452
453 vc4_hdmi_write_infoframe(encoder, &frame);
454 }
455
456 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
457 {
458 struct drm_device *drm = encoder->dev;
459 struct vc4_dev *vc4 = drm->dev_private;
460 struct vc4_hdmi *hdmi = vc4->hdmi;
461 union hdmi_infoframe frame;
462 int ret;
463
464 ret = hdmi_audio_infoframe_init(&frame.audio);
465
466 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
467 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
468 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
469 frame.audio.channels = hdmi->audio.channels;
470
471 vc4_hdmi_write_infoframe(encoder, &frame);
472 }
473
474 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
475 {
476 vc4_hdmi_set_avi_infoframe(encoder);
477 vc4_hdmi_set_spd_infoframe(encoder);
478 }
479
480 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
481 {
482 struct drm_device *dev = encoder->dev;
483 struct vc4_dev *vc4 = to_vc4_dev(dev);
484 struct vc4_hdmi *hdmi = vc4->hdmi;
485 int ret;
486
487 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0);
488
489 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
490 HD_WRITE(VC4_HD_VID_CTL,
491 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
492
493 clk_disable_unprepare(hdmi->pixel_clock);
494
495 ret = pm_runtime_put(&hdmi->pdev->dev);
496 if (ret < 0)
497 DRM_ERROR("Failed to release power domain: %d\n", ret);
498 }
499
500 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
501 {
502 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
503 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
504 struct drm_device *dev = encoder->dev;
505 struct vc4_dev *vc4 = to_vc4_dev(dev);
506 struct vc4_hdmi *hdmi = vc4->hdmi;
507 bool debug_dump_regs = false;
508 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
509 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
510 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
511 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
512 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
513 VC4_HDMI_VERTA_VSP) |
514 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
515 VC4_HDMI_VERTA_VFP) |
516 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
517 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
518 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
519 VC4_HDMI_VERTB_VBP));
520 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
521 VC4_SET_FIELD(mode->crtc_vtotal -
522 mode->crtc_vsync_end -
523 interlaced,
524 VC4_HDMI_VERTB_VBP));
525 u32 csc_ctl;
526 int ret;
527
528 ret = pm_runtime_get_sync(&hdmi->pdev->dev);
529 if (ret < 0) {
530 DRM_ERROR("Failed to retain power domain: %d\n", ret);
531 return;
532 }
533
534 ret = clk_set_rate(hdmi->pixel_clock,
535 mode->clock * 1000 *
536 ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1));
537 if (ret) {
538 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
539 return;
540 }
541
542 ret = clk_prepare_enable(hdmi->pixel_clock);
543 if (ret) {
544 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
545 return;
546 }
547
548 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
549 VC4_HDMI_SW_RESET_HDMI |
550 VC4_HDMI_SW_RESET_FORMAT_DETECT);
551
552 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
553
554 /* PHY should be in reset, like
555 * vc4_hdmi_encoder_disable() does.
556 */
557 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
558
559 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);
560
561 if (debug_dump_regs) {
562 DRM_INFO("HDMI regs before:\n");
563 vc4_hdmi_dump_regs(dev);
564 }
565
566 HD_WRITE(VC4_HD_VID_CTL, 0);
567
568 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
569 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
570 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
571 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
572
573 HDMI_WRITE(VC4_HDMI_HORZA,
574 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
575 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
576 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
577 VC4_HDMI_HORZA_HAP));
578
579 HDMI_WRITE(VC4_HDMI_HORZB,
580 VC4_SET_FIELD((mode->htotal -
581 mode->hsync_end) * pixel_rep,
582 VC4_HDMI_HORZB_HBP) |
583 VC4_SET_FIELD((mode->hsync_end -
584 mode->hsync_start) * pixel_rep,
585 VC4_HDMI_HORZB_HSP) |
586 VC4_SET_FIELD((mode->hsync_start -
587 mode->hdisplay) * pixel_rep,
588 VC4_HDMI_HORZB_HFP));
589
590 HDMI_WRITE(VC4_HDMI_VERTA0, verta);
591 HDMI_WRITE(VC4_HDMI_VERTA1, verta);
592
593 HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even);
594 HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
595
596 HD_WRITE(VC4_HD_VID_CTL,
597 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
598 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
599
600 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
601 VC4_HD_CSC_CTL_ORDER);
602
603 if (vc4_encoder->hdmi_monitor &&
604 drm_default_rgb_quant_range(mode) ==
605 HDMI_QUANTIZATION_RANGE_LIMITED) {
606 /* CEA VICs other than #1 requre limited range RGB
607 * output unless overridden by an AVI infoframe.
608 * Apply a colorspace conversion to squash 0-255 down
609 * to 16-235. The matrix here is:
610 *
611 * [ 0 0 0.8594 16]
612 * [ 0 0.8594 0 16]
613 * [ 0.8594 0 0 16]
614 * [ 0 0 0 1]
615 */
616 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
617 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
618 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
619 VC4_HD_CSC_CTL_MODE);
620
621 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000);
622 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0);
623 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000);
624 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
625 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
626 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
627 vc4_encoder->limited_rgb_range = true;
628 } else {
629 vc4_encoder->limited_rgb_range = false;
630 }
631
632 /* The RGB order applies even when CSC is disabled. */
633 HD_WRITE(VC4_HD_CSC_CTL, csc_ctl);
634
635 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
636
637 if (debug_dump_regs) {
638 DRM_INFO("HDMI regs after:\n");
639 vc4_hdmi_dump_regs(dev);
640 }
641
642 HD_WRITE(VC4_HD_VID_CTL,
643 HD_READ(VC4_HD_VID_CTL) |
644 VC4_HD_VID_CTL_ENABLE |
645 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
646 VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
647
648 if (vc4_encoder->hdmi_monitor) {
649 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
650 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
651 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
652
653 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
654 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
655 WARN_ONCE(ret, "Timeout waiting for "
656 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
657 } else {
658 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
659 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
660 ~(VC4_HDMI_RAM_PACKET_ENABLE));
661 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
662 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
663 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
664
665 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
666 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
667 WARN_ONCE(ret, "Timeout waiting for "
668 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
669 }
670
671 if (vc4_encoder->hdmi_monitor) {
672 u32 drift;
673
674 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
675 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
676 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
677 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
678 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
679
680 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
681 VC4_HDMI_RAM_PACKET_ENABLE);
682
683 vc4_hdmi_set_infoframes(encoder);
684
685 drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
686 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
687
688 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
689 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
690 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
691 drift | VC4_HDMI_FIFO_CTL_RECENTER);
692 udelay(1000);
693 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
694 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
695 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
696 drift | VC4_HDMI_FIFO_CTL_RECENTER);
697
698 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
699 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
700 WARN_ONCE(ret, "Timeout waiting for "
701 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
702 }
703 }
704
705 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
706 .disable = vc4_hdmi_encoder_disable,
707 .enable = vc4_hdmi_encoder_enable,
708 };
709
710 /* HDMI audio codec callbacks */
711 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi)
712 {
713 struct drm_device *drm = hdmi->encoder->dev;
714 struct vc4_dev *vc4 = to_vc4_dev(drm);
715 u32 hsm_clock = clk_get_rate(hdmi->hsm_clock);
716 unsigned long n, m;
717
718 rational_best_approximation(hsm_clock, hdmi->audio.samplerate,
719 VC4_HD_MAI_SMP_N_MASK >>
720 VC4_HD_MAI_SMP_N_SHIFT,
721 (VC4_HD_MAI_SMP_M_MASK >>
722 VC4_HD_MAI_SMP_M_SHIFT) + 1,
723 &n, &m);
724
725 HD_WRITE(VC4_HD_MAI_SMP,
726 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
727 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
728 }
729
730 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi)
731 {
732 struct drm_encoder *encoder = hdmi->encoder;
733 struct drm_crtc *crtc = encoder->crtc;
734 struct drm_device *drm = encoder->dev;
735 struct vc4_dev *vc4 = to_vc4_dev(drm);
736 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
737 u32 samplerate = hdmi->audio.samplerate;
738 u32 n, cts;
739 u64 tmp;
740
741 n = 128 * samplerate / 1000;
742 tmp = (u64)(mode->clock * 1000) * n;
743 do_div(tmp, 128 * samplerate);
744 cts = tmp;
745
746 HDMI_WRITE(VC4_HDMI_CRP_CFG,
747 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
748 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
749
750 /*
751 * We could get slightly more accurate clocks in some cases by
752 * providing a CTS_1 value. The two CTS values are alternated
753 * between based on the period fields
754 */
755 HDMI_WRITE(VC4_HDMI_CTS_0, cts);
756 HDMI_WRITE(VC4_HDMI_CTS_1, cts);
757 }
758
759 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
760 {
761 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
762
763 return snd_soc_card_get_drvdata(card);
764 }
765
766 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
767 struct snd_soc_dai *dai)
768 {
769 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
770 struct drm_encoder *encoder = hdmi->encoder;
771 struct vc4_dev *vc4 = to_vc4_dev(encoder->dev);
772 int ret;
773
774 if (hdmi->audio.substream && hdmi->audio.substream != substream)
775 return -EINVAL;
776
777 hdmi->audio.substream = substream;
778
779 /*
780 * If the HDMI encoder hasn't probed, or the encoder is
781 * currently in DVI mode, treat the codec dai as missing.
782 */
783 if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
784 VC4_HDMI_RAM_PACKET_ENABLE))
785 return -ENODEV;
786
787 ret = snd_pcm_hw_constraint_eld(substream->runtime,
788 hdmi->connector->eld);
789 if (ret)
790 return ret;
791
792 return 0;
793 }
794
795 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
796 {
797 return 0;
798 }
799
800 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi)
801 {
802 struct drm_encoder *encoder = hdmi->encoder;
803 struct drm_device *drm = encoder->dev;
804 struct device *dev = &hdmi->pdev->dev;
805 struct vc4_dev *vc4 = to_vc4_dev(drm);
806 int ret;
807
808 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
809 if (ret)
810 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
811
812 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET);
813 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
814 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
815 }
816
817 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
818 struct snd_soc_dai *dai)
819 {
820 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
821
822 if (substream != hdmi->audio.substream)
823 return;
824
825 vc4_hdmi_audio_reset(hdmi);
826
827 hdmi->audio.substream = NULL;
828 }
829
830 /* HDMI audio codec callbacks */
831 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
832 struct snd_pcm_hw_params *params,
833 struct snd_soc_dai *dai)
834 {
835 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
836 struct drm_encoder *encoder = hdmi->encoder;
837 struct drm_device *drm = encoder->dev;
838 struct device *dev = &hdmi->pdev->dev;
839 struct vc4_dev *vc4 = to_vc4_dev(drm);
840 u32 audio_packet_config, channel_mask;
841 u32 channel_map, i;
842
843 if (substream != hdmi->audio.substream)
844 return -EINVAL;
845
846 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
847 params_rate(params), params_width(params),
848 params_channels(params));
849
850 hdmi->audio.channels = params_channels(params);
851 hdmi->audio.samplerate = params_rate(params);
852
853 HD_WRITE(VC4_HD_MAI_CTL,
854 VC4_HD_MAI_CTL_RESET |
855 VC4_HD_MAI_CTL_FLUSH |
856 VC4_HD_MAI_CTL_DLATE |
857 VC4_HD_MAI_CTL_ERRORE |
858 VC4_HD_MAI_CTL_ERRORF);
859
860 vc4_hdmi_audio_set_mai_clock(hdmi);
861
862 audio_packet_config =
863 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
864 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
865 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
866
867 channel_mask = GENMASK(hdmi->audio.channels - 1, 0);
868 audio_packet_config |= VC4_SET_FIELD(channel_mask,
869 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
870
871 /* Set the MAI threshold. This logic mimics the firmware's. */
872 if (hdmi->audio.samplerate > 96000) {
873 HD_WRITE(VC4_HD_MAI_THR,
874 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
875 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
876 } else if (hdmi->audio.samplerate > 48000) {
877 HD_WRITE(VC4_HD_MAI_THR,
878 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
879 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
880 } else {
881 HD_WRITE(VC4_HD_MAI_THR,
882 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
883 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
884 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
885 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
886 }
887
888 HDMI_WRITE(VC4_HDMI_MAI_CONFIG,
889 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
890 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
891
892 channel_map = 0;
893 for (i = 0; i < 8; i++) {
894 if (channel_mask & BIT(i))
895 channel_map |= i << (3 * i);
896 }
897
898 HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map);
899 HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
900 vc4_hdmi_set_n_cts(hdmi);
901
902 return 0;
903 }
904
905 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
906 struct snd_soc_dai *dai)
907 {
908 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
909 struct drm_encoder *encoder = hdmi->encoder;
910 struct drm_device *drm = encoder->dev;
911 struct vc4_dev *vc4 = to_vc4_dev(drm);
912
913 switch (cmd) {
914 case SNDRV_PCM_TRIGGER_START:
915 vc4_hdmi_set_audio_infoframe(encoder);
916 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
917 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) &
918 ~VC4_HDMI_TX_PHY_RNG_PWRDN);
919 HD_WRITE(VC4_HD_MAI_CTL,
920 VC4_SET_FIELD(hdmi->audio.channels,
921 VC4_HD_MAI_CTL_CHNUM) |
922 VC4_HD_MAI_CTL_ENABLE);
923 break;
924 case SNDRV_PCM_TRIGGER_STOP:
925 HD_WRITE(VC4_HD_MAI_CTL,
926 VC4_HD_MAI_CTL_DLATE |
927 VC4_HD_MAI_CTL_ERRORE |
928 VC4_HD_MAI_CTL_ERRORF);
929 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
930 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) |
931 VC4_HDMI_TX_PHY_RNG_PWRDN);
932 break;
933 default:
934 break;
935 }
936
937 return 0;
938 }
939
940 static inline struct vc4_hdmi *
941 snd_component_to_hdmi(struct snd_soc_component *component)
942 {
943 struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
944
945 return snd_soc_card_get_drvdata(card);
946 }
947
948 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
949 struct snd_ctl_elem_info *uinfo)
950 {
951 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
952 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
953
954 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
955 uinfo->count = sizeof(hdmi->connector->eld);
956
957 return 0;
958 }
959
960 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
961 struct snd_ctl_elem_value *ucontrol)
962 {
963 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
964 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
965
966 memcpy(ucontrol->value.bytes.data, hdmi->connector->eld,
967 sizeof(hdmi->connector->eld));
968
969 return 0;
970 }
971
972 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
973 {
974 .access = SNDRV_CTL_ELEM_ACCESS_READ |
975 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
976 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
977 .name = "ELD",
978 .info = vc4_hdmi_audio_eld_ctl_info,
979 .get = vc4_hdmi_audio_eld_ctl_get,
980 },
981 };
982
983 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
984 SND_SOC_DAPM_OUTPUT("TX"),
985 };
986
987 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
988 { "TX", NULL, "Playback" },
989 };
990
991 static const struct snd_soc_codec_driver vc4_hdmi_audio_codec_drv = {
992 .component_driver = {
993 .controls = vc4_hdmi_audio_controls,
994 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls),
995 .dapm_widgets = vc4_hdmi_audio_widgets,
996 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets),
997 .dapm_routes = vc4_hdmi_audio_routes,
998 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes),
999 },
1000 };
1001
1002 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
1003 .startup = vc4_hdmi_audio_startup,
1004 .shutdown = vc4_hdmi_audio_shutdown,
1005 .hw_params = vc4_hdmi_audio_hw_params,
1006 .set_fmt = vc4_hdmi_audio_set_fmt,
1007 .trigger = vc4_hdmi_audio_trigger,
1008 };
1009
1010 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1011 .name = "vc4-hdmi-hifi",
1012 .playback = {
1013 .stream_name = "Playback",
1014 .channels_min = 2,
1015 .channels_max = 8,
1016 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1017 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1018 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1019 SNDRV_PCM_RATE_192000,
1020 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1021 },
1022 };
1023
1024 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1025 .name = "vc4-hdmi-cpu-dai-component",
1026 };
1027
1028 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1029 {
1030 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
1031
1032 snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL);
1033
1034 return 0;
1035 }
1036
1037 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1038 .name = "vc4-hdmi-cpu-dai",
1039 .probe = vc4_hdmi_audio_cpu_dai_probe,
1040 .playback = {
1041 .stream_name = "Playback",
1042 .channels_min = 1,
1043 .channels_max = 8,
1044 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1045 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1046 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1047 SNDRV_PCM_RATE_192000,
1048 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1049 },
1050 .ops = &vc4_hdmi_audio_dai_ops,
1051 };
1052
1053 static const struct snd_dmaengine_pcm_config pcm_conf = {
1054 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1055 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1056 };
1057
1058 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi)
1059 {
1060 struct snd_soc_dai_link *dai_link = &hdmi->audio.link;
1061 struct snd_soc_card *card = &hdmi->audio.card;
1062 struct device *dev = &hdmi->pdev->dev;
1063 const __be32 *addr;
1064 int ret;
1065
1066 if (!of_find_property(dev->of_node, "dmas", NULL)) {
1067 dev_warn(dev,
1068 "'dmas' DT property is missing, no HDMI audio\n");
1069 return 0;
1070 }
1071
1072 /*
1073 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1074 * the bus address specified in the DT, because the physical address
1075 * (the one returned by platform_get_resource()) is not appropriate
1076 * for DMA transfers.
1077 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1078 */
1079 addr = of_get_address(dev->of_node, 1, NULL, NULL);
1080 hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA;
1081 hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1082 hdmi->audio.dma_data.maxburst = 2;
1083
1084 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1085 if (ret) {
1086 dev_err(dev, "Could not register PCM component: %d\n", ret);
1087 return ret;
1088 }
1089
1090 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1091 &vc4_hdmi_audio_cpu_dai_drv, 1);
1092 if (ret) {
1093 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1094 return ret;
1095 }
1096
1097 /* register codec and codec dai */
1098 ret = snd_soc_register_codec(dev, &vc4_hdmi_audio_codec_drv,
1099 &vc4_hdmi_audio_codec_dai_drv, 1);
1100 if (ret) {
1101 dev_err(dev, "Could not register codec: %d\n", ret);
1102 return ret;
1103 }
1104
1105 dai_link->name = "MAI";
1106 dai_link->stream_name = "MAI PCM";
1107 dai_link->codec_dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1108 dai_link->cpu_dai_name = dev_name(dev);
1109 dai_link->codec_name = dev_name(dev);
1110 dai_link->platform_name = dev_name(dev);
1111
1112 card->dai_link = dai_link;
1113 card->num_links = 1;
1114 card->name = "vc4-hdmi";
1115 card->dev = dev;
1116
1117 /*
1118 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1119 * stores a pointer to the snd card object in dev->driver_data. This
1120 * means we cannot use it for something else. The hdmi back-pointer is
1121 * now stored in card->drvdata and should be retrieved with
1122 * snd_soc_card_get_drvdata() if needed.
1123 */
1124 snd_soc_card_set_drvdata(card, hdmi);
1125 ret = devm_snd_soc_register_card(dev, card);
1126 if (ret) {
1127 dev_err(dev, "Could not register sound card: %d\n", ret);
1128 goto unregister_codec;
1129 }
1130
1131 return 0;
1132
1133 unregister_codec:
1134 snd_soc_unregister_codec(dev);
1135
1136 return ret;
1137 }
1138
1139 static void vc4_hdmi_audio_cleanup(struct vc4_hdmi *hdmi)
1140 {
1141 struct device *dev = &hdmi->pdev->dev;
1142
1143 /*
1144 * If drvdata is not set this means the audio card was not
1145 * registered, just skip codec unregistration in this case.
1146 */
1147 if (dev_get_drvdata(dev))
1148 snd_soc_unregister_codec(dev);
1149 }
1150
1151 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1152 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1153 {
1154 struct vc4_dev *vc4 = priv;
1155 struct vc4_hdmi *hdmi = vc4->hdmi;
1156
1157 if (hdmi->cec_irq_was_rx) {
1158 if (hdmi->cec_rx_msg.len)
1159 cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg);
1160 } else if (hdmi->cec_tx_ok) {
1161 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK,
1162 0, 0, 0, 0);
1163 } else {
1164 /*
1165 * This CEC implementation makes 1 retry, so if we
1166 * get a NACK, then that means it made 2 attempts.
1167 */
1168 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK,
1169 0, 2, 0, 0);
1170 }
1171 return IRQ_HANDLED;
1172 }
1173
1174 static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1)
1175 {
1176 struct cec_msg *msg = &vc4->hdmi->cec_rx_msg;
1177 unsigned int i;
1178
1179 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1180 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1181 for (i = 0; i < msg->len; i += 4) {
1182 u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i);
1183
1184 msg->msg[i] = val & 0xff;
1185 msg->msg[i + 1] = (val >> 8) & 0xff;
1186 msg->msg[i + 2] = (val >> 16) & 0xff;
1187 msg->msg[i + 3] = (val >> 24) & 0xff;
1188 }
1189 }
1190
1191 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1192 {
1193 struct vc4_dev *vc4 = priv;
1194 struct vc4_hdmi *hdmi = vc4->hdmi;
1195 u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS);
1196 u32 cntrl1, cntrl5;
1197
1198 if (!(stat & VC4_HDMI_CPU_CEC))
1199 return IRQ_NONE;
1200 hdmi->cec_rx_msg.len = 0;
1201 cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1202 cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1203 hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1204 if (hdmi->cec_irq_was_rx) {
1205 vc4_cec_read_msg(vc4, cntrl1);
1206 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1207 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1208 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1209 } else {
1210 hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1211 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1212 }
1213 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1214 HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1215
1216 return IRQ_WAKE_THREAD;
1217 }
1218
1219 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1220 {
1221 struct vc4_dev *vc4 = cec_get_drvdata(adap);
1222 /* clock period in microseconds */
1223 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1224 u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1225
1226 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1227 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1228 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1229 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1230 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1231
1232 if (enable) {
1233 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1234 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1235 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val);
1236 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2,
1237 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1238 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1239 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1240 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1241 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1242 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3,
1243 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1244 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1245 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1246 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1247 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4,
1248 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1249 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1250 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1251 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1252
1253 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1254 } else {
1255 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1256 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1257 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1258 }
1259 return 0;
1260 }
1261
1262 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1263 {
1264 struct vc4_dev *vc4 = cec_get_drvdata(adap);
1265
1266 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1,
1267 (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1268 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1269 return 0;
1270 }
1271
1272 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1273 u32 signal_free_time, struct cec_msg *msg)
1274 {
1275 struct vc4_dev *vc4 = cec_get_drvdata(adap);
1276 u32 val;
1277 unsigned int i;
1278
1279 for (i = 0; i < msg->len; i += 4)
1280 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i,
1281 (msg->msg[i]) |
1282 (msg->msg[i + 1] << 8) |
1283 (msg->msg[i + 2] << 16) |
1284 (msg->msg[i + 3] << 24));
1285
1286 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1287 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1288 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1289 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1290 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1291 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1292
1293 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1294 return 0;
1295 }
1296
1297 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1298 .adap_enable = vc4_hdmi_cec_adap_enable,
1299 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1300 .adap_transmit = vc4_hdmi_cec_adap_transmit,
1301 };
1302 #endif
1303
1304 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1305 {
1306 struct platform_device *pdev = to_platform_device(dev);
1307 struct drm_device *drm = dev_get_drvdata(master);
1308 struct vc4_dev *vc4 = drm->dev_private;
1309 struct vc4_hdmi *hdmi;
1310 struct vc4_hdmi_encoder *vc4_hdmi_encoder;
1311 struct device_node *ddc_node;
1312 u32 value;
1313 int ret;
1314
1315 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1316 if (!hdmi)
1317 return -ENOMEM;
1318
1319 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
1320 GFP_KERNEL);
1321 if (!vc4_hdmi_encoder)
1322 return -ENOMEM;
1323 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
1324 hdmi->encoder = &vc4_hdmi_encoder->base.base;
1325
1326 hdmi->pdev = pdev;
1327 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1328 if (IS_ERR(hdmi->hdmicore_regs))
1329 return PTR_ERR(hdmi->hdmicore_regs);
1330
1331 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1332 if (IS_ERR(hdmi->hd_regs))
1333 return PTR_ERR(hdmi->hd_regs);
1334
1335 hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1336 if (IS_ERR(hdmi->pixel_clock)) {
1337 DRM_ERROR("Failed to get pixel clock\n");
1338 return PTR_ERR(hdmi->pixel_clock);
1339 }
1340 hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1341 if (IS_ERR(hdmi->hsm_clock)) {
1342 DRM_ERROR("Failed to get HDMI state machine clock\n");
1343 return PTR_ERR(hdmi->hsm_clock);
1344 }
1345
1346 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1347 if (!ddc_node) {
1348 DRM_ERROR("Failed to find ddc node in device tree\n");
1349 return -ENODEV;
1350 }
1351
1352 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1353 of_node_put(ddc_node);
1354 if (!hdmi->ddc) {
1355 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1356 return -EPROBE_DEFER;
1357 }
1358
1359 /* This is the rate that is set by the firmware. The number
1360 * needs to be a bit higher than the pixel clock rate
1361 * (generally 148.5Mhz).
1362 */
1363 ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ);
1364 if (ret) {
1365 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1366 goto err_put_i2c;
1367 }
1368
1369 ret = clk_prepare_enable(hdmi->hsm_clock);
1370 if (ret) {
1371 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
1372 ret);
1373 goto err_put_i2c;
1374 }
1375
1376 /* Only use the GPIO HPD pin if present in the DT, otherwise
1377 * we'll use the HDMI core's register.
1378 */
1379 if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1380 enum of_gpio_flags hpd_gpio_flags;
1381
1382 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1383 "hpd-gpios", 0,
1384 &hpd_gpio_flags);
1385 if (hdmi->hpd_gpio < 0) {
1386 ret = hdmi->hpd_gpio;
1387 goto err_unprepare_hsm;
1388 }
1389
1390 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1391 }
1392
1393 vc4->hdmi = hdmi;
1394
1395 /* HDMI core must be enabled. */
1396 if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
1397 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
1398 udelay(1);
1399 HD_WRITE(VC4_HD_M_CTL, 0);
1400
1401 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
1402 }
1403 pm_runtime_enable(dev);
1404
1405 drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
1406 DRM_MODE_ENCODER_TMDS, NULL);
1407 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
1408
1409 hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
1410 if (IS_ERR(hdmi->connector)) {
1411 ret = PTR_ERR(hdmi->connector);
1412 goto err_destroy_encoder;
1413 }
1414 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1415 hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1416 vc4, "vc4",
1417 CEC_CAP_TRANSMIT |
1418 CEC_CAP_LOG_ADDRS |
1419 CEC_CAP_PASSTHROUGH |
1420 CEC_CAP_RC, 1);
1421 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
1422 if (ret < 0)
1423 goto err_destroy_conn;
1424 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff);
1425 value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1426 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
1427 /*
1428 * Set the logical address to Unregistered and set the clock
1429 * divider: the hsm_clock rate and this divider setting will
1430 * give a 40 kHz CEC clock.
1431 */
1432 value |= VC4_HDMI_CEC_ADDR_MASK |
1433 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
1434 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value);
1435 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1436 vc4_cec_irq_handler,
1437 vc4_cec_irq_handler_thread, 0,
1438 "vc4 hdmi cec", vc4);
1439 if (ret)
1440 goto err_delete_cec_adap;
1441 ret = cec_register_adapter(hdmi->cec_adap, dev);
1442 if (ret < 0)
1443 goto err_delete_cec_adap;
1444 #endif
1445
1446 ret = vc4_hdmi_audio_init(hdmi);
1447 if (ret)
1448 goto err_destroy_encoder;
1449
1450 return 0;
1451
1452 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1453 err_delete_cec_adap:
1454 cec_delete_adapter(hdmi->cec_adap);
1455 err_destroy_conn:
1456 vc4_hdmi_connector_destroy(hdmi->connector);
1457 #endif
1458 err_destroy_encoder:
1459 vc4_hdmi_encoder_destroy(hdmi->encoder);
1460 err_unprepare_hsm:
1461 clk_disable_unprepare(hdmi->hsm_clock);
1462 pm_runtime_disable(dev);
1463 err_put_i2c:
1464 put_device(&hdmi->ddc->dev);
1465
1466 return ret;
1467 }
1468
1469 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1470 void *data)
1471 {
1472 struct drm_device *drm = dev_get_drvdata(master);
1473 struct vc4_dev *vc4 = drm->dev_private;
1474 struct vc4_hdmi *hdmi = vc4->hdmi;
1475
1476 vc4_hdmi_audio_cleanup(hdmi);
1477 cec_unregister_adapter(hdmi->cec_adap);
1478 vc4_hdmi_connector_destroy(hdmi->connector);
1479 vc4_hdmi_encoder_destroy(hdmi->encoder);
1480
1481 clk_disable_unprepare(hdmi->hsm_clock);
1482 pm_runtime_disable(dev);
1483
1484 put_device(&hdmi->ddc->dev);
1485
1486 vc4->hdmi = NULL;
1487 }
1488
1489 static const struct component_ops vc4_hdmi_ops = {
1490 .bind = vc4_hdmi_bind,
1491 .unbind = vc4_hdmi_unbind,
1492 };
1493
1494 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1495 {
1496 return component_add(&pdev->dev, &vc4_hdmi_ops);
1497 }
1498
1499 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1500 {
1501 component_del(&pdev->dev, &vc4_hdmi_ops);
1502 return 0;
1503 }
1504
1505 static const struct of_device_id vc4_hdmi_dt_match[] = {
1506 { .compatible = "brcm,bcm2835-hdmi" },
1507 {}
1508 };
1509
1510 struct platform_driver vc4_hdmi_driver = {
1511 .probe = vc4_hdmi_dev_probe,
1512 .remove = vc4_hdmi_dev_remove,
1513 .driver = {
1514 .name = "vc4_hdmi",
1515 .of_match_table = vc4_hdmi_dt_match,
1516 },
1517 };
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