2 * Copyright (C) 2015 Broadcom
3 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
21 * DOC: VC4 Falcon HDMI module
23 * The HDMI core has a state machine and a PHY. On BCM2835, most of
24 * the unit operates off of the HSM clock from CPRMAN. It also
25 * internally uses the PLLH_PIX clock for the PHY.
27 * HDMI infoframes are kept within a small packet ram, where each
28 * packet can be individually enabled for including in a frame.
30 * HDMI audio is implemented entirely within the HDMI IP block. A
31 * register in the HDMI encoder takes SPDIF frames from the DMA engine
32 * and transfers them over an internal MAI (multi-channel audio
33 * interconnect) bus to the encoder side for insertion into the video
36 * The driver's HDMI encoder does not yet support power management.
37 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
38 * continuously running, and only the HDMI logic and packet ram are
39 * powered off/on at disable/enable time.
41 * The driver does not yet support CEC control, though the HDMI
42 * encoder block has CEC support.
45 #include <drm/drm_atomic_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_edid.h>
48 #include <linux/clk.h>
49 #include <linux/component.h>
50 #include <linux/i2c.h>
51 #include <linux/of_address.h>
52 #include <linux/of_gpio.h>
53 #include <linux/of_platform.h>
54 #include <linux/pm_runtime.h>
55 #include <linux/rational.h>
56 #include <sound/dmaengine_pcm.h>
57 #include <sound/pcm_drm_eld.h>
58 #include <sound/pcm_params.h>
59 #include <sound/soc.h>
60 #include "media/cec.h"
64 #define HSM_CLOCK_FREQ 163682864
65 #define CEC_CLOCK_FREQ 40000
66 #define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ)
68 /* HDMI audio information */
69 struct vc4_hdmi_audio
{
70 struct snd_soc_card card
;
71 struct snd_soc_dai_link link
;
74 struct snd_dmaengine_dai_dma_data dma_data
;
75 struct snd_pcm_substream
*substream
;
78 /* General HDMI hardware state. */
80 struct platform_device
*pdev
;
82 struct drm_encoder
*encoder
;
83 struct drm_connector
*connector
;
85 struct vc4_hdmi_audio audio
;
87 struct i2c_adapter
*ddc
;
88 void __iomem
*hdmicore_regs
;
89 void __iomem
*hd_regs
;
93 struct cec_adapter
*cec_adap
;
94 struct cec_msg cec_rx_msg
;
98 struct clk
*pixel_clock
;
99 struct clk
*hsm_clock
;
102 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
103 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
104 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
105 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
107 /* VC4 HDMI encoder KMS struct */
108 struct vc4_hdmi_encoder
{
109 struct vc4_encoder base
;
111 bool limited_rgb_range
;
112 bool rgb_range_selectable
;
115 static inline struct vc4_hdmi_encoder
*
116 to_vc4_hdmi_encoder(struct drm_encoder
*encoder
)
118 return container_of(encoder
, struct vc4_hdmi_encoder
, base
.base
);
121 /* VC4 HDMI connector KMS struct */
122 struct vc4_hdmi_connector
{
123 struct drm_connector base
;
125 /* Since the connector is attached to just the one encoder,
126 * this is the reference to it so we can do the best_encoder()
129 struct drm_encoder
*encoder
;
132 static inline struct vc4_hdmi_connector
*
133 to_vc4_hdmi_connector(struct drm_connector
*connector
)
135 return container_of(connector
, struct vc4_hdmi_connector
, base
);
138 #define HDMI_REG(reg) { reg, #reg }
139 static const struct {
143 HDMI_REG(VC4_HDMI_CORE_REV
),
144 HDMI_REG(VC4_HDMI_SW_RESET_CONTROL
),
145 HDMI_REG(VC4_HDMI_HOTPLUG_INT
),
146 HDMI_REG(VC4_HDMI_HOTPLUG
),
147 HDMI_REG(VC4_HDMI_MAI_CHANNEL_MAP
),
148 HDMI_REG(VC4_HDMI_MAI_CONFIG
),
149 HDMI_REG(VC4_HDMI_MAI_FORMAT
),
150 HDMI_REG(VC4_HDMI_AUDIO_PACKET_CONFIG
),
151 HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG
),
152 HDMI_REG(VC4_HDMI_HORZA
),
153 HDMI_REG(VC4_HDMI_HORZB
),
154 HDMI_REG(VC4_HDMI_FIFO_CTL
),
155 HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL
),
156 HDMI_REG(VC4_HDMI_VERTA0
),
157 HDMI_REG(VC4_HDMI_VERTA1
),
158 HDMI_REG(VC4_HDMI_VERTB0
),
159 HDMI_REG(VC4_HDMI_VERTB1
),
160 HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL
),
161 HDMI_REG(VC4_HDMI_TX_PHY_CTL0
),
163 HDMI_REG(VC4_HDMI_CEC_CNTRL_1
),
164 HDMI_REG(VC4_HDMI_CEC_CNTRL_2
),
165 HDMI_REG(VC4_HDMI_CEC_CNTRL_3
),
166 HDMI_REG(VC4_HDMI_CEC_CNTRL_4
),
167 HDMI_REG(VC4_HDMI_CEC_CNTRL_5
),
168 HDMI_REG(VC4_HDMI_CPU_STATUS
),
169 HDMI_REG(VC4_HDMI_CPU_MASK_STATUS
),
171 HDMI_REG(VC4_HDMI_CEC_RX_DATA_1
),
172 HDMI_REG(VC4_HDMI_CEC_RX_DATA_2
),
173 HDMI_REG(VC4_HDMI_CEC_RX_DATA_3
),
174 HDMI_REG(VC4_HDMI_CEC_RX_DATA_4
),
175 HDMI_REG(VC4_HDMI_CEC_TX_DATA_1
),
176 HDMI_REG(VC4_HDMI_CEC_TX_DATA_2
),
177 HDMI_REG(VC4_HDMI_CEC_TX_DATA_3
),
178 HDMI_REG(VC4_HDMI_CEC_TX_DATA_4
),
181 static const struct {
185 HDMI_REG(VC4_HD_M_CTL
),
186 HDMI_REG(VC4_HD_MAI_CTL
),
187 HDMI_REG(VC4_HD_MAI_THR
),
188 HDMI_REG(VC4_HD_MAI_FMT
),
189 HDMI_REG(VC4_HD_MAI_SMP
),
190 HDMI_REG(VC4_HD_VID_CTL
),
191 HDMI_REG(VC4_HD_CSC_CTL
),
192 HDMI_REG(VC4_HD_FRAME_COUNT
),
195 #ifdef CONFIG_DEBUG_FS
196 int vc4_hdmi_debugfs_regs(struct seq_file
*m
, void *unused
)
198 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
199 struct drm_device
*dev
= node
->minor
->dev
;
200 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
203 for (i
= 0; i
< ARRAY_SIZE(hdmi_regs
); i
++) {
204 seq_printf(m
, "%s (0x%04x): 0x%08x\n",
205 hdmi_regs
[i
].name
, hdmi_regs
[i
].reg
,
206 HDMI_READ(hdmi_regs
[i
].reg
));
209 for (i
= 0; i
< ARRAY_SIZE(hd_regs
); i
++) {
210 seq_printf(m
, "%s (0x%04x): 0x%08x\n",
211 hd_regs
[i
].name
, hd_regs
[i
].reg
,
212 HD_READ(hd_regs
[i
].reg
));
217 #endif /* CONFIG_DEBUG_FS */
219 static void vc4_hdmi_dump_regs(struct drm_device
*dev
)
221 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
224 for (i
= 0; i
< ARRAY_SIZE(hdmi_regs
); i
++) {
225 DRM_INFO("0x%04x (%s): 0x%08x\n",
226 hdmi_regs
[i
].reg
, hdmi_regs
[i
].name
,
227 HDMI_READ(hdmi_regs
[i
].reg
));
229 for (i
= 0; i
< ARRAY_SIZE(hd_regs
); i
++) {
230 DRM_INFO("0x%04x (%s): 0x%08x\n",
231 hd_regs
[i
].reg
, hd_regs
[i
].name
,
232 HD_READ(hd_regs
[i
].reg
));
236 static enum drm_connector_status
237 vc4_hdmi_connector_detect(struct drm_connector
*connector
, bool force
)
239 struct drm_device
*dev
= connector
->dev
;
240 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
242 if (vc4
->hdmi
->hpd_gpio
) {
243 if (gpio_get_value_cansleep(vc4
->hdmi
->hpd_gpio
) ^
244 vc4
->hdmi
->hpd_active_low
)
245 return connector_status_connected
;
246 cec_phys_addr_invalidate(vc4
->hdmi
->cec_adap
);
247 return connector_status_disconnected
;
250 if (drm_probe_ddc(vc4
->hdmi
->ddc
))
251 return connector_status_connected
;
253 if (HDMI_READ(VC4_HDMI_HOTPLUG
) & VC4_HDMI_HOTPLUG_CONNECTED
)
254 return connector_status_connected
;
255 cec_phys_addr_invalidate(vc4
->hdmi
->cec_adap
);
256 return connector_status_disconnected
;
259 static void vc4_hdmi_connector_destroy(struct drm_connector
*connector
)
261 drm_connector_unregister(connector
);
262 drm_connector_cleanup(connector
);
265 static int vc4_hdmi_connector_get_modes(struct drm_connector
*connector
)
267 struct vc4_hdmi_connector
*vc4_connector
=
268 to_vc4_hdmi_connector(connector
);
269 struct drm_encoder
*encoder
= vc4_connector
->encoder
;
270 struct vc4_hdmi_encoder
*vc4_encoder
= to_vc4_hdmi_encoder(encoder
);
271 struct drm_device
*dev
= connector
->dev
;
272 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
276 edid
= drm_get_edid(connector
, vc4
->hdmi
->ddc
);
277 cec_s_phys_addr_from_edid(vc4
->hdmi
->cec_adap
, edid
);
281 vc4_encoder
->hdmi_monitor
= drm_detect_hdmi_monitor(edid
);
283 if (edid
&& edid
->input
& DRM_EDID_INPUT_DIGITAL
) {
284 vc4_encoder
->rgb_range_selectable
=
285 drm_rgb_quant_range_selectable(edid
);
288 drm_mode_connector_update_edid_property(connector
, edid
);
289 ret
= drm_add_edid_modes(connector
, edid
);
290 drm_edid_to_eld(connector
, edid
);
296 static const struct drm_connector_funcs vc4_hdmi_connector_funcs
= {
297 .detect
= vc4_hdmi_connector_detect
,
298 .fill_modes
= drm_helper_probe_single_connector_modes
,
299 .destroy
= vc4_hdmi_connector_destroy
,
300 .reset
= drm_atomic_helper_connector_reset
,
301 .atomic_duplicate_state
= drm_atomic_helper_connector_duplicate_state
,
302 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
305 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs
= {
306 .get_modes
= vc4_hdmi_connector_get_modes
,
309 static struct drm_connector
*vc4_hdmi_connector_init(struct drm_device
*dev
,
310 struct drm_encoder
*encoder
)
312 struct drm_connector
*connector
= NULL
;
313 struct vc4_hdmi_connector
*hdmi_connector
;
316 hdmi_connector
= devm_kzalloc(dev
->dev
, sizeof(*hdmi_connector
),
318 if (!hdmi_connector
) {
322 connector
= &hdmi_connector
->base
;
324 hdmi_connector
->encoder
= encoder
;
326 drm_connector_init(dev
, connector
, &vc4_hdmi_connector_funcs
,
327 DRM_MODE_CONNECTOR_HDMIA
);
328 drm_connector_helper_add(connector
, &vc4_hdmi_connector_helper_funcs
);
330 connector
->polled
= (DRM_CONNECTOR_POLL_CONNECT
|
331 DRM_CONNECTOR_POLL_DISCONNECT
);
333 connector
->interlace_allowed
= 1;
334 connector
->doublescan_allowed
= 0;
336 drm_mode_connector_attach_encoder(connector
, encoder
);
342 vc4_hdmi_connector_destroy(connector
);
347 static void vc4_hdmi_encoder_destroy(struct drm_encoder
*encoder
)
349 drm_encoder_cleanup(encoder
);
352 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs
= {
353 .destroy
= vc4_hdmi_encoder_destroy
,
356 static int vc4_hdmi_stop_packet(struct drm_encoder
*encoder
,
357 enum hdmi_infoframe_type type
)
359 struct drm_device
*dev
= encoder
->dev
;
360 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
361 u32 packet_id
= type
- 0x80;
363 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG
,
364 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG
) & ~BIT(packet_id
));
366 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS
) &
367 BIT(packet_id
)), 100);
370 static void vc4_hdmi_write_infoframe(struct drm_encoder
*encoder
,
371 union hdmi_infoframe
*frame
)
373 struct drm_device
*dev
= encoder
->dev
;
374 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
375 u32 packet_id
= frame
->any
.type
- 0x80;
376 u32 packet_reg
= VC4_HDMI_RAM_PACKET(packet_id
);
377 uint8_t buffer
[VC4_HDMI_PACKET_STRIDE
];
381 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG
) &
382 VC4_HDMI_RAM_PACKET_ENABLE
),
383 "Packet RAM has to be on to store the packet.");
385 len
= hdmi_infoframe_pack(frame
, buffer
, sizeof(buffer
));
389 ret
= vc4_hdmi_stop_packet(encoder
, frame
->any
.type
);
391 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret
);
395 for (i
= 0; i
< len
; i
+= 7) {
396 HDMI_WRITE(packet_reg
,
399 buffer
[i
+ 2] << 16);
402 HDMI_WRITE(packet_reg
,
405 buffer
[i
+ 5] << 16 |
406 buffer
[i
+ 6] << 24);
410 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG
,
411 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG
) | BIT(packet_id
));
412 ret
= wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS
) &
413 BIT(packet_id
)), 100);
415 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret
);
418 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder
*encoder
)
420 struct vc4_hdmi_encoder
*vc4_encoder
= to_vc4_hdmi_encoder(encoder
);
421 struct drm_crtc
*crtc
= encoder
->crtc
;
422 const struct drm_display_mode
*mode
= &crtc
->state
->adjusted_mode
;
423 union hdmi_infoframe frame
;
426 ret
= drm_hdmi_avi_infoframe_from_display_mode(&frame
.avi
, mode
, false);
428 DRM_ERROR("couldn't fill AVI infoframe\n");
432 drm_hdmi_avi_infoframe_quant_range(&frame
.avi
, mode
,
433 vc4_encoder
->limited_rgb_range
?
434 HDMI_QUANTIZATION_RANGE_LIMITED
:
435 HDMI_QUANTIZATION_RANGE_FULL
,
436 vc4_encoder
->rgb_range_selectable
);
438 vc4_hdmi_write_infoframe(encoder
, &frame
);
441 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder
*encoder
)
443 union hdmi_infoframe frame
;
446 ret
= hdmi_spd_infoframe_init(&frame
.spd
, "Broadcom", "Videocore");
448 DRM_ERROR("couldn't fill SPD infoframe\n");
452 frame
.spd
.sdi
= HDMI_SPD_SDI_PC
;
454 vc4_hdmi_write_infoframe(encoder
, &frame
);
457 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder
*encoder
)
459 struct drm_device
*drm
= encoder
->dev
;
460 struct vc4_dev
*vc4
= drm
->dev_private
;
461 struct vc4_hdmi
*hdmi
= vc4
->hdmi
;
462 union hdmi_infoframe frame
;
465 ret
= hdmi_audio_infoframe_init(&frame
.audio
);
467 frame
.audio
.coding_type
= HDMI_AUDIO_CODING_TYPE_STREAM
;
468 frame
.audio
.sample_frequency
= HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM
;
469 frame
.audio
.sample_size
= HDMI_AUDIO_SAMPLE_SIZE_STREAM
;
470 frame
.audio
.channels
= hdmi
->audio
.channels
;
472 vc4_hdmi_write_infoframe(encoder
, &frame
);
475 static void vc4_hdmi_set_infoframes(struct drm_encoder
*encoder
)
477 vc4_hdmi_set_avi_infoframe(encoder
);
478 vc4_hdmi_set_spd_infoframe(encoder
);
481 static void vc4_hdmi_encoder_disable(struct drm_encoder
*encoder
)
483 struct drm_device
*dev
= encoder
->dev
;
484 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
485 struct vc4_hdmi
*hdmi
= vc4
->hdmi
;
488 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG
, 0);
490 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL
, 0xf << 16);
491 HD_WRITE(VC4_HD_VID_CTL
,
492 HD_READ(VC4_HD_VID_CTL
) & ~VC4_HD_VID_CTL_ENABLE
);
494 clk_disable_unprepare(hdmi
->pixel_clock
);
496 ret
= pm_runtime_put(&hdmi
->pdev
->dev
);
498 DRM_ERROR("Failed to release power domain: %d\n", ret
);
501 static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder
)
503 struct drm_display_mode
*mode
= &encoder
->crtc
->state
->adjusted_mode
;
504 struct vc4_hdmi_encoder
*vc4_encoder
= to_vc4_hdmi_encoder(encoder
);
505 struct drm_device
*dev
= encoder
->dev
;
506 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
507 struct vc4_hdmi
*hdmi
= vc4
->hdmi
;
508 bool debug_dump_regs
= false;
509 bool hsync_pos
= mode
->flags
& DRM_MODE_FLAG_PHSYNC
;
510 bool vsync_pos
= mode
->flags
& DRM_MODE_FLAG_PVSYNC
;
511 bool interlaced
= mode
->flags
& DRM_MODE_FLAG_INTERLACE
;
512 u32 pixel_rep
= (mode
->flags
& DRM_MODE_FLAG_DBLCLK
) ? 2 : 1;
513 u32 verta
= (VC4_SET_FIELD(mode
->crtc_vsync_end
- mode
->crtc_vsync_start
,
514 VC4_HDMI_VERTA_VSP
) |
515 VC4_SET_FIELD(mode
->crtc_vsync_start
- mode
->crtc_vdisplay
,
516 VC4_HDMI_VERTA_VFP
) |
517 VC4_SET_FIELD(mode
->crtc_vdisplay
, VC4_HDMI_VERTA_VAL
));
518 u32 vertb
= (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO
) |
519 VC4_SET_FIELD(mode
->crtc_vtotal
- mode
->crtc_vsync_end
,
520 VC4_HDMI_VERTB_VBP
));
521 u32 vertb_even
= (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO
) |
522 VC4_SET_FIELD(mode
->crtc_vtotal
-
523 mode
->crtc_vsync_end
-
525 VC4_HDMI_VERTB_VBP
));
529 ret
= pm_runtime_get_sync(&hdmi
->pdev
->dev
);
531 DRM_ERROR("Failed to retain power domain: %d\n", ret
);
535 ret
= clk_set_rate(hdmi
->pixel_clock
,
537 ((mode
->flags
& DRM_MODE_FLAG_DBLCLK
) ? 2 : 1));
539 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret
);
543 ret
= clk_prepare_enable(hdmi
->pixel_clock
);
545 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret
);
549 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL
,
550 VC4_HDMI_SW_RESET_HDMI
|
551 VC4_HDMI_SW_RESET_FORMAT_DETECT
);
553 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL
, 0);
555 /* PHY should be in reset, like
556 * vc4_hdmi_encoder_disable() does.
558 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL
, 0xf << 16);
560 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL
, 0);
562 if (debug_dump_regs
) {
563 DRM_INFO("HDMI regs before:\n");
564 vc4_hdmi_dump_regs(dev
);
567 HD_WRITE(VC4_HD_VID_CTL
, 0);
569 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL
,
570 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL
) |
571 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT
|
572 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS
);
574 HDMI_WRITE(VC4_HDMI_HORZA
,
575 (vsync_pos
? VC4_HDMI_HORZA_VPOS
: 0) |
576 (hsync_pos
? VC4_HDMI_HORZA_HPOS
: 0) |
577 VC4_SET_FIELD(mode
->hdisplay
* pixel_rep
,
578 VC4_HDMI_HORZA_HAP
));
580 HDMI_WRITE(VC4_HDMI_HORZB
,
581 VC4_SET_FIELD((mode
->htotal
-
582 mode
->hsync_end
) * pixel_rep
,
583 VC4_HDMI_HORZB_HBP
) |
584 VC4_SET_FIELD((mode
->hsync_end
-
585 mode
->hsync_start
) * pixel_rep
,
586 VC4_HDMI_HORZB_HSP
) |
587 VC4_SET_FIELD((mode
->hsync_start
-
588 mode
->hdisplay
) * pixel_rep
,
589 VC4_HDMI_HORZB_HFP
));
591 HDMI_WRITE(VC4_HDMI_VERTA0
, verta
);
592 HDMI_WRITE(VC4_HDMI_VERTA1
, verta
);
594 HDMI_WRITE(VC4_HDMI_VERTB0
, vertb_even
);
595 HDMI_WRITE(VC4_HDMI_VERTB1
, vertb
);
597 HD_WRITE(VC4_HD_VID_CTL
,
598 (vsync_pos
? 0 : VC4_HD_VID_CTL_VSYNC_LOW
) |
599 (hsync_pos
? 0 : VC4_HD_VID_CTL_HSYNC_LOW
));
601 csc_ctl
= VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR
,
602 VC4_HD_CSC_CTL_ORDER
);
604 if (vc4_encoder
->hdmi_monitor
&&
605 drm_default_rgb_quant_range(mode
) ==
606 HDMI_QUANTIZATION_RANGE_LIMITED
) {
607 /* CEA VICs other than #1 requre limited range RGB
608 * output unless overridden by an AVI infoframe.
609 * Apply a colorspace conversion to squash 0-255 down
610 * to 16-235. The matrix here is:
617 csc_ctl
|= VC4_HD_CSC_CTL_ENABLE
;
618 csc_ctl
|= VC4_HD_CSC_CTL_RGB2YCC
;
619 csc_ctl
|= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM
,
620 VC4_HD_CSC_CTL_MODE
);
622 HD_WRITE(VC4_HD_CSC_12_11
, (0x000 << 16) | 0x000);
623 HD_WRITE(VC4_HD_CSC_14_13
, (0x100 << 16) | 0x6e0);
624 HD_WRITE(VC4_HD_CSC_22_21
, (0x6e0 << 16) | 0x000);
625 HD_WRITE(VC4_HD_CSC_24_23
, (0x100 << 16) | 0x000);
626 HD_WRITE(VC4_HD_CSC_32_31
, (0x000 << 16) | 0x6e0);
627 HD_WRITE(VC4_HD_CSC_34_33
, (0x100 << 16) | 0x000);
628 vc4_encoder
->limited_rgb_range
= true;
630 vc4_encoder
->limited_rgb_range
= false;
633 /* The RGB order applies even when CSC is disabled. */
634 HD_WRITE(VC4_HD_CSC_CTL
, csc_ctl
);
636 HDMI_WRITE(VC4_HDMI_FIFO_CTL
, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N
);
638 if (debug_dump_regs
) {
639 DRM_INFO("HDMI regs after:\n");
640 vc4_hdmi_dump_regs(dev
);
643 HD_WRITE(VC4_HD_VID_CTL
,
644 HD_READ(VC4_HD_VID_CTL
) |
645 VC4_HD_VID_CTL_ENABLE
|
646 VC4_HD_VID_CTL_UNDERFLOW_ENABLE
|
647 VC4_HD_VID_CTL_FRAME_COUNTER_RESET
);
649 if (vc4_encoder
->hdmi_monitor
) {
650 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL
,
651 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL
) |
652 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI
);
654 ret
= wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL
) &
655 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE
, 1000);
656 WARN_ONCE(ret
, "Timeout waiting for "
657 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
659 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG
,
660 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG
) &
661 ~(VC4_HDMI_RAM_PACKET_ENABLE
));
662 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL
,
663 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL
) &
664 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI
);
666 ret
= wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL
) &
667 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE
), 1000);
668 WARN_ONCE(ret
, "Timeout waiting for "
669 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
672 if (vc4_encoder
->hdmi_monitor
) {
675 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL
) &
676 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE
));
677 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL
,
678 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL
) |
679 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT
);
681 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG
,
682 VC4_HDMI_RAM_PACKET_ENABLE
);
684 vc4_hdmi_set_infoframes(encoder
);
686 drift
= HDMI_READ(VC4_HDMI_FIFO_CTL
);
687 drift
&= VC4_HDMI_FIFO_VALID_WRITE_MASK
;
689 HDMI_WRITE(VC4_HDMI_FIFO_CTL
,
690 drift
& ~VC4_HDMI_FIFO_CTL_RECENTER
);
691 HDMI_WRITE(VC4_HDMI_FIFO_CTL
,
692 drift
| VC4_HDMI_FIFO_CTL_RECENTER
);
694 HDMI_WRITE(VC4_HDMI_FIFO_CTL
,
695 drift
& ~VC4_HDMI_FIFO_CTL_RECENTER
);
696 HDMI_WRITE(VC4_HDMI_FIFO_CTL
,
697 drift
| VC4_HDMI_FIFO_CTL_RECENTER
);
699 ret
= wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL
) &
700 VC4_HDMI_FIFO_CTL_RECENTER_DONE
, 1);
701 WARN_ONCE(ret
, "Timeout waiting for "
702 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
706 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs
= {
707 .disable
= vc4_hdmi_encoder_disable
,
708 .enable
= vc4_hdmi_encoder_enable
,
711 /* HDMI audio codec callbacks */
712 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi
*hdmi
)
714 struct drm_device
*drm
= hdmi
->encoder
->dev
;
715 struct vc4_dev
*vc4
= to_vc4_dev(drm
);
716 u32 hsm_clock
= clk_get_rate(hdmi
->hsm_clock
);
719 rational_best_approximation(hsm_clock
, hdmi
->audio
.samplerate
,
720 VC4_HD_MAI_SMP_N_MASK
>>
721 VC4_HD_MAI_SMP_N_SHIFT
,
722 (VC4_HD_MAI_SMP_M_MASK
>>
723 VC4_HD_MAI_SMP_M_SHIFT
) + 1,
726 HD_WRITE(VC4_HD_MAI_SMP
,
727 VC4_SET_FIELD(n
, VC4_HD_MAI_SMP_N
) |
728 VC4_SET_FIELD(m
- 1, VC4_HD_MAI_SMP_M
));
731 static void vc4_hdmi_set_n_cts(struct vc4_hdmi
*hdmi
)
733 struct drm_encoder
*encoder
= hdmi
->encoder
;
734 struct drm_crtc
*crtc
= encoder
->crtc
;
735 struct drm_device
*drm
= encoder
->dev
;
736 struct vc4_dev
*vc4
= to_vc4_dev(drm
);
737 const struct drm_display_mode
*mode
= &crtc
->state
->adjusted_mode
;
738 u32 samplerate
= hdmi
->audio
.samplerate
;
742 n
= 128 * samplerate
/ 1000;
743 tmp
= (u64
)(mode
->clock
* 1000) * n
;
744 do_div(tmp
, 128 * samplerate
);
747 HDMI_WRITE(VC4_HDMI_CRP_CFG
,
748 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN
|
749 VC4_SET_FIELD(n
, VC4_HDMI_CRP_CFG_N
));
752 * We could get slightly more accurate clocks in some cases by
753 * providing a CTS_1 value. The two CTS values are alternated
754 * between based on the period fields
756 HDMI_WRITE(VC4_HDMI_CTS_0
, cts
);
757 HDMI_WRITE(VC4_HDMI_CTS_1
, cts
);
760 static inline struct vc4_hdmi
*dai_to_hdmi(struct snd_soc_dai
*dai
)
762 struct snd_soc_card
*card
= snd_soc_dai_get_drvdata(dai
);
764 return snd_soc_card_get_drvdata(card
);
767 static int vc4_hdmi_audio_startup(struct snd_pcm_substream
*substream
,
768 struct snd_soc_dai
*dai
)
770 struct vc4_hdmi
*hdmi
= dai_to_hdmi(dai
);
771 struct drm_encoder
*encoder
= hdmi
->encoder
;
772 struct vc4_dev
*vc4
= to_vc4_dev(encoder
->dev
);
775 if (hdmi
->audio
.substream
&& hdmi
->audio
.substream
!= substream
)
778 hdmi
->audio
.substream
= substream
;
781 * If the HDMI encoder hasn't probed, or the encoder is
782 * currently in DVI mode, treat the codec dai as missing.
784 if (!encoder
->crtc
|| !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG
) &
785 VC4_HDMI_RAM_PACKET_ENABLE
))
788 ret
= snd_pcm_hw_constraint_eld(substream
->runtime
,
789 hdmi
->connector
->eld
);
796 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
801 static void vc4_hdmi_audio_reset(struct vc4_hdmi
*hdmi
)
803 struct drm_encoder
*encoder
= hdmi
->encoder
;
804 struct drm_device
*drm
= encoder
->dev
;
805 struct device
*dev
= &hdmi
->pdev
->dev
;
806 struct vc4_dev
*vc4
= to_vc4_dev(drm
);
809 ret
= vc4_hdmi_stop_packet(encoder
, HDMI_INFOFRAME_TYPE_AUDIO
);
811 dev_err(dev
, "Failed to stop audio infoframe: %d\n", ret
);
813 HD_WRITE(VC4_HD_MAI_CTL
, VC4_HD_MAI_CTL_RESET
);
814 HD_WRITE(VC4_HD_MAI_CTL
, VC4_HD_MAI_CTL_ERRORF
);
815 HD_WRITE(VC4_HD_MAI_CTL
, VC4_HD_MAI_CTL_FLUSH
);
818 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream
*substream
,
819 struct snd_soc_dai
*dai
)
821 struct vc4_hdmi
*hdmi
= dai_to_hdmi(dai
);
823 if (substream
!= hdmi
->audio
.substream
)
826 vc4_hdmi_audio_reset(hdmi
);
828 hdmi
->audio
.substream
= NULL
;
831 /* HDMI audio codec callbacks */
832 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream
*substream
,
833 struct snd_pcm_hw_params
*params
,
834 struct snd_soc_dai
*dai
)
836 struct vc4_hdmi
*hdmi
= dai_to_hdmi(dai
);
837 struct drm_encoder
*encoder
= hdmi
->encoder
;
838 struct drm_device
*drm
= encoder
->dev
;
839 struct device
*dev
= &hdmi
->pdev
->dev
;
840 struct vc4_dev
*vc4
= to_vc4_dev(drm
);
841 u32 audio_packet_config
, channel_mask
;
844 if (substream
!= hdmi
->audio
.substream
)
847 dev_dbg(dev
, "%s: %u Hz, %d bit, %d channels\n", __func__
,
848 params_rate(params
), params_width(params
),
849 params_channels(params
));
851 hdmi
->audio
.channels
= params_channels(params
);
852 hdmi
->audio
.samplerate
= params_rate(params
);
854 HD_WRITE(VC4_HD_MAI_CTL
,
855 VC4_HD_MAI_CTL_RESET
|
856 VC4_HD_MAI_CTL_FLUSH
|
857 VC4_HD_MAI_CTL_DLATE
|
858 VC4_HD_MAI_CTL_ERRORE
|
859 VC4_HD_MAI_CTL_ERRORF
);
861 vc4_hdmi_audio_set_mai_clock(hdmi
);
863 audio_packet_config
=
864 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT
|
865 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS
|
866 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER
);
868 channel_mask
= GENMASK(hdmi
->audio
.channels
- 1, 0);
869 audio_packet_config
|= VC4_SET_FIELD(channel_mask
,
870 VC4_HDMI_AUDIO_PACKET_CEA_MASK
);
872 /* Set the MAI threshold. This logic mimics the firmware's. */
873 if (hdmi
->audio
.samplerate
> 96000) {
874 HD_WRITE(VC4_HD_MAI_THR
,
875 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH
) |
876 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW
));
877 } else if (hdmi
->audio
.samplerate
> 48000) {
878 HD_WRITE(VC4_HD_MAI_THR
,
879 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH
) |
880 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW
));
882 HD_WRITE(VC4_HD_MAI_THR
,
883 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH
) |
884 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW
) |
885 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH
) |
886 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW
));
889 HDMI_WRITE(VC4_HDMI_MAI_CONFIG
,
890 VC4_HDMI_MAI_CONFIG_BIT_REVERSE
|
891 VC4_SET_FIELD(channel_mask
, VC4_HDMI_MAI_CHANNEL_MASK
));
894 for (i
= 0; i
< 8; i
++) {
895 if (channel_mask
& BIT(i
))
896 channel_map
|= i
<< (3 * i
);
899 HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP
, channel_map
);
900 HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG
, audio_packet_config
);
901 vc4_hdmi_set_n_cts(hdmi
);
906 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream
*substream
, int cmd
,
907 struct snd_soc_dai
*dai
)
909 struct vc4_hdmi
*hdmi
= dai_to_hdmi(dai
);
910 struct drm_encoder
*encoder
= hdmi
->encoder
;
911 struct drm_device
*drm
= encoder
->dev
;
912 struct vc4_dev
*vc4
= to_vc4_dev(drm
);
915 case SNDRV_PCM_TRIGGER_START
:
916 vc4_hdmi_set_audio_infoframe(encoder
);
917 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0
,
918 HDMI_READ(VC4_HDMI_TX_PHY_CTL0
) &
919 ~VC4_HDMI_TX_PHY_RNG_PWRDN
);
920 HD_WRITE(VC4_HD_MAI_CTL
,
921 VC4_SET_FIELD(hdmi
->audio
.channels
,
922 VC4_HD_MAI_CTL_CHNUM
) |
923 VC4_HD_MAI_CTL_ENABLE
);
925 case SNDRV_PCM_TRIGGER_STOP
:
926 HD_WRITE(VC4_HD_MAI_CTL
,
927 VC4_HD_MAI_CTL_DLATE
|
928 VC4_HD_MAI_CTL_ERRORE
|
929 VC4_HD_MAI_CTL_ERRORF
);
930 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0
,
931 HDMI_READ(VC4_HDMI_TX_PHY_CTL0
) |
932 VC4_HDMI_TX_PHY_RNG_PWRDN
);
941 static inline struct vc4_hdmi
*
942 snd_component_to_hdmi(struct snd_soc_component
*component
)
944 struct snd_soc_card
*card
= snd_soc_component_get_drvdata(component
);
946 return snd_soc_card_get_drvdata(card
);
949 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol
*kcontrol
,
950 struct snd_ctl_elem_info
*uinfo
)
952 struct snd_soc_component
*component
= snd_kcontrol_chip(kcontrol
);
953 struct vc4_hdmi
*hdmi
= snd_component_to_hdmi(component
);
955 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BYTES
;
956 uinfo
->count
= sizeof(hdmi
->connector
->eld
);
961 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol
*kcontrol
,
962 struct snd_ctl_elem_value
*ucontrol
)
964 struct snd_soc_component
*component
= snd_kcontrol_chip(kcontrol
);
965 struct vc4_hdmi
*hdmi
= snd_component_to_hdmi(component
);
967 memcpy(ucontrol
->value
.bytes
.data
, hdmi
->connector
->eld
,
968 sizeof(hdmi
->connector
->eld
));
973 static const struct snd_kcontrol_new vc4_hdmi_audio_controls
[] = {
975 .access
= SNDRV_CTL_ELEM_ACCESS_READ
|
976 SNDRV_CTL_ELEM_ACCESS_VOLATILE
,
977 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
979 .info
= vc4_hdmi_audio_eld_ctl_info
,
980 .get
= vc4_hdmi_audio_eld_ctl_get
,
984 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets
[] = {
985 SND_SOC_DAPM_OUTPUT("TX"),
988 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes
[] = {
989 { "TX", NULL
, "Playback" },
992 static const struct snd_soc_codec_driver vc4_hdmi_audio_codec_drv
= {
993 .component_driver
= {
994 .controls
= vc4_hdmi_audio_controls
,
995 .num_controls
= ARRAY_SIZE(vc4_hdmi_audio_controls
),
996 .dapm_widgets
= vc4_hdmi_audio_widgets
,
997 .num_dapm_widgets
= ARRAY_SIZE(vc4_hdmi_audio_widgets
),
998 .dapm_routes
= vc4_hdmi_audio_routes
,
999 .num_dapm_routes
= ARRAY_SIZE(vc4_hdmi_audio_routes
),
1003 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops
= {
1004 .startup
= vc4_hdmi_audio_startup
,
1005 .shutdown
= vc4_hdmi_audio_shutdown
,
1006 .hw_params
= vc4_hdmi_audio_hw_params
,
1007 .set_fmt
= vc4_hdmi_audio_set_fmt
,
1008 .trigger
= vc4_hdmi_audio_trigger
,
1011 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv
= {
1012 .name
= "vc4-hdmi-hifi",
1014 .stream_name
= "Playback",
1017 .rates
= SNDRV_PCM_RATE_32000
| SNDRV_PCM_RATE_44100
|
1018 SNDRV_PCM_RATE_48000
| SNDRV_PCM_RATE_88200
|
1019 SNDRV_PCM_RATE_96000
| SNDRV_PCM_RATE_176400
|
1020 SNDRV_PCM_RATE_192000
,
1021 .formats
= SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE
,
1025 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp
= {
1026 .name
= "vc4-hdmi-cpu-dai-component",
1029 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai
*dai
)
1031 struct vc4_hdmi
*hdmi
= dai_to_hdmi(dai
);
1033 snd_soc_dai_init_dma_data(dai
, &hdmi
->audio
.dma_data
, NULL
);
1038 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv
= {
1039 .name
= "vc4-hdmi-cpu-dai",
1040 .probe
= vc4_hdmi_audio_cpu_dai_probe
,
1042 .stream_name
= "Playback",
1045 .rates
= SNDRV_PCM_RATE_32000
| SNDRV_PCM_RATE_44100
|
1046 SNDRV_PCM_RATE_48000
| SNDRV_PCM_RATE_88200
|
1047 SNDRV_PCM_RATE_96000
| SNDRV_PCM_RATE_176400
|
1048 SNDRV_PCM_RATE_192000
,
1049 .formats
= SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE
,
1051 .ops
= &vc4_hdmi_audio_dai_ops
,
1054 static const struct snd_dmaengine_pcm_config pcm_conf
= {
1055 .chan_names
[SNDRV_PCM_STREAM_PLAYBACK
] = "audio-rx",
1056 .prepare_slave_config
= snd_dmaengine_pcm_prepare_slave_config
,
1059 static int vc4_hdmi_audio_init(struct vc4_hdmi
*hdmi
)
1061 struct snd_soc_dai_link
*dai_link
= &hdmi
->audio
.link
;
1062 struct snd_soc_card
*card
= &hdmi
->audio
.card
;
1063 struct device
*dev
= &hdmi
->pdev
->dev
;
1067 if (!of_find_property(dev
->of_node
, "dmas", NULL
)) {
1069 "'dmas' DT property is missing, no HDMI audio\n");
1074 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1075 * the bus address specified in the DT, because the physical address
1076 * (the one returned by platform_get_resource()) is not appropriate
1077 * for DMA transfers.
1078 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1080 addr
= of_get_address(dev
->of_node
, 1, NULL
, NULL
);
1081 hdmi
->audio
.dma_data
.addr
= be32_to_cpup(addr
) + VC4_HD_MAI_DATA
;
1082 hdmi
->audio
.dma_data
.addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
1083 hdmi
->audio
.dma_data
.maxburst
= 2;
1085 ret
= devm_snd_dmaengine_pcm_register(dev
, &pcm_conf
, 0);
1087 dev_err(dev
, "Could not register PCM component: %d\n", ret
);
1091 ret
= devm_snd_soc_register_component(dev
, &vc4_hdmi_audio_cpu_dai_comp
,
1092 &vc4_hdmi_audio_cpu_dai_drv
, 1);
1094 dev_err(dev
, "Could not register CPU DAI: %d\n", ret
);
1098 /* register codec and codec dai */
1099 ret
= snd_soc_register_codec(dev
, &vc4_hdmi_audio_codec_drv
,
1100 &vc4_hdmi_audio_codec_dai_drv
, 1);
1102 dev_err(dev
, "Could not register codec: %d\n", ret
);
1106 dai_link
->name
= "MAI";
1107 dai_link
->stream_name
= "MAI PCM";
1108 dai_link
->codec_dai_name
= vc4_hdmi_audio_codec_dai_drv
.name
;
1109 dai_link
->cpu_dai_name
= dev_name(dev
);
1110 dai_link
->codec_name
= dev_name(dev
);
1111 dai_link
->platform_name
= dev_name(dev
);
1113 card
->dai_link
= dai_link
;
1114 card
->num_links
= 1;
1115 card
->name
= "vc4-hdmi";
1119 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1120 * stores a pointer to the snd card object in dev->driver_data. This
1121 * means we cannot use it for something else. The hdmi back-pointer is
1122 * now stored in card->drvdata and should be retrieved with
1123 * snd_soc_card_get_drvdata() if needed.
1125 snd_soc_card_set_drvdata(card
, hdmi
);
1126 ret
= devm_snd_soc_register_card(dev
, card
);
1128 dev_err(dev
, "Could not register sound card: %d\n", ret
);
1129 goto unregister_codec
;
1135 snd_soc_unregister_codec(dev
);
1140 static void vc4_hdmi_audio_cleanup(struct vc4_hdmi
*hdmi
)
1142 struct device
*dev
= &hdmi
->pdev
->dev
;
1145 * If drvdata is not set this means the audio card was not
1146 * registered, just skip codec unregistration in this case.
1148 if (dev_get_drvdata(dev
))
1149 snd_soc_unregister_codec(dev
);
1152 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1153 static irqreturn_t
vc4_cec_irq_handler_thread(int irq
, void *priv
)
1155 struct vc4_dev
*vc4
= priv
;
1156 struct vc4_hdmi
*hdmi
= vc4
->hdmi
;
1158 if (hdmi
->cec_irq_was_rx
) {
1159 if (hdmi
->cec_rx_msg
.len
)
1160 cec_received_msg(hdmi
->cec_adap
, &hdmi
->cec_rx_msg
);
1161 } else if (hdmi
->cec_tx_ok
) {
1162 cec_transmit_done(hdmi
->cec_adap
, CEC_TX_STATUS_OK
,
1166 * This CEC implementation makes 1 retry, so if we
1167 * get a NACK, then that means it made 2 attempts.
1169 cec_transmit_done(hdmi
->cec_adap
, CEC_TX_STATUS_NACK
,
1175 static void vc4_cec_read_msg(struct vc4_dev
*vc4
, u32 cntrl1
)
1177 struct cec_msg
*msg
= &vc4
->hdmi
->cec_rx_msg
;
1180 msg
->len
= 1 + ((cntrl1
& VC4_HDMI_CEC_REC_WRD_CNT_MASK
) >>
1181 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT
);
1182 for (i
= 0; i
< msg
->len
; i
+= 4) {
1183 u32 val
= HDMI_READ(VC4_HDMI_CEC_RX_DATA_1
+ i
);
1185 msg
->msg
[i
] = val
& 0xff;
1186 msg
->msg
[i
+ 1] = (val
>> 8) & 0xff;
1187 msg
->msg
[i
+ 2] = (val
>> 16) & 0xff;
1188 msg
->msg
[i
+ 3] = (val
>> 24) & 0xff;
1192 static irqreturn_t
vc4_cec_irq_handler(int irq
, void *priv
)
1194 struct vc4_dev
*vc4
= priv
;
1195 struct vc4_hdmi
*hdmi
= vc4
->hdmi
;
1196 u32 stat
= HDMI_READ(VC4_HDMI_CPU_STATUS
);
1199 if (!(stat
& VC4_HDMI_CPU_CEC
))
1201 hdmi
->cec_rx_msg
.len
= 0;
1202 cntrl1
= HDMI_READ(VC4_HDMI_CEC_CNTRL_1
);
1203 cntrl5
= HDMI_READ(VC4_HDMI_CEC_CNTRL_5
);
1204 hdmi
->cec_irq_was_rx
= cntrl5
& VC4_HDMI_CEC_RX_CEC_INT
;
1205 if (hdmi
->cec_irq_was_rx
) {
1206 vc4_cec_read_msg(vc4
, cntrl1
);
1207 cntrl1
|= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF
;
1208 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1
, cntrl1
);
1209 cntrl1
&= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF
;
1211 hdmi
->cec_tx_ok
= cntrl1
& VC4_HDMI_CEC_TX_STATUS_GOOD
;
1212 cntrl1
&= ~VC4_HDMI_CEC_START_XMIT_BEGIN
;
1214 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1
, cntrl1
);
1215 HDMI_WRITE(VC4_HDMI_CPU_CLEAR
, VC4_HDMI_CPU_CEC
);
1217 return IRQ_WAKE_THREAD
;
1220 static int vc4_hdmi_cec_adap_enable(struct cec_adapter
*adap
, bool enable
)
1222 struct vc4_dev
*vc4
= cec_get_drvdata(adap
);
1223 /* clock period in microseconds */
1224 const u32 usecs
= 1000000 / CEC_CLOCK_FREQ
;
1225 u32 val
= HDMI_READ(VC4_HDMI_CEC_CNTRL_5
);
1227 val
&= ~(VC4_HDMI_CEC_TX_SW_RESET
| VC4_HDMI_CEC_RX_SW_RESET
|
1228 VC4_HDMI_CEC_CNT_TO_4700_US_MASK
|
1229 VC4_HDMI_CEC_CNT_TO_4500_US_MASK
);
1230 val
|= ((4700 / usecs
) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT
) |
1231 ((4500 / usecs
) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT
);
1234 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5
, val
|
1235 VC4_HDMI_CEC_TX_SW_RESET
| VC4_HDMI_CEC_RX_SW_RESET
);
1236 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5
, val
);
1237 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2
,
1238 ((1500 / usecs
) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT
) |
1239 ((1300 / usecs
) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT
) |
1240 ((800 / usecs
) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT
) |
1241 ((600 / usecs
) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT
) |
1242 ((400 / usecs
) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT
));
1243 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3
,
1244 ((2750 / usecs
) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT
) |
1245 ((2400 / usecs
) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT
) |
1246 ((2050 / usecs
) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT
) |
1247 ((1700 / usecs
) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT
));
1248 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4
,
1249 ((4300 / usecs
) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT
) |
1250 ((3900 / usecs
) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT
) |
1251 ((3600 / usecs
) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT
) |
1252 ((3500 / usecs
) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT
));
1254 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR
, VC4_HDMI_CPU_CEC
);
1256 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET
, VC4_HDMI_CPU_CEC
);
1257 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5
, val
|
1258 VC4_HDMI_CEC_TX_SW_RESET
| VC4_HDMI_CEC_RX_SW_RESET
);
1263 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter
*adap
, u8 log_addr
)
1265 struct vc4_dev
*vc4
= cec_get_drvdata(adap
);
1267 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1
,
1268 (HDMI_READ(VC4_HDMI_CEC_CNTRL_1
) & ~VC4_HDMI_CEC_ADDR_MASK
) |
1269 (log_addr
& 0xf) << VC4_HDMI_CEC_ADDR_SHIFT
);
1273 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter
*adap
, u8 attempts
,
1274 u32 signal_free_time
, struct cec_msg
*msg
)
1276 struct vc4_dev
*vc4
= cec_get_drvdata(adap
);
1280 for (i
= 0; i
< msg
->len
; i
+= 4)
1281 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1
+ i
,
1283 (msg
->msg
[i
+ 1] << 8) |
1284 (msg
->msg
[i
+ 2] << 16) |
1285 (msg
->msg
[i
+ 3] << 24));
1287 val
= HDMI_READ(VC4_HDMI_CEC_CNTRL_1
);
1288 val
&= ~VC4_HDMI_CEC_START_XMIT_BEGIN
;
1289 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1
, val
);
1290 val
&= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK
;
1291 val
|= (msg
->len
- 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT
;
1292 val
|= VC4_HDMI_CEC_START_XMIT_BEGIN
;
1294 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1
, val
);
1298 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops
= {
1299 .adap_enable
= vc4_hdmi_cec_adap_enable
,
1300 .adap_log_addr
= vc4_hdmi_cec_adap_log_addr
,
1301 .adap_transmit
= vc4_hdmi_cec_adap_transmit
,
1305 static int vc4_hdmi_bind(struct device
*dev
, struct device
*master
, void *data
)
1307 struct platform_device
*pdev
= to_platform_device(dev
);
1308 struct drm_device
*drm
= dev_get_drvdata(master
);
1309 struct vc4_dev
*vc4
= drm
->dev_private
;
1310 struct vc4_hdmi
*hdmi
;
1311 struct vc4_hdmi_encoder
*vc4_hdmi_encoder
;
1312 struct device_node
*ddc_node
;
1316 hdmi
= devm_kzalloc(dev
, sizeof(*hdmi
), GFP_KERNEL
);
1320 vc4_hdmi_encoder
= devm_kzalloc(dev
, sizeof(*vc4_hdmi_encoder
),
1322 if (!vc4_hdmi_encoder
)
1324 vc4_hdmi_encoder
->base
.type
= VC4_ENCODER_TYPE_HDMI
;
1325 hdmi
->encoder
= &vc4_hdmi_encoder
->base
.base
;
1328 hdmi
->hdmicore_regs
= vc4_ioremap_regs(pdev
, 0);
1329 if (IS_ERR(hdmi
->hdmicore_regs
))
1330 return PTR_ERR(hdmi
->hdmicore_regs
);
1332 hdmi
->hd_regs
= vc4_ioremap_regs(pdev
, 1);
1333 if (IS_ERR(hdmi
->hd_regs
))
1334 return PTR_ERR(hdmi
->hd_regs
);
1336 hdmi
->pixel_clock
= devm_clk_get(dev
, "pixel");
1337 if (IS_ERR(hdmi
->pixel_clock
)) {
1338 DRM_ERROR("Failed to get pixel clock\n");
1339 return PTR_ERR(hdmi
->pixel_clock
);
1341 hdmi
->hsm_clock
= devm_clk_get(dev
, "hdmi");
1342 if (IS_ERR(hdmi
->hsm_clock
)) {
1343 DRM_ERROR("Failed to get HDMI state machine clock\n");
1344 return PTR_ERR(hdmi
->hsm_clock
);
1347 ddc_node
= of_parse_phandle(dev
->of_node
, "ddc", 0);
1349 DRM_ERROR("Failed to find ddc node in device tree\n");
1353 hdmi
->ddc
= of_find_i2c_adapter_by_node(ddc_node
);
1354 of_node_put(ddc_node
);
1356 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1357 return -EPROBE_DEFER
;
1360 /* This is the rate that is set by the firmware. The number
1361 * needs to be a bit higher than the pixel clock rate
1362 * (generally 148.5Mhz).
1364 ret
= clk_set_rate(hdmi
->hsm_clock
, HSM_CLOCK_FREQ
);
1366 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret
);
1370 ret
= clk_prepare_enable(hdmi
->hsm_clock
);
1372 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
1377 /* Only use the GPIO HPD pin if present in the DT, otherwise
1378 * we'll use the HDMI core's register.
1380 if (of_find_property(dev
->of_node
, "hpd-gpios", &value
)) {
1381 enum of_gpio_flags hpd_gpio_flags
;
1383 hdmi
->hpd_gpio
= of_get_named_gpio_flags(dev
->of_node
,
1386 if (hdmi
->hpd_gpio
< 0) {
1387 ret
= hdmi
->hpd_gpio
;
1388 goto err_unprepare_hsm
;
1391 hdmi
->hpd_active_low
= hpd_gpio_flags
& OF_GPIO_ACTIVE_LOW
;
1396 /* HDMI core must be enabled. */
1397 if (!(HD_READ(VC4_HD_M_CTL
) & VC4_HD_M_ENABLE
)) {
1398 HD_WRITE(VC4_HD_M_CTL
, VC4_HD_M_SW_RST
);
1400 HD_WRITE(VC4_HD_M_CTL
, 0);
1402 HD_WRITE(VC4_HD_M_CTL
, VC4_HD_M_ENABLE
);
1404 pm_runtime_enable(dev
);
1406 drm_encoder_init(drm
, hdmi
->encoder
, &vc4_hdmi_encoder_funcs
,
1407 DRM_MODE_ENCODER_TMDS
, NULL
);
1408 drm_encoder_helper_add(hdmi
->encoder
, &vc4_hdmi_encoder_helper_funcs
);
1410 hdmi
->connector
= vc4_hdmi_connector_init(drm
, hdmi
->encoder
);
1411 if (IS_ERR(hdmi
->connector
)) {
1412 ret
= PTR_ERR(hdmi
->connector
);
1413 goto err_destroy_encoder
;
1415 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1416 hdmi
->cec_adap
= cec_allocate_adapter(&vc4_hdmi_cec_adap_ops
,
1420 CEC_CAP_PASSTHROUGH
|
1422 ret
= PTR_ERR_OR_ZERO(hdmi
->cec_adap
);
1424 goto err_destroy_conn
;
1425 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET
, 0xffffffff);
1426 value
= HDMI_READ(VC4_HDMI_CEC_CNTRL_1
);
1427 value
&= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK
;
1429 * Set the logical address to Unregistered and set the clock
1430 * divider: the hsm_clock rate and this divider setting will
1431 * give a 40 kHz CEC clock.
1433 value
|= VC4_HDMI_CEC_ADDR_MASK
|
1434 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT
);
1435 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1
, value
);
1436 ret
= devm_request_threaded_irq(dev
, platform_get_irq(pdev
, 0),
1437 vc4_cec_irq_handler
,
1438 vc4_cec_irq_handler_thread
, 0,
1439 "vc4 hdmi cec", vc4
);
1441 goto err_delete_cec_adap
;
1442 ret
= cec_register_adapter(hdmi
->cec_adap
, dev
);
1444 goto err_delete_cec_adap
;
1447 ret
= vc4_hdmi_audio_init(hdmi
);
1449 goto err_destroy_encoder
;
1453 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1454 err_delete_cec_adap
:
1455 cec_delete_adapter(hdmi
->cec_adap
);
1457 vc4_hdmi_connector_destroy(hdmi
->connector
);
1459 err_destroy_encoder
:
1460 vc4_hdmi_encoder_destroy(hdmi
->encoder
);
1462 clk_disable_unprepare(hdmi
->hsm_clock
);
1463 pm_runtime_disable(dev
);
1465 put_device(&hdmi
->ddc
->dev
);
1470 static void vc4_hdmi_unbind(struct device
*dev
, struct device
*master
,
1473 struct drm_device
*drm
= dev_get_drvdata(master
);
1474 struct vc4_dev
*vc4
= drm
->dev_private
;
1475 struct vc4_hdmi
*hdmi
= vc4
->hdmi
;
1477 vc4_hdmi_audio_cleanup(hdmi
);
1478 cec_unregister_adapter(hdmi
->cec_adap
);
1479 vc4_hdmi_connector_destroy(hdmi
->connector
);
1480 vc4_hdmi_encoder_destroy(hdmi
->encoder
);
1482 clk_disable_unprepare(hdmi
->hsm_clock
);
1483 pm_runtime_disable(dev
);
1485 put_device(&hdmi
->ddc
->dev
);
1490 static const struct component_ops vc4_hdmi_ops
= {
1491 .bind
= vc4_hdmi_bind
,
1492 .unbind
= vc4_hdmi_unbind
,
1495 static int vc4_hdmi_dev_probe(struct platform_device
*pdev
)
1497 return component_add(&pdev
->dev
, &vc4_hdmi_ops
);
1500 static int vc4_hdmi_dev_remove(struct platform_device
*pdev
)
1502 component_del(&pdev
->dev
, &vc4_hdmi_ops
);
1506 static const struct of_device_id vc4_hdmi_dt_match
[] = {
1507 { .compatible
= "brcm,bcm2835-hdmi" },
1511 struct platform_driver vc4_hdmi_driver
= {
1512 .probe
= vc4_hdmi_dev_probe
,
1513 .remove
= vc4_hdmi_dev_remove
,
1516 .of_match_table
= vc4_hdmi_dt_match
,