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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / vmwgfx / vmwgfx_drv.c
1 /**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27 #include <linux/module.h>
28
29 #include <drm/drmP.h>
30 #include "vmwgfx_drv.h"
31 #include <drm/ttm/ttm_placement.h>
32 #include <drm/ttm/ttm_bo_driver.h>
33 #include <drm/ttm/ttm_object.h>
34 #include <drm/ttm/ttm_module.h>
35 #include <linux/dma_remapping.h>
36
37 #define VMWGFX_DRIVER_NAME "vmwgfx"
38 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
39 #define VMWGFX_CHIP_SVGAII 0
40 #define VMW_FB_RESERVATION 0
41
42 #define VMW_MIN_INITIAL_WIDTH 800
43 #define VMW_MIN_INITIAL_HEIGHT 600
44
45
46 /**
47 * Fully encoded drm commands. Might move to vmw_drm.h
48 */
49
50 #define DRM_IOCTL_VMW_GET_PARAM \
51 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
52 struct drm_vmw_getparam_arg)
53 #define DRM_IOCTL_VMW_ALLOC_DMABUF \
54 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
55 union drm_vmw_alloc_dmabuf_arg)
56 #define DRM_IOCTL_VMW_UNREF_DMABUF \
57 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
58 struct drm_vmw_unref_dmabuf_arg)
59 #define DRM_IOCTL_VMW_CURSOR_BYPASS \
60 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
61 struct drm_vmw_cursor_bypass_arg)
62
63 #define DRM_IOCTL_VMW_CONTROL_STREAM \
64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
65 struct drm_vmw_control_stream_arg)
66 #define DRM_IOCTL_VMW_CLAIM_STREAM \
67 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
68 struct drm_vmw_stream_arg)
69 #define DRM_IOCTL_VMW_UNREF_STREAM \
70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
71 struct drm_vmw_stream_arg)
72
73 #define DRM_IOCTL_VMW_CREATE_CONTEXT \
74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
75 struct drm_vmw_context_arg)
76 #define DRM_IOCTL_VMW_UNREF_CONTEXT \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
78 struct drm_vmw_context_arg)
79 #define DRM_IOCTL_VMW_CREATE_SURFACE \
80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
81 union drm_vmw_surface_create_arg)
82 #define DRM_IOCTL_VMW_UNREF_SURFACE \
83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
84 struct drm_vmw_surface_arg)
85 #define DRM_IOCTL_VMW_REF_SURFACE \
86 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
87 union drm_vmw_surface_reference_arg)
88 #define DRM_IOCTL_VMW_EXECBUF \
89 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
90 struct drm_vmw_execbuf_arg)
91 #define DRM_IOCTL_VMW_GET_3D_CAP \
92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
93 struct drm_vmw_get_3d_cap_arg)
94 #define DRM_IOCTL_VMW_FENCE_WAIT \
95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
96 struct drm_vmw_fence_wait_arg)
97 #define DRM_IOCTL_VMW_FENCE_SIGNALED \
98 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
99 struct drm_vmw_fence_signaled_arg)
100 #define DRM_IOCTL_VMW_FENCE_UNREF \
101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
102 struct drm_vmw_fence_arg)
103 #define DRM_IOCTL_VMW_FENCE_EVENT \
104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
105 struct drm_vmw_fence_event_arg)
106 #define DRM_IOCTL_VMW_PRESENT \
107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
108 struct drm_vmw_present_arg)
109 #define DRM_IOCTL_VMW_PRESENT_READBACK \
110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
111 struct drm_vmw_present_readback_arg)
112 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \
113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
114 struct drm_vmw_update_layout_arg)
115 #define DRM_IOCTL_VMW_CREATE_SHADER \
116 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
117 struct drm_vmw_shader_create_arg)
118 #define DRM_IOCTL_VMW_UNREF_SHADER \
119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
120 struct drm_vmw_shader_arg)
121 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
122 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
123 union drm_vmw_gb_surface_create_arg)
124 #define DRM_IOCTL_VMW_GB_SURFACE_REF \
125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
126 union drm_vmw_gb_surface_reference_arg)
127 #define DRM_IOCTL_VMW_SYNCCPU \
128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
129 struct drm_vmw_synccpu_arg)
130
131 /**
132 * The core DRM version of this macro doesn't account for
133 * DRM_COMMAND_BASE.
134 */
135
136 #define VMW_IOCTL_DEF(ioctl, func, flags) \
137 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
138
139 /**
140 * Ioctl definitions.
141 */
142
143 static const struct drm_ioctl_desc vmw_ioctls[] = {
144 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
145 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
146 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
147 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
148 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
149 DRM_UNLOCKED | DRM_RENDER_ALLOW),
150 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
151 vmw_kms_cursor_bypass_ioctl,
152 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
153
154 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
155 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
156 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
157 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
158 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
159 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
160
161 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
162 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
163 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
164 DRM_UNLOCKED | DRM_RENDER_ALLOW),
165 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
166 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
167 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
168 DRM_UNLOCKED | DRM_RENDER_ALLOW),
169 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
170 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
171 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
172 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
173 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
174 DRM_UNLOCKED | DRM_RENDER_ALLOW),
175 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
176 vmw_fence_obj_signaled_ioctl,
177 DRM_UNLOCKED | DRM_RENDER_ALLOW),
178 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
179 DRM_UNLOCKED | DRM_RENDER_ALLOW),
180 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
181 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
182 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
183 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
184
185 /* these allow direct access to the framebuffers mark as master only */
186 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
187 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
188 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
189 vmw_present_readback_ioctl,
190 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
191 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
192 vmw_kms_update_layout_ioctl,
193 DRM_MASTER | DRM_UNLOCKED),
194 VMW_IOCTL_DEF(VMW_CREATE_SHADER,
195 vmw_shader_define_ioctl,
196 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
197 VMW_IOCTL_DEF(VMW_UNREF_SHADER,
198 vmw_shader_destroy_ioctl,
199 DRM_UNLOCKED | DRM_RENDER_ALLOW),
200 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
201 vmw_gb_surface_define_ioctl,
202 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
203 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
204 vmw_gb_surface_reference_ioctl,
205 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
206 VMW_IOCTL_DEF(VMW_SYNCCPU,
207 vmw_user_dmabuf_synccpu_ioctl,
208 DRM_UNLOCKED | DRM_RENDER_ALLOW),
209 };
210
211 static struct pci_device_id vmw_pci_id_list[] = {
212 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
213 {0, 0, 0}
214 };
215 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
216
217 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
218 static int vmw_force_iommu;
219 static int vmw_restrict_iommu;
220 static int vmw_force_coherent;
221 static int vmw_restrict_dma_mask;
222
223 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
224 static void vmw_master_init(struct vmw_master *);
225 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
226 void *ptr);
227
228 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
229 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
230 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
231 module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
232 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
233 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
234 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
235 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
236 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
237 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
238
239
240 static void vmw_print_capabilities(uint32_t capabilities)
241 {
242 DRM_INFO("Capabilities:\n");
243 if (capabilities & SVGA_CAP_RECT_COPY)
244 DRM_INFO(" Rect copy.\n");
245 if (capabilities & SVGA_CAP_CURSOR)
246 DRM_INFO(" Cursor.\n");
247 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
248 DRM_INFO(" Cursor bypass.\n");
249 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
250 DRM_INFO(" Cursor bypass 2.\n");
251 if (capabilities & SVGA_CAP_8BIT_EMULATION)
252 DRM_INFO(" 8bit emulation.\n");
253 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
254 DRM_INFO(" Alpha cursor.\n");
255 if (capabilities & SVGA_CAP_3D)
256 DRM_INFO(" 3D.\n");
257 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
258 DRM_INFO(" Extended Fifo.\n");
259 if (capabilities & SVGA_CAP_MULTIMON)
260 DRM_INFO(" Multimon.\n");
261 if (capabilities & SVGA_CAP_PITCHLOCK)
262 DRM_INFO(" Pitchlock.\n");
263 if (capabilities & SVGA_CAP_IRQMASK)
264 DRM_INFO(" Irq mask.\n");
265 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
266 DRM_INFO(" Display Topology.\n");
267 if (capabilities & SVGA_CAP_GMR)
268 DRM_INFO(" GMR.\n");
269 if (capabilities & SVGA_CAP_TRACES)
270 DRM_INFO(" Traces.\n");
271 if (capabilities & SVGA_CAP_GMR2)
272 DRM_INFO(" GMR2.\n");
273 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
274 DRM_INFO(" Screen Object 2.\n");
275 if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
276 DRM_INFO(" Command Buffers.\n");
277 if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
278 DRM_INFO(" Command Buffers 2.\n");
279 if (capabilities & SVGA_CAP_GBOBJECTS)
280 DRM_INFO(" Guest Backed Resources.\n");
281 }
282
283 /**
284 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
285 *
286 * @dev_priv: A device private structure.
287 *
288 * This function creates a small buffer object that holds the query
289 * result for dummy queries emitted as query barriers.
290 * The function will then map the first page and initialize a pending
291 * occlusion query result structure, Finally it will unmap the buffer.
292 * No interruptible waits are done within this function.
293 *
294 * Returns an error if bo creation or initialization fails.
295 */
296 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
297 {
298 int ret;
299 struct ttm_buffer_object *bo;
300 struct ttm_bo_kmap_obj map;
301 volatile SVGA3dQueryResult *result;
302 bool dummy;
303
304 /*
305 * Create the bo as pinned, so that a tryreserve will
306 * immediately succeed. This is because we're the only
307 * user of the bo currently.
308 */
309 ret = ttm_bo_create(&dev_priv->bdev,
310 PAGE_SIZE,
311 ttm_bo_type_device,
312 &vmw_sys_ne_placement,
313 0, false, NULL,
314 &bo);
315
316 if (unlikely(ret != 0))
317 return ret;
318
319 ret = ttm_bo_reserve(bo, false, true, false, NULL);
320 BUG_ON(ret != 0);
321
322 ret = ttm_bo_kmap(bo, 0, 1, &map);
323 if (likely(ret == 0)) {
324 result = ttm_kmap_obj_virtual(&map, &dummy);
325 result->totalSize = sizeof(*result);
326 result->state = SVGA3D_QUERYSTATE_PENDING;
327 result->result32 = 0xff;
328 ttm_bo_kunmap(&map);
329 }
330 vmw_bo_pin(bo, false);
331 ttm_bo_unreserve(bo);
332
333 if (unlikely(ret != 0)) {
334 DRM_ERROR("Dummy query buffer map failed.\n");
335 ttm_bo_unref(&bo);
336 } else
337 dev_priv->dummy_query_bo = bo;
338
339 return ret;
340 }
341
342 static int vmw_request_device(struct vmw_private *dev_priv)
343 {
344 int ret;
345
346 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
347 if (unlikely(ret != 0)) {
348 DRM_ERROR("Unable to initialize FIFO.\n");
349 return ret;
350 }
351 vmw_fence_fifo_up(dev_priv->fman);
352 if (dev_priv->has_mob) {
353 ret = vmw_otables_setup(dev_priv);
354 if (unlikely(ret != 0)) {
355 DRM_ERROR("Unable to initialize "
356 "guest Memory OBjects.\n");
357 goto out_no_mob;
358 }
359 }
360 ret = vmw_dummy_query_bo_create(dev_priv);
361 if (unlikely(ret != 0))
362 goto out_no_query_bo;
363
364 return 0;
365
366 out_no_query_bo:
367 if (dev_priv->has_mob)
368 vmw_otables_takedown(dev_priv);
369 out_no_mob:
370 vmw_fence_fifo_down(dev_priv->fman);
371 vmw_fifo_release(dev_priv, &dev_priv->fifo);
372 return ret;
373 }
374
375 static void vmw_release_device(struct vmw_private *dev_priv)
376 {
377 /*
378 * Previous destructions should've released
379 * the pinned bo.
380 */
381
382 BUG_ON(dev_priv->pinned_bo != NULL);
383
384 ttm_bo_unref(&dev_priv->dummy_query_bo);
385 if (dev_priv->has_mob)
386 vmw_otables_takedown(dev_priv);
387 vmw_fence_fifo_down(dev_priv->fman);
388 vmw_fifo_release(dev_priv, &dev_priv->fifo);
389 }
390
391
392 /**
393 * Increase the 3d resource refcount.
394 * If the count was prevously zero, initialize the fifo, switching to svga
395 * mode. Note that the master holds a ref as well, and may request an
396 * explicit switch to svga mode if fb is not running, using @unhide_svga.
397 */
398 int vmw_3d_resource_inc(struct vmw_private *dev_priv,
399 bool unhide_svga)
400 {
401 int ret = 0;
402
403 mutex_lock(&dev_priv->release_mutex);
404 if (unlikely(dev_priv->num_3d_resources++ == 0)) {
405 ret = vmw_request_device(dev_priv);
406 if (unlikely(ret != 0))
407 --dev_priv->num_3d_resources;
408 } else if (unhide_svga) {
409 mutex_lock(&dev_priv->hw_mutex);
410 vmw_write(dev_priv, SVGA_REG_ENABLE,
411 vmw_read(dev_priv, SVGA_REG_ENABLE) &
412 ~SVGA_REG_ENABLE_HIDE);
413 mutex_unlock(&dev_priv->hw_mutex);
414 }
415
416 mutex_unlock(&dev_priv->release_mutex);
417 return ret;
418 }
419
420 /**
421 * Decrease the 3d resource refcount.
422 * If the count reaches zero, disable the fifo, switching to vga mode.
423 * Note that the master holds a refcount as well, and may request an
424 * explicit switch to vga mode when it releases its refcount to account
425 * for the situation of an X server vt switch to VGA with 3d resources
426 * active.
427 */
428 void vmw_3d_resource_dec(struct vmw_private *dev_priv,
429 bool hide_svga)
430 {
431 int32_t n3d;
432
433 mutex_lock(&dev_priv->release_mutex);
434 if (unlikely(--dev_priv->num_3d_resources == 0))
435 vmw_release_device(dev_priv);
436 else if (hide_svga) {
437 mutex_lock(&dev_priv->hw_mutex);
438 vmw_write(dev_priv, SVGA_REG_ENABLE,
439 vmw_read(dev_priv, SVGA_REG_ENABLE) |
440 SVGA_REG_ENABLE_HIDE);
441 mutex_unlock(&dev_priv->hw_mutex);
442 }
443
444 n3d = (int32_t) dev_priv->num_3d_resources;
445 mutex_unlock(&dev_priv->release_mutex);
446
447 BUG_ON(n3d < 0);
448 }
449
450 /**
451 * Sets the initial_[width|height] fields on the given vmw_private.
452 *
453 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
454 * clamping the value to fb_max_[width|height] fields and the
455 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
456 * If the values appear to be invalid, set them to
457 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
458 */
459 static void vmw_get_initial_size(struct vmw_private *dev_priv)
460 {
461 uint32_t width;
462 uint32_t height;
463
464 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
465 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
466
467 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
468 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
469
470 if (width > dev_priv->fb_max_width ||
471 height > dev_priv->fb_max_height) {
472
473 /*
474 * This is a host error and shouldn't occur.
475 */
476
477 width = VMW_MIN_INITIAL_WIDTH;
478 height = VMW_MIN_INITIAL_HEIGHT;
479 }
480
481 dev_priv->initial_width = width;
482 dev_priv->initial_height = height;
483 }
484
485 /**
486 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
487 * system.
488 *
489 * @dev_priv: Pointer to a struct vmw_private
490 *
491 * This functions tries to determine the IOMMU setup and what actions
492 * need to be taken by the driver to make system pages visible to the
493 * device.
494 * If this function decides that DMA is not possible, it returns -EINVAL.
495 * The driver may then try to disable features of the device that require
496 * DMA.
497 */
498 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
499 {
500 static const char *names[vmw_dma_map_max] = {
501 [vmw_dma_phys] = "Using physical TTM page addresses.",
502 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
503 [vmw_dma_map_populate] = "Keeping DMA mappings.",
504 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
505 #ifdef CONFIG_X86
506 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
507
508 #ifdef CONFIG_INTEL_IOMMU
509 if (intel_iommu_enabled) {
510 dev_priv->map_mode = vmw_dma_map_populate;
511 goto out_fixup;
512 }
513 #endif
514
515 if (!(vmw_force_iommu || vmw_force_coherent)) {
516 dev_priv->map_mode = vmw_dma_phys;
517 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
518 return 0;
519 }
520
521 dev_priv->map_mode = vmw_dma_map_populate;
522
523 if (dma_ops->sync_single_for_cpu)
524 dev_priv->map_mode = vmw_dma_alloc_coherent;
525 #ifdef CONFIG_SWIOTLB
526 if (swiotlb_nr_tbl() == 0)
527 dev_priv->map_mode = vmw_dma_map_populate;
528 #endif
529
530 #ifdef CONFIG_INTEL_IOMMU
531 out_fixup:
532 #endif
533 if (dev_priv->map_mode == vmw_dma_map_populate &&
534 vmw_restrict_iommu)
535 dev_priv->map_mode = vmw_dma_map_bind;
536
537 if (vmw_force_coherent)
538 dev_priv->map_mode = vmw_dma_alloc_coherent;
539
540 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
541 /*
542 * No coherent page pool
543 */
544 if (dev_priv->map_mode == vmw_dma_alloc_coherent)
545 return -EINVAL;
546 #endif
547
548 #else /* CONFIG_X86 */
549 dev_priv->map_mode = vmw_dma_map_populate;
550 #endif /* CONFIG_X86 */
551
552 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
553
554 return 0;
555 }
556
557 /**
558 * vmw_dma_masks - set required page- and dma masks
559 *
560 * @dev: Pointer to struct drm-device
561 *
562 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
563 * restriction also for 64-bit systems.
564 */
565 #ifdef CONFIG_INTEL_IOMMU
566 static int vmw_dma_masks(struct vmw_private *dev_priv)
567 {
568 struct drm_device *dev = dev_priv->dev;
569
570 if (intel_iommu_enabled &&
571 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
572 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
573 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
574 }
575 return 0;
576 }
577 #else
578 static int vmw_dma_masks(struct vmw_private *dev_priv)
579 {
580 return 0;
581 }
582 #endif
583
584 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
585 {
586 struct vmw_private *dev_priv;
587 int ret;
588 uint32_t svga_id;
589 enum vmw_res_type i;
590 bool refuse_dma = false;
591
592 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
593 if (unlikely(dev_priv == NULL)) {
594 DRM_ERROR("Failed allocating a device private struct.\n");
595 return -ENOMEM;
596 }
597
598 pci_set_master(dev->pdev);
599
600 dev_priv->dev = dev;
601 dev_priv->vmw_chipset = chipset;
602 dev_priv->last_read_seqno = (uint32_t) -100;
603 mutex_init(&dev_priv->hw_mutex);
604 mutex_init(&dev_priv->cmdbuf_mutex);
605 mutex_init(&dev_priv->release_mutex);
606 mutex_init(&dev_priv->binding_mutex);
607 rwlock_init(&dev_priv->resource_lock);
608 ttm_lock_init(&dev_priv->reservation_sem);
609
610 for (i = vmw_res_context; i < vmw_res_max; ++i) {
611 idr_init(&dev_priv->res_idr[i]);
612 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
613 }
614
615 mutex_init(&dev_priv->init_mutex);
616 init_waitqueue_head(&dev_priv->fence_queue);
617 init_waitqueue_head(&dev_priv->fifo_queue);
618 dev_priv->fence_queue_waiters = 0;
619 atomic_set(&dev_priv->fifo_queue_waiters, 0);
620
621 dev_priv->used_memory_size = 0;
622
623 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
624 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
625 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
626
627 dev_priv->enable_fb = enable_fbdev;
628
629 mutex_lock(&dev_priv->hw_mutex);
630
631 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
632 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
633 if (svga_id != SVGA_ID_2) {
634 ret = -ENOSYS;
635 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
636 mutex_unlock(&dev_priv->hw_mutex);
637 goto out_err0;
638 }
639
640 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
641 ret = vmw_dma_select_mode(dev_priv);
642 if (unlikely(ret != 0)) {
643 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
644 refuse_dma = true;
645 }
646
647 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
648 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
649 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
650 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
651
652 vmw_get_initial_size(dev_priv);
653
654 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
655 dev_priv->max_gmr_ids =
656 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
657 dev_priv->max_gmr_pages =
658 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
659 dev_priv->memory_size =
660 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
661 dev_priv->memory_size -= dev_priv->vram_size;
662 } else {
663 /*
664 * An arbitrary limit of 512MiB on surface
665 * memory. But all HWV8 hardware supports GMR2.
666 */
667 dev_priv->memory_size = 512*1024*1024;
668 }
669 dev_priv->max_mob_pages = 0;
670 dev_priv->max_mob_size = 0;
671 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
672 uint64_t mem_size =
673 vmw_read(dev_priv,
674 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
675
676 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
677 dev_priv->prim_bb_mem =
678 vmw_read(dev_priv,
679 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
680 dev_priv->max_mob_size =
681 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
682 } else
683 dev_priv->prim_bb_mem = dev_priv->vram_size;
684
685 ret = vmw_dma_masks(dev_priv);
686 if (unlikely(ret != 0)) {
687 mutex_unlock(&dev_priv->hw_mutex);
688 goto out_err0;
689 }
690
691 if (unlikely(dev_priv->prim_bb_mem < dev_priv->vram_size))
692 dev_priv->prim_bb_mem = dev_priv->vram_size;
693
694 mutex_unlock(&dev_priv->hw_mutex);
695
696 vmw_print_capabilities(dev_priv->capabilities);
697
698 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
699 DRM_INFO("Max GMR ids is %u\n",
700 (unsigned)dev_priv->max_gmr_ids);
701 DRM_INFO("Max number of GMR pages is %u\n",
702 (unsigned)dev_priv->max_gmr_pages);
703 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
704 (unsigned)dev_priv->memory_size / 1024);
705 }
706 DRM_INFO("Maximum display memory size is %u kiB\n",
707 dev_priv->prim_bb_mem / 1024);
708 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
709 dev_priv->vram_start, dev_priv->vram_size / 1024);
710 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
711 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
712
713 ret = vmw_ttm_global_init(dev_priv);
714 if (unlikely(ret != 0))
715 goto out_err0;
716
717
718 vmw_master_init(&dev_priv->fbdev_master);
719 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
720 dev_priv->active_master = &dev_priv->fbdev_master;
721
722
723 ret = ttm_bo_device_init(&dev_priv->bdev,
724 dev_priv->bo_global_ref.ref.object,
725 &vmw_bo_driver,
726 dev->anon_inode->i_mapping,
727 VMWGFX_FILE_PAGE_OFFSET,
728 false);
729 if (unlikely(ret != 0)) {
730 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
731 goto out_err1;
732 }
733
734 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
735 (dev_priv->vram_size >> PAGE_SHIFT));
736 if (unlikely(ret != 0)) {
737 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
738 goto out_err2;
739 }
740
741 dev_priv->has_gmr = true;
742 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
743 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
744 VMW_PL_GMR) != 0) {
745 DRM_INFO("No GMR memory available. "
746 "Graphics memory resources are very limited.\n");
747 dev_priv->has_gmr = false;
748 }
749
750 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
751 dev_priv->has_mob = true;
752 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
753 VMW_PL_MOB) != 0) {
754 DRM_INFO("No MOB memory available. "
755 "3D will be disabled.\n");
756 dev_priv->has_mob = false;
757 }
758 }
759
760 dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start,
761 dev_priv->mmio_size);
762
763 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
764 dev_priv->mmio_size);
765
766 if (unlikely(dev_priv->mmio_virt == NULL)) {
767 ret = -ENOMEM;
768 DRM_ERROR("Failed mapping MMIO.\n");
769 goto out_err3;
770 }
771
772 /* Need mmio memory to check for fifo pitchlock cap. */
773 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
774 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
775 !vmw_fifo_have_pitchlock(dev_priv)) {
776 ret = -ENOSYS;
777 DRM_ERROR("Hardware has no pitchlock\n");
778 goto out_err4;
779 }
780
781 dev_priv->tdev = ttm_object_device_init
782 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
783
784 if (unlikely(dev_priv->tdev == NULL)) {
785 DRM_ERROR("Unable to initialize TTM object management.\n");
786 ret = -ENOMEM;
787 goto out_err4;
788 }
789
790 dev->dev_private = dev_priv;
791
792 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
793 dev_priv->stealth = (ret != 0);
794 if (dev_priv->stealth) {
795 /**
796 * Request at least the mmio PCI resource.
797 */
798
799 DRM_INFO("It appears like vesafb is loaded. "
800 "Ignore above error if any.\n");
801 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
802 if (unlikely(ret != 0)) {
803 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
804 goto out_no_device;
805 }
806 }
807
808 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
809 ret = drm_irq_install(dev, dev->pdev->irq);
810 if (ret != 0) {
811 DRM_ERROR("Failed installing irq: %d\n", ret);
812 goto out_no_irq;
813 }
814 }
815
816 dev_priv->fman = vmw_fence_manager_init(dev_priv);
817 if (unlikely(dev_priv->fman == NULL)) {
818 ret = -ENOMEM;
819 goto out_no_fman;
820 }
821
822 vmw_kms_save_vga(dev_priv);
823
824 /* Start kms and overlay systems, needs fifo. */
825 ret = vmw_kms_init(dev_priv);
826 if (unlikely(ret != 0))
827 goto out_no_kms;
828 vmw_overlay_init(dev_priv);
829
830 if (dev_priv->enable_fb) {
831 ret = vmw_3d_resource_inc(dev_priv, true);
832 if (unlikely(ret != 0))
833 goto out_no_fifo;
834 vmw_fb_init(dev_priv);
835 }
836
837 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
838 register_pm_notifier(&dev_priv->pm_nb);
839
840 return 0;
841
842 out_no_fifo:
843 vmw_overlay_close(dev_priv);
844 vmw_kms_close(dev_priv);
845 out_no_kms:
846 vmw_kms_restore_vga(dev_priv);
847 vmw_fence_manager_takedown(dev_priv->fman);
848 out_no_fman:
849 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
850 drm_irq_uninstall(dev_priv->dev);
851 out_no_irq:
852 if (dev_priv->stealth)
853 pci_release_region(dev->pdev, 2);
854 else
855 pci_release_regions(dev->pdev);
856 out_no_device:
857 ttm_object_device_release(&dev_priv->tdev);
858 out_err4:
859 iounmap(dev_priv->mmio_virt);
860 out_err3:
861 arch_phys_wc_del(dev_priv->mmio_mtrr);
862 if (dev_priv->has_mob)
863 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
864 if (dev_priv->has_gmr)
865 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
866 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
867 out_err2:
868 (void)ttm_bo_device_release(&dev_priv->bdev);
869 out_err1:
870 vmw_ttm_global_release(dev_priv);
871 out_err0:
872 for (i = vmw_res_context; i < vmw_res_max; ++i)
873 idr_destroy(&dev_priv->res_idr[i]);
874
875 kfree(dev_priv);
876 return ret;
877 }
878
879 static int vmw_driver_unload(struct drm_device *dev)
880 {
881 struct vmw_private *dev_priv = vmw_priv(dev);
882 enum vmw_res_type i;
883
884 unregister_pm_notifier(&dev_priv->pm_nb);
885
886 if (dev_priv->ctx.res_ht_initialized)
887 drm_ht_remove(&dev_priv->ctx.res_ht);
888 if (dev_priv->ctx.cmd_bounce)
889 vfree(dev_priv->ctx.cmd_bounce);
890 if (dev_priv->enable_fb) {
891 vmw_fb_close(dev_priv);
892 vmw_kms_restore_vga(dev_priv);
893 vmw_3d_resource_dec(dev_priv, false);
894 }
895 vmw_kms_close(dev_priv);
896 vmw_overlay_close(dev_priv);
897 vmw_fence_manager_takedown(dev_priv->fman);
898 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
899 drm_irq_uninstall(dev_priv->dev);
900 if (dev_priv->stealth)
901 pci_release_region(dev->pdev, 2);
902 else
903 pci_release_regions(dev->pdev);
904
905 ttm_object_device_release(&dev_priv->tdev);
906 iounmap(dev_priv->mmio_virt);
907 arch_phys_wc_del(dev_priv->mmio_mtrr);
908 if (dev_priv->has_mob)
909 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
910 if (dev_priv->has_gmr)
911 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
912 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
913 (void)ttm_bo_device_release(&dev_priv->bdev);
914 vmw_ttm_global_release(dev_priv);
915
916 for (i = vmw_res_context; i < vmw_res_max; ++i)
917 idr_destroy(&dev_priv->res_idr[i]);
918
919 kfree(dev_priv);
920
921 return 0;
922 }
923
924 static void vmw_preclose(struct drm_device *dev,
925 struct drm_file *file_priv)
926 {
927 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
928 struct vmw_private *dev_priv = vmw_priv(dev);
929
930 vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
931 }
932
933 static void vmw_postclose(struct drm_device *dev,
934 struct drm_file *file_priv)
935 {
936 struct vmw_fpriv *vmw_fp;
937
938 vmw_fp = vmw_fpriv(file_priv);
939
940 if (vmw_fp->locked_master) {
941 struct vmw_master *vmaster =
942 vmw_master(vmw_fp->locked_master);
943
944 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
945 ttm_vt_unlock(&vmaster->lock);
946 drm_master_put(&vmw_fp->locked_master);
947 }
948
949 ttm_object_file_release(&vmw_fp->tfile);
950 kfree(vmw_fp);
951 }
952
953 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
954 {
955 struct vmw_private *dev_priv = vmw_priv(dev);
956 struct vmw_fpriv *vmw_fp;
957 int ret = -ENOMEM;
958
959 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
960 if (unlikely(vmw_fp == NULL))
961 return ret;
962
963 INIT_LIST_HEAD(&vmw_fp->fence_events);
964 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
965 if (unlikely(vmw_fp->tfile == NULL))
966 goto out_no_tfile;
967
968 file_priv->driver_priv = vmw_fp;
969
970 return 0;
971
972 out_no_tfile:
973 kfree(vmw_fp);
974 return ret;
975 }
976
977 static struct vmw_master *vmw_master_check(struct drm_device *dev,
978 struct drm_file *file_priv,
979 unsigned int flags)
980 {
981 int ret;
982 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
983 struct vmw_master *vmaster;
984
985 if (file_priv->minor->type != DRM_MINOR_LEGACY ||
986 !(flags & DRM_AUTH))
987 return NULL;
988
989 ret = mutex_lock_interruptible(&dev->master_mutex);
990 if (unlikely(ret != 0))
991 return ERR_PTR(-ERESTARTSYS);
992
993 if (file_priv->is_master) {
994 mutex_unlock(&dev->master_mutex);
995 return NULL;
996 }
997
998 /*
999 * Check if we were previously master, but now dropped.
1000 */
1001 if (vmw_fp->locked_master) {
1002 mutex_unlock(&dev->master_mutex);
1003 DRM_ERROR("Dropped master trying to access ioctl that "
1004 "requires authentication.\n");
1005 return ERR_PTR(-EACCES);
1006 }
1007 mutex_unlock(&dev->master_mutex);
1008
1009 /*
1010 * Taking the drm_global_mutex after the TTM lock might deadlock
1011 */
1012 if (!(flags & DRM_UNLOCKED)) {
1013 DRM_ERROR("Refusing locked ioctl access.\n");
1014 return ERR_PTR(-EDEADLK);
1015 }
1016
1017 /*
1018 * Take the TTM lock. Possibly sleep waiting for the authenticating
1019 * master to become master again, or for a SIGTERM if the
1020 * authenticating master exits.
1021 */
1022 vmaster = vmw_master(file_priv->master);
1023 ret = ttm_read_lock(&vmaster->lock, true);
1024 if (unlikely(ret != 0))
1025 vmaster = ERR_PTR(ret);
1026
1027 return vmaster;
1028 }
1029
1030 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1031 unsigned long arg,
1032 long (*ioctl_func)(struct file *, unsigned int,
1033 unsigned long))
1034 {
1035 struct drm_file *file_priv = filp->private_data;
1036 struct drm_device *dev = file_priv->minor->dev;
1037 unsigned int nr = DRM_IOCTL_NR(cmd);
1038 struct vmw_master *vmaster;
1039 unsigned int flags;
1040 long ret;
1041
1042 /*
1043 * Do extra checking on driver private ioctls.
1044 */
1045
1046 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1047 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1048 const struct drm_ioctl_desc *ioctl =
1049 &vmw_ioctls[nr - DRM_COMMAND_BASE];
1050
1051 if (unlikely(ioctl->cmd_drv != cmd)) {
1052 DRM_ERROR("Invalid command format, ioctl %d\n",
1053 nr - DRM_COMMAND_BASE);
1054 return -EINVAL;
1055 }
1056 flags = ioctl->flags;
1057 } else if (!drm_ioctl_flags(nr, &flags))
1058 return -EINVAL;
1059
1060 vmaster = vmw_master_check(dev, file_priv, flags);
1061 if (unlikely(IS_ERR(vmaster))) {
1062 DRM_INFO("IOCTL ERROR %d\n", nr);
1063 return PTR_ERR(vmaster);
1064 }
1065
1066 ret = ioctl_func(filp, cmd, arg);
1067 if (vmaster)
1068 ttm_read_unlock(&vmaster->lock);
1069
1070 return ret;
1071 }
1072
1073 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1074 unsigned long arg)
1075 {
1076 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1077 }
1078
1079 #ifdef CONFIG_COMPAT
1080 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1081 unsigned long arg)
1082 {
1083 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1084 }
1085 #endif
1086
1087 static void vmw_lastclose(struct drm_device *dev)
1088 {
1089 struct drm_crtc *crtc;
1090 struct drm_mode_set set;
1091 int ret;
1092
1093 set.x = 0;
1094 set.y = 0;
1095 set.fb = NULL;
1096 set.mode = NULL;
1097 set.connectors = NULL;
1098 set.num_connectors = 0;
1099
1100 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1101 set.crtc = crtc;
1102 ret = drm_mode_set_config_internal(&set);
1103 WARN_ON(ret != 0);
1104 }
1105
1106 }
1107
1108 static void vmw_master_init(struct vmw_master *vmaster)
1109 {
1110 ttm_lock_init(&vmaster->lock);
1111 INIT_LIST_HEAD(&vmaster->fb_surf);
1112 mutex_init(&vmaster->fb_surf_mutex);
1113 }
1114
1115 static int vmw_master_create(struct drm_device *dev,
1116 struct drm_master *master)
1117 {
1118 struct vmw_master *vmaster;
1119
1120 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1121 if (unlikely(vmaster == NULL))
1122 return -ENOMEM;
1123
1124 vmw_master_init(vmaster);
1125 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1126 master->driver_priv = vmaster;
1127
1128 return 0;
1129 }
1130
1131 static void vmw_master_destroy(struct drm_device *dev,
1132 struct drm_master *master)
1133 {
1134 struct vmw_master *vmaster = vmw_master(master);
1135
1136 master->driver_priv = NULL;
1137 kfree(vmaster);
1138 }
1139
1140
1141 static int vmw_master_set(struct drm_device *dev,
1142 struct drm_file *file_priv,
1143 bool from_open)
1144 {
1145 struct vmw_private *dev_priv = vmw_priv(dev);
1146 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1147 struct vmw_master *active = dev_priv->active_master;
1148 struct vmw_master *vmaster = vmw_master(file_priv->master);
1149 int ret = 0;
1150
1151 if (!dev_priv->enable_fb) {
1152 ret = vmw_3d_resource_inc(dev_priv, true);
1153 if (unlikely(ret != 0))
1154 return ret;
1155 vmw_kms_save_vga(dev_priv);
1156 mutex_lock(&dev_priv->hw_mutex);
1157 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
1158 mutex_unlock(&dev_priv->hw_mutex);
1159 }
1160
1161 if (active) {
1162 BUG_ON(active != &dev_priv->fbdev_master);
1163 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1164 if (unlikely(ret != 0))
1165 goto out_no_active_lock;
1166
1167 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1168 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1169 if (unlikely(ret != 0)) {
1170 DRM_ERROR("Unable to clean VRAM on "
1171 "master drop.\n");
1172 }
1173
1174 dev_priv->active_master = NULL;
1175 }
1176
1177 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1178 if (!from_open) {
1179 ttm_vt_unlock(&vmaster->lock);
1180 BUG_ON(vmw_fp->locked_master != file_priv->master);
1181 drm_master_put(&vmw_fp->locked_master);
1182 }
1183
1184 dev_priv->active_master = vmaster;
1185
1186 return 0;
1187
1188 out_no_active_lock:
1189 if (!dev_priv->enable_fb) {
1190 vmw_kms_restore_vga(dev_priv);
1191 vmw_3d_resource_dec(dev_priv, true);
1192 mutex_lock(&dev_priv->hw_mutex);
1193 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1194 mutex_unlock(&dev_priv->hw_mutex);
1195 }
1196 return ret;
1197 }
1198
1199 static void vmw_master_drop(struct drm_device *dev,
1200 struct drm_file *file_priv,
1201 bool from_release)
1202 {
1203 struct vmw_private *dev_priv = vmw_priv(dev);
1204 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1205 struct vmw_master *vmaster = vmw_master(file_priv->master);
1206 int ret;
1207
1208 /**
1209 * Make sure the master doesn't disappear while we have
1210 * it locked.
1211 */
1212
1213 vmw_fp->locked_master = drm_master_get(file_priv->master);
1214 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1215 if (unlikely((ret != 0))) {
1216 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1217 drm_master_put(&vmw_fp->locked_master);
1218 }
1219
1220 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1221 vmw_execbuf_release_pinned_bo(dev_priv);
1222
1223 if (!dev_priv->enable_fb) {
1224 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1225 if (unlikely(ret != 0))
1226 DRM_ERROR("Unable to clean VRAM on master drop.\n");
1227 vmw_kms_restore_vga(dev_priv);
1228 vmw_3d_resource_dec(dev_priv, true);
1229 mutex_lock(&dev_priv->hw_mutex);
1230 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1231 mutex_unlock(&dev_priv->hw_mutex);
1232 }
1233
1234 dev_priv->active_master = &dev_priv->fbdev_master;
1235 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1236 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1237
1238 if (dev_priv->enable_fb)
1239 vmw_fb_on(dev_priv);
1240 }
1241
1242
1243 static void vmw_remove(struct pci_dev *pdev)
1244 {
1245 struct drm_device *dev = pci_get_drvdata(pdev);
1246
1247 drm_put_dev(dev);
1248 }
1249
1250 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1251 void *ptr)
1252 {
1253 struct vmw_private *dev_priv =
1254 container_of(nb, struct vmw_private, pm_nb);
1255
1256 switch (val) {
1257 case PM_HIBERNATION_PREPARE:
1258 case PM_SUSPEND_PREPARE:
1259 ttm_suspend_lock(&dev_priv->reservation_sem);
1260
1261 /**
1262 * This empties VRAM and unbinds all GMR bindings.
1263 * Buffer contents is moved to swappable memory.
1264 */
1265 vmw_execbuf_release_pinned_bo(dev_priv);
1266 vmw_resource_evict_all(dev_priv);
1267 ttm_bo_swapout_all(&dev_priv->bdev);
1268
1269 break;
1270 case PM_POST_HIBERNATION:
1271 case PM_POST_SUSPEND:
1272 case PM_POST_RESTORE:
1273 ttm_suspend_unlock(&dev_priv->reservation_sem);
1274
1275 break;
1276 case PM_RESTORE_PREPARE:
1277 break;
1278 default:
1279 break;
1280 }
1281 return 0;
1282 }
1283
1284 /**
1285 * These might not be needed with the virtual SVGA device.
1286 */
1287
1288 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1289 {
1290 struct drm_device *dev = pci_get_drvdata(pdev);
1291 struct vmw_private *dev_priv = vmw_priv(dev);
1292
1293 if (dev_priv->num_3d_resources != 0) {
1294 DRM_INFO("Can't suspend or hibernate "
1295 "while 3D resources are active.\n");
1296 return -EBUSY;
1297 }
1298
1299 pci_save_state(pdev);
1300 pci_disable_device(pdev);
1301 pci_set_power_state(pdev, PCI_D3hot);
1302 return 0;
1303 }
1304
1305 static int vmw_pci_resume(struct pci_dev *pdev)
1306 {
1307 pci_set_power_state(pdev, PCI_D0);
1308 pci_restore_state(pdev);
1309 return pci_enable_device(pdev);
1310 }
1311
1312 static int vmw_pm_suspend(struct device *kdev)
1313 {
1314 struct pci_dev *pdev = to_pci_dev(kdev);
1315 struct pm_message dummy;
1316
1317 dummy.event = 0;
1318
1319 return vmw_pci_suspend(pdev, dummy);
1320 }
1321
1322 static int vmw_pm_resume(struct device *kdev)
1323 {
1324 struct pci_dev *pdev = to_pci_dev(kdev);
1325
1326 return vmw_pci_resume(pdev);
1327 }
1328
1329 static int vmw_pm_prepare(struct device *kdev)
1330 {
1331 struct pci_dev *pdev = to_pci_dev(kdev);
1332 struct drm_device *dev = pci_get_drvdata(pdev);
1333 struct vmw_private *dev_priv = vmw_priv(dev);
1334
1335 /**
1336 * Release 3d reference held by fbdev and potentially
1337 * stop fifo.
1338 */
1339 dev_priv->suspended = true;
1340 if (dev_priv->enable_fb)
1341 vmw_3d_resource_dec(dev_priv, true);
1342
1343 if (dev_priv->num_3d_resources != 0) {
1344
1345 DRM_INFO("Can't suspend or hibernate "
1346 "while 3D resources are active.\n");
1347
1348 if (dev_priv->enable_fb)
1349 vmw_3d_resource_inc(dev_priv, true);
1350 dev_priv->suspended = false;
1351 return -EBUSY;
1352 }
1353
1354 return 0;
1355 }
1356
1357 static void vmw_pm_complete(struct device *kdev)
1358 {
1359 struct pci_dev *pdev = to_pci_dev(kdev);
1360 struct drm_device *dev = pci_get_drvdata(pdev);
1361 struct vmw_private *dev_priv = vmw_priv(dev);
1362
1363 mutex_lock(&dev_priv->hw_mutex);
1364 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1365 (void) vmw_read(dev_priv, SVGA_REG_ID);
1366 mutex_unlock(&dev_priv->hw_mutex);
1367
1368 /**
1369 * Reclaim 3d reference held by fbdev and potentially
1370 * start fifo.
1371 */
1372 if (dev_priv->enable_fb)
1373 vmw_3d_resource_inc(dev_priv, false);
1374
1375 dev_priv->suspended = false;
1376 }
1377
1378 static const struct dev_pm_ops vmw_pm_ops = {
1379 .prepare = vmw_pm_prepare,
1380 .complete = vmw_pm_complete,
1381 .suspend = vmw_pm_suspend,
1382 .resume = vmw_pm_resume,
1383 };
1384
1385 static const struct file_operations vmwgfx_driver_fops = {
1386 .owner = THIS_MODULE,
1387 .open = drm_open,
1388 .release = drm_release,
1389 .unlocked_ioctl = vmw_unlocked_ioctl,
1390 .mmap = vmw_mmap,
1391 .poll = vmw_fops_poll,
1392 .read = vmw_fops_read,
1393 #if defined(CONFIG_COMPAT)
1394 .compat_ioctl = vmw_compat_ioctl,
1395 #endif
1396 .llseek = noop_llseek,
1397 };
1398
1399 static struct drm_driver driver = {
1400 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1401 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER,
1402 .load = vmw_driver_load,
1403 .unload = vmw_driver_unload,
1404 .lastclose = vmw_lastclose,
1405 .irq_preinstall = vmw_irq_preinstall,
1406 .irq_postinstall = vmw_irq_postinstall,
1407 .irq_uninstall = vmw_irq_uninstall,
1408 .irq_handler = vmw_irq_handler,
1409 .get_vblank_counter = vmw_get_vblank_counter,
1410 .enable_vblank = vmw_enable_vblank,
1411 .disable_vblank = vmw_disable_vblank,
1412 .ioctls = vmw_ioctls,
1413 .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1414 .master_create = vmw_master_create,
1415 .master_destroy = vmw_master_destroy,
1416 .master_set = vmw_master_set,
1417 .master_drop = vmw_master_drop,
1418 .open = vmw_driver_open,
1419 .preclose = vmw_preclose,
1420 .postclose = vmw_postclose,
1421 .set_busid = drm_pci_set_busid,
1422
1423 .dumb_create = vmw_dumb_create,
1424 .dumb_map_offset = vmw_dumb_map_offset,
1425 .dumb_destroy = vmw_dumb_destroy,
1426
1427 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1428 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1429
1430 .fops = &vmwgfx_driver_fops,
1431 .name = VMWGFX_DRIVER_NAME,
1432 .desc = VMWGFX_DRIVER_DESC,
1433 .date = VMWGFX_DRIVER_DATE,
1434 .major = VMWGFX_DRIVER_MAJOR,
1435 .minor = VMWGFX_DRIVER_MINOR,
1436 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1437 };
1438
1439 static struct pci_driver vmw_pci_driver = {
1440 .name = VMWGFX_DRIVER_NAME,
1441 .id_table = vmw_pci_id_list,
1442 .probe = vmw_probe,
1443 .remove = vmw_remove,
1444 .driver = {
1445 .pm = &vmw_pm_ops
1446 }
1447 };
1448
1449 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1450 {
1451 return drm_get_pci_dev(pdev, ent, &driver);
1452 }
1453
1454 static int __init vmwgfx_init(void)
1455 {
1456 int ret;
1457 ret = drm_pci_init(&driver, &vmw_pci_driver);
1458 if (ret)
1459 DRM_ERROR("Failed initializing DRM.\n");
1460 return ret;
1461 }
1462
1463 static void __exit vmwgfx_exit(void)
1464 {
1465 drm_pci_exit(&driver, &vmw_pci_driver);
1466 }
1467
1468 module_init(vmwgfx_init);
1469 module_exit(vmwgfx_exit);
1470
1471 MODULE_AUTHOR("VMware Inc. and others");
1472 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1473 MODULE_LICENSE("GPL and additional rights");
1474 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1475 __stringify(VMWGFX_DRIVER_MINOR) "."
1476 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1477 "0");
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