1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /**************************************************************************
4 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include <linux/console.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/mem_encrypt.h>
34 #include <drm/drm_aperture.h>
35 #include <drm/drm_drv.h>
36 #include <drm/drm_ioctl.h>
37 #include <drm/drm_sysfs.h>
38 #include <drm/ttm/ttm_bo_driver.h>
39 #include <drm/ttm/ttm_range_manager.h>
40 #include <drm/ttm/ttm_placement.h>
41 #include <generated/utsrelease.h>
43 #include "ttm_object.h"
44 #include "vmwgfx_binding.h"
45 #include "vmwgfx_devcaps.h"
46 #include "vmwgfx_drv.h"
47 #include "vmwgfx_mksstat.h"
49 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
51 #define VMW_MIN_INITIAL_WIDTH 800
52 #define VMW_MIN_INITIAL_HEIGHT 600
54 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE)
58 * Fully encoded drm commands. Might move to vmw_drm.h
61 #define DRM_IOCTL_VMW_GET_PARAM \
62 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
63 struct drm_vmw_getparam_arg)
64 #define DRM_IOCTL_VMW_ALLOC_DMABUF \
65 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
66 union drm_vmw_alloc_dmabuf_arg)
67 #define DRM_IOCTL_VMW_UNREF_DMABUF \
68 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
69 struct drm_vmw_unref_dmabuf_arg)
70 #define DRM_IOCTL_VMW_CURSOR_BYPASS \
71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
72 struct drm_vmw_cursor_bypass_arg)
74 #define DRM_IOCTL_VMW_CONTROL_STREAM \
75 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
76 struct drm_vmw_control_stream_arg)
77 #define DRM_IOCTL_VMW_CLAIM_STREAM \
78 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
79 struct drm_vmw_stream_arg)
80 #define DRM_IOCTL_VMW_UNREF_STREAM \
81 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
82 struct drm_vmw_stream_arg)
84 #define DRM_IOCTL_VMW_CREATE_CONTEXT \
85 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
86 struct drm_vmw_context_arg)
87 #define DRM_IOCTL_VMW_UNREF_CONTEXT \
88 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
89 struct drm_vmw_context_arg)
90 #define DRM_IOCTL_VMW_CREATE_SURFACE \
91 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
92 union drm_vmw_surface_create_arg)
93 #define DRM_IOCTL_VMW_UNREF_SURFACE \
94 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
95 struct drm_vmw_surface_arg)
96 #define DRM_IOCTL_VMW_REF_SURFACE \
97 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
98 union drm_vmw_surface_reference_arg)
99 #define DRM_IOCTL_VMW_EXECBUF \
100 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
101 struct drm_vmw_execbuf_arg)
102 #define DRM_IOCTL_VMW_GET_3D_CAP \
103 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
104 struct drm_vmw_get_3d_cap_arg)
105 #define DRM_IOCTL_VMW_FENCE_WAIT \
106 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
107 struct drm_vmw_fence_wait_arg)
108 #define DRM_IOCTL_VMW_FENCE_SIGNALED \
109 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
110 struct drm_vmw_fence_signaled_arg)
111 #define DRM_IOCTL_VMW_FENCE_UNREF \
112 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
113 struct drm_vmw_fence_arg)
114 #define DRM_IOCTL_VMW_FENCE_EVENT \
115 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
116 struct drm_vmw_fence_event_arg)
117 #define DRM_IOCTL_VMW_PRESENT \
118 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
119 struct drm_vmw_present_arg)
120 #define DRM_IOCTL_VMW_PRESENT_READBACK \
121 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
122 struct drm_vmw_present_readback_arg)
123 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \
124 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
125 struct drm_vmw_update_layout_arg)
126 #define DRM_IOCTL_VMW_CREATE_SHADER \
127 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
128 struct drm_vmw_shader_create_arg)
129 #define DRM_IOCTL_VMW_UNREF_SHADER \
130 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
131 struct drm_vmw_shader_arg)
132 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
133 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
134 union drm_vmw_gb_surface_create_arg)
135 #define DRM_IOCTL_VMW_GB_SURFACE_REF \
136 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
137 union drm_vmw_gb_surface_reference_arg)
138 #define DRM_IOCTL_VMW_SYNCCPU \
139 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
140 struct drm_vmw_synccpu_arg)
141 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \
142 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \
143 struct drm_vmw_context_arg)
144 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \
145 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \
146 union drm_vmw_gb_surface_create_ext_arg)
147 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \
148 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \
149 union drm_vmw_gb_surface_reference_ext_arg)
150 #define DRM_IOCTL_VMW_MSG \
151 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \
152 struct drm_vmw_msg_arg)
153 #define DRM_IOCTL_VMW_MKSSTAT_RESET \
154 DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET)
155 #define DRM_IOCTL_VMW_MKSSTAT_ADD \
156 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \
157 struct drm_vmw_mksstat_add_arg)
158 #define DRM_IOCTL_VMW_MKSSTAT_REMOVE \
159 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \
160 struct drm_vmw_mksstat_remove_arg)
166 static const struct drm_ioctl_desc vmw_ioctls
[] = {
167 DRM_IOCTL_DEF_DRV(VMW_GET_PARAM
, vmw_getparam_ioctl
,
169 DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF
, vmw_bo_alloc_ioctl
,
171 DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF
, vmw_bo_unref_ioctl
,
173 DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS
,
174 vmw_kms_cursor_bypass_ioctl
,
177 DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM
, vmw_overlay_ioctl
,
179 DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM
, vmw_stream_claim_ioctl
,
181 DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM
, vmw_stream_unref_ioctl
,
184 DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT
, vmw_context_define_ioctl
,
186 DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT
, vmw_context_destroy_ioctl
,
188 DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE
, vmw_surface_define_ioctl
,
190 DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE
, vmw_surface_destroy_ioctl
,
192 DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE
, vmw_surface_reference_ioctl
,
194 DRM_IOCTL_DEF_DRV(VMW_EXECBUF
, vmw_execbuf_ioctl
,
196 DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT
, vmw_fence_obj_wait_ioctl
,
198 DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED
,
199 vmw_fence_obj_signaled_ioctl
,
201 DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF
, vmw_fence_obj_unref_ioctl
,
203 DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT
, vmw_fence_event_ioctl
,
205 DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP
, vmw_get_cap_3d_ioctl
,
208 /* these allow direct access to the framebuffers mark as master only */
209 DRM_IOCTL_DEF_DRV(VMW_PRESENT
, vmw_present_ioctl
,
210 DRM_MASTER
| DRM_AUTH
),
211 DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK
,
212 vmw_present_readback_ioctl
,
213 DRM_MASTER
| DRM_AUTH
),
215 * The permissions of the below ioctl are overridden in
216 * vmw_generic_ioctl(). We require either
217 * DRM_MASTER or capable(CAP_SYS_ADMIN).
219 DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT
,
220 vmw_kms_update_layout_ioctl
,
222 DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER
,
223 vmw_shader_define_ioctl
,
225 DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER
,
226 vmw_shader_destroy_ioctl
,
228 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE
,
229 vmw_gb_surface_define_ioctl
,
231 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF
,
232 vmw_gb_surface_reference_ioctl
,
234 DRM_IOCTL_DEF_DRV(VMW_SYNCCPU
,
235 vmw_user_bo_synccpu_ioctl
,
237 DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT
,
238 vmw_extended_context_define_ioctl
,
240 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT
,
241 vmw_gb_surface_define_ext_ioctl
,
243 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT
,
244 vmw_gb_surface_reference_ext_ioctl
,
246 DRM_IOCTL_DEF_DRV(VMW_MSG
,
249 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET
,
250 vmw_mksstat_reset_ioctl
,
252 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD
,
253 vmw_mksstat_add_ioctl
,
255 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE
,
256 vmw_mksstat_remove_ioctl
,
260 static const struct pci_device_id vmw_pci_id_list
[] = {
261 { PCI_DEVICE(0x15ad, VMWGFX_PCI_ID_SVGA2
) },
262 { PCI_DEVICE(0x15ad, VMWGFX_PCI_ID_SVGA3
) },
265 MODULE_DEVICE_TABLE(pci
, vmw_pci_id_list
);
267 static int enable_fbdev
= IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON
);
268 static int vmw_restrict_iommu
;
269 static int vmw_force_coherent
;
270 static int vmw_restrict_dma_mask
;
271 static int vmw_assume_16bpp
;
273 static int vmw_probe(struct pci_dev
*, const struct pci_device_id
*);
274 static int vmwgfx_pm_notifier(struct notifier_block
*nb
, unsigned long val
,
277 MODULE_PARM_DESC(enable_fbdev
, "Enable vmwgfx fbdev");
278 module_param_named(enable_fbdev
, enable_fbdev
, int, 0600);
279 MODULE_PARM_DESC(restrict_iommu
, "Try to limit IOMMU usage for TTM pages");
280 module_param_named(restrict_iommu
, vmw_restrict_iommu
, int, 0600);
281 MODULE_PARM_DESC(force_coherent
, "Force coherent TTM pages");
282 module_param_named(force_coherent
, vmw_force_coherent
, int, 0600);
283 MODULE_PARM_DESC(restrict_dma_mask
, "Restrict DMA mask to 44 bits with IOMMU");
284 module_param_named(restrict_dma_mask
, vmw_restrict_dma_mask
, int, 0600);
285 MODULE_PARM_DESC(assume_16bpp
, "Assume 16-bpp when filtering modes");
286 module_param_named(assume_16bpp
, vmw_assume_16bpp
, int, 0600);
294 static const struct bitmap_name cap1_names
[] = {
295 { SVGA_CAP_RECT_COPY
, "rect copy" },
296 { SVGA_CAP_CURSOR
, "cursor" },
297 { SVGA_CAP_CURSOR_BYPASS
, "cursor bypass" },
298 { SVGA_CAP_CURSOR_BYPASS_2
, "cursor bypass 2" },
299 { SVGA_CAP_8BIT_EMULATION
, "8bit emulation" },
300 { SVGA_CAP_ALPHA_CURSOR
, "alpha cursor" },
301 { SVGA_CAP_3D
, "3D" },
302 { SVGA_CAP_EXTENDED_FIFO
, "extended fifo" },
303 { SVGA_CAP_MULTIMON
, "multimon" },
304 { SVGA_CAP_PITCHLOCK
, "pitchlock" },
305 { SVGA_CAP_IRQMASK
, "irq mask" },
306 { SVGA_CAP_DISPLAY_TOPOLOGY
, "display topology" },
307 { SVGA_CAP_GMR
, "gmr" },
308 { SVGA_CAP_TRACES
, "traces" },
309 { SVGA_CAP_GMR2
, "gmr2" },
310 { SVGA_CAP_SCREEN_OBJECT_2
, "screen object 2" },
311 { SVGA_CAP_COMMAND_BUFFERS
, "command buffers" },
312 { SVGA_CAP_CMD_BUFFERS_2
, "command buffers 2" },
313 { SVGA_CAP_GBOBJECTS
, "gbobject" },
314 { SVGA_CAP_DX
, "dx" },
315 { SVGA_CAP_HP_CMD_QUEUE
, "hp cmd queue" },
316 { SVGA_CAP_NO_BB_RESTRICTION
, "no bb restriction" },
317 { SVGA_CAP_CAP2_REGISTER
, "cap2 register" },
321 static const struct bitmap_name cap2_names
[] = {
322 { SVGA_CAP2_GROW_OTABLE
, "grow otable" },
323 { SVGA_CAP2_INTRA_SURFACE_COPY
, "intra surface copy" },
324 { SVGA_CAP2_DX2
, "dx2" },
325 { SVGA_CAP2_GB_MEMSIZE_2
, "gb memsize 2" },
326 { SVGA_CAP2_SCREENDMA_REG
, "screendma reg" },
327 { SVGA_CAP2_OTABLE_PTDEPTH_2
, "otable ptdepth2" },
328 { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT
, "non ms to ms stretchblt" },
329 { SVGA_CAP2_CURSOR_MOB
, "cursor mob" },
330 { SVGA_CAP2_MSHINT
, "mshint" },
331 { SVGA_CAP2_CB_MAX_SIZE_4MB
, "cb max size 4mb" },
332 { SVGA_CAP2_DX3
, "dx3" },
333 { SVGA_CAP2_FRAME_TYPE
, "frame type" },
334 { SVGA_CAP2_COTABLE_COPY
, "cotable copy" },
335 { SVGA_CAP2_TRACE_FULL_FB
, "trace full fb" },
336 { SVGA_CAP2_EXTRA_REGS
, "extra regs" },
337 { SVGA_CAP2_LO_STAGING
, "lo staging" },
340 static void vmw_print_bitmap(struct drm_device
*drm
,
341 const char *prefix
, uint32_t bitmap
,
342 const struct bitmap_name
*bnames
,
348 for (i
= 0; i
< num_names
; ++i
) {
349 if ((bitmap
& bnames
[i
].value
) != 0) {
350 offset
+= snprintf(buf
+ offset
,
351 ARRAY_SIZE(buf
) - offset
,
352 "%s, ", bnames
[i
].name
);
353 bitmap
&= ~bnames
[i
].value
;
357 drm_info(drm
, "%s: %s\n", prefix
, buf
);
359 drm_dbg(drm
, "%s: unknown enums: %x\n", prefix
, bitmap
);
363 static void vmw_print_sm_type(struct vmw_private
*dev_priv
)
365 static const char *names
[] = {
366 [VMW_SM_LEGACY
] = "Legacy",
368 [VMW_SM_4_1
] = "SM4_1",
370 [VMW_SM_MAX
] = "Invalid"
372 BUILD_BUG_ON(ARRAY_SIZE(names
) != (VMW_SM_MAX
+ 1));
373 drm_info(&dev_priv
->drm
, "Available shader model: %s.\n",
374 names
[dev_priv
->sm_type
]);
378 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
380 * @dev_priv: A device private structure.
382 * This function creates a small buffer object that holds the query
383 * result for dummy queries emitted as query barriers.
384 * The function will then map the first page and initialize a pending
385 * occlusion query result structure, Finally it will unmap the buffer.
386 * No interruptible waits are done within this function.
388 * Returns an error if bo creation or initialization fails.
390 static int vmw_dummy_query_bo_create(struct vmw_private
*dev_priv
)
393 struct vmw_buffer_object
*vbo
;
394 struct ttm_bo_kmap_obj map
;
395 volatile SVGA3dQueryResult
*result
;
399 * Create the vbo as pinned, so that a tryreserve will
400 * immediately succeed. This is because we're the only
401 * user of the bo currently.
403 vbo
= kzalloc(sizeof(*vbo
), GFP_KERNEL
);
407 ret
= vmw_bo_init(dev_priv
, vbo
, PAGE_SIZE
,
408 &vmw_sys_placement
, false, true,
410 if (unlikely(ret
!= 0))
413 ret
= ttm_bo_reserve(&vbo
->base
, false, true, NULL
);
415 vmw_bo_pin_reserved(vbo
, true);
417 ret
= ttm_bo_kmap(&vbo
->base
, 0, 1, &map
);
418 if (likely(ret
== 0)) {
419 result
= ttm_kmap_obj_virtual(&map
, &dummy
);
420 result
->totalSize
= sizeof(*result
);
421 result
->state
= SVGA3D_QUERYSTATE_PENDING
;
422 result
->result32
= 0xff;
425 vmw_bo_pin_reserved(vbo
, false);
426 ttm_bo_unreserve(&vbo
->base
);
428 if (unlikely(ret
!= 0)) {
429 DRM_ERROR("Dummy query buffer map failed.\n");
430 vmw_bo_unreference(&vbo
);
432 dev_priv
->dummy_query_bo
= vbo
;
437 static int vmw_device_init(struct vmw_private
*dev_priv
)
439 bool uses_fb_traces
= false;
441 dev_priv
->enable_state
= vmw_read(dev_priv
, SVGA_REG_ENABLE
);
442 dev_priv
->config_done_state
= vmw_read(dev_priv
, SVGA_REG_CONFIG_DONE
);
443 dev_priv
->traces_state
= vmw_read(dev_priv
, SVGA_REG_TRACES
);
445 vmw_write(dev_priv
, SVGA_REG_ENABLE
, SVGA_REG_ENABLE_ENABLE
|
446 SVGA_REG_ENABLE_HIDE
);
448 uses_fb_traces
= !vmw_cmd_supported(dev_priv
) &&
449 (dev_priv
->capabilities
& SVGA_CAP_TRACES
) != 0;
451 vmw_write(dev_priv
, SVGA_REG_TRACES
, uses_fb_traces
);
452 dev_priv
->fifo
= vmw_fifo_create(dev_priv
);
453 if (IS_ERR(dev_priv
->fifo
)) {
454 int err
= PTR_ERR(dev_priv
->fifo
);
455 dev_priv
->fifo
= NULL
;
457 } else if (!dev_priv
->fifo
) {
458 vmw_write(dev_priv
, SVGA_REG_CONFIG_DONE
, 1);
461 dev_priv
->last_read_seqno
= vmw_fence_read(dev_priv
);
462 atomic_set(&dev_priv
->marker_seq
, dev_priv
->last_read_seqno
);
466 static void vmw_device_fini(struct vmw_private
*vmw
)
471 vmw_write(vmw
, SVGA_REG_SYNC
, SVGA_SYNC_GENERIC
);
472 while (vmw_read(vmw
, SVGA_REG_BUSY
) != 0)
475 vmw
->last_read_seqno
= vmw_fence_read(vmw
);
477 vmw_write(vmw
, SVGA_REG_CONFIG_DONE
,
478 vmw
->config_done_state
);
479 vmw_write(vmw
, SVGA_REG_ENABLE
,
481 vmw_write(vmw
, SVGA_REG_TRACES
,
484 vmw_fifo_destroy(vmw
);
488 * vmw_request_device_late - Perform late device setup
490 * @dev_priv: Pointer to device private.
492 * This function performs setup of otables and enables large command
493 * buffer submission. These tasks are split out to a separate function
494 * because it reverts vmw_release_device_early and is intended to be used
495 * by an error path in the hibernation code.
497 static int vmw_request_device_late(struct vmw_private
*dev_priv
)
501 if (dev_priv
->has_mob
) {
502 ret
= vmw_otables_setup(dev_priv
);
503 if (unlikely(ret
!= 0)) {
504 DRM_ERROR("Unable to initialize "
505 "guest Memory OBjects.\n");
510 if (dev_priv
->cman
) {
511 ret
= vmw_cmdbuf_set_pool_size(dev_priv
->cman
, 256*4096);
513 struct vmw_cmdbuf_man
*man
= dev_priv
->cman
;
515 dev_priv
->cman
= NULL
;
516 vmw_cmdbuf_man_destroy(man
);
523 static int vmw_request_device(struct vmw_private
*dev_priv
)
527 ret
= vmw_device_init(dev_priv
);
528 if (unlikely(ret
!= 0)) {
529 DRM_ERROR("Unable to initialize the device.\n");
532 vmw_fence_fifo_up(dev_priv
->fman
);
533 dev_priv
->cman
= vmw_cmdbuf_man_create(dev_priv
);
534 if (IS_ERR(dev_priv
->cman
)) {
535 dev_priv
->cman
= NULL
;
536 dev_priv
->sm_type
= VMW_SM_LEGACY
;
539 ret
= vmw_request_device_late(dev_priv
);
543 ret
= vmw_dummy_query_bo_create(dev_priv
);
544 if (unlikely(ret
!= 0))
545 goto out_no_query_bo
;
551 vmw_cmdbuf_remove_pool(dev_priv
->cman
);
552 if (dev_priv
->has_mob
) {
553 struct ttm_resource_manager
*man
;
555 man
= ttm_manager_type(&dev_priv
->bdev
, VMW_PL_MOB
);
556 ttm_resource_manager_evict_all(&dev_priv
->bdev
, man
);
557 vmw_otables_takedown(dev_priv
);
560 vmw_cmdbuf_man_destroy(dev_priv
->cman
);
562 vmw_fence_fifo_down(dev_priv
->fman
);
563 vmw_device_fini(dev_priv
);
568 * vmw_release_device_early - Early part of fifo takedown.
570 * @dev_priv: Pointer to device private struct.
572 * This is the first part of command submission takedown, to be called before
573 * buffer management is taken down.
575 static void vmw_release_device_early(struct vmw_private
*dev_priv
)
578 * Previous destructions should've released
582 BUG_ON(dev_priv
->pinned_bo
!= NULL
);
584 vmw_bo_unreference(&dev_priv
->dummy_query_bo
);
586 vmw_cmdbuf_remove_pool(dev_priv
->cman
);
588 if (dev_priv
->has_mob
) {
589 struct ttm_resource_manager
*man
;
591 man
= ttm_manager_type(&dev_priv
->bdev
, VMW_PL_MOB
);
592 ttm_resource_manager_evict_all(&dev_priv
->bdev
, man
);
593 vmw_otables_takedown(dev_priv
);
598 * vmw_release_device_late - Late part of fifo takedown.
600 * @dev_priv: Pointer to device private struct.
602 * This is the last part of the command submission takedown, to be called when
603 * command submission is no longer needed. It may wait on pending fences.
605 static void vmw_release_device_late(struct vmw_private
*dev_priv
)
607 vmw_fence_fifo_down(dev_priv
->fman
);
609 vmw_cmdbuf_man_destroy(dev_priv
->cman
);
611 vmw_device_fini(dev_priv
);
615 * Sets the initial_[width|height] fields on the given vmw_private.
617 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
618 * clamping the value to fb_max_[width|height] fields and the
619 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
620 * If the values appear to be invalid, set them to
621 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
623 static void vmw_get_initial_size(struct vmw_private
*dev_priv
)
628 width
= vmw_read(dev_priv
, SVGA_REG_WIDTH
);
629 height
= vmw_read(dev_priv
, SVGA_REG_HEIGHT
);
631 width
= max_t(uint32_t, width
, VMW_MIN_INITIAL_WIDTH
);
632 height
= max_t(uint32_t, height
, VMW_MIN_INITIAL_HEIGHT
);
634 if (width
> dev_priv
->fb_max_width
||
635 height
> dev_priv
->fb_max_height
) {
638 * This is a host error and shouldn't occur.
641 width
= VMW_MIN_INITIAL_WIDTH
;
642 height
= VMW_MIN_INITIAL_HEIGHT
;
645 dev_priv
->initial_width
= width
;
646 dev_priv
->initial_height
= height
;
650 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
653 * @dev_priv: Pointer to a struct vmw_private
655 * This functions tries to determine what actions need to be taken by the
656 * driver to make system pages visible to the device.
657 * If this function decides that DMA is not possible, it returns -EINVAL.
658 * The driver may then try to disable features of the device that require
661 static int vmw_dma_select_mode(struct vmw_private
*dev_priv
)
663 static const char *names
[vmw_dma_map_max
] = {
664 [vmw_dma_alloc_coherent
] = "Using coherent TTM pages.",
665 [vmw_dma_map_populate
] = "Caching DMA mappings.",
666 [vmw_dma_map_bind
] = "Giving up DMA mappings early."};
668 /* TTM currently doesn't fully support SEV encryption. */
669 if (mem_encrypt_active())
672 if (vmw_force_coherent
)
673 dev_priv
->map_mode
= vmw_dma_alloc_coherent
;
674 else if (vmw_restrict_iommu
)
675 dev_priv
->map_mode
= vmw_dma_map_bind
;
677 dev_priv
->map_mode
= vmw_dma_map_populate
;
679 drm_info(&dev_priv
->drm
,
680 "DMA map mode: %s\n", names
[dev_priv
->map_mode
]);
685 * vmw_dma_masks - set required page- and dma masks
687 * @dev_priv: Pointer to struct drm-device
689 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
690 * restriction also for 64-bit systems.
692 static int vmw_dma_masks(struct vmw_private
*dev_priv
)
694 struct drm_device
*dev
= &dev_priv
->drm
;
697 ret
= dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64));
698 if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask
) {
699 drm_info(&dev_priv
->drm
,
700 "Restricting DMA addresses to 44 bits.\n");
701 return dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(44));
707 static int vmw_vram_manager_init(struct vmw_private
*dev_priv
)
710 ret
= ttm_range_man_init(&dev_priv
->bdev
, TTM_PL_VRAM
, false,
711 dev_priv
->vram_size
>> PAGE_SHIFT
);
712 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv
->bdev
, TTM_PL_VRAM
), false);
716 static void vmw_vram_manager_fini(struct vmw_private
*dev_priv
)
718 ttm_range_man_fini(&dev_priv
->bdev
, TTM_PL_VRAM
);
721 static int vmw_setup_pci_resources(struct vmw_private
*dev
,
724 resource_size_t rmmio_start
;
725 resource_size_t rmmio_size
;
726 resource_size_t fifo_start
;
727 resource_size_t fifo_size
;
729 struct pci_dev
*pdev
= to_pci_dev(dev
->drm
.dev
);
731 pci_set_master(pdev
);
733 ret
= pci_request_regions(pdev
, "vmwgfx probe");
737 dev
->pci_id
= pci_id
;
738 if (pci_id
== VMWGFX_PCI_ID_SVGA3
) {
739 rmmio_start
= pci_resource_start(pdev
, 0);
740 rmmio_size
= pci_resource_len(pdev
, 0);
741 dev
->vram_start
= pci_resource_start(pdev
, 2);
742 dev
->vram_size
= pci_resource_len(pdev
, 2);
745 "Register MMIO at 0x%pa size is %llu kiB\n",
746 &rmmio_start
, (uint64_t)rmmio_size
/ 1024);
747 dev
->rmmio
= devm_ioremap(dev
->drm
.dev
,
752 "Failed mapping registers mmio memory.\n");
753 pci_release_regions(pdev
);
756 } else if (pci_id
== VMWGFX_PCI_ID_SVGA2
) {
757 dev
->io_start
= pci_resource_start(pdev
, 0);
758 dev
->vram_start
= pci_resource_start(pdev
, 1);
759 dev
->vram_size
= pci_resource_len(pdev
, 1);
760 fifo_start
= pci_resource_start(pdev
, 2);
761 fifo_size
= pci_resource_len(pdev
, 2);
764 "FIFO at %pa size is %llu kiB\n",
765 &fifo_start
, (uint64_t)fifo_size
/ 1024);
766 dev
->fifo_mem
= devm_memremap(dev
->drm
.dev
,
771 if (IS_ERR(dev
->fifo_mem
)) {
773 "Failed mapping FIFO memory.\n");
774 pci_release_regions(pdev
);
775 return PTR_ERR(dev
->fifo_mem
);
778 pci_release_regions(pdev
);
783 * This is approximate size of the vram, the exact size will only
784 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource
785 * size will be equal to or bigger than the size reported by
786 * SVGA_REG_VRAM_SIZE.
789 "VRAM at %pa size is %llu kiB\n",
790 &dev
->vram_start
, (uint64_t)dev
->vram_size
/ 1024);
795 static int vmw_detect_version(struct vmw_private
*dev
)
799 vmw_write(dev
, SVGA_REG_ID
, vmw_is_svga_v3(dev
) ?
800 SVGA_ID_3
: SVGA_ID_2
);
801 svga_id
= vmw_read(dev
, SVGA_REG_ID
);
802 if (svga_id
!= SVGA_ID_2
&& svga_id
!= SVGA_ID_3
) {
804 "Unsupported SVGA ID 0x%x on chipset 0x%x\n",
805 svga_id
, dev
->pci_id
);
808 BUG_ON(vmw_is_svga_v3(dev
) && (svga_id
!= SVGA_ID_3
));
810 "Running on SVGA version %d.\n", (svga_id
& 0xff));
814 static int vmw_driver_load(struct vmw_private
*dev_priv
, u32 pci_id
)
818 bool refuse_dma
= false;
819 struct pci_dev
*pdev
= to_pci_dev(dev_priv
->drm
.dev
);
821 dev_priv
->drm
.dev_private
= dev_priv
;
823 mutex_init(&dev_priv
->cmdbuf_mutex
);
824 mutex_init(&dev_priv
->binding_mutex
);
825 spin_lock_init(&dev_priv
->resource_lock
);
826 spin_lock_init(&dev_priv
->hw_lock
);
827 spin_lock_init(&dev_priv
->waiter_lock
);
828 spin_lock_init(&dev_priv
->cursor_lock
);
830 ret
= vmw_setup_pci_resources(dev_priv
, pci_id
);
833 ret
= vmw_detect_version(dev_priv
);
835 goto out_no_pci_or_version
;
838 for (i
= vmw_res_context
; i
< vmw_res_max
; ++i
) {
839 idr_init_base(&dev_priv
->res_idr
[i
], 1);
840 INIT_LIST_HEAD(&dev_priv
->res_lru
[i
]);
843 init_waitqueue_head(&dev_priv
->fence_queue
);
844 init_waitqueue_head(&dev_priv
->fifo_queue
);
845 dev_priv
->fence_queue_waiters
= 0;
846 dev_priv
->fifo_queue_waiters
= 0;
848 dev_priv
->used_memory_size
= 0;
850 dev_priv
->assume_16bpp
= !!vmw_assume_16bpp
;
852 dev_priv
->enable_fb
= enable_fbdev
;
855 dev_priv
->capabilities
= vmw_read(dev_priv
, SVGA_REG_CAPABILITIES
);
857 if (dev_priv
->capabilities
& SVGA_CAP_CAP2_REGISTER
) {
858 dev_priv
->capabilities2
= vmw_read(dev_priv
, SVGA_REG_CAP2
);
862 ret
= vmw_dma_select_mode(dev_priv
);
863 if (unlikely(ret
!= 0)) {
864 drm_info(&dev_priv
->drm
,
865 "Restricting capabilities since DMA not available.\n");
867 if (dev_priv
->capabilities
& SVGA_CAP_GBOBJECTS
)
868 drm_info(&dev_priv
->drm
,
869 "Disabling 3D acceleration.\n");
872 dev_priv
->vram_size
= vmw_read(dev_priv
, SVGA_REG_VRAM_SIZE
);
873 dev_priv
->fifo_mem_size
= vmw_read(dev_priv
, SVGA_REG_MEM_SIZE
);
874 dev_priv
->fb_max_width
= vmw_read(dev_priv
, SVGA_REG_MAX_WIDTH
);
875 dev_priv
->fb_max_height
= vmw_read(dev_priv
, SVGA_REG_MAX_HEIGHT
);
877 vmw_get_initial_size(dev_priv
);
879 if (dev_priv
->capabilities
& SVGA_CAP_GMR2
) {
880 dev_priv
->max_gmr_ids
=
881 vmw_read(dev_priv
, SVGA_REG_GMR_MAX_IDS
);
882 dev_priv
->max_gmr_pages
=
883 vmw_read(dev_priv
, SVGA_REG_GMRS_MAX_PAGES
);
884 dev_priv
->memory_size
=
885 vmw_read(dev_priv
, SVGA_REG_MEMORY_SIZE
);
886 dev_priv
->memory_size
-= dev_priv
->vram_size
;
889 * An arbitrary limit of 512MiB on surface
890 * memory. But all HWV8 hardware supports GMR2.
892 dev_priv
->memory_size
= 512*1024*1024;
894 dev_priv
->max_mob_pages
= 0;
895 dev_priv
->max_mob_size
= 0;
896 if (dev_priv
->capabilities
& SVGA_CAP_GBOBJECTS
) {
899 if (dev_priv
->capabilities2
& SVGA_CAP2_GB_MEMSIZE_2
)
900 mem_size
= vmw_read(dev_priv
,
901 SVGA_REG_GBOBJECT_MEM_SIZE_KB
);
905 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB
);
908 * Workaround for low memory 2D VMs to compensate for the
909 * allocation taken by fbdev
911 if (!(dev_priv
->capabilities
& SVGA_CAP_3D
))
914 dev_priv
->max_mob_pages
= mem_size
* 1024 / PAGE_SIZE
;
915 dev_priv
->max_primary_mem
=
916 vmw_read(dev_priv
, SVGA_REG_MAX_PRIMARY_MEM
);
917 dev_priv
->max_mob_size
=
918 vmw_read(dev_priv
, SVGA_REG_MOB_MAX_SIZE
);
919 dev_priv
->stdu_max_width
=
920 vmw_read(dev_priv
, SVGA_REG_SCREENTARGET_MAX_WIDTH
);
921 dev_priv
->stdu_max_height
=
922 vmw_read(dev_priv
, SVGA_REG_SCREENTARGET_MAX_HEIGHT
);
924 vmw_write(dev_priv
, SVGA_REG_DEV_CAP
,
925 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH
);
926 dev_priv
->texture_max_width
= vmw_read(dev_priv
,
928 vmw_write(dev_priv
, SVGA_REG_DEV_CAP
,
929 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT
);
930 dev_priv
->texture_max_height
= vmw_read(dev_priv
,
933 dev_priv
->texture_max_width
= 8192;
934 dev_priv
->texture_max_height
= 8192;
935 dev_priv
->max_primary_mem
= dev_priv
->vram_size
;
937 drm_info(&dev_priv
->drm
,
938 "Legacy memory limits: VRAM = %llu kB, FIFO = %llu kB, surface = %u kB\n",
939 (u64
)dev_priv
->vram_size
/ 1024,
940 (u64
)dev_priv
->fifo_mem_size
/ 1024,
941 dev_priv
->memory_size
/ 1024);
943 drm_info(&dev_priv
->drm
,
944 "MOB limits: max mob size = %u kB, max mob pages = %u\n",
945 dev_priv
->max_mob_size
/ 1024, dev_priv
->max_mob_pages
);
947 vmw_print_bitmap(&dev_priv
->drm
, "Capabilities",
948 dev_priv
->capabilities
,
949 cap1_names
, ARRAY_SIZE(cap1_names
));
950 if (dev_priv
->capabilities
& SVGA_CAP_CAP2_REGISTER
)
951 vmw_print_bitmap(&dev_priv
->drm
, "Capabilities2",
952 dev_priv
->capabilities2
,
953 cap2_names
, ARRAY_SIZE(cap2_names
));
955 ret
= vmw_dma_masks(dev_priv
);
956 if (unlikely(ret
!= 0))
959 dma_set_max_seg_size(dev_priv
->drm
.dev
, U32_MAX
);
961 if (dev_priv
->capabilities
& SVGA_CAP_GMR2
) {
962 drm_info(&dev_priv
->drm
,
963 "Max GMR ids is %u\n",
964 (unsigned)dev_priv
->max_gmr_ids
);
965 drm_info(&dev_priv
->drm
,
966 "Max number of GMR pages is %u\n",
967 (unsigned)dev_priv
->max_gmr_pages
);
969 drm_info(&dev_priv
->drm
,
970 "Maximum display memory size is %llu kiB\n",
971 (uint64_t)dev_priv
->max_primary_mem
/ 1024);
973 /* Need mmio memory to check for fifo pitchlock cap. */
974 if (!(dev_priv
->capabilities
& SVGA_CAP_DISPLAY_TOPOLOGY
) &&
975 !(dev_priv
->capabilities
& SVGA_CAP_PITCHLOCK
) &&
976 !vmw_fifo_have_pitchlock(dev_priv
)) {
978 DRM_ERROR("Hardware has no pitchlock\n");
982 dev_priv
->tdev
= ttm_object_device_init(&ttm_mem_glob
, 12,
983 &vmw_prime_dmabuf_ops
);
985 if (unlikely(dev_priv
->tdev
== NULL
)) {
986 drm_err(&dev_priv
->drm
,
987 "Unable to initialize TTM object management.\n");
992 if (dev_priv
->capabilities
& SVGA_CAP_IRQMASK
) {
993 ret
= vmw_irq_install(&dev_priv
->drm
, pdev
->irq
);
995 drm_err(&dev_priv
->drm
,
996 "Failed installing irq: %d\n", ret
);
1001 dev_priv
->fman
= vmw_fence_manager_init(dev_priv
);
1002 if (unlikely(dev_priv
->fman
== NULL
)) {
1007 drm_vma_offset_manager_init(&dev_priv
->vma_manager
,
1008 DRM_FILE_PAGE_OFFSET_START
,
1009 DRM_FILE_PAGE_OFFSET_SIZE
);
1010 ret
= ttm_device_init(&dev_priv
->bdev
, &vmw_bo_driver
,
1012 dev_priv
->drm
.anon_inode
->i_mapping
,
1013 &dev_priv
->vma_manager
,
1014 dev_priv
->map_mode
== vmw_dma_alloc_coherent
,
1016 if (unlikely(ret
!= 0)) {
1017 drm_err(&dev_priv
->drm
,
1018 "Failed initializing TTM buffer object driver.\n");
1023 * Enable VRAM, but initially don't use it until SVGA is enabled and
1027 ret
= vmw_vram_manager_init(dev_priv
);
1028 if (unlikely(ret
!= 0)) {
1029 drm_err(&dev_priv
->drm
,
1030 "Failed initializing memory manager for VRAM.\n");
1034 ret
= vmw_devcaps_create(dev_priv
);
1035 if (unlikely(ret
!= 0)) {
1036 drm_err(&dev_priv
->drm
,
1037 "Failed initializing device caps.\n");
1042 * "Guest Memory Regions" is an aperture like feature with
1043 * one slot per bo. There is an upper limit of the number of
1044 * slots as well as the bo size.
1046 dev_priv
->has_gmr
= true;
1047 /* TODO: This is most likely not correct */
1048 if (((dev_priv
->capabilities
& (SVGA_CAP_GMR
| SVGA_CAP_GMR2
)) == 0) ||
1050 vmw_gmrid_man_init(dev_priv
, VMW_PL_GMR
) != 0) {
1051 drm_info(&dev_priv
->drm
,
1052 "No GMR memory available. "
1053 "Graphics memory resources are very limited.\n");
1054 dev_priv
->has_gmr
= false;
1057 if (dev_priv
->capabilities
& SVGA_CAP_GBOBJECTS
&& !refuse_dma
) {
1058 dev_priv
->has_mob
= true;
1060 if (vmw_gmrid_man_init(dev_priv
, VMW_PL_MOB
) != 0) {
1061 drm_info(&dev_priv
->drm
,
1062 "No MOB memory available. "
1063 "3D will be disabled.\n");
1064 dev_priv
->has_mob
= false;
1066 if (vmw_sys_man_init(dev_priv
) != 0) {
1067 drm_info(&dev_priv
->drm
,
1068 "No MOB page table memory available. "
1069 "3D will be disabled.\n");
1070 dev_priv
->has_mob
= false;
1074 if (dev_priv
->has_mob
&& (dev_priv
->capabilities
& SVGA_CAP_DX
)) {
1075 if (vmw_devcap_get(dev_priv
, SVGA3D_DEVCAP_DXCONTEXT
))
1076 dev_priv
->sm_type
= VMW_SM_4
;
1079 vmw_validation_mem_init_ttm(dev_priv
, VMWGFX_VALIDATION_MEM_GRAN
);
1081 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */
1082 if (has_sm4_context(dev_priv
) &&
1083 (dev_priv
->capabilities2
& SVGA_CAP2_DX2
)) {
1084 if (vmw_devcap_get(dev_priv
, SVGA3D_DEVCAP_SM41
))
1085 dev_priv
->sm_type
= VMW_SM_4_1
;
1086 if (has_sm4_1_context(dev_priv
) &&
1087 (dev_priv
->capabilities2
& SVGA_CAP2_DX3
)) {
1088 if (vmw_devcap_get(dev_priv
, SVGA3D_DEVCAP_SM5
))
1089 dev_priv
->sm_type
= VMW_SM_5
;
1093 ret
= vmw_kms_init(dev_priv
);
1094 if (unlikely(ret
!= 0))
1096 vmw_overlay_init(dev_priv
);
1098 ret
= vmw_request_device(dev_priv
);
1102 vmw_print_sm_type(dev_priv
);
1103 vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)",
1104 VMWGFX_DRIVER_MAJOR
, VMWGFX_DRIVER_MINOR
,
1105 VMWGFX_DRIVER_PATCHLEVEL
, UTS_RELEASE
);
1107 if (dev_priv
->enable_fb
) {
1108 vmw_fifo_resource_inc(dev_priv
);
1109 vmw_svga_enable(dev_priv
);
1110 vmw_fb_init(dev_priv
);
1113 dev_priv
->pm_nb
.notifier_call
= vmwgfx_pm_notifier
;
1114 register_pm_notifier(&dev_priv
->pm_nb
);
1119 vmw_overlay_close(dev_priv
);
1120 vmw_kms_close(dev_priv
);
1122 if (dev_priv
->has_mob
) {
1123 vmw_gmrid_man_fini(dev_priv
, VMW_PL_MOB
);
1124 vmw_sys_man_fini(dev_priv
);
1126 if (dev_priv
->has_gmr
)
1127 vmw_gmrid_man_fini(dev_priv
, VMW_PL_GMR
);
1128 vmw_devcaps_destroy(dev_priv
);
1129 vmw_vram_manager_fini(dev_priv
);
1131 ttm_device_fini(&dev_priv
->bdev
);
1133 vmw_fence_manager_takedown(dev_priv
->fman
);
1135 if (dev_priv
->capabilities
& SVGA_CAP_IRQMASK
)
1136 vmw_irq_uninstall(&dev_priv
->drm
);
1138 ttm_object_device_release(&dev_priv
->tdev
);
1140 for (i
= vmw_res_context
; i
< vmw_res_max
; ++i
)
1141 idr_destroy(&dev_priv
->res_idr
[i
]);
1143 if (dev_priv
->ctx
.staged_bindings
)
1144 vmw_binding_state_free(dev_priv
->ctx
.staged_bindings
);
1145 out_no_pci_or_version
:
1146 pci_release_regions(pdev
);
1150 static void vmw_driver_unload(struct drm_device
*dev
)
1152 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1153 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1154 enum vmw_res_type i
;
1156 unregister_pm_notifier(&dev_priv
->pm_nb
);
1158 if (dev_priv
->ctx
.res_ht_initialized
)
1159 drm_ht_remove(&dev_priv
->ctx
.res_ht
);
1160 vfree(dev_priv
->ctx
.cmd_bounce
);
1161 if (dev_priv
->enable_fb
) {
1162 vmw_fb_off(dev_priv
);
1163 vmw_fb_close(dev_priv
);
1164 vmw_fifo_resource_dec(dev_priv
);
1165 vmw_svga_disable(dev_priv
);
1168 vmw_kms_close(dev_priv
);
1169 vmw_overlay_close(dev_priv
);
1171 if (dev_priv
->has_gmr
)
1172 vmw_gmrid_man_fini(dev_priv
, VMW_PL_GMR
);
1174 vmw_release_device_early(dev_priv
);
1175 if (dev_priv
->has_mob
) {
1176 vmw_gmrid_man_fini(dev_priv
, VMW_PL_MOB
);
1177 vmw_sys_man_fini(dev_priv
);
1179 vmw_devcaps_destroy(dev_priv
);
1180 vmw_vram_manager_fini(dev_priv
);
1181 ttm_device_fini(&dev_priv
->bdev
);
1182 drm_vma_offset_manager_destroy(&dev_priv
->vma_manager
);
1183 vmw_release_device_late(dev_priv
);
1184 vmw_fence_manager_takedown(dev_priv
->fman
);
1185 if (dev_priv
->capabilities
& SVGA_CAP_IRQMASK
)
1186 vmw_irq_uninstall(&dev_priv
->drm
);
1188 ttm_object_device_release(&dev_priv
->tdev
);
1189 if (dev_priv
->ctx
.staged_bindings
)
1190 vmw_binding_state_free(dev_priv
->ctx
.staged_bindings
);
1192 for (i
= vmw_res_context
; i
< vmw_res_max
; ++i
)
1193 idr_destroy(&dev_priv
->res_idr
[i
]);
1195 vmw_mksstat_remove_all(dev_priv
);
1197 pci_release_regions(pdev
);
1200 static void vmw_postclose(struct drm_device
*dev
,
1201 struct drm_file
*file_priv
)
1203 struct vmw_fpriv
*vmw_fp
= vmw_fpriv(file_priv
);
1205 ttm_object_file_release(&vmw_fp
->tfile
);
1209 static int vmw_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
)
1211 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1212 struct vmw_fpriv
*vmw_fp
;
1215 vmw_fp
= kzalloc(sizeof(*vmw_fp
), GFP_KERNEL
);
1216 if (unlikely(!vmw_fp
))
1219 vmw_fp
->tfile
= ttm_object_file_init(dev_priv
->tdev
, 10);
1220 if (unlikely(vmw_fp
->tfile
== NULL
))
1223 file_priv
->driver_priv
= vmw_fp
;
1232 static long vmw_generic_ioctl(struct file
*filp
, unsigned int cmd
,
1234 long (*ioctl_func
)(struct file
*, unsigned int,
1237 struct drm_file
*file_priv
= filp
->private_data
;
1238 struct drm_device
*dev
= file_priv
->minor
->dev
;
1239 unsigned int nr
= DRM_IOCTL_NR(cmd
);
1243 * Do extra checking on driver private ioctls.
1246 if ((nr
>= DRM_COMMAND_BASE
) && (nr
< DRM_COMMAND_END
)
1247 && (nr
< DRM_COMMAND_BASE
+ dev
->driver
->num_ioctls
)) {
1248 const struct drm_ioctl_desc
*ioctl
=
1249 &vmw_ioctls
[nr
- DRM_COMMAND_BASE
];
1251 if (nr
== DRM_COMMAND_BASE
+ DRM_VMW_EXECBUF
) {
1252 return ioctl_func(filp
, cmd
, arg
);
1253 } else if (nr
== DRM_COMMAND_BASE
+ DRM_VMW_UPDATE_LAYOUT
) {
1254 if (!drm_is_current_master(file_priv
) &&
1255 !capable(CAP_SYS_ADMIN
))
1259 if (unlikely(ioctl
->cmd
!= cmd
))
1260 goto out_io_encoding
;
1262 flags
= ioctl
->flags
;
1263 } else if (!drm_ioctl_flags(nr
, &flags
))
1266 return ioctl_func(filp
, cmd
, arg
);
1269 DRM_ERROR("Invalid command format, ioctl %d\n",
1270 nr
- DRM_COMMAND_BASE
);
1275 static long vmw_unlocked_ioctl(struct file
*filp
, unsigned int cmd
,
1278 return vmw_generic_ioctl(filp
, cmd
, arg
, &drm_ioctl
);
1281 #ifdef CONFIG_COMPAT
1282 static long vmw_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1285 return vmw_generic_ioctl(filp
, cmd
, arg
, &drm_compat_ioctl
);
1289 static void vmw_master_set(struct drm_device
*dev
,
1290 struct drm_file
*file_priv
,
1294 * Inform a new master that the layout may have changed while
1298 drm_sysfs_hotplug_event(dev
);
1301 static void vmw_master_drop(struct drm_device
*dev
,
1302 struct drm_file
*file_priv
)
1304 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1306 vmw_kms_legacy_hotspot_clear(dev_priv
);
1307 if (!dev_priv
->enable_fb
)
1308 vmw_svga_disable(dev_priv
);
1312 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1314 * @dev_priv: Pointer to device private struct.
1315 * Needs the reservation sem to be held in non-exclusive mode.
1317 static void __vmw_svga_enable(struct vmw_private
*dev_priv
)
1319 struct ttm_resource_manager
*man
= ttm_manager_type(&dev_priv
->bdev
, TTM_PL_VRAM
);
1321 if (!ttm_resource_manager_used(man
)) {
1322 vmw_write(dev_priv
, SVGA_REG_ENABLE
, SVGA_REG_ENABLE_ENABLE
);
1323 ttm_resource_manager_set_used(man
, true);
1328 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1330 * @dev_priv: Pointer to device private struct.
1332 void vmw_svga_enable(struct vmw_private
*dev_priv
)
1334 __vmw_svga_enable(dev_priv
);
1338 * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1340 * @dev_priv: Pointer to device private struct.
1341 * Needs the reservation sem to be held in exclusive mode.
1342 * Will not empty VRAM. VRAM must be emptied by caller.
1344 static void __vmw_svga_disable(struct vmw_private
*dev_priv
)
1346 struct ttm_resource_manager
*man
= ttm_manager_type(&dev_priv
->bdev
, TTM_PL_VRAM
);
1348 if (ttm_resource_manager_used(man
)) {
1349 ttm_resource_manager_set_used(man
, false);
1350 vmw_write(dev_priv
, SVGA_REG_ENABLE
,
1351 SVGA_REG_ENABLE_HIDE
|
1352 SVGA_REG_ENABLE_ENABLE
);
1357 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1360 * @dev_priv: Pointer to device private struct.
1363 void vmw_svga_disable(struct vmw_private
*dev_priv
)
1365 struct ttm_resource_manager
*man
= ttm_manager_type(&dev_priv
->bdev
, TTM_PL_VRAM
);
1367 * Disabling SVGA will turn off device modesetting capabilities, so
1368 * notify KMS about that so that it doesn't cache atomic state that
1369 * isn't valid anymore, for example crtcs turned on.
1370 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex),
1371 * but vmw_kms_lost_device() takes the reservation sem and thus we'll
1372 * end up with lock order reversal. Thus, a master may actually perform
1373 * a new modeset just after we call vmw_kms_lost_device() and race with
1374 * vmw_svga_disable(), but that should at worst cause atomic KMS state
1375 * to be inconsistent with the device, causing modesetting problems.
1378 vmw_kms_lost_device(&dev_priv
->drm
);
1379 if (ttm_resource_manager_used(man
)) {
1380 if (ttm_resource_manager_evict_all(&dev_priv
->bdev
, man
))
1381 DRM_ERROR("Failed evicting VRAM buffers.\n");
1382 ttm_resource_manager_set_used(man
, false);
1383 vmw_write(dev_priv
, SVGA_REG_ENABLE
,
1384 SVGA_REG_ENABLE_HIDE
|
1385 SVGA_REG_ENABLE_ENABLE
);
1389 static void vmw_remove(struct pci_dev
*pdev
)
1391 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1393 ttm_mem_global_release(&ttm_mem_glob
);
1394 drm_dev_unregister(dev
);
1395 vmw_driver_unload(dev
);
1398 static unsigned long
1399 vmw_get_unmapped_area(struct file
*file
, unsigned long uaddr
,
1400 unsigned long len
, unsigned long pgoff
,
1401 unsigned long flags
)
1403 struct drm_file
*file_priv
= file
->private_data
;
1404 struct vmw_private
*dev_priv
= vmw_priv(file_priv
->minor
->dev
);
1406 return drm_get_unmapped_area(file
, uaddr
, len
, pgoff
, flags
,
1407 &dev_priv
->vma_manager
);
1410 static int vmwgfx_pm_notifier(struct notifier_block
*nb
, unsigned long val
,
1413 struct vmw_private
*dev_priv
=
1414 container_of(nb
, struct vmw_private
, pm_nb
);
1417 case PM_HIBERNATION_PREPARE
:
1419 * Take the reservation sem in write mode, which will make sure
1420 * there are no other processes holding a buffer object
1421 * reservation, meaning we should be able to evict all buffer
1422 * objects if needed.
1423 * Once user-space processes have been frozen, we can release
1426 dev_priv
->suspend_locked
= true;
1428 case PM_POST_HIBERNATION
:
1429 case PM_POST_RESTORE
:
1430 if (READ_ONCE(dev_priv
->suspend_locked
)) {
1431 dev_priv
->suspend_locked
= false;
1440 static int vmw_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1442 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1443 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1445 if (dev_priv
->refuse_hibernation
)
1448 pci_save_state(pdev
);
1449 pci_disable_device(pdev
);
1450 pci_set_power_state(pdev
, PCI_D3hot
);
1454 static int vmw_pci_resume(struct pci_dev
*pdev
)
1456 pci_set_power_state(pdev
, PCI_D0
);
1457 pci_restore_state(pdev
);
1458 return pci_enable_device(pdev
);
1461 static int vmw_pm_suspend(struct device
*kdev
)
1463 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1464 struct pm_message dummy
;
1468 return vmw_pci_suspend(pdev
, dummy
);
1471 static int vmw_pm_resume(struct device
*kdev
)
1473 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1475 return vmw_pci_resume(pdev
);
1478 static int vmw_pm_freeze(struct device
*kdev
)
1480 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1481 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1482 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1483 struct ttm_operation_ctx ctx
= {
1484 .interruptible
= false,
1485 .no_wait_gpu
= false
1490 * No user-space processes should be running now.
1492 ret
= vmw_kms_suspend(&dev_priv
->drm
);
1494 DRM_ERROR("Failed to freeze modesetting.\n");
1497 if (dev_priv
->enable_fb
)
1498 vmw_fb_off(dev_priv
);
1500 vmw_execbuf_release_pinned_bo(dev_priv
);
1501 vmw_resource_evict_all(dev_priv
);
1502 vmw_release_device_early(dev_priv
);
1503 while (ttm_device_swapout(&dev_priv
->bdev
, &ctx
, GFP_KERNEL
) > 0);
1504 if (dev_priv
->enable_fb
)
1505 vmw_fifo_resource_dec(dev_priv
);
1506 if (atomic_read(&dev_priv
->num_fifo_resources
) != 0) {
1507 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1508 if (dev_priv
->enable_fb
)
1509 vmw_fifo_resource_inc(dev_priv
);
1510 WARN_ON(vmw_request_device_late(dev_priv
));
1511 dev_priv
->suspend_locked
= false;
1512 if (dev_priv
->suspend_state
)
1513 vmw_kms_resume(dev
);
1514 if (dev_priv
->enable_fb
)
1515 vmw_fb_on(dev_priv
);
1519 vmw_fence_fifo_down(dev_priv
->fman
);
1520 __vmw_svga_disable(dev_priv
);
1522 vmw_release_device_late(dev_priv
);
1526 static int vmw_pm_restore(struct device
*kdev
)
1528 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1529 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1530 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1533 vmw_detect_version(dev_priv
);
1535 if (dev_priv
->enable_fb
)
1536 vmw_fifo_resource_inc(dev_priv
);
1538 ret
= vmw_request_device(dev_priv
);
1542 if (dev_priv
->enable_fb
)
1543 __vmw_svga_enable(dev_priv
);
1545 vmw_fence_fifo_up(dev_priv
->fman
);
1546 dev_priv
->suspend_locked
= false;
1547 if (dev_priv
->suspend_state
)
1548 vmw_kms_resume(&dev_priv
->drm
);
1550 if (dev_priv
->enable_fb
)
1551 vmw_fb_on(dev_priv
);
1556 static const struct dev_pm_ops vmw_pm_ops
= {
1557 .freeze
= vmw_pm_freeze
,
1558 .thaw
= vmw_pm_restore
,
1559 .restore
= vmw_pm_restore
,
1560 .suspend
= vmw_pm_suspend
,
1561 .resume
= vmw_pm_resume
,
1564 static const struct file_operations vmwgfx_driver_fops
= {
1565 .owner
= THIS_MODULE
,
1567 .release
= drm_release
,
1568 .unlocked_ioctl
= vmw_unlocked_ioctl
,
1572 #if defined(CONFIG_COMPAT)
1573 .compat_ioctl
= vmw_compat_ioctl
,
1575 .llseek
= noop_llseek
,
1576 .get_unmapped_area
= vmw_get_unmapped_area
,
1579 static const struct drm_driver driver
= {
1581 DRIVER_MODESET
| DRIVER_RENDER
| DRIVER_ATOMIC
,
1582 .ioctls
= vmw_ioctls
,
1583 .num_ioctls
= ARRAY_SIZE(vmw_ioctls
),
1584 .master_set
= vmw_master_set
,
1585 .master_drop
= vmw_master_drop
,
1586 .open
= vmw_driver_open
,
1587 .postclose
= vmw_postclose
,
1589 .dumb_create
= vmw_dumb_create
,
1590 .dumb_map_offset
= vmw_dumb_map_offset
,
1591 .dumb_destroy
= vmw_dumb_destroy
,
1593 .prime_fd_to_handle
= vmw_prime_fd_to_handle
,
1594 .prime_handle_to_fd
= vmw_prime_handle_to_fd
,
1596 .fops
= &vmwgfx_driver_fops
,
1597 .name
= VMWGFX_DRIVER_NAME
,
1598 .desc
= VMWGFX_DRIVER_DESC
,
1599 .date
= VMWGFX_DRIVER_DATE
,
1600 .major
= VMWGFX_DRIVER_MAJOR
,
1601 .minor
= VMWGFX_DRIVER_MINOR
,
1602 .patchlevel
= VMWGFX_DRIVER_PATCHLEVEL
1605 static struct pci_driver vmw_pci_driver
= {
1606 .name
= VMWGFX_DRIVER_NAME
,
1607 .id_table
= vmw_pci_id_list
,
1609 .remove
= vmw_remove
,
1615 static int vmw_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1617 struct vmw_private
*vmw
;
1620 ret
= drm_aperture_remove_conflicting_pci_framebuffers(pdev
, &driver
);
1624 ret
= pcim_enable_device(pdev
);
1628 vmw
= devm_drm_dev_alloc(&pdev
->dev
, &driver
,
1629 struct vmw_private
, drm
);
1635 pci_set_drvdata(pdev
, &vmw
->drm
);
1637 ret
= ttm_mem_global_init(&ttm_mem_glob
, &pdev
->dev
);
1641 ret
= vmw_driver_load(vmw
, ent
->device
);
1645 ret
= drm_dev_register(&vmw
->drm
, 0);
1651 vmw_driver_unload(&vmw
->drm
);
1653 ttm_mem_global_release(&ttm_mem_glob
);
1658 static int __init
vmwgfx_init(void)
1662 if (vgacon_text_force())
1665 ret
= pci_register_driver(&vmw_pci_driver
);
1667 DRM_ERROR("Failed initializing DRM.\n");
1671 static void __exit
vmwgfx_exit(void)
1673 pci_unregister_driver(&vmw_pci_driver
);
1676 module_init(vmwgfx_init
);
1677 module_exit(vmwgfx_exit
);
1679 MODULE_AUTHOR("VMware Inc. and others");
1680 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1681 MODULE_LICENSE("GPL and additional rights");
1682 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR
) "."
1683 __stringify(VMWGFX_DRIVER_MINOR
) "."
1684 __stringify(VMWGFX_DRIVER_PATCHLEVEL
) "."