2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 #include <linux/module.h>
16 #include <linux/export.h>
17 #include <linux/types.h>
18 #include <linux/reset.h>
19 #include <linux/platform_device.h>
20 #include <linux/err.h>
21 #include <linux/spinlock.h>
22 #include <linux/delay.h>
23 #include <linux/interrupt.h>
25 #include <linux/clk.h>
26 #include <linux/list.h>
27 #include <linux/irq.h>
28 #include <linux/irqchip/chained_irq.h>
29 #include <linux/irqdomain.h>
30 #include <linux/of_device.h>
32 #include <drm/drm_fourcc.h>
34 #include <video/imx-ipu-v3.h>
37 static inline u32
ipu_cm_read(struct ipu_soc
*ipu
, unsigned offset
)
39 return readl(ipu
->cm_reg
+ offset
);
42 static inline void ipu_cm_write(struct ipu_soc
*ipu
, u32 value
, unsigned offset
)
44 writel(value
, ipu
->cm_reg
+ offset
);
47 void ipu_srm_dp_sync_update(struct ipu_soc
*ipu
)
51 val
= ipu_cm_read(ipu
, IPU_SRM_PRI2
);
53 ipu_cm_write(ipu
, val
, IPU_SRM_PRI2
);
55 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update
);
57 enum ipu_color_space
ipu_drm_fourcc_to_colorspace(u32 drm_fourcc
)
60 case DRM_FORMAT_RGB565
:
61 case DRM_FORMAT_BGR565
:
62 case DRM_FORMAT_RGB888
:
63 case DRM_FORMAT_BGR888
:
64 case DRM_FORMAT_XRGB8888
:
65 case DRM_FORMAT_XBGR8888
:
66 case DRM_FORMAT_RGBX8888
:
67 case DRM_FORMAT_BGRX8888
:
68 case DRM_FORMAT_ARGB8888
:
69 case DRM_FORMAT_ABGR8888
:
70 case DRM_FORMAT_RGBA8888
:
71 case DRM_FORMAT_BGRA8888
:
72 return IPUV3_COLORSPACE_RGB
;
75 case DRM_FORMAT_YUV420
:
76 case DRM_FORMAT_YVU420
:
77 case DRM_FORMAT_YUV422
:
78 case DRM_FORMAT_YVU422
:
83 return IPUV3_COLORSPACE_YUV
;
85 return IPUV3_COLORSPACE_UNKNOWN
;
88 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace
);
90 enum ipu_color_space
ipu_pixelformat_to_colorspace(u32 pixelformat
)
92 switch (pixelformat
) {
93 case V4L2_PIX_FMT_YUV420
:
94 case V4L2_PIX_FMT_YVU420
:
95 case V4L2_PIX_FMT_YUV422P
:
96 case V4L2_PIX_FMT_UYVY
:
97 case V4L2_PIX_FMT_YUYV
:
98 case V4L2_PIX_FMT_NV12
:
99 case V4L2_PIX_FMT_NV21
:
100 case V4L2_PIX_FMT_NV16
:
101 case V4L2_PIX_FMT_NV61
:
102 return IPUV3_COLORSPACE_YUV
;
103 case V4L2_PIX_FMT_RGB32
:
104 case V4L2_PIX_FMT_BGR32
:
105 case V4L2_PIX_FMT_RGB24
:
106 case V4L2_PIX_FMT_BGR24
:
107 case V4L2_PIX_FMT_RGB565
:
108 return IPUV3_COLORSPACE_RGB
;
110 return IPUV3_COLORSPACE_UNKNOWN
;
113 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace
);
115 bool ipu_pixelformat_is_planar(u32 pixelformat
)
117 switch (pixelformat
) {
118 case V4L2_PIX_FMT_YUV420
:
119 case V4L2_PIX_FMT_YVU420
:
120 case V4L2_PIX_FMT_YUV422P
:
121 case V4L2_PIX_FMT_NV12
:
122 case V4L2_PIX_FMT_NV21
:
123 case V4L2_PIX_FMT_NV16
:
124 case V4L2_PIX_FMT_NV61
:
130 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar
);
132 enum ipu_color_space
ipu_mbus_code_to_colorspace(u32 mbus_code
)
134 switch (mbus_code
& 0xf000) {
136 return IPUV3_COLORSPACE_RGB
;
138 return IPUV3_COLORSPACE_YUV
;
140 return IPUV3_COLORSPACE_UNKNOWN
;
143 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace
);
145 int ipu_stride_to_bytes(u32 pixel_stride
, u32 pixelformat
)
147 switch (pixelformat
) {
148 case V4L2_PIX_FMT_YUV420
:
149 case V4L2_PIX_FMT_YVU420
:
150 case V4L2_PIX_FMT_YUV422P
:
151 case V4L2_PIX_FMT_NV12
:
152 case V4L2_PIX_FMT_NV21
:
153 case V4L2_PIX_FMT_NV16
:
154 case V4L2_PIX_FMT_NV61
:
156 * for the planar YUV formats, the stride passed to
157 * cpmem must be the stride in bytes of the Y plane.
158 * And all the planar YUV formats have an 8-bit
161 return (8 * pixel_stride
) >> 3;
162 case V4L2_PIX_FMT_RGB565
:
163 case V4L2_PIX_FMT_YUYV
:
164 case V4L2_PIX_FMT_UYVY
:
165 return (16 * pixel_stride
) >> 3;
166 case V4L2_PIX_FMT_BGR24
:
167 case V4L2_PIX_FMT_RGB24
:
168 return (24 * pixel_stride
) >> 3;
169 case V4L2_PIX_FMT_BGR32
:
170 case V4L2_PIX_FMT_RGB32
:
171 return (32 * pixel_stride
) >> 3;
178 EXPORT_SYMBOL_GPL(ipu_stride_to_bytes
);
180 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode
*mode
, int degrees
,
181 bool hflip
, bool vflip
)
207 *mode
= (enum ipu_rotate_mode
)((r90
<< 2) | (hf
<< 1) | vf
);
210 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode
);
212 int ipu_rot_mode_to_degrees(int *degrees
, enum ipu_rotate_mode mode
,
213 bool hflip
, bool vflip
)
217 r90
= ((u32
)mode
>> 2) & 0x1;
218 hf
= ((u32
)mode
>> 1) & 0x1;
219 vf
= ((u32
)mode
>> 0) & 0x1;
223 switch ((enum ipu_rotate_mode
)((r90
<< 2) | (hf
<< 1) | vf
)) {
224 case IPU_ROTATE_NONE
:
227 case IPU_ROTATE_90_RIGHT
:
233 case IPU_ROTATE_90_LEFT
:
242 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees
);
244 struct ipuv3_channel
*ipu_idmac_get(struct ipu_soc
*ipu
, unsigned num
)
246 struct ipuv3_channel
*channel
;
248 dev_dbg(ipu
->dev
, "%s %d\n", __func__
, num
);
251 return ERR_PTR(-ENODEV
);
253 mutex_lock(&ipu
->channel_lock
);
255 channel
= &ipu
->channel
[num
];
258 channel
= ERR_PTR(-EBUSY
);
262 channel
->busy
= true;
266 mutex_unlock(&ipu
->channel_lock
);
270 EXPORT_SYMBOL_GPL(ipu_idmac_get
);
272 void ipu_idmac_put(struct ipuv3_channel
*channel
)
274 struct ipu_soc
*ipu
= channel
->ipu
;
276 dev_dbg(ipu
->dev
, "%s %d\n", __func__
, channel
->num
);
278 mutex_lock(&ipu
->channel_lock
);
280 channel
->busy
= false;
282 mutex_unlock(&ipu
->channel_lock
);
284 EXPORT_SYMBOL_GPL(ipu_idmac_put
);
286 #define idma_mask(ch) (1 << ((ch) & 0x1f))
289 * This is an undocumented feature, a write one to a channel bit in
290 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
291 * internal current buffer pointer so that transfers start from buffer
292 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
293 * only says these are read-only registers). This operation is required
294 * for channel linking to work correctly, for instance video capture
295 * pipelines that carry out image rotations will fail after the first
296 * streaming unless this function is called for each channel before
297 * re-enabling the channels.
299 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel
*channel
)
301 struct ipu_soc
*ipu
= channel
->ipu
;
302 unsigned int chno
= channel
->num
;
304 ipu_cm_write(ipu
, idma_mask(chno
), IPU_CHA_CUR_BUF(chno
));
307 void ipu_idmac_set_double_buffer(struct ipuv3_channel
*channel
,
310 struct ipu_soc
*ipu
= channel
->ipu
;
314 spin_lock_irqsave(&ipu
->lock
, flags
);
316 reg
= ipu_cm_read(ipu
, IPU_CHA_DB_MODE_SEL(channel
->num
));
318 reg
|= idma_mask(channel
->num
);
320 reg
&= ~idma_mask(channel
->num
);
321 ipu_cm_write(ipu
, reg
, IPU_CHA_DB_MODE_SEL(channel
->num
));
323 __ipu_idmac_reset_current_buffer(channel
);
325 spin_unlock_irqrestore(&ipu
->lock
, flags
);
327 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer
);
329 static const struct {
333 } idmac_lock_en_info
[] = {
334 { .chnum
= 5, .reg
= IDMAC_CH_LOCK_EN_1
, .shift
= 0, },
335 { .chnum
= 11, .reg
= IDMAC_CH_LOCK_EN_1
, .shift
= 2, },
336 { .chnum
= 12, .reg
= IDMAC_CH_LOCK_EN_1
, .shift
= 4, },
337 { .chnum
= 14, .reg
= IDMAC_CH_LOCK_EN_1
, .shift
= 6, },
338 { .chnum
= 15, .reg
= IDMAC_CH_LOCK_EN_1
, .shift
= 8, },
339 { .chnum
= 20, .reg
= IDMAC_CH_LOCK_EN_1
, .shift
= 10, },
340 { .chnum
= 21, .reg
= IDMAC_CH_LOCK_EN_1
, .shift
= 12, },
341 { .chnum
= 22, .reg
= IDMAC_CH_LOCK_EN_1
, .shift
= 14, },
342 { .chnum
= 23, .reg
= IDMAC_CH_LOCK_EN_1
, .shift
= 16, },
343 { .chnum
= 27, .reg
= IDMAC_CH_LOCK_EN_1
, .shift
= 18, },
344 { .chnum
= 28, .reg
= IDMAC_CH_LOCK_EN_1
, .shift
= 20, },
345 { .chnum
= 45, .reg
= IDMAC_CH_LOCK_EN_2
, .shift
= 0, },
346 { .chnum
= 46, .reg
= IDMAC_CH_LOCK_EN_2
, .shift
= 2, },
347 { .chnum
= 47, .reg
= IDMAC_CH_LOCK_EN_2
, .shift
= 4, },
348 { .chnum
= 48, .reg
= IDMAC_CH_LOCK_EN_2
, .shift
= 6, },
349 { .chnum
= 49, .reg
= IDMAC_CH_LOCK_EN_2
, .shift
= 8, },
350 { .chnum
= 50, .reg
= IDMAC_CH_LOCK_EN_2
, .shift
= 10, },
353 int ipu_idmac_lock_enable(struct ipuv3_channel
*channel
, int num_bursts
)
355 struct ipu_soc
*ipu
= channel
->ipu
;
360 switch (num_bursts
) {
363 bursts
= 0x00; /* locking disabled */
378 for (i
= 0; i
< ARRAY_SIZE(idmac_lock_en_info
); i
++) {
379 if (channel
->num
== idmac_lock_en_info
[i
].chnum
)
382 if (i
>= ARRAY_SIZE(idmac_lock_en_info
))
385 spin_lock_irqsave(&ipu
->lock
, flags
);
387 regval
= ipu_idmac_read(ipu
, idmac_lock_en_info
[i
].reg
);
388 regval
&= ~(0x03 << idmac_lock_en_info
[i
].shift
);
389 regval
|= (bursts
<< idmac_lock_en_info
[i
].shift
);
390 ipu_idmac_write(ipu
, regval
, idmac_lock_en_info
[i
].reg
);
392 spin_unlock_irqrestore(&ipu
->lock
, flags
);
396 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable
);
398 int ipu_module_enable(struct ipu_soc
*ipu
, u32 mask
)
400 unsigned long lock_flags
;
403 spin_lock_irqsave(&ipu
->lock
, lock_flags
);
405 val
= ipu_cm_read(ipu
, IPU_DISP_GEN
);
407 if (mask
& IPU_CONF_DI0_EN
)
408 val
|= IPU_DI0_COUNTER_RELEASE
;
409 if (mask
& IPU_CONF_DI1_EN
)
410 val
|= IPU_DI1_COUNTER_RELEASE
;
412 ipu_cm_write(ipu
, val
, IPU_DISP_GEN
);
414 val
= ipu_cm_read(ipu
, IPU_CONF
);
416 ipu_cm_write(ipu
, val
, IPU_CONF
);
418 spin_unlock_irqrestore(&ipu
->lock
, lock_flags
);
422 EXPORT_SYMBOL_GPL(ipu_module_enable
);
424 int ipu_module_disable(struct ipu_soc
*ipu
, u32 mask
)
426 unsigned long lock_flags
;
429 spin_lock_irqsave(&ipu
->lock
, lock_flags
);
431 val
= ipu_cm_read(ipu
, IPU_CONF
);
433 ipu_cm_write(ipu
, val
, IPU_CONF
);
435 val
= ipu_cm_read(ipu
, IPU_DISP_GEN
);
437 if (mask
& IPU_CONF_DI0_EN
)
438 val
&= ~IPU_DI0_COUNTER_RELEASE
;
439 if (mask
& IPU_CONF_DI1_EN
)
440 val
&= ~IPU_DI1_COUNTER_RELEASE
;
442 ipu_cm_write(ipu
, val
, IPU_DISP_GEN
);
444 spin_unlock_irqrestore(&ipu
->lock
, lock_flags
);
448 EXPORT_SYMBOL_GPL(ipu_module_disable
);
450 int ipu_idmac_get_current_buffer(struct ipuv3_channel
*channel
)
452 struct ipu_soc
*ipu
= channel
->ipu
;
453 unsigned int chno
= channel
->num
;
455 return (ipu_cm_read(ipu
, IPU_CHA_CUR_BUF(chno
)) & idma_mask(chno
)) ? 1 : 0;
457 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer
);
459 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel
*channel
, u32 buf_num
)
461 struct ipu_soc
*ipu
= channel
->ipu
;
465 spin_lock_irqsave(&ipu
->lock
, flags
);
468 reg
= ipu_cm_read(ipu
, IPU_CHA_BUF0_RDY(channel
->num
));
471 reg
= ipu_cm_read(ipu
, IPU_CHA_BUF1_RDY(channel
->num
));
474 reg
= ipu_cm_read(ipu
, IPU_CHA_BUF2_RDY(channel
->num
));
477 spin_unlock_irqrestore(&ipu
->lock
, flags
);
479 return ((reg
& idma_mask(channel
->num
)) != 0);
481 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready
);
483 void ipu_idmac_select_buffer(struct ipuv3_channel
*channel
, u32 buf_num
)
485 struct ipu_soc
*ipu
= channel
->ipu
;
486 unsigned int chno
= channel
->num
;
489 spin_lock_irqsave(&ipu
->lock
, flags
);
491 /* Mark buffer as ready. */
493 ipu_cm_write(ipu
, idma_mask(chno
), IPU_CHA_BUF0_RDY(chno
));
495 ipu_cm_write(ipu
, idma_mask(chno
), IPU_CHA_BUF1_RDY(chno
));
497 spin_unlock_irqrestore(&ipu
->lock
, flags
);
499 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer
);
501 void ipu_idmac_clear_buffer(struct ipuv3_channel
*channel
, u32 buf_num
)
503 struct ipu_soc
*ipu
= channel
->ipu
;
504 unsigned int chno
= channel
->num
;
507 spin_lock_irqsave(&ipu
->lock
, flags
);
509 ipu_cm_write(ipu
, 0xF0300000, IPU_GPR
); /* write one to clear */
512 ipu_cm_write(ipu
, idma_mask(chno
), IPU_CHA_BUF0_RDY(chno
));
515 ipu_cm_write(ipu
, idma_mask(chno
), IPU_CHA_BUF1_RDY(chno
));
518 ipu_cm_write(ipu
, idma_mask(chno
), IPU_CHA_BUF2_RDY(chno
));
523 ipu_cm_write(ipu
, 0x0, IPU_GPR
); /* write one to set */
525 spin_unlock_irqrestore(&ipu
->lock
, flags
);
527 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer
);
529 int ipu_idmac_enable_channel(struct ipuv3_channel
*channel
)
531 struct ipu_soc
*ipu
= channel
->ipu
;
535 spin_lock_irqsave(&ipu
->lock
, flags
);
537 val
= ipu_idmac_read(ipu
, IDMAC_CHA_EN(channel
->num
));
538 val
|= idma_mask(channel
->num
);
539 ipu_idmac_write(ipu
, val
, IDMAC_CHA_EN(channel
->num
));
541 spin_unlock_irqrestore(&ipu
->lock
, flags
);
545 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel
);
547 bool ipu_idmac_channel_busy(struct ipu_soc
*ipu
, unsigned int chno
)
549 return (ipu_idmac_read(ipu
, IDMAC_CHA_BUSY(chno
)) & idma_mask(chno
));
551 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy
);
553 int ipu_idmac_wait_busy(struct ipuv3_channel
*channel
, int ms
)
555 struct ipu_soc
*ipu
= channel
->ipu
;
556 unsigned long timeout
;
558 timeout
= jiffies
+ msecs_to_jiffies(ms
);
559 while (ipu_idmac_read(ipu
, IDMAC_CHA_BUSY(channel
->num
)) &
560 idma_mask(channel
->num
)) {
561 if (time_after(jiffies
, timeout
))
568 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy
);
570 int ipu_wait_interrupt(struct ipu_soc
*ipu
, int irq
, int ms
)
572 unsigned long timeout
;
574 timeout
= jiffies
+ msecs_to_jiffies(ms
);
575 ipu_cm_write(ipu
, BIT(irq
% 32), IPU_INT_STAT(irq
/ 32));
576 while (!(ipu_cm_read(ipu
, IPU_INT_STAT(irq
/ 32) & BIT(irq
% 32)))) {
577 if (time_after(jiffies
, timeout
))
584 EXPORT_SYMBOL_GPL(ipu_wait_interrupt
);
586 int ipu_idmac_disable_channel(struct ipuv3_channel
*channel
)
588 struct ipu_soc
*ipu
= channel
->ipu
;
592 spin_lock_irqsave(&ipu
->lock
, flags
);
594 /* Disable DMA channel(s) */
595 val
= ipu_idmac_read(ipu
, IDMAC_CHA_EN(channel
->num
));
596 val
&= ~idma_mask(channel
->num
);
597 ipu_idmac_write(ipu
, val
, IDMAC_CHA_EN(channel
->num
));
599 __ipu_idmac_reset_current_buffer(channel
);
601 /* Set channel buffers NOT to be ready */
602 ipu_cm_write(ipu
, 0xf0000000, IPU_GPR
); /* write one to clear */
604 if (ipu_cm_read(ipu
, IPU_CHA_BUF0_RDY(channel
->num
)) &
605 idma_mask(channel
->num
)) {
606 ipu_cm_write(ipu
, idma_mask(channel
->num
),
607 IPU_CHA_BUF0_RDY(channel
->num
));
610 if (ipu_cm_read(ipu
, IPU_CHA_BUF1_RDY(channel
->num
)) &
611 idma_mask(channel
->num
)) {
612 ipu_cm_write(ipu
, idma_mask(channel
->num
),
613 IPU_CHA_BUF1_RDY(channel
->num
));
616 ipu_cm_write(ipu
, 0x0, IPU_GPR
); /* write one to set */
618 /* Reset the double buffer */
619 val
= ipu_cm_read(ipu
, IPU_CHA_DB_MODE_SEL(channel
->num
));
620 val
&= ~idma_mask(channel
->num
);
621 ipu_cm_write(ipu
, val
, IPU_CHA_DB_MODE_SEL(channel
->num
));
623 spin_unlock_irqrestore(&ipu
->lock
, flags
);
627 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel
);
630 * The imx6 rev. D TRM says that enabling the WM feature will increase
631 * a channel's priority. Refer to Table 36-8 Calculated priority value.
632 * The sub-module that is the sink or source for the channel must enable
633 * watermark signal for this to take effect (SMFC_WM for instance).
635 void ipu_idmac_enable_watermark(struct ipuv3_channel
*channel
, bool enable
)
637 struct ipu_soc
*ipu
= channel
->ipu
;
641 spin_lock_irqsave(&ipu
->lock
, flags
);
643 val
= ipu_idmac_read(ipu
, IDMAC_WM_EN(channel
->num
));
645 val
|= 1 << (channel
->num
% 32);
647 val
&= ~(1 << (channel
->num
% 32));
648 ipu_idmac_write(ipu
, val
, IDMAC_WM_EN(channel
->num
));
650 spin_unlock_irqrestore(&ipu
->lock
, flags
);
652 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark
);
654 static int ipu_memory_reset(struct ipu_soc
*ipu
)
656 unsigned long timeout
;
658 ipu_cm_write(ipu
, 0x807FFFFF, IPU_MEM_RST
);
660 timeout
= jiffies
+ msecs_to_jiffies(1000);
661 while (ipu_cm_read(ipu
, IPU_MEM_RST
) & 0x80000000) {
662 if (time_after(jiffies
, timeout
))
671 * Set the source mux for the given CSI. Selects either parallel or
674 void ipu_set_csi_src_mux(struct ipu_soc
*ipu
, int csi_id
, bool mipi_csi2
)
679 mask
= (csi_id
== 1) ? IPU_CONF_CSI1_DATA_SOURCE
:
680 IPU_CONF_CSI0_DATA_SOURCE
;
682 spin_lock_irqsave(&ipu
->lock
, flags
);
684 val
= ipu_cm_read(ipu
, IPU_CONF
);
689 ipu_cm_write(ipu
, val
, IPU_CONF
);
691 spin_unlock_irqrestore(&ipu
->lock
, flags
);
693 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux
);
696 * Set the source mux for the IC. Selects either CSI[01] or the VDI.
698 void ipu_set_ic_src_mux(struct ipu_soc
*ipu
, int csi_id
, bool vdi
)
703 spin_lock_irqsave(&ipu
->lock
, flags
);
705 val
= ipu_cm_read(ipu
, IPU_CONF
);
707 val
|= IPU_CONF_IC_INPUT
;
709 val
&= ~IPU_CONF_IC_INPUT
;
711 val
|= IPU_CONF_CSI_SEL
;
713 val
&= ~IPU_CONF_CSI_SEL
;
715 ipu_cm_write(ipu
, val
, IPU_CONF
);
717 spin_unlock_irqrestore(&ipu
->lock
, flags
);
719 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux
);
723 unsigned long cm_ofs
;
724 unsigned long cpmem_ofs
;
725 unsigned long srm_ofs
;
726 unsigned long tpm_ofs
;
727 unsigned long csi0_ofs
;
728 unsigned long csi1_ofs
;
729 unsigned long ic_ofs
;
730 unsigned long disp0_ofs
;
731 unsigned long disp1_ofs
;
732 unsigned long dc_tmpl_ofs
;
733 unsigned long vdi_ofs
;
734 enum ipuv3_type type
;
737 static struct ipu_devtype ipu_type_imx51
= {
739 .cm_ofs
= 0x1e000000,
740 .cpmem_ofs
= 0x1f000000,
741 .srm_ofs
= 0x1f040000,
742 .tpm_ofs
= 0x1f060000,
743 .csi0_ofs
= 0x1f030000,
744 .csi1_ofs
= 0x1f038000,
745 .ic_ofs
= 0x1e020000,
746 .disp0_ofs
= 0x1e040000,
747 .disp1_ofs
= 0x1e048000,
748 .dc_tmpl_ofs
= 0x1f080000,
749 .vdi_ofs
= 0x1e068000,
753 static struct ipu_devtype ipu_type_imx53
= {
755 .cm_ofs
= 0x06000000,
756 .cpmem_ofs
= 0x07000000,
757 .srm_ofs
= 0x07040000,
758 .tpm_ofs
= 0x07060000,
759 .csi0_ofs
= 0x07030000,
760 .csi1_ofs
= 0x07038000,
761 .ic_ofs
= 0x06020000,
762 .disp0_ofs
= 0x06040000,
763 .disp1_ofs
= 0x06048000,
764 .dc_tmpl_ofs
= 0x07080000,
765 .vdi_ofs
= 0x06068000,
769 static struct ipu_devtype ipu_type_imx6q
= {
771 .cm_ofs
= 0x00200000,
772 .cpmem_ofs
= 0x00300000,
773 .srm_ofs
= 0x00340000,
774 .tpm_ofs
= 0x00360000,
775 .csi0_ofs
= 0x00230000,
776 .csi1_ofs
= 0x00238000,
777 .ic_ofs
= 0x00220000,
778 .disp0_ofs
= 0x00240000,
779 .disp1_ofs
= 0x00248000,
780 .dc_tmpl_ofs
= 0x00380000,
781 .vdi_ofs
= 0x00268000,
785 static const struct of_device_id imx_ipu_dt_ids
[] = {
786 { .compatible
= "fsl,imx51-ipu", .data
= &ipu_type_imx51
, },
787 { .compatible
= "fsl,imx53-ipu", .data
= &ipu_type_imx53
, },
788 { .compatible
= "fsl,imx6q-ipu", .data
= &ipu_type_imx6q
, },
791 MODULE_DEVICE_TABLE(of
, imx_ipu_dt_ids
);
793 static int ipu_submodules_init(struct ipu_soc
*ipu
,
794 struct platform_device
*pdev
, unsigned long ipu_base
,
799 struct device
*dev
= &pdev
->dev
;
800 const struct ipu_devtype
*devtype
= ipu
->devtype
;
802 ret
= ipu_cpmem_init(ipu
, dev
, ipu_base
+ devtype
->cpmem_ofs
);
808 ret
= ipu_csi_init(ipu
, dev
, 0, ipu_base
+ devtype
->csi0_ofs
,
809 IPU_CONF_CSI0_EN
, ipu_clk
);
815 ret
= ipu_csi_init(ipu
, dev
, 1, ipu_base
+ devtype
->csi1_ofs
,
816 IPU_CONF_CSI1_EN
, ipu_clk
);
822 ret
= ipu_ic_init(ipu
, dev
,
823 ipu_base
+ devtype
->ic_ofs
,
824 ipu_base
+ devtype
->tpm_ofs
);
830 ret
= ipu_di_init(ipu
, dev
, 0, ipu_base
+ devtype
->disp0_ofs
,
831 IPU_CONF_DI0_EN
, ipu_clk
);
837 ret
= ipu_di_init(ipu
, dev
, 1, ipu_base
+ devtype
->disp1_ofs
,
838 IPU_CONF_DI1_EN
, ipu_clk
);
844 ret
= ipu_dc_init(ipu
, dev
, ipu_base
+ devtype
->cm_ofs
+
845 IPU_CM_DC_REG_OFS
, ipu_base
+ devtype
->dc_tmpl_ofs
);
847 unit
= "dc_template";
851 ret
= ipu_dmfc_init(ipu
, dev
, ipu_base
+
852 devtype
->cm_ofs
+ IPU_CM_DMFC_REG_OFS
, ipu_clk
);
858 ret
= ipu_dp_init(ipu
, dev
, ipu_base
+ devtype
->srm_ofs
);
864 ret
= ipu_smfc_init(ipu
, dev
, ipu_base
+
865 devtype
->cm_ofs
+ IPU_CM_SMFC_REG_OFS
);
886 ipu_csi_exit(ipu
, 1);
888 ipu_csi_exit(ipu
, 0);
892 dev_err(&pdev
->dev
, "init %s failed with %d\n", unit
, ret
);
896 static void ipu_irq_handle(struct ipu_soc
*ipu
, const int *regs
, int num_regs
)
898 unsigned long status
;
901 for (i
= 0; i
< num_regs
; i
++) {
903 status
= ipu_cm_read(ipu
, IPU_INT_STAT(regs
[i
]));
904 status
&= ipu_cm_read(ipu
, IPU_INT_CTRL(regs
[i
]));
906 for_each_set_bit(bit
, &status
, 32) {
907 irq
= irq_linear_revmap(ipu
->domain
,
910 generic_handle_irq(irq
);
915 static void ipu_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
917 struct ipu_soc
*ipu
= irq_desc_get_handler_data(desc
);
918 const int int_reg
[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
919 struct irq_chip
*chip
= irq_get_chip(irq
);
921 chained_irq_enter(chip
, desc
);
923 ipu_irq_handle(ipu
, int_reg
, ARRAY_SIZE(int_reg
));
925 chained_irq_exit(chip
, desc
);
928 static void ipu_err_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
930 struct ipu_soc
*ipu
= irq_desc_get_handler_data(desc
);
931 const int int_reg
[] = { 4, 5, 8, 9};
932 struct irq_chip
*chip
= irq_get_chip(irq
);
934 chained_irq_enter(chip
, desc
);
936 ipu_irq_handle(ipu
, int_reg
, ARRAY_SIZE(int_reg
));
938 chained_irq_exit(chip
, desc
);
941 int ipu_map_irq(struct ipu_soc
*ipu
, int irq
)
945 virq
= irq_linear_revmap(ipu
->domain
, irq
);
947 virq
= irq_create_mapping(ipu
->domain
, irq
);
951 EXPORT_SYMBOL_GPL(ipu_map_irq
);
953 int ipu_idmac_channel_irq(struct ipu_soc
*ipu
, struct ipuv3_channel
*channel
,
954 enum ipu_channel_irq irq_type
)
956 return ipu_map_irq(ipu
, irq_type
+ channel
->num
);
958 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq
);
960 static void ipu_submodules_exit(struct ipu_soc
*ipu
)
969 ipu_csi_exit(ipu
, 1);
970 ipu_csi_exit(ipu
, 0);
974 static int platform_remove_devices_fn(struct device
*dev
, void *unused
)
976 struct platform_device
*pdev
= to_platform_device(dev
);
978 platform_device_unregister(pdev
);
983 static void platform_device_unregister_children(struct platform_device
*pdev
)
985 device_for_each_child(&pdev
->dev
, NULL
, platform_remove_devices_fn
);
988 struct ipu_platform_reg
{
989 struct ipu_client_platformdata pdata
;
994 static const struct ipu_platform_reg client_reg
[] = {
999 .dp
= IPU_DP_FLOW_SYNC_BG
,
1000 .dma
[0] = IPUV3_CHANNEL_MEM_BG_SYNC
,
1001 .dma
[1] = IPUV3_CHANNEL_MEM_FG_SYNC
,
1003 .name
= "imx-ipuv3-crtc",
1009 .dma
[0] = IPUV3_CHANNEL_MEM_DC_SYNC
,
1012 .name
= "imx-ipuv3-crtc",
1016 .dma
[0] = IPUV3_CHANNEL_CSI0
,
1019 .reg_offset
= IPU_CM_CSI0_REG_OFS
,
1020 .name
= "imx-ipuv3-camera",
1024 .dma
[0] = IPUV3_CHANNEL_CSI1
,
1027 .reg_offset
= IPU_CM_CSI1_REG_OFS
,
1028 .name
= "imx-ipuv3-camera",
1032 static DEFINE_MUTEX(ipu_client_id_mutex
);
1033 static int ipu_client_id
;
1035 static int ipu_add_client_devices(struct ipu_soc
*ipu
, unsigned long ipu_base
)
1037 struct device
*dev
= ipu
->dev
;
1041 mutex_lock(&ipu_client_id_mutex
);
1043 ipu_client_id
+= ARRAY_SIZE(client_reg
);
1044 mutex_unlock(&ipu_client_id_mutex
);
1046 for (i
= 0; i
< ARRAY_SIZE(client_reg
); i
++) {
1047 const struct ipu_platform_reg
*reg
= &client_reg
[i
];
1048 struct platform_device
*pdev
;
1049 struct resource res
;
1051 if (reg
->reg_offset
) {
1052 memset(&res
, 0, sizeof(res
));
1053 res
.flags
= IORESOURCE_MEM
;
1054 res
.start
= ipu_base
+ ipu
->devtype
->cm_ofs
+ reg
->reg_offset
;
1055 res
.end
= res
.start
+ PAGE_SIZE
- 1;
1056 pdev
= platform_device_register_resndata(dev
, reg
->name
,
1057 id
++, &res
, 1, ®
->pdata
, sizeof(reg
->pdata
));
1059 pdev
= platform_device_register_data(dev
, reg
->name
,
1060 id
++, ®
->pdata
, sizeof(reg
->pdata
));
1064 ret
= PTR_ERR(pdev
);
1072 platform_device_unregister_children(to_platform_device(dev
));
1078 static int ipu_irq_init(struct ipu_soc
*ipu
)
1080 struct irq_chip_generic
*gc
;
1081 struct irq_chip_type
*ct
;
1082 unsigned long unused
[IPU_NUM_IRQS
/ 32] = {
1083 0x400100d0, 0xffe000fd,
1084 0x400100d0, 0xffe000fd,
1085 0x400100d0, 0xffe000fd,
1086 0x4077ffff, 0xffe7e1fd,
1087 0x23fffffe, 0x8880fff0,
1088 0xf98fe7d0, 0xfff81fff,
1089 0x400100d0, 0xffe000fd,
1094 ipu
->domain
= irq_domain_add_linear(ipu
->dev
->of_node
, IPU_NUM_IRQS
,
1095 &irq_generic_chip_ops
, ipu
);
1097 dev_err(ipu
->dev
, "failed to add irq domain\n");
1101 ret
= irq_alloc_domain_generic_chips(ipu
->domain
, 32, 1, "IPU",
1102 handle_level_irq
, 0,
1105 dev_err(ipu
->dev
, "failed to alloc generic irq chips\n");
1106 irq_domain_remove(ipu
->domain
);
1110 for (i
= 0; i
< IPU_NUM_IRQS
; i
+= 32)
1111 ipu_cm_write(ipu
, 0, IPU_INT_CTRL(i
/ 32));
1113 for (i
= 0; i
< IPU_NUM_IRQS
; i
+= 32) {
1114 gc
= irq_get_domain_generic_chip(ipu
->domain
, i
);
1115 gc
->reg_base
= ipu
->cm_reg
;
1116 gc
->unused
= unused
[i
/ 32];
1117 ct
= gc
->chip_types
;
1118 ct
->chip
.irq_ack
= irq_gc_ack_set_bit
;
1119 ct
->chip
.irq_mask
= irq_gc_mask_clr_bit
;
1120 ct
->chip
.irq_unmask
= irq_gc_mask_set_bit
;
1121 ct
->regs
.ack
= IPU_INT_STAT(i
/ 32);
1122 ct
->regs
.mask
= IPU_INT_CTRL(i
/ 32);
1125 irq_set_chained_handler_and_data(ipu
->irq_sync
, ipu_irq_handler
, ipu
);
1126 irq_set_chained_handler_and_data(ipu
->irq_err
, ipu_err_irq_handler
,
1132 static void ipu_irq_exit(struct ipu_soc
*ipu
)
1136 irq_set_chained_handler_and_data(ipu
->irq_err
, NULL
, NULL
);
1137 irq_set_chained_handler_and_data(ipu
->irq_sync
, NULL
, NULL
);
1139 /* TODO: remove irq_domain_generic_chips */
1141 for (i
= 0; i
< IPU_NUM_IRQS
; i
++) {
1142 irq
= irq_linear_revmap(ipu
->domain
, i
);
1144 irq_dispose_mapping(irq
);
1147 irq_domain_remove(ipu
->domain
);
1150 void ipu_dump(struct ipu_soc
*ipu
)
1154 dev_dbg(ipu
->dev
, "IPU_CONF = \t0x%08X\n",
1155 ipu_cm_read(ipu
, IPU_CONF
));
1156 dev_dbg(ipu
->dev
, "IDMAC_CONF = \t0x%08X\n",
1157 ipu_idmac_read(ipu
, IDMAC_CONF
));
1158 dev_dbg(ipu
->dev
, "IDMAC_CHA_EN1 = \t0x%08X\n",
1159 ipu_idmac_read(ipu
, IDMAC_CHA_EN(0)));
1160 dev_dbg(ipu
->dev
, "IDMAC_CHA_EN2 = \t0x%08X\n",
1161 ipu_idmac_read(ipu
, IDMAC_CHA_EN(32)));
1162 dev_dbg(ipu
->dev
, "IDMAC_CHA_PRI1 = \t0x%08X\n",
1163 ipu_idmac_read(ipu
, IDMAC_CHA_PRI(0)));
1164 dev_dbg(ipu
->dev
, "IDMAC_CHA_PRI2 = \t0x%08X\n",
1165 ipu_idmac_read(ipu
, IDMAC_CHA_PRI(32)));
1166 dev_dbg(ipu
->dev
, "IDMAC_BAND_EN1 = \t0x%08X\n",
1167 ipu_idmac_read(ipu
, IDMAC_BAND_EN(0)));
1168 dev_dbg(ipu
->dev
, "IDMAC_BAND_EN2 = \t0x%08X\n",
1169 ipu_idmac_read(ipu
, IDMAC_BAND_EN(32)));
1170 dev_dbg(ipu
->dev
, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
1171 ipu_cm_read(ipu
, IPU_CHA_DB_MODE_SEL(0)));
1172 dev_dbg(ipu
->dev
, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
1173 ipu_cm_read(ipu
, IPU_CHA_DB_MODE_SEL(32)));
1174 dev_dbg(ipu
->dev
, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
1175 ipu_cm_read(ipu
, IPU_FS_PROC_FLOW1
));
1176 dev_dbg(ipu
->dev
, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
1177 ipu_cm_read(ipu
, IPU_FS_PROC_FLOW2
));
1178 dev_dbg(ipu
->dev
, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
1179 ipu_cm_read(ipu
, IPU_FS_PROC_FLOW3
));
1180 dev_dbg(ipu
->dev
, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
1181 ipu_cm_read(ipu
, IPU_FS_DISP_FLOW1
));
1182 for (i
= 0; i
< 15; i
++)
1183 dev_dbg(ipu
->dev
, "IPU_INT_CTRL(%d) = \t%08X\n", i
,
1184 ipu_cm_read(ipu
, IPU_INT_CTRL(i
)));
1186 EXPORT_SYMBOL_GPL(ipu_dump
);
1188 static int ipu_probe(struct platform_device
*pdev
)
1190 const struct of_device_id
*of_id
=
1191 of_match_device(imx_ipu_dt_ids
, &pdev
->dev
);
1192 struct ipu_soc
*ipu
;
1193 struct resource
*res
;
1194 unsigned long ipu_base
;
1195 int i
, ret
, irq_sync
, irq_err
;
1196 const struct ipu_devtype
*devtype
;
1198 devtype
= of_id
->data
;
1200 irq_sync
= platform_get_irq(pdev
, 0);
1201 irq_err
= platform_get_irq(pdev
, 1);
1202 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1204 dev_dbg(&pdev
->dev
, "irq_sync: %d irq_err: %d\n",
1207 if (!res
|| irq_sync
< 0 || irq_err
< 0)
1210 ipu_base
= res
->start
;
1212 ipu
= devm_kzalloc(&pdev
->dev
, sizeof(*ipu
), GFP_KERNEL
);
1216 for (i
= 0; i
< 64; i
++)
1217 ipu
->channel
[i
].ipu
= ipu
;
1218 ipu
->devtype
= devtype
;
1219 ipu
->ipu_type
= devtype
->type
;
1221 spin_lock_init(&ipu
->lock
);
1222 mutex_init(&ipu
->channel_lock
);
1224 dev_dbg(&pdev
->dev
, "cm_reg: 0x%08lx\n",
1225 ipu_base
+ devtype
->cm_ofs
);
1226 dev_dbg(&pdev
->dev
, "idmac: 0x%08lx\n",
1227 ipu_base
+ devtype
->cm_ofs
+ IPU_CM_IDMAC_REG_OFS
);
1228 dev_dbg(&pdev
->dev
, "cpmem: 0x%08lx\n",
1229 ipu_base
+ devtype
->cpmem_ofs
);
1230 dev_dbg(&pdev
->dev
, "csi0: 0x%08lx\n",
1231 ipu_base
+ devtype
->csi0_ofs
);
1232 dev_dbg(&pdev
->dev
, "csi1: 0x%08lx\n",
1233 ipu_base
+ devtype
->csi1_ofs
);
1234 dev_dbg(&pdev
->dev
, "ic: 0x%08lx\n",
1235 ipu_base
+ devtype
->ic_ofs
);
1236 dev_dbg(&pdev
->dev
, "disp0: 0x%08lx\n",
1237 ipu_base
+ devtype
->disp0_ofs
);
1238 dev_dbg(&pdev
->dev
, "disp1: 0x%08lx\n",
1239 ipu_base
+ devtype
->disp1_ofs
);
1240 dev_dbg(&pdev
->dev
, "srm: 0x%08lx\n",
1241 ipu_base
+ devtype
->srm_ofs
);
1242 dev_dbg(&pdev
->dev
, "tpm: 0x%08lx\n",
1243 ipu_base
+ devtype
->tpm_ofs
);
1244 dev_dbg(&pdev
->dev
, "dc: 0x%08lx\n",
1245 ipu_base
+ devtype
->cm_ofs
+ IPU_CM_DC_REG_OFS
);
1246 dev_dbg(&pdev
->dev
, "ic: 0x%08lx\n",
1247 ipu_base
+ devtype
->cm_ofs
+ IPU_CM_IC_REG_OFS
);
1248 dev_dbg(&pdev
->dev
, "dmfc: 0x%08lx\n",
1249 ipu_base
+ devtype
->cm_ofs
+ IPU_CM_DMFC_REG_OFS
);
1250 dev_dbg(&pdev
->dev
, "vdi: 0x%08lx\n",
1251 ipu_base
+ devtype
->vdi_ofs
);
1253 ipu
->cm_reg
= devm_ioremap(&pdev
->dev
,
1254 ipu_base
+ devtype
->cm_ofs
, PAGE_SIZE
);
1255 ipu
->idmac_reg
= devm_ioremap(&pdev
->dev
,
1256 ipu_base
+ devtype
->cm_ofs
+ IPU_CM_IDMAC_REG_OFS
,
1259 if (!ipu
->cm_reg
|| !ipu
->idmac_reg
)
1262 ipu
->clk
= devm_clk_get(&pdev
->dev
, "bus");
1263 if (IS_ERR(ipu
->clk
)) {
1264 ret
= PTR_ERR(ipu
->clk
);
1265 dev_err(&pdev
->dev
, "clk_get failed with %d", ret
);
1269 platform_set_drvdata(pdev
, ipu
);
1271 ret
= clk_prepare_enable(ipu
->clk
);
1273 dev_err(&pdev
->dev
, "clk_prepare_enable failed: %d\n", ret
);
1277 ipu
->dev
= &pdev
->dev
;
1278 ipu
->irq_sync
= irq_sync
;
1279 ipu
->irq_err
= irq_err
;
1281 ret
= ipu_irq_init(ipu
);
1283 goto out_failed_irq
;
1285 ret
= device_reset(&pdev
->dev
);
1287 dev_err(&pdev
->dev
, "failed to reset: %d\n", ret
);
1288 goto out_failed_reset
;
1290 ret
= ipu_memory_reset(ipu
);
1292 goto out_failed_reset
;
1294 /* Set MCU_T to divide MCU access window into 2 */
1295 ipu_cm_write(ipu
, 0x00400000L
| (IPU_MCU_T_DEFAULT
<< 18),
1298 ret
= ipu_submodules_init(ipu
, pdev
, ipu_base
, ipu
->clk
);
1300 goto failed_submodules_init
;
1302 ret
= ipu_add_client_devices(ipu
, ipu_base
);
1304 dev_err(&pdev
->dev
, "adding client devices failed with %d\n",
1306 goto failed_add_clients
;
1309 dev_info(&pdev
->dev
, "%s probed\n", devtype
->name
);
1314 ipu_submodules_exit(ipu
);
1315 failed_submodules_init
:
1319 clk_disable_unprepare(ipu
->clk
);
1323 static int ipu_remove(struct platform_device
*pdev
)
1325 struct ipu_soc
*ipu
= platform_get_drvdata(pdev
);
1327 platform_device_unregister_children(pdev
);
1328 ipu_submodules_exit(ipu
);
1331 clk_disable_unprepare(ipu
->clk
);
1336 static struct platform_driver imx_ipu_driver
= {
1338 .name
= "imx-ipuv3",
1339 .of_match_table
= imx_ipu_dt_ids
,
1342 .remove
= ipu_remove
,
1345 module_platform_driver(imx_ipu_driver
);
1347 MODULE_ALIAS("platform:imx-ipuv3");
1348 MODULE_DESCRIPTION("i.MX IPU v3 driver");
1349 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1350 MODULE_LICENSE("GPL");