drivers/gpu/ipu-v3/ipu-dc.c

   1 /*
   2  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
   3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15
  16 #include <linux/export.h>
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/errno.h>
  20 #include <linux/delay.h>
  21 #include <linux/io.h>
  22
  23 #include <video/imx-ipu-v3.h>
  24 #include "ipu-prv.h"
  25
  26 #define DC_MAP_CONF_PTR(n)      (0x108 + ((n) & ~0x1) * 2)
  27 #define DC_MAP_CONF_VAL(n)      (0x144 + ((n) & ~0x1) * 2)
  28
  29 #define DC_EVT_NF               0
  30 #define DC_EVT_NL               1
  31 #define DC_EVT_EOF              2
  32 #define DC_EVT_NFIELD           3
  33 #define DC_EVT_EOL              4
  34 #define DC_EVT_EOFIELD          5
  35 #define DC_EVT_NEW_ADDR         6
  36 #define DC_EVT_NEW_CHAN         7
  37 #define DC_EVT_NEW_DATA         8
  38
  39 #define DC_EVT_NEW_ADDR_W_0     0
  40 #define DC_EVT_NEW_ADDR_W_1     1
  41 #define DC_EVT_NEW_CHAN_W_0     2
  42 #define DC_EVT_NEW_CHAN_W_1     3
  43 #define DC_EVT_NEW_DATA_W_0     4
  44 #define DC_EVT_NEW_DATA_W_1     5
  45 #define DC_EVT_NEW_ADDR_R_0     6
  46 #define DC_EVT_NEW_ADDR_R_1     7
  47 #define DC_EVT_NEW_CHAN_R_0     8
  48 #define DC_EVT_NEW_CHAN_R_1     9
  49 #define DC_EVT_NEW_DATA_R_0     10
  50 #define DC_EVT_NEW_DATA_R_1     11
  51
  52 #define DC_WR_CH_CONF           0x0
  53 #define DC_WR_CH_ADDR           0x4
  54 #define DC_RL_CH(evt)           (8 + ((evt) & ~0x1) * 2)
  55
  56 #define DC_GEN                  0xd4
  57 #define DC_DISP_CONF1(disp)     (0xd8 + (disp) * 4)
  58 #define DC_DISP_CONF2(disp)     (0xe8 + (disp) * 4)
  59 #define DC_STAT                 0x1c8
  60
  61 #define WROD(lf)                (0x18 | ((lf) << 1))
  62 #define WRG                     0x01
  63 #define WCLK                    0xc9
  64
  65 #define SYNC_WAVE 0
  66 #define NULL_WAVE (-1)
  67
  68 #define DC_GEN_SYNC_1_6_SYNC    (2 << 1)
  69 #define DC_GEN_SYNC_PRIORITY_1  (1 << 7)
  70
  71 #define DC_WR_CH_CONF_WORD_SIZE_8               (0 << 0)
  72 #define DC_WR_CH_CONF_WORD_SIZE_16              (1 << 0)
  73 #define DC_WR_CH_CONF_WORD_SIZE_24              (2 << 0)
  74 #define DC_WR_CH_CONF_WORD_SIZE_32              (3 << 0)
  75 #define DC_WR_CH_CONF_DISP_ID_PARALLEL(i)       (((i) & 0x1) << 3)
  76 #define DC_WR_CH_CONF_DISP_ID_SERIAL            (2 << 3)
  77 #define DC_WR_CH_CONF_DISP_ID_ASYNC             (3 << 4)
  78 #define DC_WR_CH_CONF_FIELD_MODE                (1 << 9)
  79 #define DC_WR_CH_CONF_PROG_TYPE_NORMAL          (4 << 5)
  80 #define DC_WR_CH_CONF_PROG_TYPE_MASK            (7 << 5)
  81 #define DC_WR_CH_CONF_PROG_DI_ID                (1 << 2)
  82 #define DC_WR_CH_CONF_PROG_DISP_ID(i)           (((i) & 0x1) << 3)
  83
  84 #define IPU_DC_NUM_CHANNELS     10
  85
  86 struct ipu_dc_priv;
  87
  88 enum ipu_dc_map {
  89         IPU_DC_MAP_RGB24,
  90         IPU_DC_MAP_RGB565,
  91         IPU_DC_MAP_GBR24, /* TVEv2 */
  92         IPU_DC_MAP_BGR666,
  93         IPU_DC_MAP_BGR24,
  94 };
  95
  96 struct ipu_dc {
  97         /* The display interface number assigned to this dc channel */
  98         unsigned int            di;
  99         void __iomem            *base;
 100         struct ipu_dc_priv      *priv;
 101         int                     chno;
 102         bool                    in_use;
 103 };
 104
 105 struct ipu_dc_priv {
 106         void __iomem            *dc_reg;
 107         void __iomem            *dc_tmpl_reg;
 108         struct ipu_soc          *ipu;
 109         struct device           *dev;
 110         struct ipu_dc           channels[IPU_DC_NUM_CHANNELS];
 111         struct mutex            mutex;
 112 };
 113
 114 static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
 115 {
 116         u32 reg;
 117
 118         reg = readl(dc->base + DC_RL_CH(event));
 119         reg &= ~(0xffff << (16 * (event & 0x1)));
 120         reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
 121         writel(reg, dc->base + DC_RL_CH(event));
 122 }
 123
 124 static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
 125                 int map, int wave, int glue, int sync, int stop)
 126 {
 127         struct ipu_dc_priv *priv = dc->priv;
 128         u32 reg1, reg2;
 129
 130         if (opcode == WCLK) {
 131                 reg1 = (operand << 20) & 0xfff00000;
 132                 reg2 = operand >> 12 | opcode << 1 | stop << 9;
 133         } else if (opcode == WRG) {
 134                 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);
 135                 reg2 = operand >> 17 | opcode << 7 | stop << 9;
 136         } else {
 137                 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
 138                 reg2 = operand >> 12 | opcode << 4 | stop << 9;
 139         }
 140         writel(reg1, priv->dc_tmpl_reg + word * 8);
 141         writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
 142 }
 143
 144 static int ipu_pixfmt_to_map(u32 fmt)
 145 {
 146         switch (fmt) {
 147         case V4L2_PIX_FMT_RGB24:
 148                 return IPU_DC_MAP_RGB24;
 149         case V4L2_PIX_FMT_RGB565:
 150                 return IPU_DC_MAP_RGB565;
 151         case IPU_PIX_FMT_GBR24:
 152                 return IPU_DC_MAP_GBR24;
 153         case V4L2_PIX_FMT_BGR666:
 154                 return IPU_DC_MAP_BGR666;
 155         case V4L2_PIX_FMT_BGR24:
 156                 return IPU_DC_MAP_BGR24;
 157         default:
 158                 return -EINVAL;
 159         }
 160 }
 161
 162 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
 163                 u32 pixel_fmt, u32 width)
 164 {
 165         struct ipu_dc_priv *priv = dc->priv;
 166         u32 reg = 0;
 167         int map;
 168
 169         dc->di = ipu_di_get_num(di);
 170
 171         map = ipu_pixfmt_to_map(pixel_fmt);
 172         if (map < 0) {
 173                 dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
 174                 return map;
 175         }
 176
 177         if (interlaced) {
 178                 dc_link_event(dc, DC_EVT_NL, 0, 3);
 179                 dc_link_event(dc, DC_EVT_EOL, 0, 2);
 180                 dc_link_event(dc, DC_EVT_NEW_DATA, 0, 1);
 181
 182                 /* Init template microcode */
 183                 dc_write_tmpl(dc, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);
 184         } else {
 185                 if (dc->di) {
 186                         dc_link_event(dc, DC_EVT_NL, 2, 3);
 187                         dc_link_event(dc, DC_EVT_EOL, 3, 2);
 188                         dc_link_event(dc, DC_EVT_NEW_DATA, 1, 1);
 189                         /* Init template microcode */
 190                         dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
 191                         dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
 192                         dc_write_tmpl(dc, 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
 193                         dc_write_tmpl(dc, 1, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
 194                 } else {
 195                         dc_link_event(dc, DC_EVT_NL, 5, 3);
 196                         dc_link_event(dc, DC_EVT_EOL, 6, 2);
 197                         dc_link_event(dc, DC_EVT_NEW_DATA, 8, 1);
 198                         /* Init template microcode */
 199                         dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
 200                         dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
 201                         dc_write_tmpl(dc, 7, WRG, 0, map, NULL_WAVE, 0, 0, 1);
 202                         dc_write_tmpl(dc, 8, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
 203                 }
 204         }
 205         dc_link_event(dc, DC_EVT_NF, 0, 0);
 206         dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
 207         dc_link_event(dc, DC_EVT_EOF, 0, 0);
 208         dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
 209         dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
 210         dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
 211
 212         reg = readl(dc->base + DC_WR_CH_CONF);
 213         if (interlaced)
 214                 reg |= DC_WR_CH_CONF_FIELD_MODE;
 215         else
 216                 reg &= ~DC_WR_CH_CONF_FIELD_MODE;
 217         writel(reg, dc->base + DC_WR_CH_CONF);
 218
 219         writel(0x0, dc->base + DC_WR_CH_ADDR);
 220         writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
 221
 222         ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
 223
 224         return 0;
 225 }
 226 EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
 227
 228 void ipu_dc_enable_channel(struct ipu_dc *dc)
 229 {
 230         int di;
 231         u32 reg;
 232
 233         di = dc->di;
 234
 235         reg = readl(dc->base + DC_WR_CH_CONF);
 236         reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
 237         writel(reg, dc->base + DC_WR_CH_CONF);
 238 }
 239 EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
 240
 241 void ipu_dc_disable_channel(struct ipu_dc *dc)
 242 {
 243         struct ipu_dc_priv *priv = dc->priv;
 244         u32 val;
 245         int irq = 0, timeout = 50;
 246
 247         if (dc->chno == 1)
 248                 irq = IPU_IRQ_DC_FC_1;
 249         else if (dc->chno == 5)
 250                 irq = IPU_IRQ_DP_SF_END;
 251         else
 252                 return;
 253
 254         /* should wait for the interrupt here */
 255         mdelay(50);
 256
 257         if (dc->di == 0)
 258                 val = 0x00000002;
 259         else
 260                 val = 0x00000020;
 261
 262         /* Wait for DC triple buffer to empty */
 263         while ((readl(priv->dc_reg + DC_STAT) & val) != val) {
 264                 usleep_range(2000, 20000);
 265                 timeout -= 2;
 266                 if (timeout <= 0)
 267                         break;
 268         }
 269
 270         val = readl(dc->base + DC_WR_CH_CONF);
 271         val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 272         writel(val, dc->base + DC_WR_CH_CONF);
 273 }
 274 EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
 275
 276 static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
 277                 int byte_num, int offset, int mask)
 278 {
 279         int ptr = map * 3 + byte_num;
 280         u32 reg;
 281
 282         reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
 283         reg &= ~(0xffff << (16 * (ptr & 0x1)));
 284         reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
 285         writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
 286
 287         reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
 288         reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
 289         reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
 290         writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
 291 }
 292
 293 static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
 294 {
 295         u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
 296
 297         writel(reg & ~(0xffff << (16 * (map & 0x1))),
 298                      priv->dc_reg + DC_MAP_CONF_PTR(map));
 299 }
 300
 301 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
 302 {
 303         struct ipu_dc_priv *priv = ipu->dc_priv;
 304         struct ipu_dc *dc;
 305
 306         if (channel >= IPU_DC_NUM_CHANNELS)
 307                 return ERR_PTR(-ENODEV);
 308
 309         dc = &priv->channels[channel];
 310
 311         mutex_lock(&priv->mutex);
 312
 313         if (dc->in_use) {
 314                 mutex_unlock(&priv->mutex);
 315                 return ERR_PTR(-EBUSY);
 316         }
 317
 318         dc->in_use = true;
 319
 320         mutex_unlock(&priv->mutex);
 321
 322         return dc;
 323 }
 324 EXPORT_SYMBOL_GPL(ipu_dc_get);
 325
 326 void ipu_dc_put(struct ipu_dc *dc)
 327 {
 328         struct ipu_dc_priv *priv = dc->priv;
 329
 330         mutex_lock(&priv->mutex);
 331         dc->in_use = false;
 332         mutex_unlock(&priv->mutex);
 333 }
 334 EXPORT_SYMBOL_GPL(ipu_dc_put);
 335
 336 int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
 337                 unsigned long base, unsigned long template_base)
 338 {
 339         struct ipu_dc_priv *priv;
 340         static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
 341                 0x78, 0, 0x94, 0xb4};
 342         int i;
 343
 344         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 345         if (!priv)
 346                 return -ENOMEM;
 347
 348         mutex_init(&priv->mutex);
 349
 350         priv->dev = dev;
 351         priv->ipu = ipu;
 352         priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
 353         priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
 354         if (!priv->dc_reg || !priv->dc_tmpl_reg)
 355                 return -ENOMEM;
 356
 357         for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
 358                 priv->channels[i].chno = i;
 359                 priv->channels[i].priv = priv;
 360                 priv->channels[i].base = priv->dc_reg + channel_offsets[i];
 361         }
 362
 363         writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
 364                         DC_WR_CH_CONF_PROG_DI_ID,
 365                         priv->channels[1].base + DC_WR_CH_CONF);
 366         writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
 367                         priv->channels[5].base + DC_WR_CH_CONF);
 368
 369         writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1, priv->dc_reg + DC_GEN);
 370
 371         ipu->dc_priv = priv;
 372
 373         dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
 374                         base, template_base);
 375
 376         /* rgb24 */
 377         ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
 378         ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
 379         ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
 380         ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
 381
 382         /* rgb565 */
 383         ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
 384         ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
 385         ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
 386         ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
 387
 388         /* gbr24 */
 389         ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
 390         ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
 391         ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
 392         ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */
 393
 394         /* bgr666 */
 395         ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
 396         ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
 397         ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
 398         ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
 399
 400         /* bgr24 */
 401         ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
 402         ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */
 403         ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
 404         ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */
 405
 406         return 0;
 407 }
 408
 409 void ipu_dc_exit(struct ipu_soc *ipu)
 410 {
 411 }