drivers/hid/intel-ish-hid/ipc/hw-ish-regs.h

   1 /*
   2  * ISH registers definitions
   3  *
   4  * Copyright (c) 2012-2016, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #ifndef _ISHTP_ISH_REGS_H_
  17 #define _ISHTP_ISH_REGS_H_
  18
  19
  20 /*** IPC PCI Offsets and sizes ***/
  21 /* ISH IPC Base Address */
  22 #define IPC_REG_BASE            0x0000
  23 /* Peripheral Interrupt Status Register */
  24 #define IPC_REG_PISR_CHV_AB      (IPC_REG_BASE + 0x00)
  25 /* Peripheral Interrupt Mask Register */
  26 #define IPC_REG_PIMR_CHV_AB      (IPC_REG_BASE + 0x04)
  27 /*BXT, CHV_K0*/
  28 /*Peripheral Interrupt Status Register */
  29 #define IPC_REG_PISR_BXT         (IPC_REG_BASE + 0x0C)
  30 /*Peripheral Interrupt Mask Register */
  31 #define IPC_REG_PIMR_BXT         (IPC_REG_BASE + 0x08)
  32 /***********************************/
  33 /* ISH Host Firmware status Register */
  34 #define IPC_REG_ISH_HOST_FWSTS  (IPC_REG_BASE + 0x34)
  35 /* Host Communication Register */
  36 #define IPC_REG_HOST_COMM       (IPC_REG_BASE + 0x38)
  37 /* Reset register */
  38 #define IPC_REG_ISH_RST         (IPC_REG_BASE + 0x44)
  39
  40 /* Inbound doorbell register Host to ISH */
  41 #define IPC_REG_HOST2ISH_DRBL   (IPC_REG_BASE + 0x48)
  42 /* Outbound doorbell register ISH to Host */
  43 #define IPC_REG_ISH2HOST_DRBL   (IPC_REG_BASE + 0x54)
  44 /* ISH to HOST message registers */
  45 #define IPC_REG_ISH2HOST_MSG    (IPC_REG_BASE + 0x60)
  46 /* HOST to ISH message registers */
  47 #define IPC_REG_HOST2ISH_MSG    (IPC_REG_BASE + 0xE0)
  48 /* REMAP2 to enable DMA (D3 RCR) */
  49 #define IPC_REG_ISH_RMP2        (IPC_REG_BASE + 0x368)
  50
  51 #define IPC_REG_MAX             (IPC_REG_BASE + 0x400)
  52
  53 /*** register bits - HISR ***/
  54 /* bit corresponds HOST2ISH interrupt in PISR and PIMR registers */
  55 #define IPC_INT_HOST2ISH_BIT            (1<<0)
  56 /***********************************/
  57 /*CHV_A0, CHV_B0*/
  58 /* bit corresponds ISH2HOST interrupt in PISR and PIMR registers */
  59 #define IPC_INT_ISH2HOST_BIT_CHV_AB     (1<<3)
  60 /*BXT, CHV_K0*/
  61 /* bit corresponds ISH2HOST interrupt in PISR and PIMR registers */
  62 #define IPC_INT_ISH2HOST_BIT_BXT        (1<<0)
  63 /***********************************/
  64
  65 /* bit corresponds ISH2HOST busy clear interrupt in PIMR register */
  66 #define IPC_INT_ISH2HOST_CLR_MASK_BIT   (1<<11)
  67
  68 /* offset of ISH2HOST busy clear interrupt in IPC_BUSY_CLR register */
  69 #define IPC_INT_ISH2HOST_CLR_OFFS       (0)
  70
  71 /* bit corresponds ISH2HOST busy clear interrupt in IPC_BUSY_CLR register */
  72 #define IPC_INT_ISH2HOST_CLR_BIT        (1<<IPC_INT_ISH2HOST_CLR_OFFS)
  73
  74 /* bit corresponds busy bit in doorbell registers */
  75 #define IPC_DRBL_BUSY_OFFS              (31)
  76 #define IPC_DRBL_BUSY_BIT               (1<<IPC_DRBL_BUSY_OFFS)
  77
  78 #define IPC_HOST_OWNS_MSG_OFFS          (30)
  79
  80 /*
  81  * A0: bit means that host owns MSGnn registers and is reading them.
  82  * ISH FW may not write to them
  83  */
  84 #define IPC_HOST_OWNS_MSG_BIT           (1<<IPC_HOST_OWNS_MSG_OFFS)
  85
  86 /*
  87  * Host status bits (HOSTCOMM)
  88  */
  89 /* bit corresponds host ready bit in Host Status Register (HOST_COMM) */
  90 #define IPC_HOSTCOMM_READY_OFFS         (7)
  91 #define IPC_HOSTCOMM_READY_BIT          (1<<IPC_HOSTCOMM_READY_OFFS)
  92
  93 /***********************************/
  94 /*CHV_A0, CHV_B0*/
  95 #define IPC_HOSTCOMM_INT_EN_OFFS_CHV_AB (31)
  96 #define IPC_HOSTCOMM_INT_EN_BIT_CHV_AB          \
  97         (1<<IPC_HOSTCOMM_INT_EN_OFFS_CHV_AB)
  98 /*BXT, CHV_K0*/
  99 #define IPC_PIMR_INT_EN_OFFS_BXT        (0)
 100 #define IPC_PIMR_INT_EN_BIT_BXT         (1<<IPC_PIMR_INT_EN_OFFS_BXT)
 101
 102 #define IPC_HOST2ISH_BUSYCLEAR_MASK_OFFS_BXT    (8)
 103 #define IPC_HOST2ISH_BUSYCLEAR_MASK_BIT         \
 104         (1<<IPC_HOST2ISH_BUSYCLEAR_MASK_OFFS_BXT)
 105 /***********************************/
 106 /*
 107  * both Host and ISH have ILUP at bit 0
 108  * bit corresponds host ready bit in both status registers
 109  */
 110 #define IPC_ILUP_OFFS                   (0)
 111 #define IPC_ILUP_BIT                    (1<<IPC_ILUP_OFFS)
 112
 113 /*
 114  * FW status bits (relevant)
 115  */
 116 #define IPC_FWSTS_ILUP          0x1
 117 #define IPC_FWSTS_ISHTP_UP      (1<<1)
 118 #define IPC_FWSTS_DMA0          (1<<16)
 119 #define IPC_FWSTS_DMA1          (1<<17)
 120 #define IPC_FWSTS_DMA2          (1<<18)
 121 #define IPC_FWSTS_DMA3          (1<<19)
 122
 123 #define IPC_ISH_IN_DMA          \
 124         (IPC_FWSTS_DMA0 | IPC_FWSTS_DMA1 | IPC_FWSTS_DMA2 | IPC_FWSTS_DMA3)
 125
 126 /* bit corresponds host ready bit in ISH FW Status Register */
 127 #define IPC_ISH_ISHTP_READY_OFFS                (1)
 128 #define IPC_ISH_ISHTP_READY_BIT         (1<<IPC_ISH_ISHTP_READY_OFFS)
 129
 130 #define IPC_RMP2_DMA_ENABLED    0x1     /* Value to enable DMA, per D3 RCR */
 131
 132 #define IPC_MSG_MAX_SIZE        0x80
 133
 134
 135 #define IPC_HEADER_LENGTH_MASK          0x03FF
 136 #define IPC_HEADER_PROTOCOL_MASK        0x0F
 137 #define IPC_HEADER_MNG_CMD_MASK         0x0F
 138
 139 #define IPC_HEADER_LENGTH_OFFSET        0
 140 #define IPC_HEADER_PROTOCOL_OFFSET      10
 141 #define IPC_HEADER_MNG_CMD_OFFSET       16
 142
 143 #define IPC_HEADER_GET_LENGTH(drbl_reg)         \
 144         (((drbl_reg) >> IPC_HEADER_LENGTH_OFFSET)&IPC_HEADER_LENGTH_MASK)
 145 #define IPC_HEADER_GET_PROTOCOL(drbl_reg)       \
 146         (((drbl_reg) >> IPC_HEADER_PROTOCOL_OFFSET)&IPC_HEADER_PROTOCOL_MASK)
 147 #define IPC_HEADER_GET_MNG_CMD(drbl_reg)        \
 148         (((drbl_reg) >> IPC_HEADER_MNG_CMD_OFFSET)&IPC_HEADER_MNG_CMD_MASK)
 149
 150 #define IPC_IS_BUSY(drbl_reg)                   \
 151         (((drbl_reg)&IPC_DRBL_BUSY_BIT) == ((uint32_t)IPC_DRBL_BUSY_BIT))
 152
 153 /***********************************/
 154 /*CHV_A0, CHV_B0*/
 155 #define IPC_INT_FROM_ISH_TO_HOST_CHV_AB(drbl_reg) \
 156         (((drbl_reg)&IPC_INT_ISH2HOST_BIT_CHV_AB) == \
 157         ((u32)IPC_INT_ISH2HOST_BIT_CHV_AB))
 158 /*BXT, CHV_K0*/
 159 #define IPC_INT_FROM_ISH_TO_HOST_BXT(drbl_reg) \
 160         (((drbl_reg)&IPC_INT_ISH2HOST_BIT_BXT) == \
 161         ((u32)IPC_INT_ISH2HOST_BIT_BXT))
 162 /***********************************/
 163
 164 #define IPC_BUILD_HEADER(length, protocol, busy)                \
 165         (((busy)<<IPC_DRBL_BUSY_OFFS) |                         \
 166         ((protocol) << IPC_HEADER_PROTOCOL_OFFSET) |            \
 167         ((length)<<IPC_HEADER_LENGTH_OFFSET))
 168
 169 #define IPC_BUILD_MNG_MSG(cmd, length)                          \
 170         (((1)<<IPC_DRBL_BUSY_OFFS)|                             \
 171         ((IPC_PROTOCOL_MNG)<<IPC_HEADER_PROTOCOL_OFFSET)|       \
 172         ((cmd)<<IPC_HEADER_MNG_CMD_OFFSET)|                     \
 173          ((length)<<IPC_HEADER_LENGTH_OFFSET))
 174
 175
 176 #define IPC_SET_HOST_READY(host_status)         \
 177                                 ((host_status) |= (IPC_HOSTCOMM_READY_BIT))
 178
 179 #define IPC_SET_HOST_ILUP(host_status)          \
 180                                 ((host_status) |= (IPC_ILUP_BIT))
 181
 182 #define IPC_CLEAR_HOST_READY(host_status)       \
 183                                 ((host_status) ^= (IPC_HOSTCOMM_READY_BIT))
 184
 185 #define IPC_CLEAR_HOST_ILUP(host_status)        \
 186                                 ((host_status) ^= (IPC_ILUP_BIT))
 187
 188 /* todo - temp until PIMR HW ready */
 189 #define IPC_HOST_BUSY_READING_OFFS      6
 190
 191 /* bit corresponds host ready bit in Host Status Register (HOST_COMM) */
 192 #define IPC_HOST_BUSY_READING_BIT       (1<<IPC_HOST_BUSY_READING_OFFS)
 193
 194 #define IPC_SET_HOST_BUSY_READING(host_status)  \
 195                                 ((host_status) |= (IPC_HOST_BUSY_READING_BIT))
 196
 197 #define IPC_CLEAR_HOST_BUSY_READING(host_status)\
 198                                 ((host_status) ^= (IPC_HOST_BUSY_READING_BIT))
 199
 200
 201 #define IPC_IS_ISH_ISHTP_READY(ish_status)      \
 202                 (((ish_status) & IPC_ISH_ISHTP_READY_BIT) ==    \
 203                         ((uint32_t)IPC_ISH_ISHTP_READY_BIT))
 204
 205 #define IPC_IS_ISH_ILUP(ish_status)             \
 206                 (((ish_status) & IPC_ILUP_BIT) == ((uint32_t)IPC_ILUP_BIT))
 207
 208
 209 #define IPC_PROTOCOL_ISHTP              1
 210 #define IPC_PROTOCOL_MNG                3
 211
 212 #define MNG_RX_CMPL_ENABLE              0
 213 #define MNG_RX_CMPL_DISABLE             1
 214 #define MNG_RX_CMPL_INDICATION          2
 215 #define MNG_RESET_NOTIFY                3
 216 #define MNG_RESET_NOTIFY_ACK            4
 217 #define MNG_SYNC_FW_CLOCK               5
 218 #define MNG_ILLEGAL_CMD                 0xFF
 219
 220 #endif /* _ISHTP_ISH_REGS_H_ */