drivers/hwmon/k10temp.c

   1 /*
   2  * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
   3  *
   4  * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
   5  *
   6  *
   7  * This driver is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This driver is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  14  * See the GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this driver; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/err.h>
  21 #include <linux/hwmon.h>
  22 #include <linux/hwmon-sysfs.h>
  23 #include <linux/init.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <asm/amd_nb.h>
  27 #include <asm/processor.h>
  28
  29 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
  30 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  31 MODULE_LICENSE("GPL");
  32
  33 static bool force;
  34 module_param(force, bool, 0444);
  35 MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
  36
  37 /* Provide lock for writing to NB_SMU_IND_ADDR */
  38 static DEFINE_MUTEX(nb_smu_ind_mutex);
  39
  40 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
  41 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3        0x15b3
  42 #endif
  43
  44 #ifndef PCI_DEVICE_ID_AMD_17H_DF_F3
  45 #define PCI_DEVICE_ID_AMD_17H_DF_F3     0x1463
  46 #endif
  47
  48 #ifndef PCI_DEVICE_ID_AMD_17H_M10H_DF_F3
  49 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3        0x15eb
  50 #endif
  51
  52 /* CPUID function 0x80000001, ebx */
  53 #define CPUID_PKGTYPE_MASK      0xf0000000
  54 #define CPUID_PKGTYPE_F         0x00000000
  55 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
  56
  57 /* DRAM controller (PCI function 2) */
  58 #define REG_DCT0_CONFIG_HIGH            0x094
  59 #define  DDR3_MODE                      0x00000100
  60
  61 /* miscellaneous (PCI function 3) */
  62 #define REG_HARDWARE_THERMAL_CONTROL    0x64
  63 #define  HTC_ENABLE                     0x00000001
  64
  65 #define REG_REPORTED_TEMPERATURE        0xa4
  66
  67 #define REG_NORTHBRIDGE_CAPABILITIES    0xe8
  68 #define  NB_CAP_HTC                     0x00000400
  69
  70 /*
  71  * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
  72  * and REG_REPORTED_TEMPERATURE have been moved to
  73  * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
  74  * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
  75  */
  76 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET     0xd8200c64
  77 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET     0xd8200ca4
  78
  79 /* F17h M01h Access througn SMN */
  80 #define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET     0x00059800
  81
  82 struct k10temp_data {
  83         struct pci_dev *pdev;
  84         void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
  85         void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
  86         int temp_offset;
  87         u32 temp_adjust_mask;
  88 };
  89
  90 struct tctl_offset {
  91         u8 model;
  92         char const *id;
  93         int offset;
  94 };
  95
  96 static const struct tctl_offset tctl_offset_table[] = {
  97         { 0x17, "AMD Ryzen 5 1600X", 20000 },
  98         { 0x17, "AMD Ryzen 7 1700X", 20000 },
  99         { 0x17, "AMD Ryzen 7 1800X", 20000 },
 100         { 0x17, "AMD Ryzen 7 2700X", 10000 },
 101         { 0x17, "AMD Ryzen Threadripper 1950X", 27000 },
 102         { 0x17, "AMD Ryzen Threadripper 1920X", 27000 },
 103         { 0x17, "AMD Ryzen Threadripper 1900X", 27000 },
 104         { 0x17, "AMD Ryzen Threadripper 1950", 10000 },
 105         { 0x17, "AMD Ryzen Threadripper 1920", 10000 },
 106         { 0x17, "AMD Ryzen Threadripper 1910", 10000 },
 107 };
 108
 109 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
 110 {
 111         pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
 112 }
 113
 114 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
 115 {
 116         pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
 117 }
 118
 119 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
 120                               unsigned int base, int offset, u32 *val)
 121 {
 122         mutex_lock(&nb_smu_ind_mutex);
 123         pci_bus_write_config_dword(pdev->bus, devfn,
 124                                    base, offset);
 125         pci_bus_read_config_dword(pdev->bus, devfn,
 126                                   base + 4, val);
 127         mutex_unlock(&nb_smu_ind_mutex);
 128 }
 129
 130 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
 131 {
 132         amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
 133                           F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
 134 }
 135
 136 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
 137 {
 138         amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
 139                           F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
 140 }
 141
 142 static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
 143 {
 144         amd_smn_read(amd_pci_dev_to_node_id(pdev),
 145                      F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
 146 }
 147
 148 static ssize_t temp1_input_show(struct device *dev,
 149                                 struct device_attribute *attr, char *buf)
 150 {
 151         struct k10temp_data *data = dev_get_drvdata(dev);
 152         u32 regval;
 153         unsigned int temp;
 154
 155         data->read_tempreg(data->pdev, &regval);
 156         temp = (regval >> 21) * 125;
 157         if (regval & data->temp_adjust_mask)
 158                 temp -= 49000;
 159         if (temp > data->temp_offset)
 160                 temp -= data->temp_offset;
 161         else
 162                 temp = 0;
 163
 164         return sprintf(buf, "%u\n", temp);
 165 }
 166
 167 static ssize_t temp1_max_show(struct device *dev,
 168                               struct device_attribute *attr, char *buf)
 169 {
 170         return sprintf(buf, "%d\n", 70 * 1000);
 171 }
 172
 173 static ssize_t show_temp_crit(struct device *dev,
 174                               struct device_attribute *devattr, char *buf)
 175 {
 176         struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
 177         struct k10temp_data *data = dev_get_drvdata(dev);
 178         int show_hyst = attr->index;
 179         u32 regval;
 180         int value;
 181
 182         data->read_htcreg(data->pdev, &regval);
 183         value = ((regval >> 16) & 0x7f) * 500 + 52000;
 184         if (show_hyst)
 185                 value -= ((regval >> 24) & 0xf) * 500;
 186         return sprintf(buf, "%d\n", value);
 187 }
 188
 189 static DEVICE_ATTR_RO(temp1_input);
 190 static DEVICE_ATTR_RO(temp1_max);
 191 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
 192 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);
 193
 194 static umode_t k10temp_is_visible(struct kobject *kobj,
 195                                   struct attribute *attr, int index)
 196 {
 197         struct device *dev = container_of(kobj, struct device, kobj);
 198         struct k10temp_data *data = dev_get_drvdata(dev);
 199         struct pci_dev *pdev = data->pdev;
 200
 201         if (index >= 2) {
 202                 u32 reg;
 203
 204                 if (!data->read_htcreg)
 205                         return 0;
 206
 207                 pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
 208                                       &reg);
 209                 if (!(reg & NB_CAP_HTC))
 210                         return 0;
 211
 212                 data->read_htcreg(data->pdev, &reg);
 213                 if (!(reg & HTC_ENABLE))
 214                         return 0;
 215         }
 216         return attr->mode;
 217 }
 218
 219 static struct attribute *k10temp_attrs[] = {
 220         &dev_attr_temp1_input.attr,
 221         &dev_attr_temp1_max.attr,
 222         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 223         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 224         NULL
 225 };
 226
 227 static const struct attribute_group k10temp_group = {
 228         .attrs = k10temp_attrs,
 229         .is_visible = k10temp_is_visible,
 230 };
 231 __ATTRIBUTE_GROUPS(k10temp);
 232
 233 static bool has_erratum_319(struct pci_dev *pdev)
 234 {
 235         u32 pkg_type, reg_dram_cfg;
 236
 237         if (boot_cpu_data.x86 != 0x10)
 238                 return false;
 239
 240         /*
 241          * Erratum 319: The thermal sensor of Socket F/AM2+ processors
 242          *              may be unreliable.
 243          */
 244         pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
 245         if (pkg_type == CPUID_PKGTYPE_F)
 246                 return true;
 247         if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
 248                 return false;
 249
 250         /* DDR3 memory implies socket AM3, which is good */
 251         pci_bus_read_config_dword(pdev->bus,
 252                                   PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
 253                                   REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
 254         if (reg_dram_cfg & DDR3_MODE)
 255                 return false;
 256
 257         /*
 258          * Unfortunately it is possible to run a socket AM3 CPU with DDR2
 259          * memory. We blacklist all the cores which do exist in socket AM2+
 260          * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
 261          * and AM3 formats, but that's the best we can do.
 262          */
 263         return boot_cpu_data.x86_model < 4 ||
 264                (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
 265 }
 266
 267 static int k10temp_probe(struct pci_dev *pdev,
 268                                    const struct pci_device_id *id)
 269 {
 270         int unreliable = has_erratum_319(pdev);
 271         struct device *dev = &pdev->dev;
 272         struct k10temp_data *data;
 273         struct device *hwmon_dev;
 274         int i;
 275
 276         if (unreliable) {
 277                 if (!force) {
 278                         dev_err(dev,
 279                                 "unreliable CPU thermal sensor; monitoring disabled\n");
 280                         return -ENODEV;
 281                 }
 282                 dev_warn(dev,
 283                          "unreliable CPU thermal sensor; check erratum 319\n");
 284         }
 285
 286         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 287         if (!data)
 288                 return -ENOMEM;
 289
 290         data->pdev = pdev;
 291
 292         if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 ||
 293                                           boot_cpu_data.x86_model == 0x70)) {
 294                 data->read_htcreg = read_htcreg_nb_f15;
 295                 data->read_tempreg = read_tempreg_nb_f15;
 296         } else if (boot_cpu_data.x86 == 0x17) {
 297                 data->temp_adjust_mask = 0x80000;
 298                 data->read_tempreg = read_tempreg_nb_f17;
 299         } else {
 300                 data->read_htcreg = read_htcreg_pci;
 301                 data->read_tempreg = read_tempreg_pci;
 302         }
 303
 304         for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
 305                 const struct tctl_offset *entry = &tctl_offset_table[i];
 306
 307                 if (boot_cpu_data.x86 == entry->model &&
 308                     strstr(boot_cpu_data.x86_model_id, entry->id)) {
 309                         data->temp_offset = entry->offset;
 310                         break;
 311                 }
 312         }
 313
 314         hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data,
 315                                                            k10temp_groups);
 316         return PTR_ERR_OR_ZERO(hwmon_dev);
 317 }
 318
 319 static const struct pci_device_id k10temp_id_table[] = {
 320         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
 321         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
 322         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
 323         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
 324         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
 325         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
 326         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
 327         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
 328         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
 329         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
 330         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
 331         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
 332         {}
 333 };
 334 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
 335
 336 static struct pci_driver k10temp_driver = {
 337         .name = "k10temp",
 338         .id_table = k10temp_id_table,
 339         .probe = k10temp_probe,
 340 };
 341
 342 module_pci_driver(k10temp_driver);