drivers/hwmon/k10temp.c

   1 /*
   2  * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
   3  *
   4  * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
   5  *
   6  *
   7  * This driver is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This driver is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  14  * See the GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this driver; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/err.h>
  21 #include <linux/hwmon.h>
  22 #include <linux/hwmon-sysfs.h>
  23 #include <linux/init.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <asm/processor.h>
  27
  28 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
  29 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  30 MODULE_LICENSE("GPL");
  31
  32 static bool force;
  33 module_param(force, bool, 0444);
  34 MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
  35
  36 /* Provide lock for writing to NB_SMU_IND_ADDR */
  37 static DEFINE_MUTEX(nb_smu_ind_mutex);
  38
  39 /* CPUID function 0x80000001, ebx */
  40 #define CPUID_PKGTYPE_MASK      0xf0000000
  41 #define CPUID_PKGTYPE_F         0x00000000
  42 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
  43
  44 /* DRAM controller (PCI function 2) */
  45 #define REG_DCT0_CONFIG_HIGH            0x094
  46 #define  DDR3_MODE                      0x00000100
  47
  48 /* miscellaneous (PCI function 3) */
  49 #define REG_HARDWARE_THERMAL_CONTROL    0x64
  50 #define  HTC_ENABLE                     0x00000001
  51
  52 #define REG_REPORTED_TEMPERATURE        0xa4
  53
  54 #define REG_NORTHBRIDGE_CAPABILITIES    0xe8
  55 #define  NB_CAP_HTC                     0x00000400
  56
  57 /*
  58  * For F15h M60h, functionality of REG_REPORTED_TEMPERATURE
  59  * has been moved to D0F0xBC_xD820_0CA4 [Reported Temperature
  60  * Control]
  61  */
  62 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET     0xd8200ca4
  63
  64 static void amd_nb_smu_index_read(struct pci_dev *pdev, unsigned int devfn,
  65                                   int offset, u32 *val)
  66 {
  67         mutex_lock(&nb_smu_ind_mutex);
  68         pci_bus_write_config_dword(pdev->bus, devfn,
  69                                    0xb8, offset);
  70         pci_bus_read_config_dword(pdev->bus, devfn,
  71                                   0xbc, val);
  72         mutex_unlock(&nb_smu_ind_mutex);
  73 }
  74
  75 static ssize_t temp1_input_show(struct device *dev,
  76                                 struct device_attribute *attr, char *buf)
  77 {
  78         u32 regval;
  79         struct pci_dev *pdev = dev_get_drvdata(dev);
  80
  81         if (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model == 0x60) {
  82                 amd_nb_smu_index_read(pdev, PCI_DEVFN(0, 0),
  83                                       F15H_M60H_REPORTED_TEMP_CTRL_OFFSET,
  84                                       &regval);
  85         } else {
  86                 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, &regval);
  87         }
  88         return sprintf(buf, "%u\n", (regval >> 21) * 125);
  89 }
  90
  91 static ssize_t temp1_max_show(struct device *dev,
  92                               struct device_attribute *attr, char *buf)
  93 {
  94         return sprintf(buf, "%d\n", 70 * 1000);
  95 }
  96
  97 static ssize_t show_temp_crit(struct device *dev,
  98                               struct device_attribute *devattr, char *buf)
  99 {
 100         struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
 101         int show_hyst = attr->index;
 102         u32 regval;
 103         int value;
 104
 105         pci_read_config_dword(dev_get_drvdata(dev),
 106                               REG_HARDWARE_THERMAL_CONTROL, &regval);
 107         value = ((regval >> 16) & 0x7f) * 500 + 52000;
 108         if (show_hyst)
 109                 value -= ((regval >> 24) & 0xf) * 500;
 110         return sprintf(buf, "%d\n", value);
 111 }
 112
 113 static DEVICE_ATTR_RO(temp1_input);
 114 static DEVICE_ATTR_RO(temp1_max);
 115 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
 116 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);
 117
 118 static umode_t k10temp_is_visible(struct kobject *kobj,
 119                                   struct attribute *attr, int index)
 120 {
 121         struct device *dev = container_of(kobj, struct device, kobj);
 122         struct pci_dev *pdev = dev_get_drvdata(dev);
 123
 124         if (index >= 2) {
 125                 u32 reg_caps, reg_htc;
 126
 127                 pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
 128                                       &reg_caps);
 129                 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL,
 130                                       &reg_htc);
 131                 if (!(reg_caps & NB_CAP_HTC) || !(reg_htc & HTC_ENABLE))
 132                         return 0;
 133         }
 134         return attr->mode;
 135 }
 136
 137 static struct attribute *k10temp_attrs[] = {
 138         &dev_attr_temp1_input.attr,
 139         &dev_attr_temp1_max.attr,
 140         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 141         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 142         NULL
 143 };
 144
 145 static const struct attribute_group k10temp_group = {
 146         .attrs = k10temp_attrs,
 147         .is_visible = k10temp_is_visible,
 148 };
 149 __ATTRIBUTE_GROUPS(k10temp);
 150
 151 static bool has_erratum_319(struct pci_dev *pdev)
 152 {
 153         u32 pkg_type, reg_dram_cfg;
 154
 155         if (boot_cpu_data.x86 != 0x10)
 156                 return false;
 157
 158         /*
 159          * Erratum 319: The thermal sensor of Socket F/AM2+ processors
 160          *              may be unreliable.
 161          */
 162         pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
 163         if (pkg_type == CPUID_PKGTYPE_F)
 164                 return true;
 165         if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
 166                 return false;
 167
 168         /* DDR3 memory implies socket AM3, which is good */
 169         pci_bus_read_config_dword(pdev->bus,
 170                                   PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
 171                                   REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
 172         if (reg_dram_cfg & DDR3_MODE)
 173                 return false;
 174
 175         /*
 176          * Unfortunately it is possible to run a socket AM3 CPU with DDR2
 177          * memory. We blacklist all the cores which do exist in socket AM2+
 178          * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
 179          * and AM3 formats, but that's the best we can do.
 180          */
 181         return boot_cpu_data.x86_model < 4 ||
 182                (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask <= 2);
 183 }
 184
 185 static int k10temp_probe(struct pci_dev *pdev,
 186                                    const struct pci_device_id *id)
 187 {
 188         int unreliable = has_erratum_319(pdev);
 189         struct device *dev = &pdev->dev;
 190         struct device *hwmon_dev;
 191
 192         if (unreliable) {
 193                 if (!force) {
 194                         dev_err(dev,
 195                                 "unreliable CPU thermal sensor; monitoring disabled\n");
 196                         return -ENODEV;
 197                 }
 198                 dev_warn(dev,
 199                          "unreliable CPU thermal sensor; check erratum 319\n");
 200         }
 201
 202         hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", pdev,
 203                                                            k10temp_groups);
 204         return PTR_ERR_OR_ZERO(hwmon_dev);
 205 }
 206
 207 static const struct pci_device_id k10temp_id_table[] = {
 208         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
 209         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
 210         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
 211         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
 212         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
 213         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
 214         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
 215         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
 216         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
 217         {}
 218 };
 219 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
 220
 221 static struct pci_driver k10temp_driver = {
 222         .name = "k10temp",
 223         .id_table = k10temp_id_table,
 224         .probe = k10temp_probe,
 225 };
 226
 227 module_pci_driver(k10temp_driver);