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hwmon: (w83627ehf) Fix temp2 source for W83627UHG
[mirror_ubuntu-zesty-kernel.git] / drivers / hwmon / w83627ehf.c
1 /*
2 w83627ehf - Driver for the hardware monitoring functionality of
3 the Winbond W83627EHF Super-I/O chip
4 Copyright (C) 2005-2011 Jean Delvare <khali@linux-fr.org>
5 Copyright (C) 2006 Yuan Mu (Winbond),
6 Rudolf Marek <r.marek@assembler.cz>
7 David Hubbard <david.c.hubbard@gmail.com>
8 Daniel J Blueman <daniel.blueman@gmail.com>
9 Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
10
11 Shamelessly ripped from the w83627hf driver
12 Copyright (C) 2003 Mark Studebaker
13
14 Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
15 in testing and debugging this driver.
16
17 This driver also supports the W83627EHG, which is the lead-free
18 version of the W83627EHF.
19
20 This program is free software; you can redistribute it and/or modify
21 it under the terms of the GNU General Public License as published by
22 the Free Software Foundation; either version 2 of the License, or
23 (at your option) any later version.
24
25 This program is distributed in the hope that it will be useful,
26 but WITHOUT ANY WARRANTY; without even the implied warranty of
27 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 GNU General Public License for more details.
29
30 You should have received a copy of the GNU General Public License
31 along with this program; if not, write to the Free Software
32 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33
34
35 Supports the following chips:
36
37 Chip #vin #fan #pwm #temp chip IDs man ID
38 w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
39 0x8860 0xa1
40 w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
41 w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
42 w83627uhg 8 2 2 3 0xa230 0xc1 0x5ca3
43 w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
44 w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
45 nct6775f 9 4 3 9 0xb470 0xc1 0x5ca3
46 nct6776f 9 5 3 9 0xC330 0xc1 0x5ca3
47 */
48
49 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
51 #include <linux/module.h>
52 #include <linux/init.h>
53 #include <linux/slab.h>
54 #include <linux/jiffies.h>
55 #include <linux/platform_device.h>
56 #include <linux/hwmon.h>
57 #include <linux/hwmon-sysfs.h>
58 #include <linux/hwmon-vid.h>
59 #include <linux/err.h>
60 #include <linux/mutex.h>
61 #include <linux/acpi.h>
62 #include <linux/io.h>
63 #include "lm75.h"
64
65 enum kinds {
66 w83627ehf, w83627dhg, w83627dhg_p, w83627uhg,
67 w83667hg, w83667hg_b, nct6775, nct6776,
68 };
69
70 /* used to set data->name = w83627ehf_device_names[data->sio_kind] */
71 static const char * const w83627ehf_device_names[] = {
72 "w83627ehf",
73 "w83627dhg",
74 "w83627dhg",
75 "w83627uhg",
76 "w83667hg",
77 "w83667hg",
78 "nct6775",
79 "nct6776",
80 };
81
82 static unsigned short force_id;
83 module_param(force_id, ushort, 0);
84 MODULE_PARM_DESC(force_id, "Override the detected device ID");
85
86 static unsigned short fan_debounce;
87 module_param(fan_debounce, ushort, 0);
88 MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
89
90 #define DRVNAME "w83627ehf"
91
92 /*
93 * Super-I/O constants and functions
94 */
95
96 #define W83627EHF_LD_HWM 0x0b
97 #define W83667HG_LD_VID 0x0d
98
99 #define SIO_REG_LDSEL 0x07 /* Logical device select */
100 #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
101 #define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
102 #define SIO_REG_ENABLE 0x30 /* Logical device enable */
103 #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
104 #define SIO_REG_VID_CTRL 0xF0 /* VID control */
105 #define SIO_REG_VID_DATA 0xF1 /* VID data */
106
107 #define SIO_W83627EHF_ID 0x8850
108 #define SIO_W83627EHG_ID 0x8860
109 #define SIO_W83627DHG_ID 0xa020
110 #define SIO_W83627DHG_P_ID 0xb070
111 #define SIO_W83627UHG_ID 0xa230
112 #define SIO_W83667HG_ID 0xa510
113 #define SIO_W83667HG_B_ID 0xb350
114 #define SIO_NCT6775_ID 0xb470
115 #define SIO_NCT6776_ID 0xc330
116 #define SIO_ID_MASK 0xFFF0
117
118 static inline void
119 superio_outb(int ioreg, int reg, int val)
120 {
121 outb(reg, ioreg);
122 outb(val, ioreg + 1);
123 }
124
125 static inline int
126 superio_inb(int ioreg, int reg)
127 {
128 outb(reg, ioreg);
129 return inb(ioreg + 1);
130 }
131
132 static inline void
133 superio_select(int ioreg, int ld)
134 {
135 outb(SIO_REG_LDSEL, ioreg);
136 outb(ld, ioreg + 1);
137 }
138
139 static inline void
140 superio_enter(int ioreg)
141 {
142 outb(0x87, ioreg);
143 outb(0x87, ioreg);
144 }
145
146 static inline void
147 superio_exit(int ioreg)
148 {
149 outb(0xaa, ioreg);
150 outb(0x02, ioreg);
151 outb(0x02, ioreg + 1);
152 }
153
154 /*
155 * ISA constants
156 */
157
158 #define IOREGION_ALIGNMENT (~7)
159 #define IOREGION_OFFSET 5
160 #define IOREGION_LENGTH 2
161 #define ADDR_REG_OFFSET 0
162 #define DATA_REG_OFFSET 1
163
164 #define W83627EHF_REG_BANK 0x4E
165 #define W83627EHF_REG_CONFIG 0x40
166
167 /* Not currently used:
168 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
169 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
170 * REG_MAN_ID is at port 0x4f
171 * REG_CHIP_ID is at port 0x58 */
172
173 static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
174 static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
175
176 /* The W83627EHF registers for nr=7,8,9 are in bank 5 */
177 #define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
178 (0x554 + (((nr) - 7) * 2)))
179 #define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
180 (0x555 + (((nr) - 7) * 2)))
181 #define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
182 (0x550 + (nr) - 7))
183
184 static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
185 static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
186 static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
187 static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
188
189 /* Fan clock dividers are spread over the following five registers */
190 #define W83627EHF_REG_FANDIV1 0x47
191 #define W83627EHF_REG_FANDIV2 0x4B
192 #define W83627EHF_REG_VBAT 0x5D
193 #define W83627EHF_REG_DIODE 0x59
194 #define W83627EHF_REG_SMI_OVT 0x4C
195
196 /* NCT6775F has its own fan divider registers */
197 #define NCT6775_REG_FANDIV1 0x506
198 #define NCT6775_REG_FANDIV2 0x507
199 #define NCT6775_REG_FAN_DEBOUNCE 0xf0
200
201 #define W83627EHF_REG_ALARM1 0x459
202 #define W83627EHF_REG_ALARM2 0x45A
203 #define W83627EHF_REG_ALARM3 0x45B
204
205 #define W83627EHF_REG_CASEOPEN_DET 0x42 /* SMI STATUS #2 */
206 #define W83627EHF_REG_CASEOPEN_CLR 0x46 /* SMI MASK #3 */
207
208 /* SmartFan registers */
209 #define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
210 #define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
211
212 /* DC or PWM output fan configuration */
213 static const u8 W83627EHF_REG_PWM_ENABLE[] = {
214 0x04, /* SYS FAN0 output mode and PWM mode */
215 0x04, /* CPU FAN0 output mode and PWM mode */
216 0x12, /* AUX FAN mode */
217 0x62, /* CPU FAN1 mode */
218 };
219
220 static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
221 static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
222
223 /* FAN Duty Cycle, be used to control */
224 static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
225 static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
226 static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
227
228 /* Advanced Fan control, some values are common for all fans */
229 static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
230 static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
231 static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
232
233 static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
234 = { 0xff, 0x67, 0xff, 0x69 };
235 static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
236 = { 0xff, 0x68, 0xff, 0x6a };
237
238 static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
239 static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
240 = { 0x68, 0x6a, 0x6c };
241
242 static const u16 NCT6775_REG_TARGET[] = { 0x101, 0x201, 0x301 };
243 static const u16 NCT6775_REG_FAN_MODE[] = { 0x102, 0x202, 0x302 };
244 static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = { 0x105, 0x205, 0x305 };
245 static const u16 NCT6775_REG_FAN_START_OUTPUT[] = { 0x106, 0x206, 0x306 };
246 static const u16 NCT6775_REG_FAN_STOP_TIME[] = { 0x107, 0x207, 0x307 };
247 static const u16 NCT6775_REG_PWM[] = { 0x109, 0x209, 0x309 };
248 static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
249 static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
250 static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
251 static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642};
252
253 static const u16 NCT6775_REG_TEMP[]
254 = { 0x27, 0x150, 0x250, 0x73, 0x75, 0x77, 0x62b, 0x62c, 0x62d };
255 static const u16 NCT6775_REG_TEMP_CONFIG[]
256 = { 0, 0x152, 0x252, 0, 0, 0, 0x628, 0x629, 0x62A };
257 static const u16 NCT6775_REG_TEMP_HYST[]
258 = { 0x3a, 0x153, 0x253, 0, 0, 0, 0x673, 0x678, 0x67D };
259 static const u16 NCT6775_REG_TEMP_OVER[]
260 = { 0x39, 0x155, 0x255, 0, 0, 0, 0x672, 0x677, 0x67C };
261 static const u16 NCT6775_REG_TEMP_SOURCE[]
262 = { 0x621, 0x622, 0x623, 0x100, 0x200, 0x300, 0x624, 0x625, 0x626 };
263
264 static const char *const w83667hg_b_temp_label[] = {
265 "SYSTIN",
266 "CPUTIN",
267 "AUXTIN",
268 "AMDTSI",
269 "PECI Agent 1",
270 "PECI Agent 2",
271 "PECI Agent 3",
272 "PECI Agent 4"
273 };
274
275 static const char *const nct6775_temp_label[] = {
276 "",
277 "SYSTIN",
278 "CPUTIN",
279 "AUXTIN",
280 "AMD SB-TSI",
281 "PECI Agent 0",
282 "PECI Agent 1",
283 "PECI Agent 2",
284 "PECI Agent 3",
285 "PECI Agent 4",
286 "PECI Agent 5",
287 "PECI Agent 6",
288 "PECI Agent 7",
289 "PCH_CHIP_CPU_MAX_TEMP",
290 "PCH_CHIP_TEMP",
291 "PCH_CPU_TEMP",
292 "PCH_MCH_TEMP",
293 "PCH_DIM0_TEMP",
294 "PCH_DIM1_TEMP",
295 "PCH_DIM2_TEMP",
296 "PCH_DIM3_TEMP"
297 };
298
299 static const char *const nct6776_temp_label[] = {
300 "",
301 "SYSTIN",
302 "CPUTIN",
303 "AUXTIN",
304 "SMBUSMASTER 0",
305 "SMBUSMASTER 1",
306 "SMBUSMASTER 2",
307 "SMBUSMASTER 3",
308 "SMBUSMASTER 4",
309 "SMBUSMASTER 5",
310 "SMBUSMASTER 6",
311 "SMBUSMASTER 7",
312 "PECI Agent 0",
313 "PECI Agent 1",
314 "PCH_CHIP_CPU_MAX_TEMP",
315 "PCH_CHIP_TEMP",
316 "PCH_CPU_TEMP",
317 "PCH_MCH_TEMP",
318 "PCH_DIM0_TEMP",
319 "PCH_DIM1_TEMP",
320 "PCH_DIM2_TEMP",
321 "PCH_DIM3_TEMP",
322 "BYTE_TEMP"
323 };
324
325 #define NUM_REG_TEMP ARRAY_SIZE(NCT6775_REG_TEMP)
326
327 static int is_word_sized(u16 reg)
328 {
329 return ((((reg & 0xff00) == 0x100
330 || (reg & 0xff00) == 0x200)
331 && ((reg & 0x00ff) == 0x50
332 || (reg & 0x00ff) == 0x53
333 || (reg & 0x00ff) == 0x55))
334 || (reg & 0xfff0) == 0x630
335 || reg == 0x640 || reg == 0x642
336 || ((reg & 0xfff0) == 0x650
337 && (reg & 0x000f) >= 0x06)
338 || reg == 0x73 || reg == 0x75 || reg == 0x77
339 );
340 }
341
342 /*
343 * Conversions
344 */
345
346 /* 1 is PWM mode, output in ms */
347 static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
348 {
349 return mode ? 100 * reg : 400 * reg;
350 }
351
352 static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
353 {
354 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
355 (msec + 200) / 400), 1, 255);
356 }
357
358 static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
359 {
360 if (reg == 0 || reg == 255)
361 return 0;
362 return 1350000U / (reg << divreg);
363 }
364
365 static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
366 {
367 if ((reg & 0xff1f) == 0xff1f)
368 return 0;
369
370 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
371
372 if (reg == 0)
373 return 0;
374
375 return 1350000U / reg;
376 }
377
378 static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
379 {
380 if (reg == 0 || reg == 0xffff)
381 return 0;
382
383 /*
384 * Even though the registers are 16 bit wide, the fan divisor
385 * still applies.
386 */
387 return 1350000U / (reg << divreg);
388 }
389
390 static inline unsigned int
391 div_from_reg(u8 reg)
392 {
393 return 1 << reg;
394 }
395
396 /* Some of the voltage inputs have internal scaling, the tables below
397 * contain 8 (the ADC LSB in mV) * scaling factor * 100 */
398 static const u16 scale_in_common[10] = {
399 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800
400 };
401 static const u16 scale_in_w83627uhg[9] = {
402 800, 800, 3328, 3424, 800, 800, 0, 3328, 3400
403 };
404
405 static inline long in_from_reg(u8 reg, u8 nr, const u16 *scale_in)
406 {
407 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
408 }
409
410 static inline u8 in_to_reg(u32 val, u8 nr, const u16 *scale_in)
411 {
412 return SENSORS_LIMIT(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0,
413 255);
414 }
415
416 /*
417 * Data structures and manipulation thereof
418 */
419
420 struct w83627ehf_data {
421 int addr; /* IO base of hw monitor block */
422 const char *name;
423
424 struct device *hwmon_dev;
425 struct mutex lock;
426
427 u16 reg_temp[NUM_REG_TEMP];
428 u16 reg_temp_over[NUM_REG_TEMP];
429 u16 reg_temp_hyst[NUM_REG_TEMP];
430 u16 reg_temp_config[NUM_REG_TEMP];
431 u8 temp_src[NUM_REG_TEMP];
432 const char * const *temp_label;
433
434 const u16 *REG_PWM;
435 const u16 *REG_TARGET;
436 const u16 *REG_FAN;
437 const u16 *REG_FAN_MIN;
438 const u16 *REG_FAN_START_OUTPUT;
439 const u16 *REG_FAN_STOP_OUTPUT;
440 const u16 *REG_FAN_STOP_TIME;
441 const u16 *REG_FAN_MAX_OUTPUT;
442 const u16 *REG_FAN_STEP_OUTPUT;
443 const u16 *scale_in;
444
445 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
446 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
447
448 struct mutex update_lock;
449 char valid; /* !=0 if following fields are valid */
450 unsigned long last_updated; /* In jiffies */
451
452 /* Register values */
453 u8 bank; /* current register bank */
454 u8 in_num; /* number of in inputs we have */
455 u8 in[10]; /* Register value */
456 u8 in_max[10]; /* Register value */
457 u8 in_min[10]; /* Register value */
458 unsigned int rpm[5];
459 u16 fan_min[5];
460 u8 fan_div[5];
461 u8 has_fan; /* some fan inputs can be disabled */
462 u8 has_fan_min; /* some fans don't have min register */
463 bool has_fan_div;
464 u8 temp_type[3];
465 s16 temp[9];
466 s16 temp_max[9];
467 s16 temp_max_hyst[9];
468 u32 alarms;
469 u8 caseopen;
470
471 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
472 u8 pwm_enable[4]; /* 1->manual
473 2->thermal cruise mode (also called SmartFan I)
474 3->fan speed cruise mode
475 4->variable thermal cruise (also called
476 SmartFan III)
477 5->enhanced variable thermal cruise (also called
478 SmartFan IV) */
479 u8 pwm_enable_orig[4]; /* original value of pwm_enable */
480 u8 pwm_num; /* number of pwm */
481 u8 pwm[4];
482 u8 target_temp[4];
483 u8 tolerance[4];
484
485 u8 fan_start_output[4]; /* minimum fan speed when spinning up */
486 u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
487 u8 fan_stop_time[4]; /* time at minimum before disabling fan */
488 u8 fan_max_output[4]; /* maximum fan speed */
489 u8 fan_step_output[4]; /* rate of change output value */
490
491 u8 vid;
492 u8 vrm;
493
494 u16 have_temp;
495 u8 in6_skip:1;
496 u8 temp3_val_only:1;
497 };
498
499 struct w83627ehf_sio_data {
500 int sioreg;
501 enum kinds kind;
502 };
503
504 /*
505 * On older chips, only registers 0x50-0x5f are banked.
506 * On more recent chips, all registers are banked.
507 * Assume that is the case and set the bank number for each access.
508 * Cache the bank number so it only needs to be set if it changes.
509 */
510 static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
511 {
512 u8 bank = reg >> 8;
513 if (data->bank != bank) {
514 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
515 outb_p(bank, data->addr + DATA_REG_OFFSET);
516 data->bank = bank;
517 }
518 }
519
520 static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
521 {
522 int res, word_sized = is_word_sized(reg);
523
524 mutex_lock(&data->lock);
525
526 w83627ehf_set_bank(data, reg);
527 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
528 res = inb_p(data->addr + DATA_REG_OFFSET);
529 if (word_sized) {
530 outb_p((reg & 0xff) + 1,
531 data->addr + ADDR_REG_OFFSET);
532 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
533 }
534
535 mutex_unlock(&data->lock);
536 return res;
537 }
538
539 static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
540 u16 value)
541 {
542 int word_sized = is_word_sized(reg);
543
544 mutex_lock(&data->lock);
545
546 w83627ehf_set_bank(data, reg);
547 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
548 if (word_sized) {
549 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
550 outb_p((reg & 0xff) + 1,
551 data->addr + ADDR_REG_OFFSET);
552 }
553 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
554
555 mutex_unlock(&data->lock);
556 return 0;
557 }
558
559 /* We left-align 8-bit temperature values to make the code simpler */
560 static u16 w83627ehf_read_temp(struct w83627ehf_data *data, u16 reg)
561 {
562 u16 res;
563
564 res = w83627ehf_read_value(data, reg);
565 if (!is_word_sized(reg))
566 res <<= 8;
567
568 return res;
569 }
570
571 static int w83627ehf_write_temp(struct w83627ehf_data *data, u16 reg,
572 u16 value)
573 {
574 if (!is_word_sized(reg))
575 value >>= 8;
576 return w83627ehf_write_value(data, reg, value);
577 }
578
579 /* This function assumes that the caller holds data->update_lock */
580 static void nct6775_write_fan_div(struct w83627ehf_data *data, int nr)
581 {
582 u8 reg;
583
584 switch (nr) {
585 case 0:
586 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
587 | (data->fan_div[0] & 0x7);
588 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
589 break;
590 case 1:
591 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
592 | ((data->fan_div[1] << 4) & 0x70);
593 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
594 case 2:
595 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
596 | (data->fan_div[2] & 0x7);
597 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
598 break;
599 case 3:
600 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
601 | ((data->fan_div[3] << 4) & 0x70);
602 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
603 break;
604 }
605 }
606
607 /* This function assumes that the caller holds data->update_lock */
608 static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
609 {
610 u8 reg;
611
612 switch (nr) {
613 case 0:
614 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
615 | ((data->fan_div[0] & 0x03) << 4);
616 /* fan5 input control bit is write only, compute the value */
617 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
618 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
619 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
620 | ((data->fan_div[0] & 0x04) << 3);
621 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
622 break;
623 case 1:
624 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
625 | ((data->fan_div[1] & 0x03) << 6);
626 /* fan5 input control bit is write only, compute the value */
627 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
628 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
629 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
630 | ((data->fan_div[1] & 0x04) << 4);
631 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
632 break;
633 case 2:
634 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
635 | ((data->fan_div[2] & 0x03) << 6);
636 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
637 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
638 | ((data->fan_div[2] & 0x04) << 5);
639 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
640 break;
641 case 3:
642 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
643 | (data->fan_div[3] & 0x03);
644 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
645 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
646 | ((data->fan_div[3] & 0x04) << 5);
647 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
648 break;
649 case 4:
650 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
651 | ((data->fan_div[4] & 0x03) << 2)
652 | ((data->fan_div[4] & 0x04) << 5);
653 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
654 break;
655 }
656 }
657
658 static void w83627ehf_write_fan_div_common(struct device *dev,
659 struct w83627ehf_data *data, int nr)
660 {
661 struct w83627ehf_sio_data *sio_data = dev->platform_data;
662
663 if (sio_data->kind == nct6776)
664 ; /* no dividers, do nothing */
665 else if (sio_data->kind == nct6775)
666 nct6775_write_fan_div(data, nr);
667 else
668 w83627ehf_write_fan_div(data, nr);
669 }
670
671 static void nct6775_update_fan_div(struct w83627ehf_data *data)
672 {
673 u8 i;
674
675 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
676 data->fan_div[0] = i & 0x7;
677 data->fan_div[1] = (i & 0x70) >> 4;
678 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
679 data->fan_div[2] = i & 0x7;
680 if (data->has_fan & (1<<3))
681 data->fan_div[3] = (i & 0x70) >> 4;
682 }
683
684 static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
685 {
686 int i;
687
688 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
689 data->fan_div[0] = (i >> 4) & 0x03;
690 data->fan_div[1] = (i >> 6) & 0x03;
691 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
692 data->fan_div[2] = (i >> 6) & 0x03;
693 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
694 data->fan_div[0] |= (i >> 3) & 0x04;
695 data->fan_div[1] |= (i >> 4) & 0x04;
696 data->fan_div[2] |= (i >> 5) & 0x04;
697 if (data->has_fan & ((1 << 3) | (1 << 4))) {
698 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
699 data->fan_div[3] = i & 0x03;
700 data->fan_div[4] = ((i >> 2) & 0x03)
701 | ((i >> 5) & 0x04);
702 }
703 if (data->has_fan & (1 << 3)) {
704 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
705 data->fan_div[3] |= (i >> 5) & 0x04;
706 }
707 }
708
709 static void w83627ehf_update_fan_div_common(struct device *dev,
710 struct w83627ehf_data *data)
711 {
712 struct w83627ehf_sio_data *sio_data = dev->platform_data;
713
714 if (sio_data->kind == nct6776)
715 ; /* no dividers, do nothing */
716 else if (sio_data->kind == nct6775)
717 nct6775_update_fan_div(data);
718 else
719 w83627ehf_update_fan_div(data);
720 }
721
722 static void nct6775_update_pwm(struct w83627ehf_data *data)
723 {
724 int i;
725 int pwmcfg, fanmodecfg;
726
727 for (i = 0; i < data->pwm_num; i++) {
728 pwmcfg = w83627ehf_read_value(data,
729 W83627EHF_REG_PWM_ENABLE[i]);
730 fanmodecfg = w83627ehf_read_value(data,
731 NCT6775_REG_FAN_MODE[i]);
732 data->pwm_mode[i] =
733 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
734 data->pwm_enable[i] = ((fanmodecfg >> 4) & 7) + 1;
735 data->tolerance[i] = fanmodecfg & 0x0f;
736 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
737 }
738 }
739
740 static void w83627ehf_update_pwm(struct w83627ehf_data *data)
741 {
742 int i;
743 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
744
745 for (i = 0; i < data->pwm_num; i++) {
746 if (!(data->has_fan & (1 << i)))
747 continue;
748
749 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
750 if (i != 1) {
751 pwmcfg = w83627ehf_read_value(data,
752 W83627EHF_REG_PWM_ENABLE[i]);
753 tolerance = w83627ehf_read_value(data,
754 W83627EHF_REG_TOLERANCE[i]);
755 }
756 data->pwm_mode[i] =
757 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
758 data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
759 & 3) + 1;
760 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
761
762 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
763 }
764 }
765
766 static void w83627ehf_update_pwm_common(struct device *dev,
767 struct w83627ehf_data *data)
768 {
769 struct w83627ehf_sio_data *sio_data = dev->platform_data;
770
771 if (sio_data->kind == nct6775 || sio_data->kind == nct6776)
772 nct6775_update_pwm(data);
773 else
774 w83627ehf_update_pwm(data);
775 }
776
777 static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
778 {
779 struct w83627ehf_data *data = dev_get_drvdata(dev);
780 struct w83627ehf_sio_data *sio_data = dev->platform_data;
781
782 int i;
783
784 mutex_lock(&data->update_lock);
785
786 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
787 || !data->valid) {
788 /* Fan clock dividers */
789 w83627ehf_update_fan_div_common(dev, data);
790
791 /* Measured voltages and limits */
792 for (i = 0; i < data->in_num; i++) {
793 if ((i == 6) && data->in6_skip)
794 continue;
795
796 data->in[i] = w83627ehf_read_value(data,
797 W83627EHF_REG_IN(i));
798 data->in_min[i] = w83627ehf_read_value(data,
799 W83627EHF_REG_IN_MIN(i));
800 data->in_max[i] = w83627ehf_read_value(data,
801 W83627EHF_REG_IN_MAX(i));
802 }
803
804 /* Measured fan speeds and limits */
805 for (i = 0; i < 5; i++) {
806 u16 reg;
807
808 if (!(data->has_fan & (1 << i)))
809 continue;
810
811 reg = w83627ehf_read_value(data, data->REG_FAN[i]);
812 data->rpm[i] = data->fan_from_reg(reg,
813 data->fan_div[i]);
814
815 if (data->has_fan_min & (1 << i))
816 data->fan_min[i] = w83627ehf_read_value(data,
817 data->REG_FAN_MIN[i]);
818
819 /* If we failed to measure the fan speed and clock
820 divider can be increased, let's try that for next
821 time */
822 if (data->has_fan_div
823 && (reg >= 0xff || (sio_data->kind == nct6775
824 && reg == 0x00))
825 && data->fan_div[i] < 0x07) {
826 dev_dbg(dev, "Increasing fan%d "
827 "clock divider from %u to %u\n",
828 i + 1, div_from_reg(data->fan_div[i]),
829 div_from_reg(data->fan_div[i] + 1));
830 data->fan_div[i]++;
831 w83627ehf_write_fan_div_common(dev, data, i);
832 /* Preserve min limit if possible */
833 if ((data->has_fan_min & (1 << i))
834 && data->fan_min[i] >= 2
835 && data->fan_min[i] != 255)
836 w83627ehf_write_value(data,
837 data->REG_FAN_MIN[i],
838 (data->fan_min[i] /= 2));
839 }
840 }
841
842 w83627ehf_update_pwm_common(dev, data);
843
844 for (i = 0; i < data->pwm_num; i++) {
845 if (!(data->has_fan & (1 << i)))
846 continue;
847
848 data->fan_start_output[i] =
849 w83627ehf_read_value(data,
850 data->REG_FAN_START_OUTPUT[i]);
851 data->fan_stop_output[i] =
852 w83627ehf_read_value(data,
853 data->REG_FAN_STOP_OUTPUT[i]);
854 data->fan_stop_time[i] =
855 w83627ehf_read_value(data,
856 data->REG_FAN_STOP_TIME[i]);
857
858 if (data->REG_FAN_MAX_OUTPUT &&
859 data->REG_FAN_MAX_OUTPUT[i] != 0xff)
860 data->fan_max_output[i] =
861 w83627ehf_read_value(data,
862 data->REG_FAN_MAX_OUTPUT[i]);
863
864 if (data->REG_FAN_STEP_OUTPUT &&
865 data->REG_FAN_STEP_OUTPUT[i] != 0xff)
866 data->fan_step_output[i] =
867 w83627ehf_read_value(data,
868 data->REG_FAN_STEP_OUTPUT[i]);
869
870 data->target_temp[i] =
871 w83627ehf_read_value(data,
872 data->REG_TARGET[i]) &
873 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
874 }
875
876 /* Measured temperatures and limits */
877 for (i = 0; i < NUM_REG_TEMP; i++) {
878 if (!(data->have_temp & (1 << i)))
879 continue;
880 data->temp[i] = w83627ehf_read_temp(data,
881 data->reg_temp[i]);
882 if (data->reg_temp_over[i])
883 data->temp_max[i]
884 = w83627ehf_read_temp(data,
885 data->reg_temp_over[i]);
886 if (data->reg_temp_hyst[i])
887 data->temp_max_hyst[i]
888 = w83627ehf_read_temp(data,
889 data->reg_temp_hyst[i]);
890 }
891
892 data->alarms = w83627ehf_read_value(data,
893 W83627EHF_REG_ALARM1) |
894 (w83627ehf_read_value(data,
895 W83627EHF_REG_ALARM2) << 8) |
896 (w83627ehf_read_value(data,
897 W83627EHF_REG_ALARM3) << 16);
898
899 data->caseopen = w83627ehf_read_value(data,
900 W83627EHF_REG_CASEOPEN_DET);
901
902 data->last_updated = jiffies;
903 data->valid = 1;
904 }
905
906 mutex_unlock(&data->update_lock);
907 return data;
908 }
909
910 /*
911 * Sysfs callback functions
912 */
913 #define show_in_reg(reg) \
914 static ssize_t \
915 show_##reg(struct device *dev, struct device_attribute *attr, \
916 char *buf) \
917 { \
918 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
919 struct sensor_device_attribute *sensor_attr = \
920 to_sensor_dev_attr(attr); \
921 int nr = sensor_attr->index; \
922 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr, \
923 data->scale_in)); \
924 }
925 show_in_reg(in)
926 show_in_reg(in_min)
927 show_in_reg(in_max)
928
929 #define store_in_reg(REG, reg) \
930 static ssize_t \
931 store_in_##reg(struct device *dev, struct device_attribute *attr, \
932 const char *buf, size_t count) \
933 { \
934 struct w83627ehf_data *data = dev_get_drvdata(dev); \
935 struct sensor_device_attribute *sensor_attr = \
936 to_sensor_dev_attr(attr); \
937 int nr = sensor_attr->index; \
938 unsigned long val; \
939 int err; \
940 err = kstrtoul(buf, 10, &val); \
941 if (err < 0) \
942 return err; \
943 mutex_lock(&data->update_lock); \
944 data->in_##reg[nr] = in_to_reg(val, nr, data->scale_in); \
945 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
946 data->in_##reg[nr]); \
947 mutex_unlock(&data->update_lock); \
948 return count; \
949 }
950
951 store_in_reg(MIN, min)
952 store_in_reg(MAX, max)
953
954 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
955 char *buf)
956 {
957 struct w83627ehf_data *data = w83627ehf_update_device(dev);
958 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
959 int nr = sensor_attr->index;
960 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
961 }
962
963 static struct sensor_device_attribute sda_in_input[] = {
964 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
965 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
966 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
967 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
968 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
969 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
970 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
971 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
972 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
973 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
974 };
975
976 static struct sensor_device_attribute sda_in_alarm[] = {
977 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
978 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
979 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
980 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
981 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
982 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
983 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
984 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
985 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
986 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
987 };
988
989 static struct sensor_device_attribute sda_in_min[] = {
990 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
991 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
992 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
993 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
994 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
995 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
996 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
997 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
998 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
999 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
1000 };
1001
1002 static struct sensor_device_attribute sda_in_max[] = {
1003 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
1004 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
1005 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
1006 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
1007 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
1008 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
1009 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
1010 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
1011 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
1012 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
1013 };
1014
1015 static ssize_t
1016 show_fan(struct device *dev, struct device_attribute *attr, char *buf)
1017 {
1018 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1019 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1020 int nr = sensor_attr->index;
1021 return sprintf(buf, "%d\n", data->rpm[nr]);
1022 }
1023
1024 static ssize_t
1025 show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1026 {
1027 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1028 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1029 int nr = sensor_attr->index;
1030 return sprintf(buf, "%d\n",
1031 data->fan_from_reg_min(data->fan_min[nr],
1032 data->fan_div[nr]));
1033 }
1034
1035 static ssize_t
1036 show_fan_div(struct device *dev, struct device_attribute *attr,
1037 char *buf)
1038 {
1039 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1040 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1041 int nr = sensor_attr->index;
1042 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
1043 }
1044
1045 static ssize_t
1046 store_fan_min(struct device *dev, struct device_attribute *attr,
1047 const char *buf, size_t count)
1048 {
1049 struct w83627ehf_data *data = dev_get_drvdata(dev);
1050 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1051 int nr = sensor_attr->index;
1052 unsigned long val;
1053 int err;
1054 unsigned int reg;
1055 u8 new_div;
1056
1057 err = kstrtoul(buf, 10, &val);
1058 if (err < 0)
1059 return err;
1060
1061 mutex_lock(&data->update_lock);
1062 if (!data->has_fan_div) {
1063 /*
1064 * Only NCT6776F for now, so we know that this is a 13 bit
1065 * register
1066 */
1067 if (!val) {
1068 val = 0xff1f;
1069 } else {
1070 if (val > 1350000U)
1071 val = 135000U;
1072 val = 1350000U / val;
1073 val = (val & 0x1f) | ((val << 3) & 0xff00);
1074 }
1075 data->fan_min[nr] = val;
1076 goto done; /* Leave fan divider alone */
1077 }
1078 if (!val) {
1079 /* No min limit, alarm disabled */
1080 data->fan_min[nr] = 255;
1081 new_div = data->fan_div[nr]; /* No change */
1082 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
1083 } else if ((reg = 1350000U / val) >= 128 * 255) {
1084 /* Speed below this value cannot possibly be represented,
1085 even with the highest divider (128) */
1086 data->fan_min[nr] = 254;
1087 new_div = 7; /* 128 == (1 << 7) */
1088 dev_warn(dev, "fan%u low limit %lu below minimum %u, set to "
1089 "minimum\n", nr + 1, val,
1090 data->fan_from_reg_min(254, 7));
1091 } else if (!reg) {
1092 /* Speed above this value cannot possibly be represented,
1093 even with the lowest divider (1) */
1094 data->fan_min[nr] = 1;
1095 new_div = 0; /* 1 == (1 << 0) */
1096 dev_warn(dev, "fan%u low limit %lu above maximum %u, set to "
1097 "maximum\n", nr + 1, val,
1098 data->fan_from_reg_min(1, 0));
1099 } else {
1100 /* Automatically pick the best divider, i.e. the one such
1101 that the min limit will correspond to a register value
1102 in the 96..192 range */
1103 new_div = 0;
1104 while (reg > 192 && new_div < 7) {
1105 reg >>= 1;
1106 new_div++;
1107 }
1108 data->fan_min[nr] = reg;
1109 }
1110
1111 /* Write both the fan clock divider (if it changed) and the new
1112 fan min (unconditionally) */
1113 if (new_div != data->fan_div[nr]) {
1114 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
1115 nr + 1, div_from_reg(data->fan_div[nr]),
1116 div_from_reg(new_div));
1117 data->fan_div[nr] = new_div;
1118 w83627ehf_write_fan_div_common(dev, data, nr);
1119 /* Give the chip time to sample a new speed value */
1120 data->last_updated = jiffies;
1121 }
1122 done:
1123 w83627ehf_write_value(data, data->REG_FAN_MIN[nr],
1124 data->fan_min[nr]);
1125 mutex_unlock(&data->update_lock);
1126
1127 return count;
1128 }
1129
1130 static struct sensor_device_attribute sda_fan_input[] = {
1131 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
1132 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
1133 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
1134 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
1135 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
1136 };
1137
1138 static struct sensor_device_attribute sda_fan_alarm[] = {
1139 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
1140 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
1141 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
1142 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
1143 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
1144 };
1145
1146 static struct sensor_device_attribute sda_fan_min[] = {
1147 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
1148 store_fan_min, 0),
1149 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
1150 store_fan_min, 1),
1151 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
1152 store_fan_min, 2),
1153 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
1154 store_fan_min, 3),
1155 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
1156 store_fan_min, 4),
1157 };
1158
1159 static struct sensor_device_attribute sda_fan_div[] = {
1160 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
1161 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
1162 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
1163 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
1164 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
1165 };
1166
1167 static ssize_t
1168 show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
1169 {
1170 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1171 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1172 int nr = sensor_attr->index;
1173 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
1174 }
1175
1176 #define show_temp_reg(addr, reg) \
1177 static ssize_t \
1178 show_##reg(struct device *dev, struct device_attribute *attr, \
1179 char *buf) \
1180 { \
1181 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1182 struct sensor_device_attribute *sensor_attr = \
1183 to_sensor_dev_attr(attr); \
1184 int nr = sensor_attr->index; \
1185 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->reg[nr])); \
1186 }
1187 show_temp_reg(reg_temp, temp);
1188 show_temp_reg(reg_temp_over, temp_max);
1189 show_temp_reg(reg_temp_hyst, temp_max_hyst);
1190
1191 #define store_temp_reg(addr, reg) \
1192 static ssize_t \
1193 store_##reg(struct device *dev, struct device_attribute *attr, \
1194 const char *buf, size_t count) \
1195 { \
1196 struct w83627ehf_data *data = dev_get_drvdata(dev); \
1197 struct sensor_device_attribute *sensor_attr = \
1198 to_sensor_dev_attr(attr); \
1199 int nr = sensor_attr->index; \
1200 int err; \
1201 long val; \
1202 err = kstrtol(buf, 10, &val); \
1203 if (err < 0) \
1204 return err; \
1205 mutex_lock(&data->update_lock); \
1206 data->reg[nr] = LM75_TEMP_TO_REG(val); \
1207 w83627ehf_write_temp(data, data->addr[nr], data->reg[nr]); \
1208 mutex_unlock(&data->update_lock); \
1209 return count; \
1210 }
1211 store_temp_reg(reg_temp_over, temp_max);
1212 store_temp_reg(reg_temp_hyst, temp_max_hyst);
1213
1214 static ssize_t
1215 show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
1216 {
1217 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1218 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1219 int nr = sensor_attr->index;
1220 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
1221 }
1222
1223 static struct sensor_device_attribute sda_temp_input[] = {
1224 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0),
1225 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1),
1226 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2),
1227 SENSOR_ATTR(temp4_input, S_IRUGO, show_temp, NULL, 3),
1228 SENSOR_ATTR(temp5_input, S_IRUGO, show_temp, NULL, 4),
1229 SENSOR_ATTR(temp6_input, S_IRUGO, show_temp, NULL, 5),
1230 SENSOR_ATTR(temp7_input, S_IRUGO, show_temp, NULL, 6),
1231 SENSOR_ATTR(temp8_input, S_IRUGO, show_temp, NULL, 7),
1232 SENSOR_ATTR(temp9_input, S_IRUGO, show_temp, NULL, 8),
1233 };
1234
1235 static struct sensor_device_attribute sda_temp_label[] = {
1236 SENSOR_ATTR(temp1_label, S_IRUGO, show_temp_label, NULL, 0),
1237 SENSOR_ATTR(temp2_label, S_IRUGO, show_temp_label, NULL, 1),
1238 SENSOR_ATTR(temp3_label, S_IRUGO, show_temp_label, NULL, 2),
1239 SENSOR_ATTR(temp4_label, S_IRUGO, show_temp_label, NULL, 3),
1240 SENSOR_ATTR(temp5_label, S_IRUGO, show_temp_label, NULL, 4),
1241 SENSOR_ATTR(temp6_label, S_IRUGO, show_temp_label, NULL, 5),
1242 SENSOR_ATTR(temp7_label, S_IRUGO, show_temp_label, NULL, 6),
1243 SENSOR_ATTR(temp8_label, S_IRUGO, show_temp_label, NULL, 7),
1244 SENSOR_ATTR(temp9_label, S_IRUGO, show_temp_label, NULL, 8),
1245 };
1246
1247 static struct sensor_device_attribute sda_temp_max[] = {
1248 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp_max,
1249 store_temp_max, 0),
1250 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
1251 store_temp_max, 1),
1252 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
1253 store_temp_max, 2),
1254 SENSOR_ATTR(temp4_max, S_IRUGO | S_IWUSR, show_temp_max,
1255 store_temp_max, 3),
1256 SENSOR_ATTR(temp5_max, S_IRUGO | S_IWUSR, show_temp_max,
1257 store_temp_max, 4),
1258 SENSOR_ATTR(temp6_max, S_IRUGO | S_IWUSR, show_temp_max,
1259 store_temp_max, 5),
1260 SENSOR_ATTR(temp7_max, S_IRUGO | S_IWUSR, show_temp_max,
1261 store_temp_max, 6),
1262 SENSOR_ATTR(temp8_max, S_IRUGO | S_IWUSR, show_temp_max,
1263 store_temp_max, 7),
1264 SENSOR_ATTR(temp9_max, S_IRUGO | S_IWUSR, show_temp_max,
1265 store_temp_max, 8),
1266 };
1267
1268 static struct sensor_device_attribute sda_temp_max_hyst[] = {
1269 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1270 store_temp_max_hyst, 0),
1271 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1272 store_temp_max_hyst, 1),
1273 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1274 store_temp_max_hyst, 2),
1275 SENSOR_ATTR(temp4_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1276 store_temp_max_hyst, 3),
1277 SENSOR_ATTR(temp5_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1278 store_temp_max_hyst, 4),
1279 SENSOR_ATTR(temp6_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1280 store_temp_max_hyst, 5),
1281 SENSOR_ATTR(temp7_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1282 store_temp_max_hyst, 6),
1283 SENSOR_ATTR(temp8_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1284 store_temp_max_hyst, 7),
1285 SENSOR_ATTR(temp9_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1286 store_temp_max_hyst, 8),
1287 };
1288
1289 static struct sensor_device_attribute sda_temp_alarm[] = {
1290 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
1291 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
1292 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
1293 };
1294
1295 static struct sensor_device_attribute sda_temp_type[] = {
1296 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
1297 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
1298 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
1299 };
1300
1301 #define show_pwm_reg(reg) \
1302 static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1303 char *buf) \
1304 { \
1305 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1306 struct sensor_device_attribute *sensor_attr = \
1307 to_sensor_dev_attr(attr); \
1308 int nr = sensor_attr->index; \
1309 return sprintf(buf, "%d\n", data->reg[nr]); \
1310 }
1311
1312 show_pwm_reg(pwm_mode)
1313 show_pwm_reg(pwm_enable)
1314 show_pwm_reg(pwm)
1315
1316 static ssize_t
1317 store_pwm_mode(struct device *dev, struct device_attribute *attr,
1318 const char *buf, size_t count)
1319 {
1320 struct w83627ehf_data *data = dev_get_drvdata(dev);
1321 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1322 struct w83627ehf_sio_data *sio_data = dev->platform_data;
1323 int nr = sensor_attr->index;
1324 unsigned long val;
1325 int err;
1326 u16 reg;
1327
1328 err = kstrtoul(buf, 10, &val);
1329 if (err < 0)
1330 return err;
1331
1332 if (val > 1)
1333 return -EINVAL;
1334
1335 /* On NCT67766F, DC mode is only supported for pwm1 */
1336 if (sio_data->kind == nct6776 && nr && val != 1)
1337 return -EINVAL;
1338
1339 mutex_lock(&data->update_lock);
1340 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
1341 data->pwm_mode[nr] = val;
1342 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
1343 if (!val)
1344 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1345 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
1346 mutex_unlock(&data->update_lock);
1347 return count;
1348 }
1349
1350 static ssize_t
1351 store_pwm(struct device *dev, struct device_attribute *attr,
1352 const char *buf, size_t count)
1353 {
1354 struct w83627ehf_data *data = dev_get_drvdata(dev);
1355 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1356 int nr = sensor_attr->index;
1357 unsigned long val;
1358 int err;
1359
1360 err = kstrtoul(buf, 10, &val);
1361 if (err < 0)
1362 return err;
1363
1364 val = SENSORS_LIMIT(val, 0, 255);
1365
1366 mutex_lock(&data->update_lock);
1367 data->pwm[nr] = val;
1368 w83627ehf_write_value(data, data->REG_PWM[nr], val);
1369 mutex_unlock(&data->update_lock);
1370 return count;
1371 }
1372
1373 static ssize_t
1374 store_pwm_enable(struct device *dev, struct device_attribute *attr,
1375 const char *buf, size_t count)
1376 {
1377 struct w83627ehf_data *data = dev_get_drvdata(dev);
1378 struct w83627ehf_sio_data *sio_data = dev->platform_data;
1379 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1380 int nr = sensor_attr->index;
1381 unsigned long val;
1382 int err;
1383 u16 reg;
1384
1385 err = kstrtoul(buf, 10, &val);
1386 if (err < 0)
1387 return err;
1388
1389 if (!val || (val > 4 && val != data->pwm_enable_orig[nr]))
1390 return -EINVAL;
1391 /* SmartFan III mode is not supported on NCT6776F */
1392 if (sio_data->kind == nct6776 && val == 4)
1393 return -EINVAL;
1394
1395 mutex_lock(&data->update_lock);
1396 data->pwm_enable[nr] = val;
1397 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1398 reg = w83627ehf_read_value(data,
1399 NCT6775_REG_FAN_MODE[nr]);
1400 reg &= 0x0f;
1401 reg |= (val - 1) << 4;
1402 w83627ehf_write_value(data,
1403 NCT6775_REG_FAN_MODE[nr], reg);
1404 } else {
1405 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
1406 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
1407 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1408 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
1409 }
1410 mutex_unlock(&data->update_lock);
1411 return count;
1412 }
1413
1414
1415 #define show_tol_temp(reg) \
1416 static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1417 char *buf) \
1418 { \
1419 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1420 struct sensor_device_attribute *sensor_attr = \
1421 to_sensor_dev_attr(attr); \
1422 int nr = sensor_attr->index; \
1423 return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
1424 }
1425
1426 show_tol_temp(tolerance)
1427 show_tol_temp(target_temp)
1428
1429 static ssize_t
1430 store_target_temp(struct device *dev, struct device_attribute *attr,
1431 const char *buf, size_t count)
1432 {
1433 struct w83627ehf_data *data = dev_get_drvdata(dev);
1434 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1435 int nr = sensor_attr->index;
1436 long val;
1437 int err;
1438
1439 err = kstrtol(buf, 10, &val);
1440 if (err < 0)
1441 return err;
1442
1443 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
1444
1445 mutex_lock(&data->update_lock);
1446 data->target_temp[nr] = val;
1447 w83627ehf_write_value(data, data->REG_TARGET[nr], val);
1448 mutex_unlock(&data->update_lock);
1449 return count;
1450 }
1451
1452 static ssize_t
1453 store_tolerance(struct device *dev, struct device_attribute *attr,
1454 const char *buf, size_t count)
1455 {
1456 struct w83627ehf_data *data = dev_get_drvdata(dev);
1457 struct w83627ehf_sio_data *sio_data = dev->platform_data;
1458 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1459 int nr = sensor_attr->index;
1460 u16 reg;
1461 long val;
1462 int err;
1463
1464 err = kstrtol(buf, 10, &val);
1465 if (err < 0)
1466 return err;
1467
1468 /* Limit the temp to 0C - 15C */
1469 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
1470
1471 mutex_lock(&data->update_lock);
1472 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1473 /* Limit tolerance further for NCT6776F */
1474 if (sio_data->kind == nct6776 && val > 7)
1475 val = 7;
1476 reg = w83627ehf_read_value(data, NCT6775_REG_FAN_MODE[nr]);
1477 reg = (reg & 0xf0) | val;
1478 w83627ehf_write_value(data, NCT6775_REG_FAN_MODE[nr], reg);
1479 } else {
1480 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
1481 if (nr == 1)
1482 reg = (reg & 0x0f) | (val << 4);
1483 else
1484 reg = (reg & 0xf0) | val;
1485 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
1486 }
1487 data->tolerance[nr] = val;
1488 mutex_unlock(&data->update_lock);
1489 return count;
1490 }
1491
1492 static struct sensor_device_attribute sda_pwm[] = {
1493 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1494 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1495 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1496 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1497 };
1498
1499 static struct sensor_device_attribute sda_pwm_mode[] = {
1500 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1501 store_pwm_mode, 0),
1502 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1503 store_pwm_mode, 1),
1504 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1505 store_pwm_mode, 2),
1506 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1507 store_pwm_mode, 3),
1508 };
1509
1510 static struct sensor_device_attribute sda_pwm_enable[] = {
1511 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1512 store_pwm_enable, 0),
1513 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1514 store_pwm_enable, 1),
1515 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1516 store_pwm_enable, 2),
1517 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1518 store_pwm_enable, 3),
1519 };
1520
1521 static struct sensor_device_attribute sda_target_temp[] = {
1522 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1523 store_target_temp, 0),
1524 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1525 store_target_temp, 1),
1526 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1527 store_target_temp, 2),
1528 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1529 store_target_temp, 3),
1530 };
1531
1532 static struct sensor_device_attribute sda_tolerance[] = {
1533 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1534 store_tolerance, 0),
1535 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1536 store_tolerance, 1),
1537 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1538 store_tolerance, 2),
1539 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1540 store_tolerance, 3),
1541 };
1542
1543 /* Smart Fan registers */
1544
1545 #define fan_functions(reg, REG) \
1546 static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1547 char *buf) \
1548 { \
1549 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1550 struct sensor_device_attribute *sensor_attr = \
1551 to_sensor_dev_attr(attr); \
1552 int nr = sensor_attr->index; \
1553 return sprintf(buf, "%d\n", data->reg[nr]); \
1554 } \
1555 static ssize_t \
1556 store_##reg(struct device *dev, struct device_attribute *attr, \
1557 const char *buf, size_t count) \
1558 { \
1559 struct w83627ehf_data *data = dev_get_drvdata(dev); \
1560 struct sensor_device_attribute *sensor_attr = \
1561 to_sensor_dev_attr(attr); \
1562 int nr = sensor_attr->index; \
1563 unsigned long val; \
1564 int err; \
1565 err = kstrtoul(buf, 10, &val); \
1566 if (err < 0) \
1567 return err; \
1568 val = SENSORS_LIMIT(val, 1, 255); \
1569 mutex_lock(&data->update_lock); \
1570 data->reg[nr] = val; \
1571 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
1572 mutex_unlock(&data->update_lock); \
1573 return count; \
1574 }
1575
1576 fan_functions(fan_start_output, FAN_START_OUTPUT)
1577 fan_functions(fan_stop_output, FAN_STOP_OUTPUT)
1578 fan_functions(fan_max_output, FAN_MAX_OUTPUT)
1579 fan_functions(fan_step_output, FAN_STEP_OUTPUT)
1580
1581 #define fan_time_functions(reg, REG) \
1582 static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1583 char *buf) \
1584 { \
1585 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1586 struct sensor_device_attribute *sensor_attr = \
1587 to_sensor_dev_attr(attr); \
1588 int nr = sensor_attr->index; \
1589 return sprintf(buf, "%d\n", \
1590 step_time_from_reg(data->reg[nr], \
1591 data->pwm_mode[nr])); \
1592 } \
1593 \
1594 static ssize_t \
1595 store_##reg(struct device *dev, struct device_attribute *attr, \
1596 const char *buf, size_t count) \
1597 { \
1598 struct w83627ehf_data *data = dev_get_drvdata(dev); \
1599 struct sensor_device_attribute *sensor_attr = \
1600 to_sensor_dev_attr(attr); \
1601 int nr = sensor_attr->index; \
1602 unsigned long val; \
1603 int err; \
1604 err = kstrtoul(buf, 10, &val); \
1605 if (err < 0) \
1606 return err; \
1607 val = step_time_to_reg(val, data->pwm_mode[nr]); \
1608 mutex_lock(&data->update_lock); \
1609 data->reg[nr] = val; \
1610 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
1611 mutex_unlock(&data->update_lock); \
1612 return count; \
1613 } \
1614
1615 fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1616
1617 static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1618 char *buf)
1619 {
1620 struct w83627ehf_data *data = dev_get_drvdata(dev);
1621
1622 return sprintf(buf, "%s\n", data->name);
1623 }
1624 static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
1625
1626 static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1627 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1628 store_fan_stop_time, 3),
1629 SENSOR_ATTR(pwm4_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1630 store_fan_start_output, 3),
1631 SENSOR_ATTR(pwm4_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1632 store_fan_stop_output, 3),
1633 SENSOR_ATTR(pwm4_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1634 store_fan_max_output, 3),
1635 SENSOR_ATTR(pwm4_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1636 store_fan_step_output, 3),
1637 };
1638
1639 static struct sensor_device_attribute sda_sf3_arrays_fan3[] = {
1640 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1641 store_fan_stop_time, 2),
1642 SENSOR_ATTR(pwm3_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1643 store_fan_start_output, 2),
1644 SENSOR_ATTR(pwm3_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1645 store_fan_stop_output, 2),
1646 };
1647
1648 static struct sensor_device_attribute sda_sf3_arrays[] = {
1649 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1650 store_fan_stop_time, 0),
1651 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1652 store_fan_stop_time, 1),
1653 SENSOR_ATTR(pwm1_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1654 store_fan_start_output, 0),
1655 SENSOR_ATTR(pwm2_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1656 store_fan_start_output, 1),
1657 SENSOR_ATTR(pwm1_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1658 store_fan_stop_output, 0),
1659 SENSOR_ATTR(pwm2_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1660 store_fan_stop_output, 1),
1661 };
1662
1663
1664 /*
1665 * pwm1 and pwm3 don't support max and step settings on all chips.
1666 * Need to check support while generating/removing attribute files.
1667 */
1668 static struct sensor_device_attribute sda_sf3_max_step_arrays[] = {
1669 SENSOR_ATTR(pwm1_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1670 store_fan_max_output, 0),
1671 SENSOR_ATTR(pwm1_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1672 store_fan_step_output, 0),
1673 SENSOR_ATTR(pwm2_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1674 store_fan_max_output, 1),
1675 SENSOR_ATTR(pwm2_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1676 store_fan_step_output, 1),
1677 SENSOR_ATTR(pwm3_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1678 store_fan_max_output, 2),
1679 SENSOR_ATTR(pwm3_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1680 store_fan_step_output, 2),
1681 };
1682
1683 static ssize_t
1684 show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1685 {
1686 struct w83627ehf_data *data = dev_get_drvdata(dev);
1687 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1688 }
1689 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1690
1691
1692 /* Case open detection */
1693
1694 static ssize_t
1695 show_caseopen(struct device *dev, struct device_attribute *attr, char *buf)
1696 {
1697 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1698
1699 return sprintf(buf, "%d\n",
1700 !!(data->caseopen & to_sensor_dev_attr_2(attr)->index));
1701 }
1702
1703 static ssize_t
1704 clear_caseopen(struct device *dev, struct device_attribute *attr,
1705 const char *buf, size_t count)
1706 {
1707 struct w83627ehf_data *data = dev_get_drvdata(dev);
1708 unsigned long val;
1709 u16 reg, mask;
1710
1711 if (kstrtoul(buf, 10, &val) || val != 0)
1712 return -EINVAL;
1713
1714 mask = to_sensor_dev_attr_2(attr)->nr;
1715
1716 mutex_lock(&data->update_lock);
1717 reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR);
1718 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
1719 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
1720 data->valid = 0; /* Force cache refresh */
1721 mutex_unlock(&data->update_lock);
1722
1723 return count;
1724 }
1725
1726 static struct sensor_device_attribute_2 sda_caseopen[] = {
1727 SENSOR_ATTR_2(intrusion0_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1728 clear_caseopen, 0x80, 0x10),
1729 SENSOR_ATTR_2(intrusion1_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1730 clear_caseopen, 0x40, 0x40),
1731 };
1732
1733 /*
1734 * Driver and device management
1735 */
1736
1737 static void w83627ehf_device_remove_files(struct device *dev)
1738 {
1739 /* some entries in the following arrays may not have been used in
1740 * device_create_file(), but device_remove_file() will ignore them */
1741 int i;
1742 struct w83627ehf_data *data = dev_get_drvdata(dev);
1743
1744 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1745 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
1746 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1747 struct sensor_device_attribute *attr =
1748 &sda_sf3_max_step_arrays[i];
1749 if (data->REG_FAN_STEP_OUTPUT &&
1750 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff)
1751 device_remove_file(dev, &attr->dev_attr);
1752 }
1753 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan3); i++)
1754 device_remove_file(dev, &sda_sf3_arrays_fan3[i].dev_attr);
1755 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1756 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1757 for (i = 0; i < data->in_num; i++) {
1758 if ((i == 6) && data->in6_skip)
1759 continue;
1760 device_remove_file(dev, &sda_in_input[i].dev_attr);
1761 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1762 device_remove_file(dev, &sda_in_min[i].dev_attr);
1763 device_remove_file(dev, &sda_in_max[i].dev_attr);
1764 }
1765 for (i = 0; i < 5; i++) {
1766 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1767 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1768 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1769 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1770 }
1771 for (i = 0; i < data->pwm_num; i++) {
1772 device_remove_file(dev, &sda_pwm[i].dev_attr);
1773 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1774 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1775 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1776 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1777 }
1778 for (i = 0; i < NUM_REG_TEMP; i++) {
1779 if (!(data->have_temp & (1 << i)))
1780 continue;
1781 device_remove_file(dev, &sda_temp_input[i].dev_attr);
1782 device_remove_file(dev, &sda_temp_label[i].dev_attr);
1783 if (i == 2 && data->temp3_val_only)
1784 continue;
1785 device_remove_file(dev, &sda_temp_max[i].dev_attr);
1786 device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr);
1787 if (i > 2)
1788 continue;
1789 device_remove_file(dev, &sda_temp_alarm[i].dev_attr);
1790 device_remove_file(dev, &sda_temp_type[i].dev_attr);
1791 }
1792
1793 device_remove_file(dev, &sda_caseopen[0].dev_attr);
1794 device_remove_file(dev, &sda_caseopen[1].dev_attr);
1795
1796 device_remove_file(dev, &dev_attr_name);
1797 device_remove_file(dev, &dev_attr_cpu0_vid);
1798 }
1799
1800 /* Get the monitoring functions started */
1801 static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data,
1802 enum kinds kind)
1803 {
1804 int i;
1805 u8 tmp, diode;
1806
1807 /* Start monitoring is needed */
1808 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
1809 if (!(tmp & 0x01))
1810 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
1811 tmp | 0x01);
1812
1813 /* Enable temperature sensors if needed */
1814 for (i = 0; i < NUM_REG_TEMP; i++) {
1815 if (!(data->have_temp & (1 << i)))
1816 continue;
1817 if (!data->reg_temp_config[i])
1818 continue;
1819 tmp = w83627ehf_read_value(data,
1820 data->reg_temp_config[i]);
1821 if (tmp & 0x01)
1822 w83627ehf_write_value(data,
1823 data->reg_temp_config[i],
1824 tmp & 0xfe);
1825 }
1826
1827 /* Enable VBAT monitoring if needed */
1828 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1829 if (!(tmp & 0x01))
1830 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
1831
1832 /* Get thermal sensor types */
1833 switch (kind) {
1834 case w83627ehf:
1835 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1836 break;
1837 case w83627uhg:
1838 diode = 0x00;
1839 break;
1840 default:
1841 diode = 0x70;
1842 }
1843 for (i = 0; i < 3; i++) {
1844 const char *label = NULL;
1845
1846 if (data->temp_label)
1847 label = data->temp_label[data->temp_src[i]];
1848
1849 /* Digital source overrides analog type */
1850 if (label && strncmp(label, "PECI", 4) == 0)
1851 data->temp_type[i] = 6;
1852 else if (label && strncmp(label, "AMD", 3) == 0)
1853 data->temp_type[i] = 5;
1854 else if ((tmp & (0x02 << i)))
1855 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
1856 else
1857 data->temp_type[i] = 4; /* thermistor */
1858 }
1859 }
1860
1861 static void w82627ehf_swap_tempreg(struct w83627ehf_data *data,
1862 int r1, int r2)
1863 {
1864 u16 tmp;
1865
1866 tmp = data->temp_src[r1];
1867 data->temp_src[r1] = data->temp_src[r2];
1868 data->temp_src[r2] = tmp;
1869
1870 tmp = data->reg_temp[r1];
1871 data->reg_temp[r1] = data->reg_temp[r2];
1872 data->reg_temp[r2] = tmp;
1873
1874 tmp = data->reg_temp_over[r1];
1875 data->reg_temp_over[r1] = data->reg_temp_over[r2];
1876 data->reg_temp_over[r2] = tmp;
1877
1878 tmp = data->reg_temp_hyst[r1];
1879 data->reg_temp_hyst[r1] = data->reg_temp_hyst[r2];
1880 data->reg_temp_hyst[r2] = tmp;
1881
1882 tmp = data->reg_temp_config[r1];
1883 data->reg_temp_config[r1] = data->reg_temp_config[r2];
1884 data->reg_temp_config[r2] = tmp;
1885 }
1886
1887 static void __devinit
1888 w83627ehf_set_temp_reg_ehf(struct w83627ehf_data *data, int n_temp)
1889 {
1890 int i;
1891
1892 for (i = 0; i < n_temp; i++) {
1893 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
1894 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
1895 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
1896 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
1897 }
1898 }
1899
1900 static void __devinit
1901 w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data *sio_data,
1902 struct w83627ehf_data *data)
1903 {
1904 int fan3pin, fan4pin, fan4min, fan5pin, regval;
1905
1906 /* The W83627UHG is simple, only two fan inputs, no config */
1907 if (sio_data->kind == w83627uhg) {
1908 data->has_fan = 0x03; /* fan1 and fan2 */
1909 data->has_fan_min = 0x03;
1910 return;
1911 }
1912
1913 superio_enter(sio_data->sioreg);
1914
1915 /* fan4 and fan5 share some pins with the GPIO and serial flash */
1916 if (sio_data->kind == nct6775) {
1917 /* On NCT6775, fan4 shares pins with the fdc interface */
1918 fan3pin = 1;
1919 fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80);
1920 fan4min = 0;
1921 fan5pin = 0;
1922 } else if (sio_data->kind == nct6776) {
1923 bool gpok = superio_inb(sio_data->sioreg, 0x27) & 0x80;
1924
1925 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
1926 regval = superio_inb(sio_data->sioreg, SIO_REG_ENABLE);
1927
1928 if (regval & 0x80)
1929 fan3pin = gpok;
1930 else
1931 fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40);
1932
1933 if (regval & 0x40)
1934 fan4pin = gpok;
1935 else
1936 fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01);
1937
1938 if (regval & 0x20)
1939 fan5pin = gpok;
1940 else
1941 fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02);
1942
1943 fan4min = fan4pin;
1944 } else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
1945 fan3pin = 1;
1946 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
1947 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
1948 fan4min = fan4pin;
1949 } else {
1950 fan3pin = 1;
1951 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
1952 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
1953 fan4min = fan4pin;
1954 }
1955
1956 superio_exit(sio_data->sioreg);
1957
1958 data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
1959 data->has_fan |= (fan3pin << 2);
1960 data->has_fan_min |= (fan3pin << 2);
1961
1962 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1963 /*
1964 * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1
1965 * register
1966 */
1967 data->has_fan |= (fan4pin << 3) | (fan5pin << 4);
1968 data->has_fan_min |= (fan4min << 3) | (fan5pin << 4);
1969 } else {
1970 /*
1971 * It looks like fan4 and fan5 pins can be alternatively used
1972 * as fan on/off switches, but fan5 control is write only :/
1973 * We assume that if the serial interface is disabled, designers
1974 * connected fan5 as input unless they are emitting log 1, which
1975 * is not the default.
1976 */
1977 regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
1978 if ((regval & (1 << 2)) && fan4pin) {
1979 data->has_fan |= (1 << 3);
1980 data->has_fan_min |= (1 << 3);
1981 }
1982 if (!(regval & (1 << 1)) && fan5pin) {
1983 data->has_fan |= (1 << 4);
1984 data->has_fan_min |= (1 << 4);
1985 }
1986 }
1987 }
1988
1989 static int __devinit w83627ehf_probe(struct platform_device *pdev)
1990 {
1991 struct device *dev = &pdev->dev;
1992 struct w83627ehf_sio_data *sio_data = dev->platform_data;
1993 struct w83627ehf_data *data;
1994 struct resource *res;
1995 u8 en_vrm10;
1996 int i, err = 0;
1997
1998 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1999 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
2000 err = -EBUSY;
2001 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2002 (unsigned long)res->start,
2003 (unsigned long)res->start + IOREGION_LENGTH - 1);
2004 goto exit;
2005 }
2006
2007 data = devm_kzalloc(&pdev->dev, sizeof(struct w83627ehf_data),
2008 GFP_KERNEL);
2009 if (!data) {
2010 err = -ENOMEM;
2011 goto exit_release;
2012 }
2013
2014 data->addr = res->start;
2015 mutex_init(&data->lock);
2016 mutex_init(&data->update_lock);
2017 data->name = w83627ehf_device_names[sio_data->kind];
2018 platform_set_drvdata(pdev, data);
2019
2020 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
2021 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
2022 /* 667HG, NCT6775F, and NCT6776F have 3 pwms, and 627UHG has only 2 */
2023 switch (sio_data->kind) {
2024 default:
2025 data->pwm_num = 4;
2026 break;
2027 case w83667hg:
2028 case w83667hg_b:
2029 case nct6775:
2030 case nct6776:
2031 data->pwm_num = 3;
2032 break;
2033 case w83627uhg:
2034 data->pwm_num = 2;
2035 break;
2036 }
2037
2038 /* Default to 3 temperature inputs, code below will adjust as needed */
2039 data->have_temp = 0x07;
2040
2041 /* Deal with temperature register setup first. */
2042 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2043 int mask = 0;
2044
2045 /*
2046 * Display temperature sensor output only if it monitors
2047 * a source other than one already reported. Always display
2048 * first three temperature registers, though.
2049 */
2050 for (i = 0; i < NUM_REG_TEMP; i++) {
2051 u8 src;
2052
2053 data->reg_temp[i] = NCT6775_REG_TEMP[i];
2054 data->reg_temp_over[i] = NCT6775_REG_TEMP_OVER[i];
2055 data->reg_temp_hyst[i] = NCT6775_REG_TEMP_HYST[i];
2056 data->reg_temp_config[i] = NCT6775_REG_TEMP_CONFIG[i];
2057
2058 src = w83627ehf_read_value(data,
2059 NCT6775_REG_TEMP_SOURCE[i]);
2060 src &= 0x1f;
2061 if (src && !(mask & (1 << src))) {
2062 data->have_temp |= 1 << i;
2063 mask |= 1 << src;
2064 }
2065
2066 data->temp_src[i] = src;
2067
2068 /*
2069 * Now do some register swapping if index 0..2 don't
2070 * point to SYSTIN(1), CPUIN(2), and AUXIN(3).
2071 * Idea is to have the first three attributes
2072 * report SYSTIN, CPUIN, and AUXIN if possible
2073 * without overriding the basic system configuration.
2074 */
2075 if (i > 0 && data->temp_src[0] != 1
2076 && data->temp_src[i] == 1)
2077 w82627ehf_swap_tempreg(data, 0, i);
2078 if (i > 1 && data->temp_src[1] != 2
2079 && data->temp_src[i] == 2)
2080 w82627ehf_swap_tempreg(data, 1, i);
2081 if (i > 2 && data->temp_src[2] != 3
2082 && data->temp_src[i] == 3)
2083 w82627ehf_swap_tempreg(data, 2, i);
2084 }
2085 if (sio_data->kind == nct6776) {
2086 /*
2087 * On NCT6776, AUXTIN and VIN3 pins are shared.
2088 * Only way to detect it is to check if AUXTIN is used
2089 * as a temperature source, and if that source is
2090 * enabled.
2091 *
2092 * If that is the case, disable in6, which reports VIN3.
2093 * Otherwise disable temp3.
2094 */
2095 if (data->temp_src[2] == 3) {
2096 u8 reg;
2097
2098 if (data->reg_temp_config[2])
2099 reg = w83627ehf_read_value(data,
2100 data->reg_temp_config[2]);
2101 else
2102 reg = 0; /* Assume AUXTIN is used */
2103
2104 if (reg & 0x01)
2105 data->have_temp &= ~(1 << 2);
2106 else
2107 data->in6_skip = 1;
2108 }
2109 data->temp_label = nct6776_temp_label;
2110 } else {
2111 data->temp_label = nct6775_temp_label;
2112 }
2113 } else if (sio_data->kind == w83667hg_b) {
2114 u8 reg;
2115
2116 w83627ehf_set_temp_reg_ehf(data, 4);
2117
2118 /*
2119 * Temperature sources are selected with bank 0, registers 0x49
2120 * and 0x4a.
2121 */
2122 reg = w83627ehf_read_value(data, 0x4a);
2123 data->temp_src[0] = reg >> 5;
2124 reg = w83627ehf_read_value(data, 0x49);
2125 data->temp_src[1] = reg & 0x07;
2126 data->temp_src[2] = (reg >> 4) & 0x07;
2127
2128 /*
2129 * W83667HG-B has another temperature register at 0x7e.
2130 * The temperature source is selected with register 0x7d.
2131 * Support it if the source differs from already reported
2132 * sources.
2133 */
2134 reg = w83627ehf_read_value(data, 0x7d);
2135 reg &= 0x07;
2136 if (reg != data->temp_src[0] && reg != data->temp_src[1]
2137 && reg != data->temp_src[2]) {
2138 data->temp_src[3] = reg;
2139 data->have_temp |= 1 << 3;
2140 }
2141
2142 /*
2143 * Chip supports either AUXTIN or VIN3. Try to find out which
2144 * one.
2145 */
2146 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
2147 if (data->temp_src[2] == 2 && (reg & 0x01))
2148 data->have_temp &= ~(1 << 2);
2149
2150 if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
2151 || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
2152 data->in6_skip = 1;
2153
2154 data->temp_label = w83667hg_b_temp_label;
2155 } else if (sio_data->kind == w83627uhg) {
2156 u8 reg;
2157
2158 w83627ehf_set_temp_reg_ehf(data, 3);
2159
2160 /*
2161 * Temperature sources for temp2 and temp3 are selected with
2162 * bank 0, registers 0x49 and 0x4a.
2163 */
2164 data->temp_src[0] = 0; /* SYSTIN */
2165 reg = w83627ehf_read_value(data, 0x49) & 0x07;
2166 /* Adjust to have the same mapping as other source registers */
2167 if (reg == 0)
2168 data->temp_src[1] = 1;
2169 else if (reg >= 2 && reg <= 5)
2170 data->temp_src[1] = reg + 2;
2171 else /* should never happen */
2172 data->have_temp &= ~(1 << 1);
2173 reg = w83627ehf_read_value(data, 0x4a);
2174 data->temp_src[2] = reg >> 5;
2175
2176 /*
2177 * Skip temp3 if source is invalid or the same as temp1
2178 * or temp2.
2179 */
2180 if (data->temp_src[2] == 2 || data->temp_src[2] == 3 ||
2181 data->temp_src[2] == data->temp_src[0] ||
2182 ((data->have_temp & (1 << 1)) &&
2183 data->temp_src[2] == data->temp_src[1]))
2184 data->have_temp &= ~(1 << 2);
2185 else
2186 data->temp3_val_only = 1; /* No limit regs */
2187
2188 data->in6_skip = 1; /* No VIN3 */
2189
2190 data->temp_label = w83667hg_b_temp_label;
2191 } else {
2192 w83627ehf_set_temp_reg_ehf(data, 3);
2193
2194 /* Temperature sources are fixed */
2195
2196 if (sio_data->kind == w83667hg) {
2197 u8 reg;
2198
2199 /*
2200 * Chip supports either AUXTIN or VIN3. Try to find
2201 * out which one.
2202 */
2203 reg = w83627ehf_read_value(data,
2204 W83627EHF_REG_TEMP_CONFIG[2]);
2205 if (reg & 0x01)
2206 data->have_temp &= ~(1 << 2);
2207 else
2208 data->in6_skip = 1;
2209 }
2210 }
2211
2212 if (sio_data->kind == nct6775) {
2213 data->has_fan_div = true;
2214 data->fan_from_reg = fan_from_reg16;
2215 data->fan_from_reg_min = fan_from_reg8;
2216 data->REG_PWM = NCT6775_REG_PWM;
2217 data->REG_TARGET = NCT6775_REG_TARGET;
2218 data->REG_FAN = NCT6775_REG_FAN;
2219 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2220 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2221 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2222 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2223 data->REG_FAN_MAX_OUTPUT = NCT6775_REG_FAN_MAX_OUTPUT;
2224 data->REG_FAN_STEP_OUTPUT = NCT6775_REG_FAN_STEP_OUTPUT;
2225 } else if (sio_data->kind == nct6776) {
2226 data->has_fan_div = false;
2227 data->fan_from_reg = fan_from_reg13;
2228 data->fan_from_reg_min = fan_from_reg13;
2229 data->REG_PWM = NCT6775_REG_PWM;
2230 data->REG_TARGET = NCT6775_REG_TARGET;
2231 data->REG_FAN = NCT6775_REG_FAN;
2232 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
2233 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2234 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2235 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2236 } else if (sio_data->kind == w83667hg_b) {
2237 data->has_fan_div = true;
2238 data->fan_from_reg = fan_from_reg8;
2239 data->fan_from_reg_min = fan_from_reg8;
2240 data->REG_PWM = W83627EHF_REG_PWM;
2241 data->REG_TARGET = W83627EHF_REG_TARGET;
2242 data->REG_FAN = W83627EHF_REG_FAN;
2243 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2244 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2245 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2246 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
2247 data->REG_FAN_MAX_OUTPUT =
2248 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
2249 data->REG_FAN_STEP_OUTPUT =
2250 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
2251 } else {
2252 data->has_fan_div = true;
2253 data->fan_from_reg = fan_from_reg8;
2254 data->fan_from_reg_min = fan_from_reg8;
2255 data->REG_PWM = W83627EHF_REG_PWM;
2256 data->REG_TARGET = W83627EHF_REG_TARGET;
2257 data->REG_FAN = W83627EHF_REG_FAN;
2258 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2259 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2260 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2261 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
2262 data->REG_FAN_MAX_OUTPUT =
2263 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
2264 data->REG_FAN_STEP_OUTPUT =
2265 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
2266 }
2267
2268 /* Setup input voltage scaling factors */
2269 if (sio_data->kind == w83627uhg)
2270 data->scale_in = scale_in_w83627uhg;
2271 else
2272 data->scale_in = scale_in_common;
2273
2274 /* Initialize the chip */
2275 w83627ehf_init_device(data, sio_data->kind);
2276
2277 data->vrm = vid_which_vrm();
2278 superio_enter(sio_data->sioreg);
2279 /* Read VID value */
2280 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b ||
2281 sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2282 /* W83667HG has different pins for VID input and output, so
2283 we can get the VID input values directly at logical device D
2284 0xe3. */
2285 superio_select(sio_data->sioreg, W83667HG_LD_VID);
2286 data->vid = superio_inb(sio_data->sioreg, 0xe3);
2287 err = device_create_file(dev, &dev_attr_cpu0_vid);
2288 if (err)
2289 goto exit_release;
2290 } else if (sio_data->kind != w83627uhg) {
2291 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2292 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
2293 /* Set VID input sensibility if needed. In theory the
2294 BIOS should have set it, but in practice it's not
2295 always the case. We only do it for the W83627EHF/EHG
2296 because the W83627DHG is more complex in this
2297 respect. */
2298 if (sio_data->kind == w83627ehf) {
2299 en_vrm10 = superio_inb(sio_data->sioreg,
2300 SIO_REG_EN_VRM10);
2301 if ((en_vrm10 & 0x08) && data->vrm == 90) {
2302 dev_warn(dev, "Setting VID input "
2303 "voltage to TTL\n");
2304 superio_outb(sio_data->sioreg,
2305 SIO_REG_EN_VRM10,
2306 en_vrm10 & ~0x08);
2307 } else if (!(en_vrm10 & 0x08)
2308 && data->vrm == 100) {
2309 dev_warn(dev, "Setting VID input "
2310 "voltage to VRM10\n");
2311 superio_outb(sio_data->sioreg,
2312 SIO_REG_EN_VRM10,
2313 en_vrm10 | 0x08);
2314 }
2315 }
2316
2317 data->vid = superio_inb(sio_data->sioreg,
2318 SIO_REG_VID_DATA);
2319 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
2320 data->vid &= 0x3f;
2321
2322 err = device_create_file(dev, &dev_attr_cpu0_vid);
2323 if (err)
2324 goto exit_release;
2325 } else {
2326 dev_info(dev, "VID pins in output mode, CPU VID not "
2327 "available\n");
2328 }
2329 }
2330
2331 if (fan_debounce &&
2332 (sio_data->kind == nct6775 || sio_data->kind == nct6776)) {
2333 u8 tmp;
2334
2335 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2336 tmp = superio_inb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE);
2337 if (sio_data->kind == nct6776)
2338 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2339 0x3e | tmp);
2340 else
2341 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2342 0x1e | tmp);
2343 pr_info("Enabled fan debounce for chip %s\n", data->name);
2344 }
2345
2346 superio_exit(sio_data->sioreg);
2347
2348 w83627ehf_check_fan_inputs(sio_data, data);
2349
2350 /* Read fan clock dividers immediately */
2351 w83627ehf_update_fan_div_common(dev, data);
2352
2353 /* Read pwm data to save original values */
2354 w83627ehf_update_pwm_common(dev, data);
2355 for (i = 0; i < data->pwm_num; i++)
2356 data->pwm_enable_orig[i] = data->pwm_enable[i];
2357
2358 /* Register sysfs hooks */
2359 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++) {
2360 err = device_create_file(dev, &sda_sf3_arrays[i].dev_attr);
2361 if (err)
2362 goto exit_remove;
2363 }
2364
2365 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
2366 struct sensor_device_attribute *attr =
2367 &sda_sf3_max_step_arrays[i];
2368 if (data->REG_FAN_STEP_OUTPUT &&
2369 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) {
2370 err = device_create_file(dev, &attr->dev_attr);
2371 if (err)
2372 goto exit_remove;
2373 }
2374 }
2375 /* if fan3 and fan4 are enabled create the sf3 files for them */
2376 if ((data->has_fan & (1 << 2)) && data->pwm_num >= 3)
2377 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan3); i++) {
2378 err = device_create_file(dev,
2379 &sda_sf3_arrays_fan3[i].dev_attr);
2380 if (err)
2381 goto exit_remove;
2382 }
2383 if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4)
2384 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
2385 err = device_create_file(dev,
2386 &sda_sf3_arrays_fan4[i].dev_attr);
2387 if (err)
2388 goto exit_remove;
2389 }
2390
2391 for (i = 0; i < data->in_num; i++) {
2392 if ((i == 6) && data->in6_skip)
2393 continue;
2394 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
2395 || (err = device_create_file(dev,
2396 &sda_in_alarm[i].dev_attr))
2397 || (err = device_create_file(dev,
2398 &sda_in_min[i].dev_attr))
2399 || (err = device_create_file(dev,
2400 &sda_in_max[i].dev_attr)))
2401 goto exit_remove;
2402 }
2403
2404 for (i = 0; i < 5; i++) {
2405 if (data->has_fan & (1 << i)) {
2406 if ((err = device_create_file(dev,
2407 &sda_fan_input[i].dev_attr))
2408 || (err = device_create_file(dev,
2409 &sda_fan_alarm[i].dev_attr)))
2410 goto exit_remove;
2411 if (sio_data->kind != nct6776) {
2412 err = device_create_file(dev,
2413 &sda_fan_div[i].dev_attr);
2414 if (err)
2415 goto exit_remove;
2416 }
2417 if (data->has_fan_min & (1 << i)) {
2418 err = device_create_file(dev,
2419 &sda_fan_min[i].dev_attr);
2420 if (err)
2421 goto exit_remove;
2422 }
2423 if (i < data->pwm_num &&
2424 ((err = device_create_file(dev,
2425 &sda_pwm[i].dev_attr))
2426 || (err = device_create_file(dev,
2427 &sda_pwm_mode[i].dev_attr))
2428 || (err = device_create_file(dev,
2429 &sda_pwm_enable[i].dev_attr))
2430 || (err = device_create_file(dev,
2431 &sda_target_temp[i].dev_attr))
2432 || (err = device_create_file(dev,
2433 &sda_tolerance[i].dev_attr))))
2434 goto exit_remove;
2435 }
2436 }
2437
2438 for (i = 0; i < NUM_REG_TEMP; i++) {
2439 if (!(data->have_temp & (1 << i)))
2440 continue;
2441 err = device_create_file(dev, &sda_temp_input[i].dev_attr);
2442 if (err)
2443 goto exit_remove;
2444 if (data->temp_label) {
2445 err = device_create_file(dev,
2446 &sda_temp_label[i].dev_attr);
2447 if (err)
2448 goto exit_remove;
2449 }
2450 if (i == 2 && data->temp3_val_only)
2451 continue;
2452 if (data->reg_temp_over[i]) {
2453 err = device_create_file(dev,
2454 &sda_temp_max[i].dev_attr);
2455 if (err)
2456 goto exit_remove;
2457 }
2458 if (data->reg_temp_hyst[i]) {
2459 err = device_create_file(dev,
2460 &sda_temp_max_hyst[i].dev_attr);
2461 if (err)
2462 goto exit_remove;
2463 }
2464 if (i > 2)
2465 continue;
2466 if ((err = device_create_file(dev,
2467 &sda_temp_alarm[i].dev_attr))
2468 || (err = device_create_file(dev,
2469 &sda_temp_type[i].dev_attr)))
2470 goto exit_remove;
2471 }
2472
2473 err = device_create_file(dev, &sda_caseopen[0].dev_attr);
2474 if (err)
2475 goto exit_remove;
2476
2477 if (sio_data->kind == nct6776) {
2478 err = device_create_file(dev, &sda_caseopen[1].dev_attr);
2479 if (err)
2480 goto exit_remove;
2481 }
2482
2483 err = device_create_file(dev, &dev_attr_name);
2484 if (err)
2485 goto exit_remove;
2486
2487 data->hwmon_dev = hwmon_device_register(dev);
2488 if (IS_ERR(data->hwmon_dev)) {
2489 err = PTR_ERR(data->hwmon_dev);
2490 goto exit_remove;
2491 }
2492
2493 return 0;
2494
2495 exit_remove:
2496 w83627ehf_device_remove_files(dev);
2497 exit_release:
2498 platform_set_drvdata(pdev, NULL);
2499 release_region(res->start, IOREGION_LENGTH);
2500 exit:
2501 return err;
2502 }
2503
2504 static int __devexit w83627ehf_remove(struct platform_device *pdev)
2505 {
2506 struct w83627ehf_data *data = platform_get_drvdata(pdev);
2507
2508 hwmon_device_unregister(data->hwmon_dev);
2509 w83627ehf_device_remove_files(&pdev->dev);
2510 release_region(data->addr, IOREGION_LENGTH);
2511 platform_set_drvdata(pdev, NULL);
2512
2513 return 0;
2514 }
2515
2516 static struct platform_driver w83627ehf_driver = {
2517 .driver = {
2518 .owner = THIS_MODULE,
2519 .name = DRVNAME,
2520 },
2521 .probe = w83627ehf_probe,
2522 .remove = __devexit_p(w83627ehf_remove),
2523 };
2524
2525 /* w83627ehf_find() looks for a '627 in the Super-I/O config space */
2526 static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
2527 struct w83627ehf_sio_data *sio_data)
2528 {
2529 static const char __initdata sio_name_W83627EHF[] = "W83627EHF";
2530 static const char __initdata sio_name_W83627EHG[] = "W83627EHG";
2531 static const char __initdata sio_name_W83627DHG[] = "W83627DHG";
2532 static const char __initdata sio_name_W83627DHG_P[] = "W83627DHG-P";
2533 static const char __initdata sio_name_W83627UHG[] = "W83627UHG";
2534 static const char __initdata sio_name_W83667HG[] = "W83667HG";
2535 static const char __initdata sio_name_W83667HG_B[] = "W83667HG-B";
2536 static const char __initdata sio_name_NCT6775[] = "NCT6775F";
2537 static const char __initdata sio_name_NCT6776[] = "NCT6776F";
2538
2539 u16 val;
2540 const char *sio_name;
2541
2542 superio_enter(sioaddr);
2543
2544 if (force_id)
2545 val = force_id;
2546 else
2547 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
2548 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
2549 switch (val & SIO_ID_MASK) {
2550 case SIO_W83627EHF_ID:
2551 sio_data->kind = w83627ehf;
2552 sio_name = sio_name_W83627EHF;
2553 break;
2554 case SIO_W83627EHG_ID:
2555 sio_data->kind = w83627ehf;
2556 sio_name = sio_name_W83627EHG;
2557 break;
2558 case SIO_W83627DHG_ID:
2559 sio_data->kind = w83627dhg;
2560 sio_name = sio_name_W83627DHG;
2561 break;
2562 case SIO_W83627DHG_P_ID:
2563 sio_data->kind = w83627dhg_p;
2564 sio_name = sio_name_W83627DHG_P;
2565 break;
2566 case SIO_W83627UHG_ID:
2567 sio_data->kind = w83627uhg;
2568 sio_name = sio_name_W83627UHG;
2569 break;
2570 case SIO_W83667HG_ID:
2571 sio_data->kind = w83667hg;
2572 sio_name = sio_name_W83667HG;
2573 break;
2574 case SIO_W83667HG_B_ID:
2575 sio_data->kind = w83667hg_b;
2576 sio_name = sio_name_W83667HG_B;
2577 break;
2578 case SIO_NCT6775_ID:
2579 sio_data->kind = nct6775;
2580 sio_name = sio_name_NCT6775;
2581 break;
2582 case SIO_NCT6776_ID:
2583 sio_data->kind = nct6776;
2584 sio_name = sio_name_NCT6776;
2585 break;
2586 default:
2587 if (val != 0xffff)
2588 pr_debug("unsupported chip ID: 0x%04x\n", val);
2589 superio_exit(sioaddr);
2590 return -ENODEV;
2591 }
2592
2593 /* We have a known chip, find the HWM I/O address */
2594 superio_select(sioaddr, W83627EHF_LD_HWM);
2595 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
2596 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
2597 *addr = val & IOREGION_ALIGNMENT;
2598 if (*addr == 0) {
2599 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
2600 superio_exit(sioaddr);
2601 return -ENODEV;
2602 }
2603
2604 /* Activate logical device if needed */
2605 val = superio_inb(sioaddr, SIO_REG_ENABLE);
2606 if (!(val & 0x01)) {
2607 pr_warn("Forcibly enabling Super-I/O. "
2608 "Sensor is probably unusable.\n");
2609 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
2610 }
2611
2612 superio_exit(sioaddr);
2613 pr_info("Found %s chip at %#x\n", sio_name, *addr);
2614 sio_data->sioreg = sioaddr;
2615
2616 return 0;
2617 }
2618
2619 /* when Super-I/O functions move to a separate file, the Super-I/O
2620 * bus will manage the lifetime of the device and this module will only keep
2621 * track of the w83627ehf driver. But since we platform_device_alloc(), we
2622 * must keep track of the device */
2623 static struct platform_device *pdev;
2624
2625 static int __init sensors_w83627ehf_init(void)
2626 {
2627 int err;
2628 unsigned short address;
2629 struct resource res;
2630 struct w83627ehf_sio_data sio_data;
2631
2632 /* initialize sio_data->kind and sio_data->sioreg.
2633 *
2634 * when Super-I/O functions move to a separate file, the Super-I/O
2635 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
2636 * w83627ehf hardware monitor, and call probe() */
2637 if (w83627ehf_find(0x2e, &address, &sio_data) &&
2638 w83627ehf_find(0x4e, &address, &sio_data))
2639 return -ENODEV;
2640
2641 err = platform_driver_register(&w83627ehf_driver);
2642 if (err)
2643 goto exit;
2644
2645 pdev = platform_device_alloc(DRVNAME, address);
2646 if (!pdev) {
2647 err = -ENOMEM;
2648 pr_err("Device allocation failed\n");
2649 goto exit_unregister;
2650 }
2651
2652 err = platform_device_add_data(pdev, &sio_data,
2653 sizeof(struct w83627ehf_sio_data));
2654 if (err) {
2655 pr_err("Platform data allocation failed\n");
2656 goto exit_device_put;
2657 }
2658
2659 memset(&res, 0, sizeof(res));
2660 res.name = DRVNAME;
2661 res.start = address + IOREGION_OFFSET;
2662 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
2663 res.flags = IORESOURCE_IO;
2664
2665 err = acpi_check_resource_conflict(&res);
2666 if (err)
2667 goto exit_device_put;
2668
2669 err = platform_device_add_resources(pdev, &res, 1);
2670 if (err) {
2671 pr_err("Device resource addition failed (%d)\n", err);
2672 goto exit_device_put;
2673 }
2674
2675 /* platform_device_add calls probe() */
2676 err = platform_device_add(pdev);
2677 if (err) {
2678 pr_err("Device addition failed (%d)\n", err);
2679 goto exit_device_put;
2680 }
2681
2682 return 0;
2683
2684 exit_device_put:
2685 platform_device_put(pdev);
2686 exit_unregister:
2687 platform_driver_unregister(&w83627ehf_driver);
2688 exit:
2689 return err;
2690 }
2691
2692 static void __exit sensors_w83627ehf_exit(void)
2693 {
2694 platform_device_unregister(pdev);
2695 platform_driver_unregister(&w83627ehf_driver);
2696 }
2697
2698 MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
2699 MODULE_DESCRIPTION("W83627EHF driver");
2700 MODULE_LICENSE("GPL");
2701
2702 module_init(sensors_w83627ehf_init);
2703 module_exit(sensors_w83627ehf_exit);
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