1 /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <linux/kernel.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/types.h>
17 #include <linux/device.h>
19 #include <linux/err.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/smp.h>
24 #include <linux/sysfs.h>
25 #include <linux/stat.h>
26 #include <linux/clk.h>
27 #include <linux/cpu.h>
28 #include <linux/coresight.h>
29 #include <linux/coresight-pmu.h>
30 #include <linux/pm_wakeup.h>
31 #include <linux/amba/bus.h>
32 #include <linux/seq_file.h>
33 #include <linux/uaccess.h>
34 #include <linux/perf_event.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/perf_event.h>
37 #include <asm/sections.h>
38 #include <asm/local.h>
40 #include "coresight-etm4x.h"
41 #include "coresight-etm-perf.h"
43 static int boot_enable
;
44 module_param_named(boot_enable
, boot_enable
, int, S_IRUGO
);
46 /* The number of ETMv4 currently registered */
47 static int etm4_count
;
48 static struct etmv4_drvdata
*etmdrvdata
[NR_CPUS
];
49 static void etm4_set_default(struct etmv4_config
*config
);
51 static enum cpuhp_state hp_online
;
53 static void etm4_os_unlock(struct etmv4_drvdata
*drvdata
)
55 /* Writing any value to ETMOSLAR unlocks the trace registers */
56 writel_relaxed(0x0, drvdata
->base
+ TRCOSLAR
);
57 drvdata
->os_unlock
= true;
61 static bool etm4_arch_supported(u8 arch
)
72 static int etm4_cpu_id(struct coresight_device
*csdev
)
74 struct etmv4_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
79 static int etm4_trace_id(struct coresight_device
*csdev
)
81 struct etmv4_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
83 return drvdata
->trcid
;
86 static void etm4_enable_hw(void *info
)
89 struct etmv4_drvdata
*drvdata
= info
;
90 struct etmv4_config
*config
= &drvdata
->config
;
92 CS_UNLOCK(drvdata
->base
);
94 etm4_os_unlock(drvdata
);
96 /* Disable the trace unit before programming trace registers */
97 writel_relaxed(0, drvdata
->base
+ TRCPRGCTLR
);
99 /* wait for TRCSTATR.IDLE to go up */
100 if (coresight_timeout(drvdata
->base
, TRCSTATR
, TRCSTATR_IDLE_BIT
, 1))
101 dev_err(drvdata
->dev
,
102 "timeout observed when probing at offset %#x\n",
105 writel_relaxed(config
->pe_sel
, drvdata
->base
+ TRCPROCSELR
);
106 writel_relaxed(config
->cfg
, drvdata
->base
+ TRCCONFIGR
);
107 /* nothing specific implemented */
108 writel_relaxed(0x0, drvdata
->base
+ TRCAUXCTLR
);
109 writel_relaxed(config
->eventctrl0
, drvdata
->base
+ TRCEVENTCTL0R
);
110 writel_relaxed(config
->eventctrl1
, drvdata
->base
+ TRCEVENTCTL1R
);
111 writel_relaxed(config
->stall_ctrl
, drvdata
->base
+ TRCSTALLCTLR
);
112 writel_relaxed(config
->ts_ctrl
, drvdata
->base
+ TRCTSCTLR
);
113 writel_relaxed(config
->syncfreq
, drvdata
->base
+ TRCSYNCPR
);
114 writel_relaxed(config
->ccctlr
, drvdata
->base
+ TRCCCCTLR
);
115 writel_relaxed(config
->bb_ctrl
, drvdata
->base
+ TRCBBCTLR
);
116 writel_relaxed(drvdata
->trcid
, drvdata
->base
+ TRCTRACEIDR
);
117 writel_relaxed(config
->vinst_ctrl
, drvdata
->base
+ TRCVICTLR
);
118 writel_relaxed(config
->viiectlr
, drvdata
->base
+ TRCVIIECTLR
);
119 writel_relaxed(config
->vissctlr
,
120 drvdata
->base
+ TRCVISSCTLR
);
121 writel_relaxed(config
->vipcssctlr
,
122 drvdata
->base
+ TRCVIPCSSCTLR
);
123 for (i
= 0; i
< drvdata
->nrseqstate
- 1; i
++)
124 writel_relaxed(config
->seq_ctrl
[i
],
125 drvdata
->base
+ TRCSEQEVRn(i
));
126 writel_relaxed(config
->seq_rst
, drvdata
->base
+ TRCSEQRSTEVR
);
127 writel_relaxed(config
->seq_state
, drvdata
->base
+ TRCSEQSTR
);
128 writel_relaxed(config
->ext_inp
, drvdata
->base
+ TRCEXTINSELR
);
129 for (i
= 0; i
< drvdata
->nr_cntr
; i
++) {
130 writel_relaxed(config
->cntrldvr
[i
],
131 drvdata
->base
+ TRCCNTRLDVRn(i
));
132 writel_relaxed(config
->cntr_ctrl
[i
],
133 drvdata
->base
+ TRCCNTCTLRn(i
));
134 writel_relaxed(config
->cntr_val
[i
],
135 drvdata
->base
+ TRCCNTVRn(i
));
138 /* Resource selector pair 0 is always implemented and reserved */
139 for (i
= 0; i
< drvdata
->nr_resource
* 2; i
++)
140 writel_relaxed(config
->res_ctrl
[i
],
141 drvdata
->base
+ TRCRSCTLRn(i
));
143 for (i
= 0; i
< drvdata
->nr_ss_cmp
; i
++) {
144 writel_relaxed(config
->ss_ctrl
[i
],
145 drvdata
->base
+ TRCSSCCRn(i
));
146 writel_relaxed(config
->ss_status
[i
],
147 drvdata
->base
+ TRCSSCSRn(i
));
148 writel_relaxed(config
->ss_pe_cmp
[i
],
149 drvdata
->base
+ TRCSSPCICRn(i
));
151 for (i
= 0; i
< drvdata
->nr_addr_cmp
; i
++) {
152 writeq_relaxed(config
->addr_val
[i
],
153 drvdata
->base
+ TRCACVRn(i
));
154 writeq_relaxed(config
->addr_acc
[i
],
155 drvdata
->base
+ TRCACATRn(i
));
157 for (i
= 0; i
< drvdata
->numcidc
; i
++)
158 writeq_relaxed(config
->ctxid_pid
[i
],
159 drvdata
->base
+ TRCCIDCVRn(i
));
160 writel_relaxed(config
->ctxid_mask0
, drvdata
->base
+ TRCCIDCCTLR0
);
161 writel_relaxed(config
->ctxid_mask1
, drvdata
->base
+ TRCCIDCCTLR1
);
163 for (i
= 0; i
< drvdata
->numvmidc
; i
++)
164 writeq_relaxed(config
->vmid_val
[i
],
165 drvdata
->base
+ TRCVMIDCVRn(i
));
166 writel_relaxed(config
->vmid_mask0
, drvdata
->base
+ TRCVMIDCCTLR0
);
167 writel_relaxed(config
->vmid_mask1
, drvdata
->base
+ TRCVMIDCCTLR1
);
169 /* Enable the trace unit */
170 writel_relaxed(1, drvdata
->base
+ TRCPRGCTLR
);
172 /* wait for TRCSTATR.IDLE to go back down to '0' */
173 if (coresight_timeout(drvdata
->base
, TRCSTATR
, TRCSTATR_IDLE_BIT
, 0))
174 dev_err(drvdata
->dev
,
175 "timeout observed when probing at offset %#x\n",
178 CS_LOCK(drvdata
->base
);
180 dev_dbg(drvdata
->dev
, "cpu: %d enable smp call done\n", drvdata
->cpu
);
183 static int etm4_parse_event_config(struct etmv4_drvdata
*drvdata
,
184 struct perf_event_attr
*attr
)
186 struct etmv4_config
*config
= &drvdata
->config
;
191 /* Clear configuration from previous run */
192 memset(config
, 0, sizeof(struct etmv4_config
));
194 if (attr
->exclude_kernel
)
195 config
->mode
= ETM_MODE_EXCL_KERN
;
197 if (attr
->exclude_user
)
198 config
->mode
= ETM_MODE_EXCL_USER
;
200 /* Always start from the default config */
201 etm4_set_default(config
);
204 * By default the tracers are configured to trace the whole address
205 * range. Narrow the field only if requested by user space.
208 etm4_config_trace_mode(config
);
210 /* Go from generic option to ETMv4 specifics */
211 if (attr
->config
& BIT(ETM_OPT_CYCACC
))
212 config
->cfg
|= ETMv4_MODE_CYCACC
;
213 if (attr
->config
& BIT(ETM_OPT_TS
))
214 config
->cfg
|= ETMv4_MODE_TIMESTAMP
;
219 static int etm4_enable_perf(struct coresight_device
*csdev
,
220 struct perf_event_attr
*attr
)
222 struct etmv4_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
224 if (WARN_ON_ONCE(drvdata
->cpu
!= smp_processor_id()))
227 /* Configure the tracer based on the session's specifics */
228 etm4_parse_event_config(drvdata
, attr
);
230 etm4_enable_hw(drvdata
);
235 static int etm4_enable_sysfs(struct coresight_device
*csdev
)
237 struct etmv4_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
240 spin_lock(&drvdata
->spinlock
);
243 * Executing etm4_enable_hw on the cpu whose ETM is being enabled
244 * ensures that register writes occur when cpu is powered.
246 ret
= smp_call_function_single(drvdata
->cpu
,
247 etm4_enable_hw
, drvdata
, 1);
251 drvdata
->sticky_enable
= true;
252 spin_unlock(&drvdata
->spinlock
);
254 dev_info(drvdata
->dev
, "ETM tracing enabled\n");
258 spin_unlock(&drvdata
->spinlock
);
262 static int etm4_enable(struct coresight_device
*csdev
,
263 struct perf_event_attr
*attr
, u32 mode
)
267 struct etmv4_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
269 val
= local_cmpxchg(&drvdata
->mode
, CS_MODE_DISABLED
, mode
);
271 /* Someone is already using the tracer */
277 ret
= etm4_enable_sysfs(csdev
);
280 ret
= etm4_enable_perf(csdev
, attr
);
286 /* The tracer didn't start */
288 local_set(&drvdata
->mode
, CS_MODE_DISABLED
);
293 static void etm4_disable_hw(void *info
)
296 struct etmv4_drvdata
*drvdata
= info
;
298 CS_UNLOCK(drvdata
->base
);
300 control
= readl_relaxed(drvdata
->base
+ TRCPRGCTLR
);
302 /* EN, bit[0] Trace unit enable bit */
305 /* make sure everything completes before disabling */
308 writel_relaxed(control
, drvdata
->base
+ TRCPRGCTLR
);
310 CS_LOCK(drvdata
->base
);
312 dev_dbg(drvdata
->dev
, "cpu: %d disable smp call done\n", drvdata
->cpu
);
315 static int etm4_disable_perf(struct coresight_device
*csdev
)
317 struct etmv4_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
319 if (WARN_ON_ONCE(drvdata
->cpu
!= smp_processor_id()))
322 etm4_disable_hw(drvdata
);
326 static void etm4_disable_sysfs(struct coresight_device
*csdev
)
328 struct etmv4_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
331 * Taking hotplug lock here protects from clocks getting disabled
332 * with tracing being left on (crash scenario) if user disable occurs
333 * after cpu online mask indicates the cpu is offline but before the
334 * DYING hotplug callback is serviced by the ETM driver.
337 spin_lock(&drvdata
->spinlock
);
340 * Executing etm4_disable_hw on the cpu whose ETM is being disabled
341 * ensures that register writes occur when cpu is powered.
343 smp_call_function_single(drvdata
->cpu
, etm4_disable_hw
, drvdata
, 1);
345 spin_unlock(&drvdata
->spinlock
);
348 dev_info(drvdata
->dev
, "ETM tracing disabled\n");
351 static void etm4_disable(struct coresight_device
*csdev
)
354 struct etmv4_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
357 * For as long as the tracer isn't disabled another entity can't
358 * change its status. As such we can read the status here without
359 * fearing it will change under us.
361 mode
= local_read(&drvdata
->mode
);
364 case CS_MODE_DISABLED
:
367 etm4_disable_sysfs(csdev
);
370 etm4_disable_perf(csdev
);
375 local_set(&drvdata
->mode
, CS_MODE_DISABLED
);
378 static const struct coresight_ops_source etm4_source_ops
= {
379 .cpu_id
= etm4_cpu_id
,
380 .trace_id
= etm4_trace_id
,
381 .enable
= etm4_enable
,
382 .disable
= etm4_disable
,
385 static const struct coresight_ops etm4_cs_ops
= {
386 .source_ops
= &etm4_source_ops
,
389 static void etm4_init_arch_data(void *info
)
397 struct etmv4_drvdata
*drvdata
= info
;
399 /* Make sure all registers are accessible */
400 etm4_os_unlock(drvdata
);
402 CS_UNLOCK(drvdata
->base
);
404 /* find all capabilities of the tracing unit */
405 etmidr0
= readl_relaxed(drvdata
->base
+ TRCIDR0
);
407 /* INSTP0, bits[2:1] P0 tracing support field */
408 if (BMVAL(etmidr0
, 1, 1) && BMVAL(etmidr0
, 2, 2))
409 drvdata
->instrp0
= true;
411 drvdata
->instrp0
= false;
413 /* TRCBB, bit[5] Branch broadcast tracing support bit */
414 if (BMVAL(etmidr0
, 5, 5))
415 drvdata
->trcbb
= true;
417 drvdata
->trcbb
= false;
419 /* TRCCOND, bit[6] Conditional instruction tracing support bit */
420 if (BMVAL(etmidr0
, 6, 6))
421 drvdata
->trccond
= true;
423 drvdata
->trccond
= false;
425 /* TRCCCI, bit[7] Cycle counting instruction bit */
426 if (BMVAL(etmidr0
, 7, 7))
427 drvdata
->trccci
= true;
429 drvdata
->trccci
= false;
431 /* RETSTACK, bit[9] Return stack bit */
432 if (BMVAL(etmidr0
, 9, 9))
433 drvdata
->retstack
= true;
435 drvdata
->retstack
= false;
437 /* NUMEVENT, bits[11:10] Number of events field */
438 drvdata
->nr_event
= BMVAL(etmidr0
, 10, 11);
439 /* QSUPP, bits[16:15] Q element support field */
440 drvdata
->q_support
= BMVAL(etmidr0
, 15, 16);
441 /* TSSIZE, bits[28:24] Global timestamp size field */
442 drvdata
->ts_size
= BMVAL(etmidr0
, 24, 28);
444 /* base architecture of trace unit */
445 etmidr1
= readl_relaxed(drvdata
->base
+ TRCIDR1
);
447 * TRCARCHMIN, bits[7:4] architecture the minor version number
448 * TRCARCHMAJ, bits[11:8] architecture major versin number
450 drvdata
->arch
= BMVAL(etmidr1
, 4, 11);
452 /* maximum size of resources */
453 etmidr2
= readl_relaxed(drvdata
->base
+ TRCIDR2
);
454 /* CIDSIZE, bits[9:5] Indicates the Context ID size */
455 drvdata
->ctxid_size
= BMVAL(etmidr2
, 5, 9);
456 /* VMIDSIZE, bits[14:10] Indicates the VMID size */
457 drvdata
->vmid_size
= BMVAL(etmidr2
, 10, 14);
458 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
459 drvdata
->ccsize
= BMVAL(etmidr2
, 25, 28);
461 etmidr3
= readl_relaxed(drvdata
->base
+ TRCIDR3
);
462 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
463 drvdata
->ccitmin
= BMVAL(etmidr3
, 0, 11);
464 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
465 drvdata
->s_ex_level
= BMVAL(etmidr3
, 16, 19);
466 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
467 drvdata
->ns_ex_level
= BMVAL(etmidr3
, 20, 23);
470 * TRCERR, bit[24] whether a trace unit can trace a
471 * system error exception.
473 if (BMVAL(etmidr3
, 24, 24))
474 drvdata
->trc_error
= true;
476 drvdata
->trc_error
= false;
478 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
479 if (BMVAL(etmidr3
, 25, 25))
480 drvdata
->syncpr
= true;
482 drvdata
->syncpr
= false;
484 /* STALLCTL, bit[26] is stall control implemented? */
485 if (BMVAL(etmidr3
, 26, 26))
486 drvdata
->stallctl
= true;
488 drvdata
->stallctl
= false;
490 /* SYSSTALL, bit[27] implementation can support stall control? */
491 if (BMVAL(etmidr3
, 27, 27))
492 drvdata
->sysstall
= true;
494 drvdata
->sysstall
= false;
496 /* NUMPROC, bits[30:28] the number of PEs available for tracing */
497 drvdata
->nr_pe
= BMVAL(etmidr3
, 28, 30);
499 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
500 if (BMVAL(etmidr3
, 31, 31))
501 drvdata
->nooverflow
= true;
503 drvdata
->nooverflow
= false;
505 /* number of resources trace unit supports */
506 etmidr4
= readl_relaxed(drvdata
->base
+ TRCIDR4
);
507 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
508 drvdata
->nr_addr_cmp
= BMVAL(etmidr4
, 0, 3);
509 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
510 drvdata
->nr_pe_cmp
= BMVAL(etmidr4
, 12, 15);
512 * NUMRSPAIR, bits[19:16]
513 * The number of resource pairs conveyed by the HW starts at 0, i.e a
514 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
515 * As such add 1 to the value of NUMRSPAIR for a better representation.
517 drvdata
->nr_resource
= BMVAL(etmidr4
, 16, 19) + 1;
519 * NUMSSCC, bits[23:20] the number of single-shot
520 * comparator control for tracing
522 drvdata
->nr_ss_cmp
= BMVAL(etmidr4
, 20, 23);
523 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
524 drvdata
->numcidc
= BMVAL(etmidr4
, 24, 27);
525 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
526 drvdata
->numvmidc
= BMVAL(etmidr4
, 28, 31);
528 etmidr5
= readl_relaxed(drvdata
->base
+ TRCIDR5
);
529 /* NUMEXTIN, bits[8:0] number of external inputs implemented */
530 drvdata
->nr_ext_inp
= BMVAL(etmidr5
, 0, 8);
531 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
532 drvdata
->trcid_size
= BMVAL(etmidr5
, 16, 21);
533 /* ATBTRIG, bit[22] implementation can support ATB triggers? */
534 if (BMVAL(etmidr5
, 22, 22))
535 drvdata
->atbtrig
= true;
537 drvdata
->atbtrig
= false;
539 * LPOVERRIDE, bit[23] implementation supports
540 * low-power state override
542 if (BMVAL(etmidr5
, 23, 23))
543 drvdata
->lpoverride
= true;
545 drvdata
->lpoverride
= false;
546 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
547 drvdata
->nrseqstate
= BMVAL(etmidr5
, 25, 27);
548 /* NUMCNTR, bits[30:28] number of counters available for tracing */
549 drvdata
->nr_cntr
= BMVAL(etmidr5
, 28, 30);
550 CS_LOCK(drvdata
->base
);
553 static void etm4_set_default(struct etmv4_config
*config
)
555 if (WARN_ON_ONCE(!config
))
559 * Make default initialisation trace everything
561 * Select the "always true" resource selector on the
562 * "Enablign Event" line and configure address range comparator
563 * '0' to trace all the possible address range. From there
564 * configure the "include/exclude" engine to include address
565 * range comparator '0'.
568 /* disable all events tracing */
569 config
->eventctrl0
= 0x0;
570 config
->eventctrl1
= 0x0;
572 /* disable stalling */
573 config
->stall_ctrl
= 0x0;
575 /* enable trace synchronization every 4096 bytes, if available */
576 config
->syncfreq
= 0xC;
578 /* disable timestamp event */
579 config
->ts_ctrl
= 0x0;
581 /* TRCVICTLR::EVENT = 0x01, select the always on logic */
582 config
->vinst_ctrl
|= BIT(0);
585 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
586 * in the started state
588 config
->vinst_ctrl
|= BIT(9);
591 * Configure address range comparator '0' to encompass all
592 * possible addresses.
595 /* First half of default address comparator: start at address 0 */
596 config
->addr_val
[ETM_DEFAULT_ADDR_COMP
] = 0x0;
597 /* trace instruction addresses */
598 config
->addr_acc
[ETM_DEFAULT_ADDR_COMP
] &= ~(BIT(0) | BIT(1));
599 /* EXLEVEL_NS, bits[12:15], only trace application and kernel space */
600 config
->addr_acc
[ETM_DEFAULT_ADDR_COMP
] |= ETM_EXLEVEL_NS_HYP
;
601 /* EXLEVEL_S, bits[11:8], don't trace anything in secure state */
602 config
->addr_acc
[ETM_DEFAULT_ADDR_COMP
] |= (ETM_EXLEVEL_S_APP
|
605 config
->addr_type
[ETM_DEFAULT_ADDR_COMP
] = ETM_ADDR_TYPE_RANGE
;
608 * Second half of default address comparator: go all
609 * the way to the top.
611 config
->addr_val
[ETM_DEFAULT_ADDR_COMP
+ 1] = ~0x0;
612 /* trace instruction addresses */
613 config
->addr_acc
[ETM_DEFAULT_ADDR_COMP
+ 1] &= ~(BIT(0) | BIT(1));
614 /* Address comparator type must be equal for both halves */
615 config
->addr_acc
[ETM_DEFAULT_ADDR_COMP
+ 1] =
616 config
->addr_acc
[ETM_DEFAULT_ADDR_COMP
];
617 config
->addr_type
[ETM_DEFAULT_ADDR_COMP
+ 1] = ETM_ADDR_TYPE_RANGE
;
620 * Configure the ViewInst function to filter on address range
623 config
->viiectlr
= BIT(0);
625 /* no start-stop filtering for ViewInst */
626 config
->vissctlr
= 0x0;
629 void etm4_config_trace_mode(struct etmv4_config
*config
)
634 mode
&= (ETM_MODE_EXCL_KERN
| ETM_MODE_EXCL_USER
);
636 /* excluding kernel AND user space doesn't make sense */
637 WARN_ON_ONCE(mode
== (ETM_MODE_EXCL_KERN
| ETM_MODE_EXCL_USER
));
639 /* nothing to do if neither flags are set */
640 if (!(mode
& ETM_MODE_EXCL_KERN
) && !(mode
& ETM_MODE_EXCL_USER
))
643 addr_acc
= config
->addr_acc
[ETM_DEFAULT_ADDR_COMP
];
644 /* clear default config */
645 addr_acc
&= ~(ETM_EXLEVEL_NS_APP
| ETM_EXLEVEL_NS_OS
);
648 * EXLEVEL_NS, bits[15:12]
649 * The Exception levels are:
650 * Bit[12] Exception level 0 - Application
651 * Bit[13] Exception level 1 - OS
652 * Bit[14] Exception level 2 - Hypervisor
653 * Bit[15] Never implemented
655 if (mode
& ETM_MODE_EXCL_KERN
)
656 addr_acc
|= ETM_EXLEVEL_NS_OS
;
658 addr_acc
|= ETM_EXLEVEL_NS_APP
;
660 config
->addr_acc
[ETM_DEFAULT_ADDR_COMP
] = addr_acc
;
661 config
->addr_acc
[ETM_DEFAULT_ADDR_COMP
+ 1] = addr_acc
;
664 static int etm4_online_cpu(unsigned int cpu
)
666 if (!etmdrvdata
[cpu
])
669 if (etmdrvdata
[cpu
]->boot_enable
&& !etmdrvdata
[cpu
]->sticky_enable
)
670 coresight_enable(etmdrvdata
[cpu
]->csdev
);
674 static int etm4_starting_cpu(unsigned int cpu
)
676 if (!etmdrvdata
[cpu
])
679 spin_lock(&etmdrvdata
[cpu
]->spinlock
);
680 if (!etmdrvdata
[cpu
]->os_unlock
) {
681 etm4_os_unlock(etmdrvdata
[cpu
]);
682 etmdrvdata
[cpu
]->os_unlock
= true;
685 if (local_read(&etmdrvdata
[cpu
]->mode
))
686 etm4_enable_hw(etmdrvdata
[cpu
]);
687 spin_unlock(&etmdrvdata
[cpu
]->spinlock
);
691 static int etm4_dying_cpu(unsigned int cpu
)
693 if (!etmdrvdata
[cpu
])
696 spin_lock(&etmdrvdata
[cpu
]->spinlock
);
697 if (local_read(&etmdrvdata
[cpu
]->mode
))
698 etm4_disable_hw(etmdrvdata
[cpu
]);
699 spin_unlock(&etmdrvdata
[cpu
]->spinlock
);
703 static void etm4_init_trace_id(struct etmv4_drvdata
*drvdata
)
705 drvdata
->trcid
= coresight_get_trace_id(drvdata
->cpu
);
708 static int etm4_probe(struct amba_device
*adev
, const struct amba_id
*id
)
712 struct device
*dev
= &adev
->dev
;
713 struct coresight_platform_data
*pdata
= NULL
;
714 struct etmv4_drvdata
*drvdata
;
715 struct resource
*res
= &adev
->res
;
716 struct coresight_desc
*desc
;
717 struct device_node
*np
= adev
->dev
.of_node
;
719 desc
= devm_kzalloc(dev
, sizeof(*desc
), GFP_KERNEL
);
723 drvdata
= devm_kzalloc(dev
, sizeof(*drvdata
), GFP_KERNEL
);
728 pdata
= of_get_coresight_platform_data(dev
, np
);
730 return PTR_ERR(pdata
);
731 adev
->dev
.platform_data
= pdata
;
734 drvdata
->dev
= &adev
->dev
;
735 dev_set_drvdata(dev
, drvdata
);
737 /* Validity for the resource is already checked by the AMBA core */
738 base
= devm_ioremap_resource(dev
, res
);
740 return PTR_ERR(base
);
742 drvdata
->base
= base
;
744 spin_lock_init(&drvdata
->spinlock
);
746 drvdata
->cpu
= pdata
? pdata
->cpu
: 0;
749 etmdrvdata
[drvdata
->cpu
] = drvdata
;
751 if (smp_call_function_single(drvdata
->cpu
,
752 etm4_init_arch_data
, drvdata
, 1))
753 dev_err(dev
, "ETM arch init failed\n");
756 cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT4_STARTING
,
757 "AP_ARM_CORESIGHT4_STARTING",
758 etm4_starting_cpu
, etm4_dying_cpu
);
759 ret
= cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN
,
760 "AP_ARM_CORESIGHT4_ONLINE",
761 etm4_online_cpu
, NULL
);
763 goto err_arch_supported
;
769 if (etm4_arch_supported(drvdata
->arch
) == false) {
771 goto err_arch_supported
;
774 etm4_init_trace_id(drvdata
);
775 etm4_set_default(&drvdata
->config
);
777 desc
->type
= CORESIGHT_DEV_TYPE_SOURCE
;
778 desc
->subtype
.source_subtype
= CORESIGHT_DEV_SUBTYPE_SOURCE_PROC
;
779 desc
->ops
= &etm4_cs_ops
;
782 desc
->groups
= coresight_etmv4_groups
;
783 drvdata
->csdev
= coresight_register(desc
);
784 if (IS_ERR(drvdata
->csdev
)) {
785 ret
= PTR_ERR(drvdata
->csdev
);
786 goto err_arch_supported
;
789 ret
= etm_perf_symlink(drvdata
->csdev
, true);
791 coresight_unregister(drvdata
->csdev
);
792 goto err_arch_supported
;
795 pm_runtime_put(&adev
->dev
);
796 dev_info(dev
, "%s initialized\n", (char *)id
->data
);
799 coresight_enable(drvdata
->csdev
);
800 drvdata
->boot_enable
= true;
806 if (--etm4_count
== 0) {
807 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT4_STARTING
);
809 cpuhp_remove_state_nocalls(hp_online
);
814 static struct amba_id etm4_ids
[] = {
815 { /* ETM 4.0 - Cortex-A53 */
820 { /* ETM 4.0 - Cortex-A57 */
825 { /* ETM 4.0 - A72, Maia, HiSilicon */
833 static struct amba_driver etm4x_driver
= {
835 .name
= "coresight-etm4x",
836 .suppress_bind_attrs
= true,
839 .id_table
= etm4_ids
,
841 builtin_amba_driver(etm4x_driver
);