drivers/i2c/busses/i2c-amd-pci-mp2.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  *   redistributing this file, you may do so under either license.
   5  *
   6  *   GPL LICENSE SUMMARY
   7  *
   8  *   Copyright (C) 2018 Advanced Micro Devices, Inc. All Rights Reserved.
   9  *
  10  *   This program is free software; you can redistribute it and/or modify
  11  *   it under the terms of version 2 of the GNU General Public License as
  12  *   published by the Free Software Foundation.
  13  *
  14  *   BSD LICENSE
  15  *
  16  *   Copyright (C) 2018 Advanced Micro Devices, Inc. All Rights Reserved.
  17  *
  18  *   Redistribution and use in source and binary forms, with or without
  19  *   modification, are permitted provided that the following conditions
  20  *   are met:
  21  *
  22  *     * Redistributions of source code must retain the above copyright
  23  *       notice, this list of conditions and the following disclaimer.
  24  *     * Redistributions in binary form must reproduce the above copy
  25  *       notice, this list of conditions and the following disclaimer in
  26  *       the documentation and/or other materials provided with the
  27  *       distribution.
  28  *     * Neither the name of AMD Corporation nor the names of its
  29  *       contributors may be used to endorse or promote products derived
  30  *       from this software without specific prior written permission.
  31  *
  32  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  33  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  34  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  35  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  36  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  37  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  38  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  39  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  40  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  41  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  42  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  43  *
  44  * AMD PCIe MP2 Communication Interface Driver
  45  * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
  46  */
  47
  48 #ifndef I2C_AMD_PCI_MP2_H
  49 #define I2C_AMD_PCI_MP2_H
  50
  51 #include <linux/pci.h>
  52
  53 #define PCI_DEVICE_ID_AMD_MP2   0x15E6
  54
  55 #define write64 _write64
  56 static inline void _write64(u64 val, void __iomem *mmio)
  57 {
  58         writel(val, mmio);
  59         writel(val >> 32, mmio + sizeof(u32));
  60 }
  61
  62 #define read64 _read64
  63 static inline u64 _read64(void __iomem *mmio)
  64 {
  65         u64 low, high;
  66
  67         low = readl(mmio);
  68         high = readl(mmio + sizeof(u32));
  69         return low | (high << 32);
  70 }
  71
  72 enum {
  73         /* MP2 C2P Message Registers */
  74         AMD_C2P_MSG0 = 0x10500, /*MP2 Message for I2C0*/
  75         AMD_C2P_MSG1 = 0x10504, /*MP2 Message for I2C1*/
  76         AMD_C2P_MSG2 = 0x10508, /*DRAM Address Lo / Data 0*/
  77         AMD_C2P_MSG3 = 0x1050c, /*DRAM Address HI / Data 1*/
  78         AMD_C2P_MSG4 = 0x10510, /*Data 2*/
  79         AMD_C2P_MSG5 = 0x10514, /*Data 3*/
  80         AMD_C2P_MSG6 = 0x10518, /*Data 4*/
  81         AMD_C2P_MSG7 = 0x1051c, /*Data 5*/
  82         AMD_C2P_MSG8 = 0x10520, /*Data 6*/
  83         AMD_C2P_MSG9 = 0x10524, /*Data 7*/
  84
  85         /* MP2 P2C Message Registers */
  86         AMD_P2C_MSG0 = 0x10680, /*Do not use*/
  87         AMD_P2C_MSG1 = 0x10684, /*I2c0 int reg*/
  88         AMD_P2C_MSG2 = 0x10688, /*I2c1 int reg*/
  89         AMD_P2C_MSG3 = 0x1068C, /*MP2 debug info*/
  90         AMD_P2C_MSG_INTEN = 0x10690, /*MP2 int gen register*/
  91         AMD_P2C_MSG_INTSTS = 0x10694, /*Interrupt sts*/
  92 };
  93
  94 /* Command register data structures */
  95
  96 enum i2c_cmd {
  97         i2c_read,
  98         i2c_write,
  99         i2c_enable,
 100         i2c_disable,
 101         number_of_sensor_discovered,
 102         is_mp2_active,
 103         invalid_cmd = 0xF,
 104 };
 105
 106 enum i2c_bus_index {
 107         i2c_bus_0 = 0,
 108         i2c_bus_1 = 1,
 109         i2c_bus_max
 110 };
 111
 112 enum speed_enum {
 113         speed100k = 0,
 114         speed400k = 1,
 115         speed1000k = 2,
 116         speed1400k = 3,
 117         speed3400k = 4
 118 };
 119
 120 enum mem_type {
 121         use_dram = 0,
 122         use_c2pmsg = 1,
 123 };
 124
 125 union i2c_cmd_base {
 126         u32 ul;
 127         struct {
 128                 enum i2c_cmd i2c_cmd : 4; /*!< bit: 0..3 i2c R/W command */
 129                 enum i2c_bus_index bus_id : 4; /*!< bit: 4..7 i2c bus index */
 130                 u32 dev_addr : 8; /*!< bit: 8..15 device address or Bus Speed*/
 131                 u32 length : 12; /*!< bit: 16..29 read/write length */
 132                 enum speed_enum i2c_speed : 3; /*!< bit: 30 register address*/
 133                 enum mem_type mem_type : 1; /*!< bit: 15 mem type*/
 134         } s; /*!< Structure used for bit access */
 135 };
 136
 137 /* Response register data structures */
 138
 139 /*Response - Response of SFI*/
 140 enum response_type {
 141         invalid_response = 0,
 142         command_success = 1,
 143         command_failed = 2,
 144 };
 145
 146 /*Status - Command ID to indicate a command*/
 147 enum status_type {
 148         i2c_readcomplete_event = 0,
 149         i2c_readfail_event = 1,
 150         i2c_writecomplete_event = 2,
 151         i2c_writefail_event = 3,
 152         i2c_busenable_complete = 4,
 153         i2c_busenable_failed = 5,
 154         i2c_busdisable_complete = 6,
 155         i2c_busdisable_failed = 7,
 156         invalid_data_length = 8,
 157         invalid_slave_address = 9,
 158         invalid_i2cbus_id = 10,
 159         invalid_dram_addr = 11,
 160         invalid_command = 12,
 161         mp2_active = 13,
 162         numberof_sensors_discovered_resp = 14,
 163         i2C_bus_notinitialized
 164 };
 165
 166 struct i2c_event {
 167         union {
 168                 u32 ul;
 169                 struct {
 170                         enum response_type response : 2; /*!< bit: 0..1 I2C res type */
 171                         enum status_type status : 5; /*!< bit: 2..6 status_type */
 172                         enum mem_type mem_type : 1; /*!< bit: 7 0-DRAM;1- C2PMsg o/p */
 173                         enum i2c_bus_index bus_id : 4; /*!< bit: 8..11 I2C Bus ID */
 174                         u32 length : 12; /*!< bit:16..29 length */
 175                         u32 slave_addr : 8; /*!< bit: 15 debug msg include in p2c msg */
 176                 } r; /*!< Structure used for bit access */
 177         } base;
 178         u32 *buf;
 179 };
 180
 181 /* data structures for communication with I2c*/
 182
 183 struct i2c_connect_config {
 184         enum i2c_bus_index bus_id;
 185         u64 i2c_speed;
 186         u16 dev_addr;
 187 };
 188
 189 struct i2c_write_config {
 190         enum i2c_bus_index bus_id;
 191         u64 i2c_speed;
 192         u16 dev_addr;
 193         u32 length;
 194         phys_addr_t phy_addr;
 195         u32 *buf;
 196 };
 197
 198 struct i2c_read_config {
 199         enum i2c_bus_index bus_id;
 200         u64 i2c_speed;
 201         u16 dev_addr;
 202         u32 length;
 203         phys_addr_t phy_addr;
 204         u8 *buf;
 205 };
 206
 207 // struct to send/receive data b/w pci and i2c drivers
 208 struct amd_i2c_pci_ops {
 209         int (*read_complete)(struct i2c_event event, void *dev_ctx);
 210         int (*write_complete)(struct i2c_event event, void *dev_ctx);
 211         int (*connect_complete)(struct i2c_event event, void *dev_ctx);
 212 };
 213
 214 struct amd_i2c_common {
 215         struct i2c_connect_config connect_cfg;
 216         struct i2c_read_config read_cfg;
 217         struct i2c_write_config write_cfg;
 218         const struct amd_i2c_pci_ops *ops;
 219         struct pci_dev *pdev;
 220 };
 221
 222 struct amd_mp2_dev {
 223         struct pci_dev *pdev;
 224         struct dentry *debugfs_dir;
 225         struct dentry *debugfs_info;
 226         void __iomem *mmio;
 227         struct i2c_event eventval;
 228         enum i2c_cmd reqcmd;
 229         struct i2c_connect_config connect_cfg;
 230         struct i2c_read_config read_cfg;
 231         struct i2c_write_config write_cfg;
 232         union i2c_cmd_base i2c_cmd_base;
 233         const struct amd_i2c_pci_ops *ops;
 234         struct delayed_work work;
 235         void *i2c_dev_ctx;
 236         bool    requested;
 237         raw_spinlock_t lock;
 238 };
 239
 240 int amd_mp2_read(struct pci_dev *pdev, struct i2c_read_config read_cfg);
 241 int amd_mp2_write(struct pci_dev *pdev,
 242                   struct i2c_write_config write_cfg);
 243 int amd_mp2_connect(struct pci_dev *pdev,
 244                     struct i2c_connect_config connect_cfg);
 245 int amd_i2c_register_cb(struct pci_dev *pdev, const struct amd_i2c_pci_ops *ops,
 246                         void *dev_ctx);
 247
 248 #define ndev_pdev(ndev) ((ndev)->pdev)
 249 #define ndev_name(ndev) pci_name(ndev_pdev(ndev))
 250 #define ndev_dev(ndev) (&ndev_pdev(ndev)->dev)
 251 #define mp2_dev(__work) container_of(__work, struct amd_mp2_dev, work.work)
 252
 253 #endif