2 * Aspeed 24XX/25XX I2C Controller.
4 * Copyright (C) 2012-2017 ASPEED Technology Inc.
5 * Copyright 2017 IBM Corporation
6 * Copyright 2017 Google, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/clk.h>
14 #include <linux/completion.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
17 #include <linux/i2c.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
33 #define ASPEED_I2C_FUN_CTRL_REG 0x00
34 #define ASPEED_I2C_AC_TIMING_REG1 0x04
35 #define ASPEED_I2C_AC_TIMING_REG2 0x08
36 #define ASPEED_I2C_INTR_CTRL_REG 0x0c
37 #define ASPEED_I2C_INTR_STS_REG 0x10
38 #define ASPEED_I2C_CMD_REG 0x14
39 #define ASPEED_I2C_DEV_ADDR_REG 0x18
40 #define ASPEED_I2C_BYTE_BUF_REG 0x20
42 /* Global Register Definition */
43 /* 0x00 : I2C Interrupt Status Register */
44 /* 0x08 : I2C Interrupt Target Assignment */
46 /* Device Register Definition */
47 /* 0x00 : I2CD Function Control Register */
48 #define ASPEED_I2CD_MULTI_MASTER_DIS BIT(15)
49 #define ASPEED_I2CD_SDA_DRIVE_1T_EN BIT(8)
50 #define ASPEED_I2CD_M_SDA_DRIVE_1T_EN BIT(7)
51 #define ASPEED_I2CD_M_HIGH_SPEED_EN BIT(6)
52 #define ASPEED_I2CD_SLAVE_EN BIT(1)
53 #define ASPEED_I2CD_MASTER_EN BIT(0)
55 /* 0x04 : I2CD Clock and AC Timing Control Register #1 */
56 #define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT 16
57 #define ASPEED_I2CD_TIME_SCL_HIGH_MASK GENMASK(19, 16)
58 #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT 12
59 #define ASPEED_I2CD_TIME_SCL_LOW_MASK GENMASK(15, 12)
60 #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK GENMASK(3, 0)
61 #define ASPEED_I2CD_TIME_SCL_REG_MAX GENMASK(3, 0)
62 /* 0x08 : I2CD Clock and AC Timing Control Register #2 */
63 #define ASPEED_NO_TIMEOUT_CTRL 0
65 /* 0x0c : I2CD Interrupt Control Register &
66 * 0x10 : I2CD Interrupt Status Register
68 * These share bit definitions, so use the same values for the enable &
71 #define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT BIT(14)
72 #define ASPEED_I2CD_INTR_BUS_RECOVER_DONE BIT(13)
73 #define ASPEED_I2CD_INTR_SLAVE_MATCH BIT(7)
74 #define ASPEED_I2CD_INTR_SCL_TIMEOUT BIT(6)
75 #define ASPEED_I2CD_INTR_ABNORMAL BIT(5)
76 #define ASPEED_I2CD_INTR_NORMAL_STOP BIT(4)
77 #define ASPEED_I2CD_INTR_ARBIT_LOSS BIT(3)
78 #define ASPEED_I2CD_INTR_RX_DONE BIT(2)
79 #define ASPEED_I2CD_INTR_TX_NAK BIT(1)
80 #define ASPEED_I2CD_INTR_TX_ACK BIT(0)
81 #define ASPEED_I2CD_INTR_ALL \
82 (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | \
83 ASPEED_I2CD_INTR_BUS_RECOVER_DONE | \
84 ASPEED_I2CD_INTR_SCL_TIMEOUT | \
85 ASPEED_I2CD_INTR_ABNORMAL | \
86 ASPEED_I2CD_INTR_NORMAL_STOP | \
87 ASPEED_I2CD_INTR_ARBIT_LOSS | \
88 ASPEED_I2CD_INTR_RX_DONE | \
89 ASPEED_I2CD_INTR_TX_NAK | \
90 ASPEED_I2CD_INTR_TX_ACK)
92 /* 0x14 : I2CD Command/Status Register */
93 #define ASPEED_I2CD_SCL_LINE_STS BIT(18)
94 #define ASPEED_I2CD_SDA_LINE_STS BIT(17)
95 #define ASPEED_I2CD_BUS_BUSY_STS BIT(16)
96 #define ASPEED_I2CD_BUS_RECOVER_CMD BIT(11)
99 #define ASPEED_I2CD_M_STOP_CMD BIT(5)
100 #define ASPEED_I2CD_M_S_RX_CMD_LAST BIT(4)
101 #define ASPEED_I2CD_M_RX_CMD BIT(3)
102 #define ASPEED_I2CD_S_TX_CMD BIT(2)
103 #define ASPEED_I2CD_M_TX_CMD BIT(1)
104 #define ASPEED_I2CD_M_START_CMD BIT(0)
106 /* 0x18 : I2CD Slave Device Address Register */
107 #define ASPEED_I2CD_DEV_ADDR_MASK GENMASK(6, 0)
109 enum aspeed_i2c_master_state
{
110 ASPEED_I2C_MASTER_START
,
111 ASPEED_I2C_MASTER_TX_FIRST
,
112 ASPEED_I2C_MASTER_TX
,
113 ASPEED_I2C_MASTER_RX_FIRST
,
114 ASPEED_I2C_MASTER_RX
,
115 ASPEED_I2C_MASTER_STOP
,
116 ASPEED_I2C_MASTER_INACTIVE
,
119 enum aspeed_i2c_slave_state
{
120 ASPEED_I2C_SLAVE_START
,
121 ASPEED_I2C_SLAVE_READ_REQUESTED
,
122 ASPEED_I2C_SLAVE_READ_PROCESSED
,
123 ASPEED_I2C_SLAVE_WRITE_REQUESTED
,
124 ASPEED_I2C_SLAVE_WRITE_RECEIVED
,
125 ASPEED_I2C_SLAVE_STOP
,
128 struct aspeed_i2c_bus
{
129 struct i2c_adapter adap
;
132 /* Synchronizes I/O mem access to base. */
134 struct completion cmd_complete
;
135 unsigned long parent_clk_frequency
;
137 /* Transaction state. */
138 enum aspeed_i2c_master_state master_state
;
139 struct i2c_msg
*msgs
;
145 /* Protected only by i2c_lock_bus */
146 int master_xfer_result
;
147 #if IS_ENABLED(CONFIG_I2C_SLAVE)
148 struct i2c_client
*slave
;
149 enum aspeed_i2c_slave_state slave_state
;
150 #endif /* CONFIG_I2C_SLAVE */
153 static int aspeed_i2c_reset(struct aspeed_i2c_bus
*bus
);
155 static int aspeed_i2c_recover_bus(struct aspeed_i2c_bus
*bus
)
157 unsigned long time_left
, flags
;
161 spin_lock_irqsave(&bus
->lock
, flags
);
162 command
= readl(bus
->base
+ ASPEED_I2C_CMD_REG
);
164 if (command
& ASPEED_I2CD_SDA_LINE_STS
) {
165 /* Bus is idle: no recovery needed. */
166 if (command
& ASPEED_I2CD_SCL_LINE_STS
)
168 dev_dbg(bus
->dev
, "SCL hung (state %x), attempting recovery\n",
171 reinit_completion(&bus
->cmd_complete
);
172 writel(ASPEED_I2CD_M_STOP_CMD
, bus
->base
+ ASPEED_I2C_CMD_REG
);
173 spin_unlock_irqrestore(&bus
->lock
, flags
);
175 time_left
= wait_for_completion_timeout(
176 &bus
->cmd_complete
, bus
->adap
.timeout
);
178 spin_lock_irqsave(&bus
->lock
, flags
);
181 else if (bus
->cmd_err
)
183 /* Recovery failed. */
184 else if (!(readl(bus
->base
+ ASPEED_I2C_CMD_REG
) &
185 ASPEED_I2CD_SCL_LINE_STS
))
189 dev_dbg(bus
->dev
, "SDA hung (state %x), attempting recovery\n",
192 reinit_completion(&bus
->cmd_complete
);
193 /* Writes 1 to 8 SCL clock cycles until SDA is released. */
194 writel(ASPEED_I2CD_BUS_RECOVER_CMD
,
195 bus
->base
+ ASPEED_I2C_CMD_REG
);
196 spin_unlock_irqrestore(&bus
->lock
, flags
);
198 time_left
= wait_for_completion_timeout(
199 &bus
->cmd_complete
, bus
->adap
.timeout
);
201 spin_lock_irqsave(&bus
->lock
, flags
);
204 else if (bus
->cmd_err
)
206 /* Recovery failed. */
207 else if (!(readl(bus
->base
+ ASPEED_I2C_CMD_REG
) &
208 ASPEED_I2CD_SDA_LINE_STS
))
213 spin_unlock_irqrestore(&bus
->lock
, flags
);
218 spin_unlock_irqrestore(&bus
->lock
, flags
);
220 return aspeed_i2c_reset(bus
);
223 #if IS_ENABLED(CONFIG_I2C_SLAVE)
224 static bool aspeed_i2c_slave_irq(struct aspeed_i2c_bus
*bus
)
226 u32 command
, irq_status
, status_ack
= 0;
227 struct i2c_client
*slave
= bus
->slave
;
228 bool irq_handled
= true;
231 spin_lock(&bus
->lock
);
237 command
= readl(bus
->base
+ ASPEED_I2C_CMD_REG
);
238 irq_status
= readl(bus
->base
+ ASPEED_I2C_INTR_STS_REG
);
240 /* Slave was requested, restart state machine. */
241 if (irq_status
& ASPEED_I2CD_INTR_SLAVE_MATCH
) {
242 status_ack
|= ASPEED_I2CD_INTR_SLAVE_MATCH
;
243 bus
->slave_state
= ASPEED_I2C_SLAVE_START
;
246 /* Slave is not currently active, irq was for someone else. */
247 if (bus
->slave_state
== ASPEED_I2C_SLAVE_STOP
) {
252 dev_dbg(bus
->dev
, "slave irq status 0x%08x, cmd 0x%08x\n",
253 irq_status
, command
);
255 /* Slave was sent something. */
256 if (irq_status
& ASPEED_I2CD_INTR_RX_DONE
) {
257 value
= readl(bus
->base
+ ASPEED_I2C_BYTE_BUF_REG
) >> 8;
258 /* Handle address frame. */
259 if (bus
->slave_state
== ASPEED_I2C_SLAVE_START
) {
262 ASPEED_I2C_SLAVE_READ_REQUESTED
;
265 ASPEED_I2C_SLAVE_WRITE_REQUESTED
;
267 status_ack
|= ASPEED_I2CD_INTR_RX_DONE
;
270 /* Slave was asked to stop. */
271 if (irq_status
& ASPEED_I2CD_INTR_NORMAL_STOP
) {
272 status_ack
|= ASPEED_I2CD_INTR_NORMAL_STOP
;
273 bus
->slave_state
= ASPEED_I2C_SLAVE_STOP
;
275 if (irq_status
& ASPEED_I2CD_INTR_TX_NAK
) {
276 status_ack
|= ASPEED_I2CD_INTR_TX_NAK
;
277 bus
->slave_state
= ASPEED_I2C_SLAVE_STOP
;
280 switch (bus
->slave_state
) {
281 case ASPEED_I2C_SLAVE_READ_REQUESTED
:
282 if (irq_status
& ASPEED_I2CD_INTR_TX_ACK
)
283 dev_err(bus
->dev
, "Unexpected ACK on read request.\n");
284 bus
->slave_state
= ASPEED_I2C_SLAVE_READ_PROCESSED
;
286 i2c_slave_event(slave
, I2C_SLAVE_READ_REQUESTED
, &value
);
287 writel(value
, bus
->base
+ ASPEED_I2C_BYTE_BUF_REG
);
288 writel(ASPEED_I2CD_S_TX_CMD
, bus
->base
+ ASPEED_I2C_CMD_REG
);
290 case ASPEED_I2C_SLAVE_READ_PROCESSED
:
291 status_ack
|= ASPEED_I2CD_INTR_TX_ACK
;
292 if (!(irq_status
& ASPEED_I2CD_INTR_TX_ACK
))
294 "Expected ACK after processed read.\n");
295 i2c_slave_event(slave
, I2C_SLAVE_READ_PROCESSED
, &value
);
296 writel(value
, bus
->base
+ ASPEED_I2C_BYTE_BUF_REG
);
297 writel(ASPEED_I2CD_S_TX_CMD
, bus
->base
+ ASPEED_I2C_CMD_REG
);
299 case ASPEED_I2C_SLAVE_WRITE_REQUESTED
:
300 bus
->slave_state
= ASPEED_I2C_SLAVE_WRITE_RECEIVED
;
301 i2c_slave_event(slave
, I2C_SLAVE_WRITE_REQUESTED
, &value
);
303 case ASPEED_I2C_SLAVE_WRITE_RECEIVED
:
304 i2c_slave_event(slave
, I2C_SLAVE_WRITE_RECEIVED
, &value
);
306 case ASPEED_I2C_SLAVE_STOP
:
307 i2c_slave_event(slave
, I2C_SLAVE_STOP
, &value
);
310 dev_err(bus
->dev
, "unhandled slave_state: %d\n",
315 if (status_ack
!= irq_status
)
317 "irq handled != irq. expected %x, but was %x\n",
318 irq_status
, status_ack
);
319 writel(status_ack
, bus
->base
+ ASPEED_I2C_INTR_STS_REG
);
322 spin_unlock(&bus
->lock
);
325 #endif /* CONFIG_I2C_SLAVE */
327 /* precondition: bus.lock has been acquired. */
328 static void aspeed_i2c_do_start(struct aspeed_i2c_bus
*bus
)
330 u32 command
= ASPEED_I2CD_M_START_CMD
| ASPEED_I2CD_M_TX_CMD
;
331 struct i2c_msg
*msg
= &bus
->msgs
[bus
->msgs_index
];
332 u8 slave_addr
= msg
->addr
<< 1;
334 bus
->master_state
= ASPEED_I2C_MASTER_START
;
337 if (msg
->flags
& I2C_M_RD
) {
339 command
|= ASPEED_I2CD_M_RX_CMD
;
340 /* Need to let the hardware know to NACK after RX. */
341 if (msg
->len
== 1 && !(msg
->flags
& I2C_M_RECV_LEN
))
342 command
|= ASPEED_I2CD_M_S_RX_CMD_LAST
;
345 writel(slave_addr
, bus
->base
+ ASPEED_I2C_BYTE_BUF_REG
);
346 writel(command
, bus
->base
+ ASPEED_I2C_CMD_REG
);
349 /* precondition: bus.lock has been acquired. */
350 static void aspeed_i2c_do_stop(struct aspeed_i2c_bus
*bus
)
352 bus
->master_state
= ASPEED_I2C_MASTER_STOP
;
353 writel(ASPEED_I2CD_M_STOP_CMD
, bus
->base
+ ASPEED_I2C_CMD_REG
);
356 /* precondition: bus.lock has been acquired. */
357 static void aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus
*bus
)
359 if (bus
->msgs_index
+ 1 < bus
->msgs_count
) {
361 aspeed_i2c_do_start(bus
);
363 aspeed_i2c_do_stop(bus
);
367 static int aspeed_i2c_is_irq_error(u32 irq_status
)
369 if (irq_status
& ASPEED_I2CD_INTR_ARBIT_LOSS
)
371 if (irq_status
& (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT
|
372 ASPEED_I2CD_INTR_SCL_TIMEOUT
))
374 if (irq_status
& (ASPEED_I2CD_INTR_ABNORMAL
))
380 static bool aspeed_i2c_master_irq(struct aspeed_i2c_bus
*bus
)
382 u32 irq_status
, status_ack
= 0, command
= 0;
387 spin_lock(&bus
->lock
);
388 irq_status
= readl(bus
->base
+ ASPEED_I2C_INTR_STS_REG
);
389 /* Ack all interrupt bits. */
390 writel(irq_status
, bus
->base
+ ASPEED_I2C_INTR_STS_REG
);
392 if (irq_status
& ASPEED_I2CD_INTR_BUS_RECOVER_DONE
) {
393 bus
->master_state
= ASPEED_I2C_MASTER_INACTIVE
;
394 status_ack
|= ASPEED_I2CD_INTR_BUS_RECOVER_DONE
;
399 * We encountered an interrupt that reports an error: the hardware
400 * should clear the command queue effectively taking us back to the
403 ret
= aspeed_i2c_is_irq_error(irq_status
);
405 dev_dbg(bus
->dev
, "received error interrupt: 0x%08x",
408 bus
->master_state
= ASPEED_I2C_MASTER_INACTIVE
;
412 /* We are in an invalid state; reset bus to a known state. */
413 if (!bus
->msgs
&& bus
->master_state
!= ASPEED_I2C_MASTER_STOP
) {
414 dev_err(bus
->dev
, "bus in unknown state");
416 aspeed_i2c_do_stop(bus
);
417 goto out_no_complete
;
419 msg
= &bus
->msgs
[bus
->msgs_index
];
422 * START is a special case because we still have to handle a subsequent
423 * TX or RX immediately after we handle it, so we handle it here and
424 * then update the state and handle the new state below.
426 if (bus
->master_state
== ASPEED_I2C_MASTER_START
) {
427 if (unlikely(!(irq_status
& ASPEED_I2CD_INTR_TX_ACK
))) {
428 pr_devel("no slave present at %02x", msg
->addr
);
429 status_ack
|= ASPEED_I2CD_INTR_TX_NAK
;
430 bus
->cmd_err
= -ENXIO
;
431 aspeed_i2c_do_stop(bus
);
432 goto out_no_complete
;
434 status_ack
|= ASPEED_I2CD_INTR_TX_ACK
;
435 if (msg
->len
== 0) { /* SMBUS_QUICK */
436 aspeed_i2c_do_stop(bus
);
437 goto out_no_complete
;
439 if (msg
->flags
& I2C_M_RD
)
440 bus
->master_state
= ASPEED_I2C_MASTER_RX_FIRST
;
442 bus
->master_state
= ASPEED_I2C_MASTER_TX_FIRST
;
445 switch (bus
->master_state
) {
446 case ASPEED_I2C_MASTER_TX
:
447 if (unlikely(irq_status
& ASPEED_I2CD_INTR_TX_NAK
)) {
448 dev_dbg(bus
->dev
, "slave NACKed TX");
449 status_ack
|= ASPEED_I2CD_INTR_TX_NAK
;
451 } else if (unlikely(!(irq_status
& ASPEED_I2CD_INTR_TX_ACK
))) {
452 dev_err(bus
->dev
, "slave failed to ACK TX");
455 status_ack
|= ASPEED_I2CD_INTR_TX_ACK
;
456 /* fallthrough intended */
457 case ASPEED_I2C_MASTER_TX_FIRST
:
458 if (bus
->buf_index
< msg
->len
) {
459 bus
->master_state
= ASPEED_I2C_MASTER_TX
;
460 writel(msg
->buf
[bus
->buf_index
++],
461 bus
->base
+ ASPEED_I2C_BYTE_BUF_REG
);
462 writel(ASPEED_I2CD_M_TX_CMD
,
463 bus
->base
+ ASPEED_I2C_CMD_REG
);
465 aspeed_i2c_next_msg_or_stop(bus
);
467 goto out_no_complete
;
468 case ASPEED_I2C_MASTER_RX_FIRST
:
469 /* RX may not have completed yet (only address cycle) */
470 if (!(irq_status
& ASPEED_I2CD_INTR_RX_DONE
))
471 goto out_no_complete
;
472 /* fallthrough intended */
473 case ASPEED_I2C_MASTER_RX
:
474 if (unlikely(!(irq_status
& ASPEED_I2CD_INTR_RX_DONE
))) {
475 dev_err(bus
->dev
, "master failed to RX");
478 status_ack
|= ASPEED_I2CD_INTR_RX_DONE
;
480 recv_byte
= readl(bus
->base
+ ASPEED_I2C_BYTE_BUF_REG
) >> 8;
481 msg
->buf
[bus
->buf_index
++] = recv_byte
;
483 if (msg
->flags
& I2C_M_RECV_LEN
) {
484 if (unlikely(recv_byte
> I2C_SMBUS_BLOCK_MAX
)) {
485 bus
->cmd_err
= -EPROTO
;
486 aspeed_i2c_do_stop(bus
);
487 goto out_no_complete
;
489 msg
->len
= recv_byte
+
490 ((msg
->flags
& I2C_CLIENT_PEC
) ? 2 : 1);
491 msg
->flags
&= ~I2C_M_RECV_LEN
;
494 if (bus
->buf_index
< msg
->len
) {
495 bus
->master_state
= ASPEED_I2C_MASTER_RX
;
496 command
= ASPEED_I2CD_M_RX_CMD
;
497 if (bus
->buf_index
+ 1 == msg
->len
)
498 command
|= ASPEED_I2CD_M_S_RX_CMD_LAST
;
499 writel(command
, bus
->base
+ ASPEED_I2C_CMD_REG
);
501 aspeed_i2c_next_msg_or_stop(bus
);
503 goto out_no_complete
;
504 case ASPEED_I2C_MASTER_STOP
:
505 if (unlikely(!(irq_status
& ASPEED_I2CD_INTR_NORMAL_STOP
))) {
506 dev_err(bus
->dev
, "master failed to STOP");
508 /* Do not STOP as we have already tried. */
510 status_ack
|= ASPEED_I2CD_INTR_NORMAL_STOP
;
513 bus
->master_state
= ASPEED_I2C_MASTER_INACTIVE
;
515 case ASPEED_I2C_MASTER_INACTIVE
:
517 "master received interrupt 0x%08x, but is inactive",
520 /* Do not STOP as we should be inactive. */
523 WARN(1, "unknown master state\n");
524 bus
->master_state
= ASPEED_I2C_MASTER_INACTIVE
;
525 bus
->cmd_err
= -EINVAL
;
530 aspeed_i2c_do_stop(bus
);
531 goto out_no_complete
;
535 bus
->master_xfer_result
= bus
->cmd_err
;
537 bus
->master_xfer_result
= bus
->msgs_index
+ 1;
538 complete(&bus
->cmd_complete
);
540 if (irq_status
!= status_ack
)
542 "irq handled != irq. expected 0x%08x, but was 0x%08x\n",
543 irq_status
, status_ack
);
544 spin_unlock(&bus
->lock
);
548 static irqreturn_t
aspeed_i2c_bus_irq(int irq
, void *dev_id
)
550 struct aspeed_i2c_bus
*bus
= dev_id
;
552 #if IS_ENABLED(CONFIG_I2C_SLAVE)
553 if (aspeed_i2c_slave_irq(bus
)) {
554 dev_dbg(bus
->dev
, "irq handled by slave.\n");
557 #endif /* CONFIG_I2C_SLAVE */
559 return aspeed_i2c_master_irq(bus
) ? IRQ_HANDLED
: IRQ_NONE
;
562 static int aspeed_i2c_master_xfer(struct i2c_adapter
*adap
,
563 struct i2c_msg
*msgs
, int num
)
565 struct aspeed_i2c_bus
*bus
= i2c_get_adapdata(adap
);
566 unsigned long time_left
, flags
;
569 spin_lock_irqsave(&bus
->lock
, flags
);
572 /* If bus is busy, attempt recovery. We assume a single master
575 if (readl(bus
->base
+ ASPEED_I2C_CMD_REG
) & ASPEED_I2CD_BUS_BUSY_STS
) {
576 spin_unlock_irqrestore(&bus
->lock
, flags
);
577 ret
= aspeed_i2c_recover_bus(bus
);
580 spin_lock_irqsave(&bus
->lock
, flags
);
586 bus
->msgs_count
= num
;
588 reinit_completion(&bus
->cmd_complete
);
589 aspeed_i2c_do_start(bus
);
590 spin_unlock_irqrestore(&bus
->lock
, flags
);
592 time_left
= wait_for_completion_timeout(&bus
->cmd_complete
,
598 return bus
->master_xfer_result
;
601 static u32
aspeed_i2c_functionality(struct i2c_adapter
*adap
)
603 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
| I2C_FUNC_SMBUS_BLOCK_DATA
;
606 #if IS_ENABLED(CONFIG_I2C_SLAVE)
607 /* precondition: bus.lock has been acquired. */
608 static void __aspeed_i2c_reg_slave(struct aspeed_i2c_bus
*bus
, u16 slave_addr
)
610 u32 addr_reg_val
, func_ctrl_reg_val
;
612 /* Set slave addr. */
613 addr_reg_val
= readl(bus
->base
+ ASPEED_I2C_DEV_ADDR_REG
);
614 addr_reg_val
&= ~ASPEED_I2CD_DEV_ADDR_MASK
;
615 addr_reg_val
|= slave_addr
& ASPEED_I2CD_DEV_ADDR_MASK
;
616 writel(addr_reg_val
, bus
->base
+ ASPEED_I2C_DEV_ADDR_REG
);
618 /* Turn on slave mode. */
619 func_ctrl_reg_val
= readl(bus
->base
+ ASPEED_I2C_FUN_CTRL_REG
);
620 func_ctrl_reg_val
|= ASPEED_I2CD_SLAVE_EN
;
621 writel(func_ctrl_reg_val
, bus
->base
+ ASPEED_I2C_FUN_CTRL_REG
);
624 static int aspeed_i2c_reg_slave(struct i2c_client
*client
)
626 struct aspeed_i2c_bus
*bus
= i2c_get_adapdata(client
->adapter
);
629 spin_lock_irqsave(&bus
->lock
, flags
);
631 spin_unlock_irqrestore(&bus
->lock
, flags
);
635 __aspeed_i2c_reg_slave(bus
, client
->addr
);
638 bus
->slave_state
= ASPEED_I2C_SLAVE_STOP
;
639 spin_unlock_irqrestore(&bus
->lock
, flags
);
644 static int aspeed_i2c_unreg_slave(struct i2c_client
*client
)
646 struct aspeed_i2c_bus
*bus
= i2c_get_adapdata(client
->adapter
);
647 u32 func_ctrl_reg_val
;
650 spin_lock_irqsave(&bus
->lock
, flags
);
652 spin_unlock_irqrestore(&bus
->lock
, flags
);
656 /* Turn off slave mode. */
657 func_ctrl_reg_val
= readl(bus
->base
+ ASPEED_I2C_FUN_CTRL_REG
);
658 func_ctrl_reg_val
&= ~ASPEED_I2CD_SLAVE_EN
;
659 writel(func_ctrl_reg_val
, bus
->base
+ ASPEED_I2C_FUN_CTRL_REG
);
662 spin_unlock_irqrestore(&bus
->lock
, flags
);
666 #endif /* CONFIG_I2C_SLAVE */
668 static const struct i2c_algorithm aspeed_i2c_algo
= {
669 .master_xfer
= aspeed_i2c_master_xfer
,
670 .functionality
= aspeed_i2c_functionality
,
671 #if IS_ENABLED(CONFIG_I2C_SLAVE)
672 .reg_slave
= aspeed_i2c_reg_slave
,
673 .unreg_slave
= aspeed_i2c_unreg_slave
,
674 #endif /* CONFIG_I2C_SLAVE */
677 static u32
aspeed_i2c_get_clk_reg_val(u32 divisor
)
679 u32 base_clk
, clk_high
, clk_low
, tmp
;
682 * The actual clock frequency of SCL is:
683 * SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low))
684 * = APB_freq / divisor
685 * where base_freq is a programmable clock divider; its value is
686 * base_freq = 1 << base_clk
687 * SCL_high is the number of base_freq clock cycles that SCL stays high
688 * and SCL_low is the number of base_freq clock cycles that SCL stays
689 * low for a period of SCL.
690 * The actual register has a minimum SCL_high and SCL_low minimum of 1;
691 * thus, they start counting at zero. So
692 * SCL_high = clk_high + 1
693 * SCL_low = clk_low + 1
695 * SCL_freq = APB_freq /
696 * ((1 << base_clk) * (clk_high + 1 + clk_low + 1))
697 * The documentation recommends clk_high >= 8 and clk_low >= 7 when
698 * possible; this last constraint gives us the following solution:
700 base_clk
= divisor
> 33 ? ilog2((divisor
- 1) / 32) + 1 : 0;
701 tmp
= divisor
/ (1 << base_clk
);
702 clk_high
= tmp
/ 2 + tmp
% 2;
703 clk_low
= tmp
- clk_high
;
708 return ((clk_high
<< ASPEED_I2CD_TIME_SCL_HIGH_SHIFT
)
709 & ASPEED_I2CD_TIME_SCL_HIGH_MASK
)
710 | ((clk_low
<< ASPEED_I2CD_TIME_SCL_LOW_SHIFT
)
711 & ASPEED_I2CD_TIME_SCL_LOW_MASK
)
712 | (base_clk
& ASPEED_I2CD_TIME_BASE_DIVISOR_MASK
);
715 /* precondition: bus.lock has been acquired. */
716 static int aspeed_i2c_init_clk(struct aspeed_i2c_bus
*bus
)
718 u32 divisor
, clk_reg_val
;
720 divisor
= bus
->parent_clk_frequency
/ bus
->bus_frequency
;
721 clk_reg_val
= aspeed_i2c_get_clk_reg_val(divisor
);
722 writel(clk_reg_val
, bus
->base
+ ASPEED_I2C_AC_TIMING_REG1
);
723 writel(ASPEED_NO_TIMEOUT_CTRL
, bus
->base
+ ASPEED_I2C_AC_TIMING_REG2
);
728 /* precondition: bus.lock has been acquired. */
729 static int aspeed_i2c_init(struct aspeed_i2c_bus
*bus
,
730 struct platform_device
*pdev
)
732 u32 fun_ctrl_reg
= ASPEED_I2CD_MASTER_EN
;
735 /* Disable everything. */
736 writel(0, bus
->base
+ ASPEED_I2C_FUN_CTRL_REG
);
738 ret
= aspeed_i2c_init_clk(bus
);
742 if (!of_property_read_bool(pdev
->dev
.of_node
, "multi-master"))
743 fun_ctrl_reg
|= ASPEED_I2CD_MULTI_MASTER_DIS
;
745 /* Enable Master Mode */
746 writel(readl(bus
->base
+ ASPEED_I2C_FUN_CTRL_REG
) | fun_ctrl_reg
,
747 bus
->base
+ ASPEED_I2C_FUN_CTRL_REG
);
749 #if IS_ENABLED(CONFIG_I2C_SLAVE)
750 /* If slave has already been registered, re-enable it. */
752 __aspeed_i2c_reg_slave(bus
, bus
->slave
->addr
);
753 #endif /* CONFIG_I2C_SLAVE */
755 /* Set interrupt generation of I2C controller */
756 writel(ASPEED_I2CD_INTR_ALL
, bus
->base
+ ASPEED_I2C_INTR_CTRL_REG
);
761 static int aspeed_i2c_reset(struct aspeed_i2c_bus
*bus
)
763 struct platform_device
*pdev
= to_platform_device(bus
->dev
);
767 spin_lock_irqsave(&bus
->lock
, flags
);
769 /* Disable and ack all interrupts. */
770 writel(0, bus
->base
+ ASPEED_I2C_INTR_CTRL_REG
);
771 writel(0xffffffff, bus
->base
+ ASPEED_I2C_INTR_STS_REG
);
773 ret
= aspeed_i2c_init(bus
, pdev
);
775 spin_unlock_irqrestore(&bus
->lock
, flags
);
780 static int aspeed_i2c_probe_bus(struct platform_device
*pdev
)
782 struct aspeed_i2c_bus
*bus
;
783 struct clk
*parent_clk
;
784 struct resource
*res
;
787 bus
= devm_kzalloc(&pdev
->dev
, sizeof(*bus
), GFP_KERNEL
);
791 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
792 bus
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
793 if (IS_ERR(bus
->base
))
794 return PTR_ERR(bus
->base
);
796 parent_clk
= devm_clk_get(&pdev
->dev
, NULL
);
797 if (IS_ERR(parent_clk
))
798 return PTR_ERR(parent_clk
);
799 bus
->parent_clk_frequency
= clk_get_rate(parent_clk
);
800 /* We just need the clock rate, we don't actually use the clk object. */
801 devm_clk_put(&pdev
->dev
, parent_clk
);
803 ret
= of_property_read_u32(pdev
->dev
.of_node
,
804 "bus-frequency", &bus
->bus_frequency
);
807 "Could not read bus-frequency property\n");
808 bus
->bus_frequency
= 100000;
811 /* Initialize the I2C adapter */
812 spin_lock_init(&bus
->lock
);
813 init_completion(&bus
->cmd_complete
);
814 bus
->adap
.owner
= THIS_MODULE
;
815 bus
->adap
.retries
= 0;
816 bus
->adap
.timeout
= 5 * HZ
;
817 bus
->adap
.algo
= &aspeed_i2c_algo
;
818 bus
->adap
.dev
.parent
= &pdev
->dev
;
819 bus
->adap
.dev
.of_node
= pdev
->dev
.of_node
;
820 strlcpy(bus
->adap
.name
, pdev
->name
, sizeof(bus
->adap
.name
));
821 i2c_set_adapdata(&bus
->adap
, bus
);
823 bus
->dev
= &pdev
->dev
;
825 /* Clean up any left over interrupt state. */
826 writel(0, bus
->base
+ ASPEED_I2C_INTR_CTRL_REG
);
827 writel(0xffffffff, bus
->base
+ ASPEED_I2C_INTR_STS_REG
);
829 * bus.lock does not need to be held because the interrupt handler has
830 * not been enabled yet.
832 ret
= aspeed_i2c_init(bus
, pdev
);
836 irq
= irq_of_parse_and_map(pdev
->dev
.of_node
, 0);
837 ret
= devm_request_irq(&pdev
->dev
, irq
, aspeed_i2c_bus_irq
,
838 0, dev_name(&pdev
->dev
), bus
);
842 ret
= i2c_add_adapter(&bus
->adap
);
846 platform_set_drvdata(pdev
, bus
);
848 dev_info(bus
->dev
, "i2c bus %d registered, irq %d\n",
854 static int aspeed_i2c_remove_bus(struct platform_device
*pdev
)
856 struct aspeed_i2c_bus
*bus
= platform_get_drvdata(pdev
);
859 spin_lock_irqsave(&bus
->lock
, flags
);
861 /* Disable everything. */
862 writel(0, bus
->base
+ ASPEED_I2C_FUN_CTRL_REG
);
863 writel(0, bus
->base
+ ASPEED_I2C_INTR_CTRL_REG
);
865 spin_unlock_irqrestore(&bus
->lock
, flags
);
867 i2c_del_adapter(&bus
->adap
);
872 static const struct of_device_id aspeed_i2c_bus_of_table
[] = {
873 { .compatible
= "aspeed,ast2400-i2c-bus", },
874 { .compatible
= "aspeed,ast2500-i2c-bus", },
877 MODULE_DEVICE_TABLE(of
, aspeed_i2c_bus_of_table
);
879 static struct platform_driver aspeed_i2c_bus_driver
= {
880 .probe
= aspeed_i2c_probe_bus
,
881 .remove
= aspeed_i2c_remove_bus
,
883 .name
= "aspeed-i2c-bus",
884 .of_match_table
= aspeed_i2c_bus_of_table
,
887 module_platform_driver(aspeed_i2c_bus_driver
);
889 MODULE_AUTHOR("Brendan Higgins <brendanhiggins@google.com>");
890 MODULE_DESCRIPTION("Aspeed I2C Bus Driver");
891 MODULE_LICENSE("GPL v2");