drivers/i2c/busses/i2c-bcm-iproc.c

   1 /*
   2  * Copyright (C) 2014 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/i2c.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22
  23 #define CFG_OFFSET                   0x00
  24 #define CFG_RESET_SHIFT              31
  25 #define CFG_EN_SHIFT                 30
  26 #define CFG_M_RETRY_CNT_SHIFT        16
  27 #define CFG_M_RETRY_CNT_MASK         0x0f
  28
  29 #define TIM_CFG_OFFSET               0x04
  30 #define TIM_CFG_MODE_400_SHIFT       31
  31
  32 #define M_FIFO_CTRL_OFFSET           0x0c
  33 #define M_FIFO_RX_FLUSH_SHIFT        31
  34 #define M_FIFO_TX_FLUSH_SHIFT        30
  35 #define M_FIFO_RX_CNT_SHIFT          16
  36 #define M_FIFO_RX_CNT_MASK           0x7f
  37 #define M_FIFO_RX_THLD_SHIFT         8
  38 #define M_FIFO_RX_THLD_MASK          0x3f
  39
  40 #define M_CMD_OFFSET                 0x30
  41 #define M_CMD_START_BUSY_SHIFT       31
  42 #define M_CMD_STATUS_SHIFT           25
  43 #define M_CMD_STATUS_MASK            0x07
  44 #define M_CMD_STATUS_SUCCESS         0x0
  45 #define M_CMD_STATUS_LOST_ARB        0x1
  46 #define M_CMD_STATUS_NACK_ADDR       0x2
  47 #define M_CMD_STATUS_NACK_DATA       0x3
  48 #define M_CMD_STATUS_TIMEOUT         0x4
  49 #define M_CMD_PROTOCOL_SHIFT         9
  50 #define M_CMD_PROTOCOL_MASK          0xf
  51 #define M_CMD_PROTOCOL_BLK_WR        0x7
  52 #define M_CMD_PROTOCOL_BLK_RD        0x8
  53 #define M_CMD_PEC_SHIFT              8
  54 #define M_CMD_RD_CNT_SHIFT           0
  55 #define M_CMD_RD_CNT_MASK            0xff
  56
  57 #define IE_OFFSET                    0x38
  58 #define IE_M_RX_FIFO_FULL_SHIFT      31
  59 #define IE_M_RX_THLD_SHIFT           30
  60 #define IE_M_START_BUSY_SHIFT        28
  61 #define IE_M_TX_UNDERRUN_SHIFT       27
  62
  63 #define IS_OFFSET                    0x3c
  64 #define IS_M_RX_FIFO_FULL_SHIFT      31
  65 #define IS_M_RX_THLD_SHIFT           30
  66 #define IS_M_START_BUSY_SHIFT        28
  67 #define IS_M_TX_UNDERRUN_SHIFT       27
  68
  69 #define M_TX_OFFSET                  0x40
  70 #define M_TX_WR_STATUS_SHIFT         31
  71 #define M_TX_DATA_SHIFT              0
  72 #define M_TX_DATA_MASK               0xff
  73
  74 #define M_RX_OFFSET                  0x44
  75 #define M_RX_STATUS_SHIFT            30
  76 #define M_RX_STATUS_MASK             0x03
  77 #define M_RX_PEC_ERR_SHIFT           29
  78 #define M_RX_DATA_SHIFT              0
  79 #define M_RX_DATA_MASK               0xff
  80
  81 #define I2C_TIMEOUT_MSEC             50000
  82 #define M_TX_RX_FIFO_SIZE            64
  83
  84 enum bus_speed_index {
  85         I2C_SPD_100K = 0,
  86         I2C_SPD_400K,
  87 };
  88
  89 struct bcm_iproc_i2c_dev {
  90         struct device *device;
  91         int irq;
  92
  93         void __iomem *base;
  94
  95         struct i2c_adapter adapter;
  96         unsigned int bus_speed;
  97
  98         struct completion done;
  99         int xfer_is_done;
 100
 101         struct i2c_msg *msg;
 102
 103         /* bytes that have been transferred */
 104         unsigned int tx_bytes;
 105 };
 106
 107 /*
 108  * Can be expanded in the future if more interrupt status bits are utilized
 109  */
 110 #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT))
 111
 112 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
 113 {
 114         struct bcm_iproc_i2c_dev *iproc_i2c = data;
 115         u32 status = readl(iproc_i2c->base + IS_OFFSET);
 116
 117         status &= ISR_MASK;
 118
 119         if (!status)
 120                 return IRQ_NONE;
 121
 122         /* TX FIFO is empty and we have more data to send */
 123         if (status & BIT(IS_M_TX_UNDERRUN_SHIFT)) {
 124                 struct i2c_msg *msg = iproc_i2c->msg;
 125                 unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
 126                 unsigned int i;
 127                 u32 val;
 128
 129                 /* can only fill up to the FIFO size */
 130                 tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
 131                 for (i = 0; i < tx_bytes; i++) {
 132                         /* start from where we left over */
 133                         unsigned int idx = iproc_i2c->tx_bytes + i;
 134
 135                         val = msg->buf[idx];
 136
 137                         /* mark the last byte */
 138                         if (idx == msg->len - 1) {
 139                                 u32 tmp;
 140
 141                                 val |= BIT(M_TX_WR_STATUS_SHIFT);
 142
 143                                 /*
 144                                  * Since this is the last byte, we should
 145                                  * now disable TX FIFO underrun interrupt
 146                                  */
 147                                 tmp = readl(iproc_i2c->base + IE_OFFSET);
 148                                 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
 149                                 writel(tmp, iproc_i2c->base + IE_OFFSET);
 150                         }
 151
 152                         /* load data into TX FIFO */
 153                         writel(val, iproc_i2c->base + M_TX_OFFSET);
 154                 }
 155                 /* update number of transferred bytes */
 156                 iproc_i2c->tx_bytes += tx_bytes;
 157         }
 158
 159         if (status & BIT(IS_M_START_BUSY_SHIFT)) {
 160                 iproc_i2c->xfer_is_done = 1;
 161                 complete(&iproc_i2c->done);
 162         }
 163
 164         writel(status, iproc_i2c->base + IS_OFFSET);
 165
 166         return IRQ_HANDLED;
 167 }
 168
 169 static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
 170 {
 171         u32 val;
 172
 173         /* put controller in reset */
 174         val = readl(iproc_i2c->base + CFG_OFFSET);
 175         val |= 1 << CFG_RESET_SHIFT;
 176         val &= ~(1 << CFG_EN_SHIFT);
 177         writel(val, iproc_i2c->base + CFG_OFFSET);
 178
 179         /* wait 100 usec per spec */
 180         udelay(100);
 181
 182         /* bring controller out of reset */
 183         val &= ~(1 << CFG_RESET_SHIFT);
 184         writel(val, iproc_i2c->base + CFG_OFFSET);
 185
 186         /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
 187         val = (1 << M_FIFO_RX_FLUSH_SHIFT) | (1 << M_FIFO_TX_FLUSH_SHIFT);
 188         writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
 189         /* disable all interrupts */
 190         writel(0, iproc_i2c->base + IE_OFFSET);
 191
 192         /* clear all pending interrupts */
 193         writel(0xffffffff, iproc_i2c->base + IS_OFFSET);
 194
 195         return 0;
 196 }
 197
 198 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
 199                                          bool enable)
 200 {
 201         u32 val;
 202
 203         val = readl(iproc_i2c->base + CFG_OFFSET);
 204         if (enable)
 205                 val |= BIT(CFG_EN_SHIFT);
 206         else
 207                 val &= ~BIT(CFG_EN_SHIFT);
 208         writel(val, iproc_i2c->base + CFG_OFFSET);
 209 }
 210
 211 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
 212                                       struct i2c_msg *msg)
 213 {
 214         u32 val;
 215
 216         val = readl(iproc_i2c->base + M_CMD_OFFSET);
 217         val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
 218
 219         switch (val) {
 220         case M_CMD_STATUS_SUCCESS:
 221                 return 0;
 222
 223         case M_CMD_STATUS_LOST_ARB:
 224                 dev_dbg(iproc_i2c->device, "lost bus arbitration\n");
 225                 return -EAGAIN;
 226
 227         case M_CMD_STATUS_NACK_ADDR:
 228                 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
 229                 return -ENXIO;
 230
 231         case M_CMD_STATUS_NACK_DATA:
 232                 dev_dbg(iproc_i2c->device, "NAK data\n");
 233                 return -ENXIO;
 234
 235         case M_CMD_STATUS_TIMEOUT:
 236                 dev_dbg(iproc_i2c->device, "bus timeout\n");
 237                 return -ETIMEDOUT;
 238
 239         default:
 240                 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
 241
 242                 /* re-initialize i2c for recovery */
 243                 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 244                 bcm_iproc_i2c_init(iproc_i2c);
 245                 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 246
 247                 return -EIO;
 248         }
 249 }
 250
 251 static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c,
 252                                          struct i2c_msg *msg)
 253 {
 254         int ret, i;
 255         u8 addr;
 256         u32 val;
 257         unsigned int tx_bytes;
 258         unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
 259
 260         /* check if bus is busy */
 261         if (!!(readl(iproc_i2c->base + M_CMD_OFFSET) &
 262                BIT(M_CMD_START_BUSY_SHIFT))) {
 263                 dev_warn(iproc_i2c->device, "bus is busy\n");
 264                 return -EBUSY;
 265         }
 266
 267         iproc_i2c->msg = msg;
 268
 269         /* format and load slave address into the TX FIFO */
 270         addr = i2c_8bit_addr_from_msg(msg);
 271         writel(addr, iproc_i2c->base + M_TX_OFFSET);
 272
 273         /*
 274          * For a write transaction, load data into the TX FIFO. Only allow
 275          * loading up to TX FIFO size - 1 bytes of data since the first byte
 276          * has been used up by the slave address
 277          */
 278         tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1);
 279         if (!(msg->flags & I2C_M_RD)) {
 280                 for (i = 0; i < tx_bytes; i++) {
 281                         val = msg->buf[i];
 282
 283                         /* mark the last byte */
 284                         if (i == msg->len - 1)
 285                                 val |= 1 << M_TX_WR_STATUS_SHIFT;
 286
 287                         writel(val, iproc_i2c->base + M_TX_OFFSET);
 288                 }
 289                 iproc_i2c->tx_bytes = tx_bytes;
 290         }
 291
 292         /* mark as incomplete before starting the transaction */
 293         reinit_completion(&iproc_i2c->done);
 294         iproc_i2c->xfer_is_done = 0;
 295
 296         /*
 297          * Enable the "start busy" interrupt, which will be triggered after the
 298          * transaction is done, i.e., the internal start_busy bit, transitions
 299          * from 1 to 0.
 300          */
 301         val = BIT(IE_M_START_BUSY_SHIFT);
 302
 303         /*
 304          * If TX data size is larger than the TX FIFO, need to enable TX
 305          * underrun interrupt, which will be triggerred when the TX FIFO is
 306          * empty. When that happens we can then pump more data into the FIFO
 307          */
 308         if (!(msg->flags & I2C_M_RD) &&
 309             msg->len > iproc_i2c->tx_bytes)
 310                 val |= BIT(IE_M_TX_UNDERRUN_SHIFT);
 311
 312         writel(val, iproc_i2c->base + IE_OFFSET);
 313
 314         /*
 315          * Now we can activate the transfer. For a read operation, specify the
 316          * number of bytes to read
 317          */
 318         val = BIT(M_CMD_START_BUSY_SHIFT);
 319         if (msg->flags & I2C_M_RD) {
 320                 val |= (M_CMD_PROTOCOL_BLK_RD << M_CMD_PROTOCOL_SHIFT) |
 321                        (msg->len << M_CMD_RD_CNT_SHIFT);
 322         } else {
 323                 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
 324         }
 325         writel(val, iproc_i2c->base + M_CMD_OFFSET);
 326
 327         time_left = wait_for_completion_timeout(&iproc_i2c->done, time_left);
 328
 329         /* disable all interrupts */
 330         writel(0, iproc_i2c->base + IE_OFFSET);
 331         /* read it back to flush the write */
 332         readl(iproc_i2c->base + IE_OFFSET);
 333
 334         /* make sure the interrupt handler isn't running */
 335         synchronize_irq(iproc_i2c->irq);
 336
 337         if (!time_left && !iproc_i2c->xfer_is_done) {
 338                 dev_err(iproc_i2c->device, "transaction timed out\n");
 339
 340                 /* flush FIFOs */
 341                 val = (1 << M_FIFO_RX_FLUSH_SHIFT) |
 342                       (1 << M_FIFO_TX_FLUSH_SHIFT);
 343                 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
 344                 return -ETIMEDOUT;
 345         }
 346
 347         ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
 348         if (ret) {
 349                 /* flush both TX/RX FIFOs */
 350                 val = (1 << M_FIFO_RX_FLUSH_SHIFT) |
 351                       (1 << M_FIFO_TX_FLUSH_SHIFT);
 352                 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
 353                 return ret;
 354         }
 355
 356         /*
 357          * For a read operation, we now need to load the data from FIFO
 358          * into the memory buffer
 359          */
 360         if (msg->flags & I2C_M_RD) {
 361                 for (i = 0; i < msg->len; i++) {
 362                         msg->buf[i] = (readl(iproc_i2c->base + M_RX_OFFSET) >>
 363                                       M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
 364                 }
 365         }
 366
 367         return 0;
 368 }
 369
 370 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
 371                               struct i2c_msg msgs[], int num)
 372 {
 373         struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
 374         int ret, i;
 375
 376         /* go through all messages */
 377         for (i = 0; i < num; i++) {
 378                 ret = bcm_iproc_i2c_xfer_single_msg(iproc_i2c, &msgs[i]);
 379                 if (ret) {
 380                         dev_dbg(iproc_i2c->device, "xfer failed\n");
 381                         return ret;
 382                 }
 383         }
 384
 385         return num;
 386 }
 387
 388 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
 389 {
 390         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 391 }
 392
 393 static const struct i2c_algorithm bcm_iproc_algo = {
 394         .master_xfer = bcm_iproc_i2c_xfer,
 395         .functionality = bcm_iproc_i2c_functionality,
 396 };
 397
 398 static struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
 399         /* need to reserve one byte in the FIFO for the slave address */
 400         .max_read_len = M_TX_RX_FIFO_SIZE - 1,
 401 };
 402
 403 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
 404 {
 405         unsigned int bus_speed;
 406         u32 val;
 407         int ret = of_property_read_u32(iproc_i2c->device->of_node,
 408                                        "clock-frequency", &bus_speed);
 409         if (ret < 0) {
 410                 dev_info(iproc_i2c->device,
 411                         "unable to interpret clock-frequency DT property\n");
 412                 bus_speed = 100000;
 413         }
 414
 415         if (bus_speed < 100000) {
 416                 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
 417                         bus_speed);
 418                 dev_err(iproc_i2c->device,
 419                         "valid speeds are 100khz and 400khz\n");
 420                 return -EINVAL;
 421         } else if (bus_speed < 400000) {
 422                 bus_speed = 100000;
 423         } else {
 424                 bus_speed = 400000;
 425         }
 426
 427         iproc_i2c->bus_speed = bus_speed;
 428         val = readl(iproc_i2c->base + TIM_CFG_OFFSET);
 429         val &= ~(1 << TIM_CFG_MODE_400_SHIFT);
 430         val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
 431         writel(val, iproc_i2c->base + TIM_CFG_OFFSET);
 432
 433         dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
 434
 435         return 0;
 436 }
 437
 438 static int bcm_iproc_i2c_probe(struct platform_device *pdev)
 439 {
 440         int irq, ret = 0;
 441         struct bcm_iproc_i2c_dev *iproc_i2c;
 442         struct i2c_adapter *adap;
 443         struct resource *res;
 444
 445         iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
 446                                  GFP_KERNEL);
 447         if (!iproc_i2c)
 448                 return -ENOMEM;
 449
 450         platform_set_drvdata(pdev, iproc_i2c);
 451         iproc_i2c->device = &pdev->dev;
 452         init_completion(&iproc_i2c->done);
 453
 454         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 455         iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
 456         if (IS_ERR(iproc_i2c->base))
 457                 return PTR_ERR(iproc_i2c->base);
 458
 459         ret = bcm_iproc_i2c_init(iproc_i2c);
 460         if (ret)
 461                 return ret;
 462
 463         ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
 464         if (ret)
 465                 return ret;
 466
 467         irq = platform_get_irq(pdev, 0);
 468         if (irq <= 0) {
 469                 dev_err(iproc_i2c->device, "no irq resource\n");
 470                 return irq;
 471         }
 472         iproc_i2c->irq = irq;
 473
 474         ret = devm_request_irq(iproc_i2c->device, irq, bcm_iproc_i2c_isr, 0,
 475                                pdev->name, iproc_i2c);
 476         if (ret < 0) {
 477                 dev_err(iproc_i2c->device, "unable to request irq %i\n", irq);
 478                 return ret;
 479         }
 480
 481         bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 482
 483         adap = &iproc_i2c->adapter;
 484         i2c_set_adapdata(adap, iproc_i2c);
 485         strlcpy(adap->name, "Broadcom iProc I2C adapter", sizeof(adap->name));
 486         adap->algo = &bcm_iproc_algo;
 487         adap->quirks = &bcm_iproc_i2c_quirks;
 488         adap->dev.parent = &pdev->dev;
 489         adap->dev.of_node = pdev->dev.of_node;
 490
 491         ret = i2c_add_adapter(adap);
 492         if (ret) {
 493                 dev_err(iproc_i2c->device, "failed to add adapter\n");
 494                 return ret;
 495         }
 496
 497         return 0;
 498 }
 499
 500 static int bcm_iproc_i2c_remove(struct platform_device *pdev)
 501 {
 502         struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
 503
 504         /* make sure there's no pending interrupt when we remove the adapter */
 505         writel(0, iproc_i2c->base + IE_OFFSET);
 506         readl(iproc_i2c->base + IE_OFFSET);
 507         synchronize_irq(iproc_i2c->irq);
 508
 509         i2c_del_adapter(&iproc_i2c->adapter);
 510         bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 511
 512         return 0;
 513 }
 514
 515 #ifdef CONFIG_PM_SLEEP
 516
 517 static int bcm_iproc_i2c_suspend(struct device *dev)
 518 {
 519         struct platform_device *pdev = to_platform_device(dev);
 520         struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
 521
 522         /* make sure there's no pending interrupt when we go into suspend */
 523         writel(0, iproc_i2c->base + IE_OFFSET);
 524         readl(iproc_i2c->base + IE_OFFSET);
 525         synchronize_irq(iproc_i2c->irq);
 526
 527         /* now disable the controller */
 528         bcm_iproc_i2c_enable_disable(iproc_i2c, false);
 529
 530         return 0;
 531 }
 532
 533 static int bcm_iproc_i2c_resume(struct device *dev)
 534 {
 535         struct platform_device *pdev = to_platform_device(dev);
 536         struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
 537         int ret;
 538         u32 val;
 539
 540         /*
 541          * Power domain could have been shut off completely in system deep
 542          * sleep, so re-initialize the block here
 543          */
 544         ret = bcm_iproc_i2c_init(iproc_i2c);
 545         if (ret)
 546                 return ret;
 547
 548         /* configure to the desired bus speed */
 549         val = readl(iproc_i2c->base + TIM_CFG_OFFSET);
 550         val &= ~(1 << TIM_CFG_MODE_400_SHIFT);
 551         val |= (iproc_i2c->bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
 552         writel(val, iproc_i2c->base + TIM_CFG_OFFSET);
 553
 554         bcm_iproc_i2c_enable_disable(iproc_i2c, true);
 555
 556         return 0;
 557 }
 558
 559 static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
 560         .suspend_late = &bcm_iproc_i2c_suspend,
 561         .resume_early = &bcm_iproc_i2c_resume
 562 };
 563
 564 #define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops)
 565 #else
 566 #define BCM_IPROC_I2C_PM_OPS NULL
 567 #endif /* CONFIG_PM_SLEEP */
 568
 569 static const struct of_device_id bcm_iproc_i2c_of_match[] = {
 570         { .compatible = "brcm,iproc-i2c" },
 571         { /* sentinel */ }
 572 };
 573 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
 574
 575 static struct platform_driver bcm_iproc_i2c_driver = {
 576         .driver = {
 577                 .name = "bcm-iproc-i2c",
 578                 .of_match_table = bcm_iproc_i2c_of_match,
 579                 .pm = BCM_IPROC_I2C_PM_OPS,
 580         },
 581         .probe = bcm_iproc_i2c_probe,
 582         .remove = bcm_iproc_i2c_remove,
 583 };
 584 module_platform_driver(bcm_iproc_i2c_driver);
 585
 586 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
 587 MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
 588 MODULE_LICENSE("GPL v2");