2 * I2C bus driver for the Cadence I2C controller.
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/i2c.h>
16 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
23 /* Register offsets for the I2C device. */
24 #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */
25 #define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */
26 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
27 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
28 #define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */
29 #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */
30 #define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */
31 #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */
32 #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */
34 /* Control Register Bit mask definitions */
35 #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */
36 #define CDNS_I2C_CR_ACK_EN BIT(3)
37 #define CDNS_I2C_CR_NEA BIT(2)
38 #define CDNS_I2C_CR_MS BIT(1)
39 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
40 #define CDNS_I2C_CR_RW BIT(0)
41 /* 1 = Auto init FIFO to zeroes */
42 #define CDNS_I2C_CR_CLR_FIFO BIT(6)
43 #define CDNS_I2C_CR_DIVA_SHIFT 14
44 #define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT)
45 #define CDNS_I2C_CR_DIVB_SHIFT 8
46 #define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT)
48 /* Status Register Bit mask definitions */
49 #define CDNS_I2C_SR_BA BIT(8)
50 #define CDNS_I2C_SR_RXDV BIT(5)
53 * I2C Address Register Bit mask definitions
54 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
55 * bits. A write access to this register always initiates a transfer if the I2C
58 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */
61 * I2C Interrupt Registers Bit mask definitions
62 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
65 #define CDNS_I2C_IXR_ARB_LOST BIT(9)
66 #define CDNS_I2C_IXR_RX_UNF BIT(7)
67 #define CDNS_I2C_IXR_TX_OVF BIT(6)
68 #define CDNS_I2C_IXR_RX_OVF BIT(5)
69 #define CDNS_I2C_IXR_SLV_RDY BIT(4)
70 #define CDNS_I2C_IXR_TO BIT(3)
71 #define CDNS_I2C_IXR_NACK BIT(2)
72 #define CDNS_I2C_IXR_DATA BIT(1)
73 #define CDNS_I2C_IXR_COMP BIT(0)
75 #define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
76 CDNS_I2C_IXR_RX_UNF | \
77 CDNS_I2C_IXR_TX_OVF | \
78 CDNS_I2C_IXR_RX_OVF | \
79 CDNS_I2C_IXR_SLV_RDY | \
85 #define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
86 CDNS_I2C_IXR_RX_UNF | \
87 CDNS_I2C_IXR_TX_OVF | \
88 CDNS_I2C_IXR_RX_OVF | \
91 #define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
92 CDNS_I2C_IXR_RX_UNF | \
93 CDNS_I2C_IXR_TX_OVF | \
94 CDNS_I2C_IXR_RX_OVF | \
99 #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000)
100 /* timeout for pm runtime autosuspend */
101 #define CNDS_I2C_PM_TIMEOUT 1000 /* ms */
103 #define CDNS_I2C_FIFO_DEPTH 16
104 /* FIFO depth at which the DATA interrupt occurs */
105 #define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2)
106 #define CDNS_I2C_MAX_TRANSFER_SIZE 255
107 /* Transfer size in multiples of data interrupt depth */
108 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3)
110 #define DRIVER_NAME "cdns-i2c"
112 #define CDNS_I2C_SPEED_MAX 400000
113 #define CDNS_I2C_SPEED_DEFAULT 100000
115 #define CDNS_I2C_DIVA_MAX 4
116 #define CDNS_I2C_DIVB_MAX 64
118 #define CDNS_I2C_TIMEOUT_MAX 0xFF
120 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
122 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
123 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
126 * struct cdns_i2c - I2C device private data structure
127 * @membase: Base address of the I2C device
128 * @adap: I2C adapter instance
129 * @p_msg: Message pointer
130 * @err_status: Error status in Interrupt Status Register
131 * @xfer_done: Transfer complete status
132 * @p_send_buf: Pointer to transmit buffer
133 * @p_recv_buf: Pointer to receive buffer
134 * @send_count: Number of bytes still expected to send
135 * @recv_count: Number of bytes still expected to receive
136 * @curr_recv_count: Number of bytes to be received in current transfer
138 * @input_clk: Input clock to I2C controller
139 * @i2c_clk: Maximum I2C clock speed
140 * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit
141 * @clk: Pointer to struct clk
142 * @clk_rate_change_nb: Notifier block for clock rate changes
143 * @quirks: flag for broken hold bit usage in r1p10
147 void __iomem
*membase
;
148 struct i2c_adapter adap
;
149 struct i2c_msg
*p_msg
;
151 struct completion xfer_done
;
152 unsigned char *p_send_buf
;
153 unsigned char *p_recv_buf
;
154 unsigned int send_count
;
155 unsigned int recv_count
;
156 unsigned int curr_recv_count
;
158 unsigned long input_clk
;
159 unsigned int i2c_clk
;
160 unsigned int bus_hold_flag
;
162 struct notifier_block clk_rate_change_nb
;
166 struct cdns_platform_data
{
170 #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \
174 * cdns_i2c_clear_bus_hold() - Clear bus hold bit
175 * @id: Pointer to driver data struct
177 * Helper to clear the controller's bus hold bit.
179 static void cdns_i2c_clear_bus_hold(struct cdns_i2c
*id
)
181 u32 reg
= cdns_i2c_readreg(CDNS_I2C_CR_OFFSET
);
182 if (reg
& CDNS_I2C_CR_HOLD
)
183 cdns_i2c_writereg(reg
& ~CDNS_I2C_CR_HOLD
, CDNS_I2C_CR_OFFSET
);
186 static inline bool cdns_is_holdquirk(struct cdns_i2c
*id
, bool hold_wrkaround
)
188 return (hold_wrkaround
&&
189 (id
->curr_recv_count
== CDNS_I2C_FIFO_DEPTH
+ 1));
193 * cdns_i2c_isr - Interrupt handler for the I2C device
194 * @irq: irq number for the I2C device
195 * @ptr: void pointer to cdns_i2c structure
197 * This function handles the data interrupt, transfer complete interrupt and
198 * the error interrupts of the I2C device.
200 * Return: IRQ_HANDLED always
202 static irqreturn_t
cdns_i2c_isr(int irq
, void *ptr
)
204 unsigned int isr_status
, avail_bytes
, updatetx
;
205 unsigned int bytes_to_send
;
207 struct cdns_i2c
*id
= ptr
;
208 /* Signal completion only after everything is updated */
210 irqreturn_t status
= IRQ_NONE
;
212 isr_status
= cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET
);
213 cdns_i2c_writereg(isr_status
, CDNS_I2C_ISR_OFFSET
);
215 /* Handling nack and arbitration lost interrupt */
216 if (isr_status
& (CDNS_I2C_IXR_NACK
| CDNS_I2C_IXR_ARB_LOST
)) {
218 status
= IRQ_HANDLED
;
222 * Check if transfer size register needs to be updated again for a
223 * large data receive operation.
226 if (id
->recv_count
> id
->curr_recv_count
)
229 hold_quirk
= (id
->quirks
& CDNS_I2C_BROKEN_HOLD_BIT
) && updatetx
;
231 /* When receiving, handle data interrupt and completion interrupt */
232 if (id
->p_recv_buf
&&
233 ((isr_status
& CDNS_I2C_IXR_COMP
) ||
234 (isr_status
& CDNS_I2C_IXR_DATA
))) {
235 /* Read data if receive data valid is set */
236 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET
) &
239 * Clear hold bit that was set for FIFO control if
240 * RX data left is less than FIFO depth, unless
241 * repeated start is selected.
243 if ((id
->recv_count
< CDNS_I2C_FIFO_DEPTH
) &&
245 cdns_i2c_clear_bus_hold(id
);
247 *(id
->p_recv_buf
)++ =
248 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET
);
250 id
->curr_recv_count
--;
252 if (cdns_is_holdquirk(id
, hold_quirk
))
257 * The controller sends NACK to the slave when transfer size
258 * register reaches zero without considering the HOLD bit.
259 * This workaround is implemented for large data transfers to
260 * maintain transfer size non-zero while performing a large
263 if (cdns_is_holdquirk(id
, hold_quirk
)) {
264 /* wait while fifo is full */
265 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET
) !=
266 (id
->curr_recv_count
- CDNS_I2C_FIFO_DEPTH
))
270 * Check number of bytes to be received against maximum
271 * transfer size and update register accordingly.
273 if (((int)(id
->recv_count
) - CDNS_I2C_FIFO_DEPTH
) >
274 CDNS_I2C_TRANSFER_SIZE
) {
275 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE
,
276 CDNS_I2C_XFER_SIZE_OFFSET
);
277 id
->curr_recv_count
= CDNS_I2C_TRANSFER_SIZE
+
280 cdns_i2c_writereg(id
->recv_count
-
282 CDNS_I2C_XFER_SIZE_OFFSET
);
283 id
->curr_recv_count
= id
->recv_count
;
285 } else if (id
->recv_count
&& !hold_quirk
&&
286 !id
->curr_recv_count
) {
288 /* Set the slave address in address register*/
289 cdns_i2c_writereg(id
->p_msg
->addr
& CDNS_I2C_ADDR_MASK
,
290 CDNS_I2C_ADDR_OFFSET
);
292 if (id
->recv_count
> CDNS_I2C_TRANSFER_SIZE
) {
293 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE
,
294 CDNS_I2C_XFER_SIZE_OFFSET
);
295 id
->curr_recv_count
= CDNS_I2C_TRANSFER_SIZE
;
297 cdns_i2c_writereg(id
->recv_count
,
298 CDNS_I2C_XFER_SIZE_OFFSET
);
299 id
->curr_recv_count
= id
->recv_count
;
303 /* Clear hold (if not repeated start) and signal completion */
304 if ((isr_status
& CDNS_I2C_IXR_COMP
) && !id
->recv_count
) {
305 if (!id
->bus_hold_flag
)
306 cdns_i2c_clear_bus_hold(id
);
310 status
= IRQ_HANDLED
;
313 /* When sending, handle transfer complete interrupt */
314 if ((isr_status
& CDNS_I2C_IXR_COMP
) && !id
->p_recv_buf
) {
316 * If there is more data to be sent, calculate the
317 * space available in FIFO and fill with that many bytes.
319 if (id
->send_count
) {
320 avail_bytes
= CDNS_I2C_FIFO_DEPTH
-
321 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET
);
322 if (id
->send_count
> avail_bytes
)
323 bytes_to_send
= avail_bytes
;
325 bytes_to_send
= id
->send_count
;
327 while (bytes_to_send
--) {
329 (*(id
->p_send_buf
)++),
330 CDNS_I2C_DATA_OFFSET
);
335 * Signal the completion of transaction and
336 * clear the hold bus bit if there are no
337 * further messages to be processed.
341 if (!id
->send_count
&& !id
->bus_hold_flag
)
342 cdns_i2c_clear_bus_hold(id
);
344 status
= IRQ_HANDLED
;
347 /* Update the status for errors */
348 id
->err_status
= isr_status
& CDNS_I2C_IXR_ERR_INTR_MASK
;
350 status
= IRQ_HANDLED
;
353 complete(&id
->xfer_done
);
359 * cdns_i2c_mrecv - Prepare and start a master receive operation
360 * @id: pointer to the i2c device structure
362 static void cdns_i2c_mrecv(struct cdns_i2c
*id
)
364 unsigned int ctrl_reg
;
365 unsigned int isr_status
;
367 id
->p_recv_buf
= id
->p_msg
->buf
;
368 id
->recv_count
= id
->p_msg
->len
;
370 /* Put the controller in master receive mode and clear the FIFO */
371 ctrl_reg
= cdns_i2c_readreg(CDNS_I2C_CR_OFFSET
);
372 ctrl_reg
|= CDNS_I2C_CR_RW
| CDNS_I2C_CR_CLR_FIFO
;
374 if (id
->p_msg
->flags
& I2C_M_RECV_LEN
)
375 id
->recv_count
= I2C_SMBUS_BLOCK_MAX
+ 1;
377 id
->curr_recv_count
= id
->recv_count
;
380 * Check for the message size against FIFO depth and set the
381 * 'hold bus' bit if it is greater than FIFO depth.
383 if (id
->recv_count
> CDNS_I2C_FIFO_DEPTH
)
384 ctrl_reg
|= CDNS_I2C_CR_HOLD
;
386 cdns_i2c_writereg(ctrl_reg
, CDNS_I2C_CR_OFFSET
);
388 /* Clear the interrupts in interrupt status register */
389 isr_status
= cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET
);
390 cdns_i2c_writereg(isr_status
, CDNS_I2C_ISR_OFFSET
);
393 * The no. of bytes to receive is checked against the limit of
394 * max transfer size. Set transfer size register with no of bytes
395 * receive if it is less than transfer size and transfer size if
396 * it is more. Enable the interrupts.
398 if (id
->recv_count
> CDNS_I2C_TRANSFER_SIZE
) {
399 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE
,
400 CDNS_I2C_XFER_SIZE_OFFSET
);
401 id
->curr_recv_count
= CDNS_I2C_TRANSFER_SIZE
;
403 cdns_i2c_writereg(id
->recv_count
, CDNS_I2C_XFER_SIZE_OFFSET
);
406 /* Clear the bus hold flag if bytes to receive is less than FIFO size */
407 if (!id
->bus_hold_flag
&&
408 ((id
->p_msg
->flags
& I2C_M_RECV_LEN
) != I2C_M_RECV_LEN
) &&
409 (id
->recv_count
<= CDNS_I2C_FIFO_DEPTH
))
410 cdns_i2c_clear_bus_hold(id
);
411 /* Set the slave address in address register - triggers operation */
412 cdns_i2c_writereg(id
->p_msg
->addr
& CDNS_I2C_ADDR_MASK
,
413 CDNS_I2C_ADDR_OFFSET
);
414 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK
, CDNS_I2C_IER_OFFSET
);
418 * cdns_i2c_msend - Prepare and start a master send operation
419 * @id: pointer to the i2c device
421 static void cdns_i2c_msend(struct cdns_i2c
*id
)
423 unsigned int avail_bytes
;
424 unsigned int bytes_to_send
;
425 unsigned int ctrl_reg
;
426 unsigned int isr_status
;
428 id
->p_recv_buf
= NULL
;
429 id
->p_send_buf
= id
->p_msg
->buf
;
430 id
->send_count
= id
->p_msg
->len
;
432 /* Set the controller in Master transmit mode and clear the FIFO. */
433 ctrl_reg
= cdns_i2c_readreg(CDNS_I2C_CR_OFFSET
);
434 ctrl_reg
&= ~CDNS_I2C_CR_RW
;
435 ctrl_reg
|= CDNS_I2C_CR_CLR_FIFO
;
438 * Check for the message size against FIFO depth and set the
439 * 'hold bus' bit if it is greater than FIFO depth.
441 if (id
->send_count
> CDNS_I2C_FIFO_DEPTH
)
442 ctrl_reg
|= CDNS_I2C_CR_HOLD
;
443 cdns_i2c_writereg(ctrl_reg
, CDNS_I2C_CR_OFFSET
);
445 /* Clear the interrupts in interrupt status register. */
446 isr_status
= cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET
);
447 cdns_i2c_writereg(isr_status
, CDNS_I2C_ISR_OFFSET
);
450 * Calculate the space available in FIFO. Check the message length
451 * against the space available, and fill the FIFO accordingly.
452 * Enable the interrupts.
454 avail_bytes
= CDNS_I2C_FIFO_DEPTH
-
455 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET
);
457 if (id
->send_count
> avail_bytes
)
458 bytes_to_send
= avail_bytes
;
460 bytes_to_send
= id
->send_count
;
462 while (bytes_to_send
--) {
463 cdns_i2c_writereg((*(id
->p_send_buf
)++), CDNS_I2C_DATA_OFFSET
);
468 * Clear the bus hold flag if there is no more data
469 * and if it is the last message.
471 if (!id
->bus_hold_flag
&& !id
->send_count
)
472 cdns_i2c_clear_bus_hold(id
);
473 /* Set the slave address in address register - triggers operation. */
474 cdns_i2c_writereg(id
->p_msg
->addr
& CDNS_I2C_ADDR_MASK
,
475 CDNS_I2C_ADDR_OFFSET
);
477 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK
, CDNS_I2C_IER_OFFSET
);
481 * cdns_i2c_master_reset - Reset the interface
482 * @adap: pointer to the i2c adapter driver instance
484 * This function cleanup the fifos, clear the hold bit and status
485 * and disable the interrupts.
487 static void cdns_i2c_master_reset(struct i2c_adapter
*adap
)
489 struct cdns_i2c
*id
= adap
->algo_data
;
492 /* Disable the interrupts */
493 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK
, CDNS_I2C_IDR_OFFSET
);
494 /* Clear the hold bit and fifos */
495 regval
= cdns_i2c_readreg(CDNS_I2C_CR_OFFSET
);
496 regval
&= ~CDNS_I2C_CR_HOLD
;
497 regval
|= CDNS_I2C_CR_CLR_FIFO
;
498 cdns_i2c_writereg(regval
, CDNS_I2C_CR_OFFSET
);
499 /* Update the transfercount register to zero */
500 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET
);
501 /* Clear the interupt status register */
502 regval
= cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET
);
503 cdns_i2c_writereg(regval
, CDNS_I2C_ISR_OFFSET
);
504 /* Clear the status register */
505 regval
= cdns_i2c_readreg(CDNS_I2C_SR_OFFSET
);
506 cdns_i2c_writereg(regval
, CDNS_I2C_SR_OFFSET
);
509 static int cdns_i2c_process_msg(struct cdns_i2c
*id
, struct i2c_msg
*msg
,
510 struct i2c_adapter
*adap
)
512 unsigned long time_left
;
517 reinit_completion(&id
->xfer_done
);
519 /* Check for the TEN Bit mode on each msg */
520 reg
= cdns_i2c_readreg(CDNS_I2C_CR_OFFSET
);
521 if (msg
->flags
& I2C_M_TEN
) {
522 if (reg
& CDNS_I2C_CR_NEA
)
523 cdns_i2c_writereg(reg
& ~CDNS_I2C_CR_NEA
,
526 if (!(reg
& CDNS_I2C_CR_NEA
))
527 cdns_i2c_writereg(reg
| CDNS_I2C_CR_NEA
,
531 /* Check for the R/W flag on each msg */
532 if (msg
->flags
& I2C_M_RD
)
537 /* Wait for the signal of completion */
538 time_left
= wait_for_completion_timeout(&id
->xfer_done
, adap
->timeout
);
539 if (time_left
== 0) {
540 cdns_i2c_master_reset(adap
);
541 dev_err(id
->adap
.dev
.parent
,
542 "timeout waiting on completion\n");
546 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK
,
547 CDNS_I2C_IDR_OFFSET
);
549 /* If it is bus arbitration error, try again */
550 if (id
->err_status
& CDNS_I2C_IXR_ARB_LOST
)
557 * cdns_i2c_master_xfer - The main i2c transfer function
558 * @adap: pointer to the i2c adapter driver instance
559 * @msgs: pointer to the i2c message structure
560 * @num: the number of messages to transfer
562 * Initiates the send/recv activity based on the transfer message received.
564 * Return: number of msgs processed on success, negative error otherwise
566 static int cdns_i2c_master_xfer(struct i2c_adapter
*adap
, struct i2c_msg
*msgs
,
571 struct cdns_i2c
*id
= adap
->algo_data
;
574 ret
= pm_runtime_get_sync(id
->dev
);
577 /* Check if the bus is free */
578 if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET
) & CDNS_I2C_SR_BA
) {
583 hold_quirk
= !!(id
->quirks
& CDNS_I2C_BROKEN_HOLD_BIT
);
585 * Set the flag to one when multiple messages are to be
586 * processed with a repeated start.
590 * This controller does not give completion interrupt after a
591 * master receive message if HOLD bit is set (repeated start),
592 * resulting in SW timeout. Hence, if a receive message is
593 * followed by any other message, an error is returned
594 * indicating that this sequence is not supported.
596 for (count
= 0; (count
< num
- 1 && hold_quirk
); count
++) {
597 if (msgs
[count
].flags
& I2C_M_RD
) {
598 dev_warn(adap
->dev
.parent
,
599 "Can't do repeated start after a receive message\n");
604 id
->bus_hold_flag
= 1;
605 reg
= cdns_i2c_readreg(CDNS_I2C_CR_OFFSET
);
606 reg
|= CDNS_I2C_CR_HOLD
;
607 cdns_i2c_writereg(reg
, CDNS_I2C_CR_OFFSET
);
609 id
->bus_hold_flag
= 0;
612 /* Process the msg one by one */
613 for (count
= 0; count
< num
; count
++, msgs
++) {
614 if (count
== (num
- 1))
615 id
->bus_hold_flag
= 0;
617 ret
= cdns_i2c_process_msg(id
, msgs
, adap
);
621 /* Report the other error interrupts to application */
622 if (id
->err_status
) {
623 cdns_i2c_master_reset(adap
);
625 if (id
->err_status
& CDNS_I2C_IXR_NACK
) {
636 pm_runtime_mark_last_busy(id
->dev
);
637 pm_runtime_put_autosuspend(id
->dev
);
642 * cdns_i2c_func - Returns the supported features of the I2C driver
643 * @adap: pointer to the i2c adapter structure
645 * Return: 32 bit value, each bit corresponding to a feature
647 static u32
cdns_i2c_func(struct i2c_adapter
*adap
)
649 return I2C_FUNC_I2C
| I2C_FUNC_10BIT_ADDR
|
650 (I2C_FUNC_SMBUS_EMUL
& ~I2C_FUNC_SMBUS_QUICK
) |
651 I2C_FUNC_SMBUS_BLOCK_DATA
;
654 static const struct i2c_algorithm cdns_i2c_algo
= {
655 .master_xfer
= cdns_i2c_master_xfer
,
656 .functionality
= cdns_i2c_func
,
660 * cdns_i2c_calc_divs - Calculate clock dividers
661 * @f: I2C clock frequency
662 * @input_clk: Input clock frequency
663 * @a: First divider (return value)
664 * @b: Second divider (return value)
666 * f is used as input and output variable. As input it is used as target I2C
667 * frequency. On function exit f holds the actually resulting I2C frequency.
669 * Return: 0 on success, negative errno otherwise.
671 static int cdns_i2c_calc_divs(unsigned long *f
, unsigned long input_clk
,
672 unsigned int *a
, unsigned int *b
)
674 unsigned long fscl
= *f
, best_fscl
= *f
, actual_fscl
, temp
;
675 unsigned int div_a
, div_b
, calc_div_a
= 0, calc_div_b
= 0;
676 unsigned int last_error
, current_error
;
678 /* calculate (divisor_a+1) x (divisor_b+1) */
679 temp
= input_clk
/ (22 * fscl
);
682 * If the calculated value is negative or 0, the fscl input is out of
683 * range. Return error.
685 if (!temp
|| (temp
> (CDNS_I2C_DIVA_MAX
* CDNS_I2C_DIVB_MAX
)))
689 for (div_a
= 0; div_a
< CDNS_I2C_DIVA_MAX
; div_a
++) {
690 div_b
= DIV_ROUND_UP(input_clk
, 22 * fscl
* (div_a
+ 1));
692 if ((div_b
< 1) || (div_b
> CDNS_I2C_DIVB_MAX
))
696 actual_fscl
= input_clk
/ (22 * (div_a
+ 1) * (div_b
+ 1));
698 if (actual_fscl
> fscl
)
701 current_error
= ((actual_fscl
> fscl
) ? (actual_fscl
- fscl
) :
702 (fscl
- actual_fscl
));
704 if (last_error
> current_error
) {
707 best_fscl
= actual_fscl
;
708 last_error
= current_error
;
720 * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device
721 * @clk_in: I2C clock input frequency in Hz
722 * @id: Pointer to the I2C device structure
724 * The device must be idle rather than busy transferring data before setting
725 * these device options.
726 * The data rate is set by values in the control register.
727 * The formula for determining the correct register values is
728 * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
729 * See the hardware data sheet for a full explanation of setting the serial
730 * clock rate. The clock can not be faster than the input clock divide by 22.
731 * The two most common clock rates are 100KHz and 400KHz.
733 * Return: 0 on success, negative error otherwise
735 static int cdns_i2c_setclk(unsigned long clk_in
, struct cdns_i2c
*id
)
737 unsigned int div_a
, div_b
;
738 unsigned int ctrl_reg
;
740 unsigned long fscl
= id
->i2c_clk
;
742 ret
= cdns_i2c_calc_divs(&fscl
, clk_in
, &div_a
, &div_b
);
746 ctrl_reg
= cdns_i2c_readreg(CDNS_I2C_CR_OFFSET
);
747 ctrl_reg
&= ~(CDNS_I2C_CR_DIVA_MASK
| CDNS_I2C_CR_DIVB_MASK
);
748 ctrl_reg
|= ((div_a
<< CDNS_I2C_CR_DIVA_SHIFT
) |
749 (div_b
<< CDNS_I2C_CR_DIVB_SHIFT
));
750 cdns_i2c_writereg(ctrl_reg
, CDNS_I2C_CR_OFFSET
);
756 * cdns_i2c_clk_notifier_cb - Clock rate change callback
757 * @nb: Pointer to notifier block
758 * @event: Notification reason
759 * @data: Pointer to notification data object
761 * This function is called when the cdns_i2c input clock frequency changes.
762 * The callback checks whether a valid bus frequency can be generated after the
763 * change. If so, the change is acknowledged, otherwise the change is aborted.
764 * New dividers are written to the HW in the pre- or post change notification
765 * depending on the scaling direction.
767 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
768 * to acknowedge the change, NOTIFY_DONE if the notification is
769 * considered irrelevant.
771 static int cdns_i2c_clk_notifier_cb(struct notifier_block
*nb
, unsigned long
774 struct clk_notifier_data
*ndata
= data
;
775 struct cdns_i2c
*id
= to_cdns_i2c(nb
);
777 if (pm_runtime_suspended(id
->dev
))
781 case PRE_RATE_CHANGE
:
783 unsigned long input_clk
= ndata
->new_rate
;
784 unsigned long fscl
= id
->i2c_clk
;
785 unsigned int div_a
, div_b
;
788 ret
= cdns_i2c_calc_divs(&fscl
, input_clk
, &div_a
, &div_b
);
790 dev_warn(id
->adap
.dev
.parent
,
791 "clock rate change rejected\n");
796 if (ndata
->new_rate
> ndata
->old_rate
)
797 cdns_i2c_setclk(ndata
->new_rate
, id
);
801 case POST_RATE_CHANGE
:
802 id
->input_clk
= ndata
->new_rate
;
804 if (ndata
->new_rate
< ndata
->old_rate
)
805 cdns_i2c_setclk(ndata
->new_rate
, id
);
807 case ABORT_RATE_CHANGE
:
809 if (ndata
->new_rate
> ndata
->old_rate
)
810 cdns_i2c_setclk(ndata
->old_rate
, id
);
818 * cdns_i2c_suspend - Suspend method for the driver
819 * @_dev: Address of the platform_device structure
821 * Put the driver into low power mode.
825 static int __maybe_unused
cdns_i2c_runtime_suspend(struct device
*dev
)
827 struct platform_device
*pdev
= to_platform_device(dev
);
828 struct cdns_i2c
*xi2c
= platform_get_drvdata(pdev
);
830 clk_disable(xi2c
->clk
);
836 * cdns_i2c_resume - Resume from suspend
837 * @_dev: Address of the platform_device structure
839 * Resume operation after suspend.
841 * Return: 0 on success and error value on error
843 static int __maybe_unused
cdns_i2c_runtime_resume(struct device
*dev
)
845 struct platform_device
*pdev
= to_platform_device(dev
);
846 struct cdns_i2c
*xi2c
= platform_get_drvdata(pdev
);
849 ret
= clk_enable(xi2c
->clk
);
851 dev_err(dev
, "Cannot enable clock.\n");
858 static const struct dev_pm_ops cdns_i2c_dev_pm_ops
= {
859 SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend
,
860 cdns_i2c_runtime_resume
, NULL
)
863 static const struct cdns_platform_data r1p10_i2c_def
= {
864 .quirks
= CDNS_I2C_BROKEN_HOLD_BIT
,
867 static const struct of_device_id cdns_i2c_of_match
[] = {
868 { .compatible
= "cdns,i2c-r1p10", .data
= &r1p10_i2c_def
},
869 { .compatible
= "cdns,i2c-r1p14",},
870 { /* end of table */ }
872 MODULE_DEVICE_TABLE(of
, cdns_i2c_of_match
);
875 * cdns_i2c_probe - Platform registration call
876 * @pdev: Handle to the platform device structure
878 * This function does all the memory allocation and registration for the i2c
879 * device. User can modify the address mode to 10 bit address mode using the
880 * ioctl call with option I2C_TENBIT.
882 * Return: 0 on success, negative error otherwise
884 static int cdns_i2c_probe(struct platform_device
*pdev
)
886 struct resource
*r_mem
;
889 const struct of_device_id
*match
;
891 id
= devm_kzalloc(&pdev
->dev
, sizeof(*id
), GFP_KERNEL
);
895 id
->dev
= &pdev
->dev
;
896 platform_set_drvdata(pdev
, id
);
898 match
= of_match_node(cdns_i2c_of_match
, pdev
->dev
.of_node
);
899 if (match
&& match
->data
) {
900 const struct cdns_platform_data
*data
= match
->data
;
901 id
->quirks
= data
->quirks
;
904 r_mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
905 id
->membase
= devm_ioremap_resource(&pdev
->dev
, r_mem
);
906 if (IS_ERR(id
->membase
))
907 return PTR_ERR(id
->membase
);
909 id
->irq
= platform_get_irq(pdev
, 0);
911 id
->adap
.owner
= THIS_MODULE
;
912 id
->adap
.dev
.of_node
= pdev
->dev
.of_node
;
913 id
->adap
.algo
= &cdns_i2c_algo
;
914 id
->adap
.timeout
= CDNS_I2C_TIMEOUT
;
915 id
->adap
.retries
= 3; /* Default retry value. */
916 id
->adap
.algo_data
= id
;
917 id
->adap
.dev
.parent
= &pdev
->dev
;
918 init_completion(&id
->xfer_done
);
919 snprintf(id
->adap
.name
, sizeof(id
->adap
.name
),
920 "Cadence I2C at %08lx", (unsigned long)r_mem
->start
);
922 id
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
923 if (IS_ERR(id
->clk
)) {
924 dev_err(&pdev
->dev
, "input clock not found.\n");
925 return PTR_ERR(id
->clk
);
927 ret
= clk_prepare_enable(id
->clk
);
929 dev_err(&pdev
->dev
, "Unable to enable clock.\n");
931 pm_runtime_enable(id
->dev
);
932 pm_runtime_set_autosuspend_delay(id
->dev
, CNDS_I2C_PM_TIMEOUT
);
933 pm_runtime_use_autosuspend(id
->dev
);
934 pm_runtime_set_active(id
->dev
);
936 id
->clk_rate_change_nb
.notifier_call
= cdns_i2c_clk_notifier_cb
;
937 if (clk_notifier_register(id
->clk
, &id
->clk_rate_change_nb
))
938 dev_warn(&pdev
->dev
, "Unable to register clock notifier.\n");
939 id
->input_clk
= clk_get_rate(id
->clk
);
941 ret
= of_property_read_u32(pdev
->dev
.of_node
, "clock-frequency",
943 if (ret
|| (id
->i2c_clk
> CDNS_I2C_SPEED_MAX
))
944 id
->i2c_clk
= CDNS_I2C_SPEED_DEFAULT
;
946 cdns_i2c_writereg(CDNS_I2C_CR_ACK_EN
| CDNS_I2C_CR_NEA
| CDNS_I2C_CR_MS
,
949 ret
= cdns_i2c_setclk(id
->input_clk
, id
);
951 dev_err(&pdev
->dev
, "invalid SCL clock: %u Hz\n", id
->i2c_clk
);
956 ret
= devm_request_irq(&pdev
->dev
, id
->irq
, cdns_i2c_isr
, 0,
959 dev_err(&pdev
->dev
, "cannot get irq %d\n", id
->irq
);
963 ret
= i2c_add_adapter(&id
->adap
);
965 dev_err(&pdev
->dev
, "reg adap failed: %d\n", ret
);
970 * Cadence I2C controller has a bug wherein it generates
971 * invalid read transaction after HW timeout in master receiver mode.
972 * HW timeout is not used by this driver and the interrupt is disabled.
973 * But the feature itself cannot be disabled. Hence maximum value
974 * is written to this register to reduce the chances of error.
976 cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX
, CDNS_I2C_TIME_OUT_OFFSET
);
978 dev_info(&pdev
->dev
, "%u kHz mmio %08lx irq %d\n",
979 id
->i2c_clk
/ 1000, (unsigned long)r_mem
->start
, id
->irq
);
984 clk_disable_unprepare(id
->clk
);
985 pm_runtime_set_suspended(&pdev
->dev
);
986 pm_runtime_disable(&pdev
->dev
);
991 * cdns_i2c_remove - Unregister the device after releasing the resources
992 * @pdev: Handle to the platform device structure
994 * This function frees all the resources allocated to the device.
998 static int cdns_i2c_remove(struct platform_device
*pdev
)
1000 struct cdns_i2c
*id
= platform_get_drvdata(pdev
);
1002 i2c_del_adapter(&id
->adap
);
1003 clk_notifier_unregister(id
->clk
, &id
->clk_rate_change_nb
);
1004 clk_disable_unprepare(id
->clk
);
1005 pm_runtime_disable(&pdev
->dev
);
1010 static struct platform_driver cdns_i2c_drv
= {
1012 .name
= DRIVER_NAME
,
1013 .of_match_table
= cdns_i2c_of_match
,
1014 .pm
= &cdns_i2c_dev_pm_ops
,
1016 .probe
= cdns_i2c_probe
,
1017 .remove
= cdns_i2c_remove
,
1020 module_platform_driver(cdns_i2c_drv
);
1022 MODULE_AUTHOR("Xilinx Inc.");
1023 MODULE_DESCRIPTION("Cadence I2C bus driver");
1024 MODULE_LICENSE("GPL");