drivers/i2c/busses/i2c-davinci.c

   1 /*
   2  * TI DAVINCI I2C adapter driver.
   3  *
   4  * Copyright (C) 2006 Texas Instruments.
   5  * Copyright (C) 2007 MontaVista Software Inc.
   6  *
   7  * Updated by Vinod & Sudhakar Feb 2005
   8  *
   9  * ----------------------------------------------------------------------------
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  * ----------------------------------------------------------------------------
  25  *
  26  */
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/i2c.h>
  31 #include <linux/clk.h>
  32 #include <linux/errno.h>
  33 #include <linux/sched.h>
  34 #include <linux/err.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/io.h>
  38
  39 #include <asm/hardware.h>
  40 #include <asm/mach-types.h>
  41
  42 #include <asm/arch/i2c.h>
  43
  44 /* ----- global defines ----------------------------------------------- */
  45
  46 #define DAVINCI_I2C_TIMEOUT     (1*HZ)
  47 #define I2C_DAVINCI_INTR_ALL    (DAVINCI_I2C_IMR_AAS | \
  48                                  DAVINCI_I2C_IMR_SCD | \
  49                                  DAVINCI_I2C_IMR_ARDY | \
  50                                  DAVINCI_I2C_IMR_NACK | \
  51                                  DAVINCI_I2C_IMR_AL)
  52
  53 #define DAVINCI_I2C_OAR_REG     0x00
  54 #define DAVINCI_I2C_IMR_REG     0x04
  55 #define DAVINCI_I2C_STR_REG     0x08
  56 #define DAVINCI_I2C_CLKL_REG    0x0c
  57 #define DAVINCI_I2C_CLKH_REG    0x10
  58 #define DAVINCI_I2C_CNT_REG     0x14
  59 #define DAVINCI_I2C_DRR_REG     0x18
  60 #define DAVINCI_I2C_SAR_REG     0x1c
  61 #define DAVINCI_I2C_DXR_REG     0x20
  62 #define DAVINCI_I2C_MDR_REG     0x24
  63 #define DAVINCI_I2C_IVR_REG     0x28
  64 #define DAVINCI_I2C_EMDR_REG    0x2c
  65 #define DAVINCI_I2C_PSC_REG     0x30
  66
  67 #define DAVINCI_I2C_IVR_AAS     0x07
  68 #define DAVINCI_I2C_IVR_SCD     0x06
  69 #define DAVINCI_I2C_IVR_XRDY    0x05
  70 #define DAVINCI_I2C_IVR_RDR     0x04
  71 #define DAVINCI_I2C_IVR_ARDY    0x03
  72 #define DAVINCI_I2C_IVR_NACK    0x02
  73 #define DAVINCI_I2C_IVR_AL      0x01
  74
  75 #define DAVINCI_I2C_STR_BB      (1 << 12)
  76 #define DAVINCI_I2C_STR_RSFULL  (1 << 11)
  77 #define DAVINCI_I2C_STR_SCD     (1 << 5)
  78 #define DAVINCI_I2C_STR_ARDY    (1 << 2)
  79 #define DAVINCI_I2C_STR_NACK    (1 << 1)
  80 #define DAVINCI_I2C_STR_AL      (1 << 0)
  81
  82 #define DAVINCI_I2C_MDR_NACK    (1 << 15)
  83 #define DAVINCI_I2C_MDR_STT     (1 << 13)
  84 #define DAVINCI_I2C_MDR_STP     (1 << 11)
  85 #define DAVINCI_I2C_MDR_MST     (1 << 10)
  86 #define DAVINCI_I2C_MDR_TRX     (1 << 9)
  87 #define DAVINCI_I2C_MDR_XA      (1 << 8)
  88 #define DAVINCI_I2C_MDR_IRS     (1 << 5)
  89
  90 #define DAVINCI_I2C_IMR_AAS     (1 << 6)
  91 #define DAVINCI_I2C_IMR_SCD     (1 << 5)
  92 #define DAVINCI_I2C_IMR_XRDY    (1 << 4)
  93 #define DAVINCI_I2C_IMR_RRDY    (1 << 3)
  94 #define DAVINCI_I2C_IMR_ARDY    (1 << 2)
  95 #define DAVINCI_I2C_IMR_NACK    (1 << 1)
  96 #define DAVINCI_I2C_IMR_AL      (1 << 0)
  97
  98 #define MOD_REG_BIT(val, mask, set) do { \
  99         if (set) { \
 100                 val |= mask; \
 101         } else { \
 102                 val &= ~mask; \
 103         } \
 104 } while (0)
 105
 106 struct davinci_i2c_dev {
 107         struct device           *dev;
 108         void __iomem            *base;
 109         struct completion       cmd_complete;
 110         struct clk              *clk;
 111         int                     cmd_err;
 112         u8                      *buf;
 113         size_t                  buf_len;
 114         int                     irq;
 115         struct i2c_adapter      adapter;
 116 };
 117
 118 /* default platform data to use if not supplied in the platform_device */
 119 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
 120         .bus_freq       = 100,
 121         .bus_delay      = 0,
 122 };
 123
 124 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
 125                                          int reg, u16 val)
 126 {
 127         __raw_writew(val, i2c_dev->base + reg);
 128 }
 129
 130 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
 131 {
 132         return __raw_readw(i2c_dev->base + reg);
 133 }
 134
 135 /*
 136  * This functions configures I2C and brings I2C out of reset.
 137  * This function is called during I2C init function. This function
 138  * also gets called if I2C encounters any errors.
 139  */
 140 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
 141 {
 142         struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
 143         u16 psc;
 144         u32 clk;
 145         u32 d;
 146         u32 clkh;
 147         u32 clkl;
 148         u32 input_clock = clk_get_rate(dev->clk);
 149         u16 w;
 150
 151         if (!pdata)
 152                 pdata = &davinci_i2c_platform_data_default;
 153
 154         /* put I2C into reset */
 155         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 156         MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 0);
 157         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 158
 159         /* NOTE: I2C Clock divider programming info
 160          * As per I2C specs the following formulas provide prescaler
 161          * and low/high divider values
 162          * input clk --> PSC Div -----------> ICCL/H Div --> output clock
 163          *                       module clk
 164          *
 165          * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
 166          *
 167          * Thus,
 168          * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
 169          *
 170          * where if PSC == 0, d = 7,
 171          *       if PSC == 1, d = 6
 172          *       if PSC > 1 , d = 5
 173          */
 174
 175         /* get minimum of 7 MHz clock, but max of 12 MHz */
 176         psc = (input_clock / 7000000) - 1;
 177         if ((input_clock / (psc + 1)) > 12000000)
 178                 psc++;  /* better to run under spec than over */
 179         d = (psc >= 2) ? 5 : 7 - psc;
 180
 181         clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
 182         clkh = clk >> 1;
 183         clkl = clk - clkh;
 184
 185         davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
 186         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
 187         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
 188
 189         dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
 190         dev_dbg(dev->dev, "PSC  = %d\n",
 191                 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
 192         dev_dbg(dev->dev, "CLKL = %d\n",
 193                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
 194         dev_dbg(dev->dev, "CLKH = %d\n",
 195                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
 196         dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
 197                 pdata->bus_freq, pdata->bus_delay);
 198
 199         /* Take the I2C module out of reset: */
 200         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 201         MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 1);
 202         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 203
 204         /* Enable interrupts */
 205         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
 206
 207         return 0;
 208 }
 209
 210 /*
 211  * Waiting for bus not busy
 212  */
 213 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
 214                                          char allow_sleep)
 215 {
 216         unsigned long timeout;
 217
 218         timeout = jiffies + DAVINCI_I2C_TIMEOUT;
 219         while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
 220                & DAVINCI_I2C_STR_BB) {
 221                 if (time_after(jiffies, timeout)) {
 222                         dev_warn(dev->dev,
 223                                  "timeout waiting for bus ready\n");
 224                         return -ETIMEDOUT;
 225                 }
 226                 if (allow_sleep)
 227                         schedule_timeout(1);
 228         }
 229
 230         return 0;
 231 }
 232
 233 /*
 234  * Low level master read/write transaction. This function is called
 235  * from i2c_davinci_xfer.
 236  */
 237 static int
 238 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
 239 {
 240         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 241         struct davinci_i2c_platform_data *pdata = dev->dev->platform_data;
 242         u32 flag;
 243         u16 w;
 244         int r;
 245
 246         if (msg->len == 0)
 247                 return -EINVAL;
 248
 249         if (!pdata)
 250                 pdata = &davinci_i2c_platform_data_default;
 251         /* Introduce a delay, required for some boards (e.g Davinci EVM) */
 252         if (pdata->bus_delay)
 253                 udelay(pdata->bus_delay);
 254
 255         /* set the slave address */
 256         davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
 257
 258         dev->buf = msg->buf;
 259         dev->buf_len = msg->len;
 260
 261         davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
 262
 263         init_completion(&dev->cmd_complete);
 264         dev->cmd_err = 0;
 265
 266         /* Take I2C out of reset, configure it as master and set the
 267          * start bit */
 268         flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST | DAVINCI_I2C_MDR_STT;
 269
 270         /* if the slave address is ten bit address, enable XA bit */
 271         if (msg->flags & I2C_M_TEN)
 272                 flag |= DAVINCI_I2C_MDR_XA;
 273         if (!(msg->flags & I2C_M_RD))
 274                 flag |= DAVINCI_I2C_MDR_TRX;
 275         if (stop)
 276                 flag |= DAVINCI_I2C_MDR_STP;
 277
 278         /* Enable receive or transmit interrupts */
 279         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
 280         if (msg->flags & I2C_M_RD)
 281                 MOD_REG_BIT(w, DAVINCI_I2C_IMR_RRDY, 1);
 282         else
 283                 MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 1);
 284         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
 285
 286         /* write the data into mode register */
 287         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 288
 289         r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
 290                                                       DAVINCI_I2C_TIMEOUT);
 291         dev->buf_len = 0;
 292         if (r < 0)
 293                 return r;
 294
 295         if (r == 0) {
 296                 dev_err(dev->dev, "controller timed out\n");
 297                 i2c_davinci_init(dev);
 298                 return -ETIMEDOUT;
 299         }
 300
 301         /* no error */
 302         if (likely(!dev->cmd_err))
 303                 return msg->len;
 304
 305         /* We have an error */
 306         if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
 307                 i2c_davinci_init(dev);
 308                 return -EIO;
 309         }
 310
 311         if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
 312                 if (msg->flags & I2C_M_IGNORE_NAK)
 313                         return msg->len;
 314                 if (stop) {
 315                         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 316                         MOD_REG_BIT(w, DAVINCI_I2C_MDR_STP, 1);
 317                         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 318                 }
 319                 return -EREMOTEIO;
 320         }
 321         return -EIO;
 322 }
 323
 324 /*
 325  * Prepare controller for a transaction and call i2c_davinci_xfer_msg
 326  */
 327 static int
 328 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 329 {
 330         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 331         int i;
 332         int ret;
 333
 334         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 335
 336         ret = i2c_davinci_wait_bus_not_busy(dev, 1);
 337         if (ret < 0) {
 338                 dev_warn(dev->dev, "timeout waiting for bus ready\n");
 339                 return ret;
 340         }
 341
 342         for (i = 0; i < num; i++) {
 343                 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 344                 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
 345                         ret);
 346                 if (ret < 0)
 347                         return ret;
 348         }
 349         return num;
 350 }
 351
 352 static u32 i2c_davinci_func(struct i2c_adapter *adap)
 353 {
 354         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 355 }
 356
 357 /*
 358  * Interrupt service routine. This gets called whenever an I2C interrupt
 359  * occurs.
 360  */
 361 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
 362 {
 363         struct davinci_i2c_dev *dev = dev_id;
 364         u32 stat;
 365         int count = 0;
 366         u16 w;
 367
 368         while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
 369                 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
 370                 if (count++ == 100) {
 371                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 372                         break;
 373                 }
 374
 375                 switch (stat) {
 376                 case DAVINCI_I2C_IVR_AL:
 377                         dev->cmd_err |= DAVINCI_I2C_STR_AL;
 378                         complete(&dev->cmd_complete);
 379                         break;
 380
 381                 case DAVINCI_I2C_IVR_NACK:
 382                         dev->cmd_err |= DAVINCI_I2C_STR_NACK;
 383                         complete(&dev->cmd_complete);
 384                         break;
 385
 386                 case DAVINCI_I2C_IVR_ARDY:
 387                         davinci_i2c_write_reg(dev,
 388                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
 389                         complete(&dev->cmd_complete);
 390                         break;
 391
 392                 case DAVINCI_I2C_IVR_RDR:
 393                         if (dev->buf_len) {
 394                                 *dev->buf++ =
 395                                     davinci_i2c_read_reg(dev,
 396                                                          DAVINCI_I2C_DRR_REG);
 397                                 dev->buf_len--;
 398                                 if (dev->buf_len)
 399                                         continue;
 400
 401                                 davinci_i2c_write_reg(dev,
 402                                         DAVINCI_I2C_STR_REG,
 403                                         DAVINCI_I2C_IMR_RRDY);
 404                         } else
 405                                 dev_err(dev->dev, "RDR IRQ while no "
 406                                         "data requested\n");
 407                         break;
 408
 409                 case DAVINCI_I2C_IVR_XRDY:
 410                         if (dev->buf_len) {
 411                                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
 412                                                       *dev->buf++);
 413                                 dev->buf_len--;
 414                                 if (dev->buf_len)
 415                                         continue;
 416
 417                                 w = davinci_i2c_read_reg(dev,
 418                                                          DAVINCI_I2C_IMR_REG);
 419                                 MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 0);
 420                                 davinci_i2c_write_reg(dev,
 421                                                       DAVINCI_I2C_IMR_REG,
 422                                                       w);
 423                         } else
 424                                 dev_err(dev->dev, "TDR IRQ while no data to "
 425                                         "send\n");
 426                         break;
 427
 428                 case DAVINCI_I2C_IVR_SCD:
 429                         davinci_i2c_write_reg(dev,
 430                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
 431                         complete(&dev->cmd_complete);
 432                         break;
 433
 434                 case DAVINCI_I2C_IVR_AAS:
 435                         dev_warn(dev->dev, "Address as slave interrupt\n");
 436                 }/* switch */
 437         }/* while */
 438
 439         return count ? IRQ_HANDLED : IRQ_NONE;
 440 }
 441
 442 static struct i2c_algorithm i2c_davinci_algo = {
 443         .master_xfer    = i2c_davinci_xfer,
 444         .functionality  = i2c_davinci_func,
 445 };
 446
 447 static int davinci_i2c_probe(struct platform_device *pdev)
 448 {
 449         struct davinci_i2c_dev *dev;
 450         struct i2c_adapter *adap;
 451         struct resource *mem, *irq, *ioarea;
 452         int r;
 453
 454         /* NOTE: driver uses the static register mapping */
 455         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 456         if (!mem) {
 457                 dev_err(&pdev->dev, "no mem resource?\n");
 458                 return -ENODEV;
 459         }
 460
 461         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 462         if (!irq) {
 463                 dev_err(&pdev->dev, "no irq resource?\n");
 464                 return -ENODEV;
 465         }
 466
 467         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 468                                     pdev->name);
 469         if (!ioarea) {
 470                 dev_err(&pdev->dev, "I2C region already claimed\n");
 471                 return -EBUSY;
 472         }
 473
 474         dev = kzalloc(sizeof(struct davinci_i2c_dev), GFP_KERNEL);
 475         if (!dev) {
 476                 r = -ENOMEM;
 477                 goto err_release_region;
 478         }
 479
 480         dev->dev = get_device(&pdev->dev);
 481         dev->irq = irq->start;
 482         platform_set_drvdata(pdev, dev);
 483
 484         dev->clk = clk_get(&pdev->dev, "I2CCLK");
 485         if (IS_ERR(dev->clk)) {
 486                 r = -ENODEV;
 487                 goto err_free_mem;
 488         }
 489         clk_enable(dev->clk);
 490
 491         dev->base = (void __iomem *)IO_ADDRESS(mem->start);
 492         i2c_davinci_init(dev);
 493
 494         r = request_irq(dev->irq, i2c_davinci_isr, 0, pdev->name, dev);
 495         if (r) {
 496                 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
 497                 goto err_unuse_clocks;
 498         }
 499
 500         adap = &dev->adapter;
 501         i2c_set_adapdata(adap, dev);
 502         adap->owner = THIS_MODULE;
 503         adap->class = I2C_CLASS_HWMON;
 504         strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
 505         adap->algo = &i2c_davinci_algo;
 506         adap->dev.parent = &pdev->dev;
 507
 508         /* FIXME */
 509         adap->timeout = 1;
 510
 511         adap->nr = pdev->id;
 512         r = i2c_add_numbered_adapter(adap);
 513         if (r) {
 514                 dev_err(&pdev->dev, "failure adding adapter\n");
 515                 goto err_free_irq;
 516         }
 517
 518         return 0;
 519
 520 err_free_irq:
 521         free_irq(dev->irq, dev);
 522 err_unuse_clocks:
 523         clk_disable(dev->clk);
 524         clk_put(dev->clk);
 525         dev->clk = NULL;
 526 err_free_mem:
 527         platform_set_drvdata(pdev, NULL);
 528         put_device(&pdev->dev);
 529         kfree(dev);
 530 err_release_region:
 531         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 532
 533         return r;
 534 }
 535
 536 static int davinci_i2c_remove(struct platform_device *pdev)
 537 {
 538         struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
 539         struct resource *mem;
 540
 541         platform_set_drvdata(pdev, NULL);
 542         i2c_del_adapter(&dev->adapter);
 543         put_device(&pdev->dev);
 544
 545         clk_disable(dev->clk);
 546         clk_put(dev->clk);
 547         dev->clk = NULL;
 548
 549         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
 550         free_irq(IRQ_I2C, dev);
 551         kfree(dev);
 552
 553         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 554         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 555         return 0;
 556 }
 557
 558 /* work with hotplug and coldplug */
 559 MODULE_ALIAS("platform:i2c_davinci");
 560
 561 static struct platform_driver davinci_i2c_driver = {
 562         .probe          = davinci_i2c_probe,
 563         .remove         = davinci_i2c_remove,
 564         .driver         = {
 565                 .name   = "i2c_davinci",
 566                 .owner  = THIS_MODULE,
 567         },
 568 };
 569
 570 /* I2C may be needed to bring up other drivers */
 571 static int __init davinci_i2c_init_driver(void)
 572 {
 573         return platform_driver_register(&davinci_i2c_driver);
 574 }
 575 subsys_initcall(davinci_i2c_init_driver);
 576
 577 static void __exit davinci_i2c_exit_driver(void)
 578 {
 579         platform_driver_unregister(&davinci_i2c_driver);
 580 }
 581 module_exit(davinci_i2c_exit_driver);
 582
 583 MODULE_AUTHOR("Texas Instruments India");
 584 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
 585 MODULE_LICENSE("GPL");