drivers/i2c/busses/i2c-designware-core.c

   1 /*
   2  * Synopsys DesignWare I2C adapter driver (master only).
   3  *
   4  * Based on the TI DAVINCI I2C adapter driver.
   5  *
   6  * Copyright (C) 2006 Texas Instruments.
   7  * Copyright (C) 2007 MontaVista Software Inc.
   8  * Copyright (C) 2009 Provigent Ltd.
   9  *
  10  * ----------------------------------------------------------------------------
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  * ----------------------------------------------------------------------------
  26  *
  27  */
  28 #include <linux/export.h>
  29 #include <linux/errno.h>
  30 #include <linux/err.h>
  31 #include <linux/i2c.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/delay.h>
  36 #include <linux/module.h>
  37 #include "i2c-designware-core.h"
  38
  39 /*
  40  * Registers offset
  41  */
  42 #define DW_IC_CON               0x0
  43 #define DW_IC_TAR               0x4
  44 #define DW_IC_DATA_CMD          0x10
  45 #define DW_IC_SS_SCL_HCNT       0x14
  46 #define DW_IC_SS_SCL_LCNT       0x18
  47 #define DW_IC_FS_SCL_HCNT       0x1c
  48 #define DW_IC_FS_SCL_LCNT       0x20
  49 #define DW_IC_INTR_STAT         0x2c
  50 #define DW_IC_INTR_MASK         0x30
  51 #define DW_IC_RAW_INTR_STAT     0x34
  52 #define DW_IC_RX_TL             0x38
  53 #define DW_IC_TX_TL             0x3c
  54 #define DW_IC_CLR_INTR          0x40
  55 #define DW_IC_CLR_RX_UNDER      0x44
  56 #define DW_IC_CLR_RX_OVER       0x48
  57 #define DW_IC_CLR_TX_OVER       0x4c
  58 #define DW_IC_CLR_RD_REQ        0x50
  59 #define DW_IC_CLR_TX_ABRT       0x54
  60 #define DW_IC_CLR_RX_DONE       0x58
  61 #define DW_IC_CLR_ACTIVITY      0x5c
  62 #define DW_IC_CLR_STOP_DET      0x60
  63 #define DW_IC_CLR_START_DET     0x64
  64 #define DW_IC_CLR_GEN_CALL      0x68
  65 #define DW_IC_ENABLE            0x6c
  66 #define DW_IC_STATUS            0x70
  67 #define DW_IC_TXFLR             0x74
  68 #define DW_IC_RXFLR             0x78
  69 #define DW_IC_SDA_HOLD          0x7c
  70 #define DW_IC_TX_ABRT_SOURCE    0x80
  71 #define DW_IC_ENABLE_STATUS     0x9c
  72 #define DW_IC_COMP_PARAM_1      0xf4
  73 #define DW_IC_COMP_VERSION      0xf8
  74 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
  75 #define DW_IC_COMP_TYPE         0xfc
  76 #define DW_IC_COMP_TYPE_VALUE   0x44570140
  77
  78 #define DW_IC_INTR_RX_UNDER     0x001
  79 #define DW_IC_INTR_RX_OVER      0x002
  80 #define DW_IC_INTR_RX_FULL      0x004
  81 #define DW_IC_INTR_TX_OVER      0x008
  82 #define DW_IC_INTR_TX_EMPTY     0x010
  83 #define DW_IC_INTR_RD_REQ       0x020
  84 #define DW_IC_INTR_TX_ABRT      0x040
  85 #define DW_IC_INTR_RX_DONE      0x080
  86 #define DW_IC_INTR_ACTIVITY     0x100
  87 #define DW_IC_INTR_STOP_DET     0x200
  88 #define DW_IC_INTR_START_DET    0x400
  89 #define DW_IC_INTR_GEN_CALL     0x800
  90
  91 #define DW_IC_INTR_DEFAULT_MASK         (DW_IC_INTR_RX_FULL | \
  92                                          DW_IC_INTR_TX_EMPTY | \
  93                                          DW_IC_INTR_TX_ABRT | \
  94                                          DW_IC_INTR_STOP_DET)
  95
  96 #define DW_IC_STATUS_ACTIVITY   0x1
  97
  98 #define DW_IC_ERR_TX_ABRT       0x1
  99
 100 #define DW_IC_TAR_10BITADDR_MASTER BIT(12)
 101
 102 /*
 103  * status codes
 104  */
 105 #define STATUS_IDLE                     0x0
 106 #define STATUS_WRITE_IN_PROGRESS        0x1
 107 #define STATUS_READ_IN_PROGRESS         0x2
 108
 109 #define TIMEOUT                 20 /* ms */
 110
 111 /*
 112  * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
 113  *
 114  * only expected abort codes are listed here
 115  * refer to the datasheet for the full list
 116  */
 117 #define ABRT_7B_ADDR_NOACK      0
 118 #define ABRT_10ADDR1_NOACK      1
 119 #define ABRT_10ADDR2_NOACK      2
 120 #define ABRT_TXDATA_NOACK       3
 121 #define ABRT_GCALL_NOACK        4
 122 #define ABRT_GCALL_READ         5
 123 #define ABRT_SBYTE_ACKDET       7
 124 #define ABRT_SBYTE_NORSTRT      9
 125 #define ABRT_10B_RD_NORSTRT     10
 126 #define ABRT_MASTER_DIS         11
 127 #define ARB_LOST                12
 128
 129 #define DW_IC_TX_ABRT_7B_ADDR_NOACK     (1UL << ABRT_7B_ADDR_NOACK)
 130 #define DW_IC_TX_ABRT_10ADDR1_NOACK     (1UL << ABRT_10ADDR1_NOACK)
 131 #define DW_IC_TX_ABRT_10ADDR2_NOACK     (1UL << ABRT_10ADDR2_NOACK)
 132 #define DW_IC_TX_ABRT_TXDATA_NOACK      (1UL << ABRT_TXDATA_NOACK)
 133 #define DW_IC_TX_ABRT_GCALL_NOACK       (1UL << ABRT_GCALL_NOACK)
 134 #define DW_IC_TX_ABRT_GCALL_READ        (1UL << ABRT_GCALL_READ)
 135 #define DW_IC_TX_ABRT_SBYTE_ACKDET      (1UL << ABRT_SBYTE_ACKDET)
 136 #define DW_IC_TX_ABRT_SBYTE_NORSTRT     (1UL << ABRT_SBYTE_NORSTRT)
 137 #define DW_IC_TX_ABRT_10B_RD_NORSTRT    (1UL << ABRT_10B_RD_NORSTRT)
 138 #define DW_IC_TX_ABRT_MASTER_DIS        (1UL << ABRT_MASTER_DIS)
 139 #define DW_IC_TX_ARB_LOST               (1UL << ARB_LOST)
 140
 141 #define DW_IC_TX_ABRT_NOACK             (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
 142                                          DW_IC_TX_ABRT_10ADDR1_NOACK | \
 143                                          DW_IC_TX_ABRT_10ADDR2_NOACK | \
 144                                          DW_IC_TX_ABRT_TXDATA_NOACK | \
 145                                          DW_IC_TX_ABRT_GCALL_NOACK)
 146
 147 static char *abort_sources[] = {
 148         [ABRT_7B_ADDR_NOACK] =
 149                 "slave address not acknowledged (7bit mode)",
 150         [ABRT_10ADDR1_NOACK] =
 151                 "first address byte not acknowledged (10bit mode)",
 152         [ABRT_10ADDR2_NOACK] =
 153                 "second address byte not acknowledged (10bit mode)",
 154         [ABRT_TXDATA_NOACK] =
 155                 "data not acknowledged",
 156         [ABRT_GCALL_NOACK] =
 157                 "no acknowledgement for a general call",
 158         [ABRT_GCALL_READ] =
 159                 "read after general call",
 160         [ABRT_SBYTE_ACKDET] =
 161                 "start byte acknowledged",
 162         [ABRT_SBYTE_NORSTRT] =
 163                 "trying to send start byte when restart is disabled",
 164         [ABRT_10B_RD_NORSTRT] =
 165                 "trying to read when restart is disabled (10bit mode)",
 166         [ABRT_MASTER_DIS] =
 167                 "trying to use disabled adapter",
 168         [ARB_LOST] =
 169                 "lost arbitration",
 170 };
 171
 172 u32 dw_readl(struct dw_i2c_dev *dev, int offset)
 173 {
 174         u32 value;
 175
 176         if (dev->accessor_flags & ACCESS_16BIT)
 177                 value = readw(dev->base + offset) |
 178                         (readw(dev->base + offset + 2) << 16);
 179         else
 180                 value = readl(dev->base + offset);
 181
 182         if (dev->accessor_flags & ACCESS_SWAP)
 183                 return swab32(value);
 184         else
 185                 return value;
 186 }
 187
 188 void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
 189 {
 190         if (dev->accessor_flags & ACCESS_SWAP)
 191                 b = swab32(b);
 192
 193         if (dev->accessor_flags & ACCESS_16BIT) {
 194                 writew((u16)b, dev->base + offset);
 195                 writew((u16)(b >> 16), dev->base + offset + 2);
 196         } else {
 197                 writel(b, dev->base + offset);
 198         }
 199 }
 200
 201 static u32
 202 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
 203 {
 204         /*
 205          * DesignWare I2C core doesn't seem to have solid strategy to meet
 206          * the tHD;STA timing spec.  Configuring _HCNT based on tHIGH spec
 207          * will result in violation of the tHD;STA spec.
 208          */
 209         if (cond)
 210                 /*
 211                  * Conditional expression:
 212                  *
 213                  *   IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
 214                  *
 215                  * This is based on the DW manuals, and represents an ideal
 216                  * configuration.  The resulting I2C bus speed will be
 217                  * faster than any of the others.
 218                  *
 219                  * If your hardware is free from tHD;STA issue, try this one.
 220                  */
 221                 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
 222         else
 223                 /*
 224                  * Conditional expression:
 225                  *
 226                  *   IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
 227                  *
 228                  * This is just experimental rule; the tHD;STA period turned
 229                  * out to be proportinal to (_HCNT + 3).  With this setting,
 230                  * we could meet both tHIGH and tHD;STA timing specs.
 231                  *
 232                  * If unsure, you'd better to take this alternative.
 233                  *
 234                  * The reason why we need to take into account "tf" here,
 235                  * is the same as described in i2c_dw_scl_lcnt().
 236                  */
 237                 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
 238                         - 3 + offset;
 239 }
 240
 241 static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
 242 {
 243         /*
 244          * Conditional expression:
 245          *
 246          *   IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
 247          *
 248          * DW I2C core starts counting the SCL CNTs for the LOW period
 249          * of the SCL clock (tLOW) as soon as it pulls the SCL line.
 250          * In order to meet the tLOW timing spec, we need to take into
 251          * account the fall time of SCL signal (tf).  Default tf value
 252          * should be 0.3 us, for safety.
 253          */
 254         return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
 255 }
 256
 257 static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable)
 258 {
 259         int timeout = 100;
 260
 261         do {
 262                 dw_writel(dev, enable, DW_IC_ENABLE);
 263                 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)
 264                         return;
 265
 266                 /*
 267                  * Wait 10 times the signaling period of the highest I2C
 268                  * transfer supported by the driver (for 400KHz this is
 269                  * 25us) as described in the DesignWare I2C databook.
 270                  */
 271                 usleep_range(25, 250);
 272         } while (timeout--);
 273
 274         dev_warn(dev->dev, "timeout in %sabling adapter\n",
 275                  enable ? "en" : "dis");
 276 }
 277
 278 /**
 279  * i2c_dw_init() - initialize the designware i2c master hardware
 280  * @dev: device private data
 281  *
 282  * This functions configures and enables the I2C master.
 283  * This function is called during I2C init function, and in case of timeout at
 284  * run time.
 285  */
 286 int i2c_dw_init(struct dw_i2c_dev *dev)
 287 {
 288         u32 input_clock_khz;
 289         u32 hcnt, lcnt;
 290         u32 reg;
 291         u32 sda_falling_time, scl_falling_time;
 292
 293         input_clock_khz = dev->get_clk_rate_khz(dev);
 294
 295         reg = dw_readl(dev, DW_IC_COMP_TYPE);
 296         if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
 297                 /* Configure register endianess access */
 298                 dev->accessor_flags |= ACCESS_SWAP;
 299         } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
 300                 /* Configure register access mode 16bit */
 301                 dev->accessor_flags |= ACCESS_16BIT;
 302         } else if (reg != DW_IC_COMP_TYPE_VALUE) {
 303                 dev_err(dev->dev, "Unknown Synopsys component type: "
 304                         "0x%08x\n", reg);
 305                 return -ENODEV;
 306         }
 307
 308         /* Disable the adapter */
 309         __i2c_dw_enable(dev, false);
 310
 311         /* set standard and fast speed deviders for high/low periods */
 312
 313         sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
 314         scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
 315
 316         /* Standard-mode */
 317         hcnt = i2c_dw_scl_hcnt(input_clock_khz,
 318                                 4000,   /* tHD;STA = tHIGH = 4.0 us */
 319                                 sda_falling_time,
 320                                 0,      /* 0: DW default, 1: Ideal */
 321                                 0);     /* No offset */
 322         lcnt = i2c_dw_scl_lcnt(input_clock_khz,
 323                                 4700,   /* tLOW = 4.7 us */
 324                                 scl_falling_time,
 325                                 0);     /* No offset */
 326
 327         /* Allow platforms to specify the ideal HCNT and LCNT values */
 328         if (dev->ss_hcnt && dev->ss_lcnt) {
 329                 hcnt = dev->ss_hcnt;
 330                 lcnt = dev->ss_lcnt;
 331         }
 332         dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
 333         dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
 334         dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 335
 336         /* Fast-mode */
 337         hcnt = i2c_dw_scl_hcnt(input_clock_khz,
 338                                 600,    /* tHD;STA = tHIGH = 0.6 us */
 339                                 sda_falling_time,
 340                                 0,      /* 0: DW default, 1: Ideal */
 341                                 0);     /* No offset */
 342         lcnt = i2c_dw_scl_lcnt(input_clock_khz,
 343                                 1300,   /* tLOW = 1.3 us */
 344                                 scl_falling_time,
 345                                 0);     /* No offset */
 346
 347         if (dev->fs_hcnt && dev->fs_lcnt) {
 348                 hcnt = dev->fs_hcnt;
 349                 lcnt = dev->fs_lcnt;
 350         }
 351         dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
 352         dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
 353         dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 354
 355         /* Configure SDA Hold Time if required */
 356         if (dev->sda_hold_time) {
 357                 reg = dw_readl(dev, DW_IC_COMP_VERSION);
 358                 if (reg >= DW_IC_SDA_HOLD_MIN_VERS)
 359                         dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
 360                 else
 361                         dev_warn(dev->dev,
 362                                 "Hardware too old to adjust SDA hold time.");
 363         }
 364
 365         /* Configure Tx/Rx FIFO threshold levels */
 366         dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL);
 367         dw_writel(dev, 0, DW_IC_RX_TL);
 368
 369         /* configure the i2c master */
 370         dw_writel(dev, dev->master_cfg , DW_IC_CON);
 371         return 0;
 372 }
 373 EXPORT_SYMBOL_GPL(i2c_dw_init);
 374
 375 /*
 376  * Waiting for bus not busy
 377  */
 378 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
 379 {
 380         int timeout = TIMEOUT;
 381
 382         while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
 383                 if (timeout <= 0) {
 384                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 385                         return -ETIMEDOUT;
 386                 }
 387                 timeout--;
 388                 usleep_range(1000, 1100);
 389         }
 390
 391         return 0;
 392 }
 393
 394 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 395 {
 396         struct i2c_msg *msgs = dev->msgs;
 397         u32 ic_con, ic_tar = 0;
 398
 399         /* Disable the adapter */
 400         __i2c_dw_enable(dev, false);
 401
 402         /* if the slave address is ten bit address, enable 10BITADDR */
 403         ic_con = dw_readl(dev, DW_IC_CON);
 404         if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
 405                 ic_con |= DW_IC_CON_10BITADDR_MASTER;
 406                 /*
 407                  * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
 408                  * mode has to be enabled via bit 12 of IC_TAR register.
 409                  * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
 410                  * detected from registers.
 411                  */
 412                 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
 413         } else {
 414                 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
 415         }
 416
 417         dw_writel(dev, ic_con, DW_IC_CON);
 418
 419         /*
 420          * Set the slave (target) address and enable 10-bit addressing mode
 421          * if applicable.
 422          */
 423         dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
 424
 425         /* Enable the adapter */
 426         __i2c_dw_enable(dev, true);
 427
 428         /* Clear and enable interrupts */
 429         i2c_dw_clear_int(dev);
 430         dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
 431 }
 432
 433 /*
 434  * Initiate (and continue) low level master read/write transaction.
 435  * This function is only called from i2c_dw_isr, and pumping i2c_msg
 436  * messages into the tx buffer.  Even if the size of i2c_msg data is
 437  * longer than the size of the tx buffer, it handles everything.
 438  */
 439 static void
 440 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 441 {
 442         struct i2c_msg *msgs = dev->msgs;
 443         u32 intr_mask;
 444         int tx_limit, rx_limit;
 445         u32 addr = msgs[dev->msg_write_idx].addr;
 446         u32 buf_len = dev->tx_buf_len;
 447         u8 *buf = dev->tx_buf;
 448         bool need_restart = false;
 449
 450         intr_mask = DW_IC_INTR_DEFAULT_MASK;
 451
 452         for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
 453                 /*
 454                  * if target address has changed, we need to
 455                  * reprogram the target address in the i2c
 456                  * adapter when we are done with this transfer
 457                  */
 458                 if (msgs[dev->msg_write_idx].addr != addr) {
 459                         dev_err(dev->dev,
 460                                 "%s: invalid target address\n", __func__);
 461                         dev->msg_err = -EINVAL;
 462                         break;
 463                 }
 464
 465                 if (msgs[dev->msg_write_idx].len == 0) {
 466                         dev_err(dev->dev,
 467                                 "%s: invalid message length\n", __func__);
 468                         dev->msg_err = -EINVAL;
 469                         break;
 470                 }
 471
 472                 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
 473                         /* new i2c_msg */
 474                         buf = msgs[dev->msg_write_idx].buf;
 475                         buf_len = msgs[dev->msg_write_idx].len;
 476
 477                         /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
 478                          * IC_RESTART_EN are set, we must manually
 479                          * set restart bit between messages.
 480                          */
 481                         if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
 482                                         (dev->msg_write_idx > 0))
 483                                 need_restart = true;
 484                 }
 485
 486                 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
 487                 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
 488
 489                 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
 490                         u32 cmd = 0;
 491
 492                         /*
 493                          * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
 494                          * manually set the stop bit. However, it cannot be
 495                          * detected from the registers so we set it always
 496                          * when writing/reading the last byte.
 497                          */
 498                         if (dev->msg_write_idx == dev->msgs_num - 1 &&
 499                             buf_len == 1)
 500                                 cmd |= BIT(9);
 501
 502                         if (need_restart) {
 503                                 cmd |= BIT(10);
 504                                 need_restart = false;
 505                         }
 506
 507                         if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
 508
 509                                 /* avoid rx buffer overrun */
 510                                 if (rx_limit - dev->rx_outstanding <= 0)
 511                                         break;
 512
 513                                 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
 514                                 rx_limit--;
 515                                 dev->rx_outstanding++;
 516                         } else
 517                                 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
 518                         tx_limit--; buf_len--;
 519                 }
 520
 521                 dev->tx_buf = buf;
 522                 dev->tx_buf_len = buf_len;
 523
 524                 if (buf_len > 0) {
 525                         /* more bytes to be written */
 526                         dev->status |= STATUS_WRITE_IN_PROGRESS;
 527                         break;
 528                 } else
 529                         dev->status &= ~STATUS_WRITE_IN_PROGRESS;
 530         }
 531
 532         /*
 533          * If i2c_msg index search is completed, we don't need TX_EMPTY
 534          * interrupt any more.
 535          */
 536         if (dev->msg_write_idx == dev->msgs_num)
 537                 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
 538
 539         if (dev->msg_err)
 540                 intr_mask = 0;
 541
 542         dw_writel(dev, intr_mask,  DW_IC_INTR_MASK);
 543 }
 544
 545 static void
 546 i2c_dw_read(struct dw_i2c_dev *dev)
 547 {
 548         struct i2c_msg *msgs = dev->msgs;
 549         int rx_valid;
 550
 551         for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
 552                 u32 len;
 553                 u8 *buf;
 554
 555                 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
 556                         continue;
 557
 558                 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
 559                         len = msgs[dev->msg_read_idx].len;
 560                         buf = msgs[dev->msg_read_idx].buf;
 561                 } else {
 562                         len = dev->rx_buf_len;
 563                         buf = dev->rx_buf;
 564                 }
 565
 566                 rx_valid = dw_readl(dev, DW_IC_RXFLR);
 567
 568                 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
 569                         *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
 570                         dev->rx_outstanding--;
 571                 }
 572
 573                 if (len > 0) {
 574                         dev->status |= STATUS_READ_IN_PROGRESS;
 575                         dev->rx_buf_len = len;
 576                         dev->rx_buf = buf;
 577                         return;
 578                 } else
 579                         dev->status &= ~STATUS_READ_IN_PROGRESS;
 580         }
 581 }
 582
 583 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
 584 {
 585         unsigned long abort_source = dev->abort_source;
 586         int i;
 587
 588         if (abort_source & DW_IC_TX_ABRT_NOACK) {
 589                 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
 590                         dev_dbg(dev->dev,
 591                                 "%s: %s\n", __func__, abort_sources[i]);
 592                 return -EREMOTEIO;
 593         }
 594
 595         for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
 596                 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
 597
 598         if (abort_source & DW_IC_TX_ARB_LOST)
 599                 return -EAGAIN;
 600         else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
 601                 return -EINVAL; /* wrong msgs[] data */
 602         else
 603                 return -EIO;
 604 }
 605
 606 /*
 607  * Prepare controller for a transaction and call i2c_dw_xfer_msg
 608  */
 609 int
 610 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 611 {
 612         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 613         int ret;
 614
 615         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 616
 617         mutex_lock(&dev->lock);
 618         pm_runtime_get_sync(dev->dev);
 619
 620         reinit_completion(&dev->cmd_complete);
 621         dev->msgs = msgs;
 622         dev->msgs_num = num;
 623         dev->cmd_err = 0;
 624         dev->msg_write_idx = 0;
 625         dev->msg_read_idx = 0;
 626         dev->msg_err = 0;
 627         dev->status = STATUS_IDLE;
 628         dev->abort_source = 0;
 629         dev->rx_outstanding = 0;
 630
 631         ret = i2c_dw_wait_bus_not_busy(dev);
 632         if (ret < 0)
 633                 goto done;
 634
 635         /* start the transfers */
 636         i2c_dw_xfer_init(dev);
 637
 638         /* wait for tx to complete */
 639         ret = wait_for_completion_timeout(&dev->cmd_complete, HZ);
 640         if (ret == 0) {
 641                 dev_err(dev->dev, "controller timed out\n");
 642                 /* i2c_dw_init implicitly disables the adapter */
 643                 i2c_dw_init(dev);
 644                 ret = -ETIMEDOUT;
 645                 goto done;
 646         }
 647
 648         /*
 649          * We must disable the adapter before unlocking the &dev->lock mutex
 650          * below. Otherwise the hardware might continue generating interrupts
 651          * which in turn causes a race condition with the following transfer.
 652          * Needs some more investigation if the additional interrupts are
 653          * a hardware bug or this driver doesn't handle them correctly yet.
 654          */
 655         __i2c_dw_enable(dev, false);
 656
 657         if (dev->msg_err) {
 658                 ret = dev->msg_err;
 659                 goto done;
 660         }
 661
 662         /* no error */
 663         if (likely(!dev->cmd_err)) {
 664                 ret = num;
 665                 goto done;
 666         }
 667
 668         /* We have an error */
 669         if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
 670                 ret = i2c_dw_handle_tx_abort(dev);
 671                 goto done;
 672         }
 673         ret = -EIO;
 674
 675 done:
 676         pm_runtime_mark_last_busy(dev->dev);
 677         pm_runtime_put_autosuspend(dev->dev);
 678         mutex_unlock(&dev->lock);
 679
 680         return ret;
 681 }
 682 EXPORT_SYMBOL_GPL(i2c_dw_xfer);
 683
 684 u32 i2c_dw_func(struct i2c_adapter *adap)
 685 {
 686         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 687         return dev->functionality;
 688 }
 689 EXPORT_SYMBOL_GPL(i2c_dw_func);
 690
 691 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
 692 {
 693         u32 stat;
 694
 695         /*
 696          * The IC_INTR_STAT register just indicates "enabled" interrupts.
 697          * Ths unmasked raw version of interrupt status bits are available
 698          * in the IC_RAW_INTR_STAT register.
 699          *
 700          * That is,
 701          *   stat = dw_readl(IC_INTR_STAT);
 702          * equals to,
 703          *   stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
 704          *
 705          * The raw version might be useful for debugging purposes.
 706          */
 707         stat = dw_readl(dev, DW_IC_INTR_STAT);
 708
 709         /*
 710          * Do not use the IC_CLR_INTR register to clear interrupts, or
 711          * you'll miss some interrupts, triggered during the period from
 712          * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
 713          *
 714          * Instead, use the separately-prepared IC_CLR_* registers.
 715          */
 716         if (stat & DW_IC_INTR_RX_UNDER)
 717                 dw_readl(dev, DW_IC_CLR_RX_UNDER);
 718         if (stat & DW_IC_INTR_RX_OVER)
 719                 dw_readl(dev, DW_IC_CLR_RX_OVER);
 720         if (stat & DW_IC_INTR_TX_OVER)
 721                 dw_readl(dev, DW_IC_CLR_TX_OVER);
 722         if (stat & DW_IC_INTR_RD_REQ)
 723                 dw_readl(dev, DW_IC_CLR_RD_REQ);
 724         if (stat & DW_IC_INTR_TX_ABRT) {
 725                 /*
 726                  * The IC_TX_ABRT_SOURCE register is cleared whenever
 727                  * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
 728                  */
 729                 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
 730                 dw_readl(dev, DW_IC_CLR_TX_ABRT);
 731         }
 732         if (stat & DW_IC_INTR_RX_DONE)
 733                 dw_readl(dev, DW_IC_CLR_RX_DONE);
 734         if (stat & DW_IC_INTR_ACTIVITY)
 735                 dw_readl(dev, DW_IC_CLR_ACTIVITY);
 736         if (stat & DW_IC_INTR_STOP_DET)
 737                 dw_readl(dev, DW_IC_CLR_STOP_DET);
 738         if (stat & DW_IC_INTR_START_DET)
 739                 dw_readl(dev, DW_IC_CLR_START_DET);
 740         if (stat & DW_IC_INTR_GEN_CALL)
 741                 dw_readl(dev, DW_IC_CLR_GEN_CALL);
 742
 743         return stat;
 744 }
 745
 746 /*
 747  * Interrupt service routine. This gets called whenever an I2C interrupt
 748  * occurs.
 749  */
 750 irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
 751 {
 752         struct dw_i2c_dev *dev = dev_id;
 753         u32 stat, enabled;
 754
 755         enabled = dw_readl(dev, DW_IC_ENABLE);
 756         stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
 757         dev_dbg(dev->dev, "%s:  %s enabled= 0x%x stat=0x%x\n", __func__,
 758                 dev->adapter.name, enabled, stat);
 759         if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
 760                 return IRQ_NONE;
 761
 762         stat = i2c_dw_read_clear_intrbits(dev);
 763
 764         if (stat & DW_IC_INTR_TX_ABRT) {
 765                 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
 766                 dev->status = STATUS_IDLE;
 767
 768                 /*
 769                  * Anytime TX_ABRT is set, the contents of the tx/rx
 770                  * buffers are flushed.  Make sure to skip them.
 771                  */
 772                 dw_writel(dev, 0, DW_IC_INTR_MASK);
 773                 goto tx_aborted;
 774         }
 775
 776         if (stat & DW_IC_INTR_RX_FULL)
 777                 i2c_dw_read(dev);
 778
 779         if (stat & DW_IC_INTR_TX_EMPTY)
 780                 i2c_dw_xfer_msg(dev);
 781
 782         /*
 783          * No need to modify or disable the interrupt mask here.
 784          * i2c_dw_xfer_msg() will take care of it according to
 785          * the current transmit status.
 786          */
 787
 788 tx_aborted:
 789         if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
 790                 complete(&dev->cmd_complete);
 791
 792         return IRQ_HANDLED;
 793 }
 794 EXPORT_SYMBOL_GPL(i2c_dw_isr);
 795
 796 void i2c_dw_enable(struct dw_i2c_dev *dev)
 797 {
 798        /* Enable the adapter */
 799         __i2c_dw_enable(dev, true);
 800 }
 801 EXPORT_SYMBOL_GPL(i2c_dw_enable);
 802
 803 u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev)
 804 {
 805         return dw_readl(dev, DW_IC_ENABLE);
 806 }
 807 EXPORT_SYMBOL_GPL(i2c_dw_is_enabled);
 808
 809 void i2c_dw_disable(struct dw_i2c_dev *dev)
 810 {
 811         /* Disable controller */
 812         __i2c_dw_enable(dev, false);
 813
 814         /* Disable all interupts */
 815         dw_writel(dev, 0, DW_IC_INTR_MASK);
 816         dw_readl(dev, DW_IC_CLR_INTR);
 817 }
 818 EXPORT_SYMBOL_GPL(i2c_dw_disable);
 819
 820 void i2c_dw_clear_int(struct dw_i2c_dev *dev)
 821 {
 822         dw_readl(dev, DW_IC_CLR_INTR);
 823 }
 824 EXPORT_SYMBOL_GPL(i2c_dw_clear_int);
 825
 826 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
 827 {
 828         dw_writel(dev, 0, DW_IC_INTR_MASK);
 829 }
 830 EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
 831
 832 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
 833 {
 834         return dw_readl(dev, DW_IC_COMP_PARAM_1);
 835 }
 836 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
 837
 838 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
 839 MODULE_LICENSE("GPL");